| T1341 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.453589960 |
|
|
Sep 05 01:51:06 AM UTC 24 |
Sep 05 02:00:47 AM UTC 24 |
5111690824 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2892952343 |
|
|
Sep 05 12:52:08 AM UTC 24 |
Sep 05 02:02:31 AM UTC 24 |
17660378842 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2841081715 |
|
|
Sep 05 12:53:05 AM UTC 24 |
Sep 05 02:11:53 AM UTC 24 |
19842060290 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1907162791 |
|
|
Sep 05 12:21:08 AM UTC 24 |
Sep 05 02:12:09 AM UTC 24 |
27513833840 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1434978735 |
|
|
Sep 04 09:40:20 PM UTC 24 |
Sep 05 02:13:43 AM UTC 24 |
78572779670 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.2120545654 |
|
|
Sep 05 12:54:47 AM UTC 24 |
Sep 05 02:14:45 AM UTC 24 |
20357119720 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3240226162 |
|
|
Sep 05 01:05:58 AM UTC 24 |
Sep 05 02:17:15 AM UTC 24 |
19478835972 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1400588537 |
|
|
Sep 04 11:01:26 PM UTC 24 |
Sep 05 02:31:16 AM UTC 24 |
59282079800 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2328655901 |
|
|
Sep 04 11:00:41 PM UTC 24 |
Sep 05 02:36:33 AM UTC 24 |
66063300941 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3507801062 |
|
|
Sep 04 11:40:30 PM UTC 24 |
Sep 05 03:05:28 AM UTC 24 |
255301263320 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1485805752 |
|
|
Sep 04 11:01:43 PM UTC 24 |
Sep 05 03:14:18 AM UTC 24 |
79358826380 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4106333473 |
|
|
Sep 04 10:46:41 PM UTC 24 |
Sep 05 04:13:24 AM UTC 24 |
132096754462 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.315932432 |
|
|
Sep 04 05:09:06 PM UTC 24 |
Sep 04 05:09:29 PM UTC 24 |
195983086 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2992381981 |
|
|
Sep 04 05:00:53 PM UTC 24 |
Sep 04 05:01:00 PM UTC 24 |
54728013 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.1112543128 |
|
|
Sep 04 05:00:53 PM UTC 24 |
Sep 04 05:01:05 PM UTC 24 |
230477030 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3178324020 |
|
|
Sep 04 05:01:12 PM UTC 24 |
Sep 04 05:01:25 PM UTC 24 |
94559514 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.423158289 |
|
|
Sep 04 05:01:03 PM UTC 24 |
Sep 04 05:01:27 PM UTC 24 |
324463213 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2289798422 |
|
|
Sep 04 05:01:01 PM UTC 24 |
Sep 04 05:01:35 PM UTC 24 |
499583536 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.2175155296 |
|
|
Sep 04 05:01:00 PM UTC 24 |
Sep 04 05:01:44 PM UTC 24 |
446493348 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.439711345 |
|
|
Sep 04 05:01:42 PM UTC 24 |
Sep 04 05:01:52 PM UTC 24 |
53469544 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3930055496 |
|
|
Sep 04 05:00:57 PM UTC 24 |
Sep 04 05:01:56 PM UTC 24 |
1481427573 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.787379769 |
|
|
Sep 04 05:01:01 PM UTC 24 |
Sep 04 05:01:59 PM UTC 24 |
944012051 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1121441097 |
|
|
Sep 04 05:01:51 PM UTC 24 |
Sep 04 05:02:00 PM UTC 24 |
46957786 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.24419114 |
|
|
Sep 04 05:00:57 PM UTC 24 |
Sep 04 05:02:04 PM UTC 24 |
4687563203 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3478113997 |
|
|
Sep 04 05:01:04 PM UTC 24 |
Sep 04 05:02:13 PM UTC 24 |
2339840871 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.4121402015 |
|
|
Sep 04 05:02:04 PM UTC 24 |
Sep 04 05:02:32 PM UTC 24 |
200348149 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.3530112270 |
|
|
Sep 04 05:02:32 PM UTC 24 |
Sep 04 05:02:46 PM UTC 24 |
134098217 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3297838459 |
|
|
Sep 04 05:02:28 PM UTC 24 |
Sep 04 05:02:46 PM UTC 24 |
177196515 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.934920279 |
|
|
Sep 04 05:02:29 PM UTC 24 |
Sep 04 05:02:54 PM UTC 24 |
592067762 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.888116776 |
|
|
Sep 04 05:02:01 PM UTC 24 |
Sep 04 05:02:55 PM UTC 24 |
1451851955 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1648047502 |
|
|
Sep 04 05:02:34 PM UTC 24 |
Sep 04 05:03:00 PM UTC 24 |
202124330 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1734152381 |
|
|
Sep 04 05:01:01 PM UTC 24 |
Sep 04 05:03:01 PM UTC 24 |
5507743937 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3562552039 |
|
|
Sep 04 05:02:41 PM UTC 24 |
Sep 04 05:03:06 PM UTC 24 |
279874807 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2628494267 |
|
|
Sep 04 05:01:11 PM UTC 24 |
Sep 04 05:03:22 PM UTC 24 |
215465608 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1610462269 |
|
|
Sep 04 05:03:30 PM UTC 24 |
Sep 04 05:03:42 PM UTC 24 |
171122030 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3158010458 |
|
|
Sep 04 05:03:36 PM UTC 24 |
Sep 04 05:03:46 PM UTC 24 |
45640238 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.3401270078 |
|
|
Sep 04 05:01:13 PM UTC 24 |
Sep 04 05:03:47 PM UTC 24 |
3725711380 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3960596190 |
|
|
Sep 04 05:01:58 PM UTC 24 |
Sep 04 05:03:50 PM UTC 24 |
8514280868 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1111106384 |
|
|
Sep 04 05:01:59 PM UTC 24 |
Sep 04 05:03:53 PM UTC 24 |
4283716769 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.842577752 |
|
|
Sep 04 05:04:10 PM UTC 24 |
Sep 04 05:04:31 PM UTC 24 |
166330340 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3724090083 |
|
|
Sep 04 05:04:17 PM UTC 24 |
Sep 04 05:04:32 PM UTC 24 |
342383316 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.3249036629 |
|
|
Sep 04 05:04:22 PM UTC 24 |
Sep 04 05:04:35 PM UTC 24 |
193895622 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2110634503 |
|
|
Sep 04 05:02:28 PM UTC 24 |
Sep 04 05:04:48 PM UTC 24 |
8979494072 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.1766862590 |
|
|
Sep 04 05:03:43 PM UTC 24 |
Sep 04 05:04:48 PM UTC 24 |
4981571147 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3626924378 |
|
|
Sep 04 05:03:48 PM UTC 24 |
Sep 04 05:05:01 PM UTC 24 |
4914759358 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.40458190 |
|
|
Sep 04 05:04:02 PM UTC 24 |
Sep 04 05:05:14 PM UTC 24 |
1589109367 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.3660146346 |
|
|
Sep 04 05:04:59 PM UTC 24 |
Sep 04 05:05:18 PM UTC 24 |
117007288 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2102285619 |
|
|
Sep 04 05:05:02 PM UTC 24 |
Sep 04 05:05:31 PM UTC 24 |
189187745 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3668077134 |
|
|
Sep 04 05:01:20 PM UTC 24 |
Sep 04 05:05:40 PM UTC 24 |
4372754928 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1379531410 |
|
|
Sep 04 05:00:57 PM UTC 24 |
Sep 04 05:05:48 PM UTC 24 |
3599861632 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2252640587 |
|
|
Sep 04 05:02:47 PM UTC 24 |
Sep 04 05:05:51 PM UTC 24 |
382241924 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.2816195187 |
|
|
Sep 04 05:04:54 PM UTC 24 |
Sep 04 05:05:59 PM UTC 24 |
566402870 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1190239318 |
|
|
Sep 04 05:06:16 PM UTC 24 |
Sep 04 05:06:30 PM UTC 24 |
209996993 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.4239284362 |
|
|
Sep 04 05:06:21 PM UTC 24 |
Sep 04 05:06:31 PM UTC 24 |
49151525 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.3748146615 |
|
|
Sep 04 05:03:28 PM UTC 24 |
Sep 04 05:06:32 PM UTC 24 |
3549797500 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2493249983 |
|
|
Sep 04 05:01:14 PM UTC 24 |
Sep 04 05:06:37 PM UTC 24 |
3943149221 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.395330188 |
|
|
Sep 04 05:01:33 PM UTC 24 |
Sep 04 05:06:39 PM UTC 24 |
8195657084 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3996314033 |
|
|
Sep 04 05:01:18 PM UTC 24 |
Sep 04 05:06:40 PM UTC 24 |
2068964918 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.1936467664 |
|
|
Sep 04 05:02:45 PM UTC 24 |
Sep 04 05:06:51 PM UTC 24 |
6525159397 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.855993093 |
|
|
Sep 04 05:01:21 PM UTC 24 |
Sep 04 05:06:54 PM UTC 24 |
4286351252 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.1845297777 |
|
|
Sep 04 05:05:06 PM UTC 24 |
Sep 04 05:07:07 PM UTC 24 |
1564017739 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.3691863542 |
|
|
Sep 04 05:06:58 PM UTC 24 |
Sep 04 05:07:10 PM UTC 24 |
182216585 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1236073263 |
|
|
Sep 04 05:03:09 PM UTC 24 |
Sep 04 05:07:13 PM UTC 24 |
4623221198 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.936463139 |
|
|
Sep 04 05:01:17 PM UTC 24 |
Sep 04 05:07:16 PM UTC 24 |
7090581900 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3535604668 |
|
|
Sep 04 05:05:19 PM UTC 24 |
Sep 04 05:07:24 PM UTC 24 |
3530498932 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3706357708 |
|
|
Sep 04 05:07:09 PM UTC 24 |
Sep 04 05:07:27 PM UTC 24 |
513477151 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.4079623178 |
|
|
Sep 04 05:07:08 PM UTC 24 |
Sep 04 05:07:35 PM UTC 24 |
963775633 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1207640922 |
|
|
Sep 04 05:03:23 PM UTC 24 |
Sep 04 05:07:40 PM UTC 24 |
3529003624 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1669445097 |
|
|
Sep 04 05:07:17 PM UTC 24 |
Sep 04 05:07:43 PM UTC 24 |
378198447 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2142175107 |
|
|
Sep 04 05:03:05 PM UTC 24 |
Sep 04 05:07:46 PM UTC 24 |
3575159125 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.3297549052 |
|
|
Sep 04 05:07:06 PM UTC 24 |
Sep 04 05:07:55 PM UTC 24 |
382706088 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.739420271 |
|
|
Sep 04 05:07:01 PM UTC 24 |
Sep 04 05:07:56 PM UTC 24 |
565492330 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2130724703 |
|
|
Sep 04 05:07:21 PM UTC 24 |
Sep 04 05:08:11 PM UTC 24 |
1024017335 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3373645298 |
|
|
Sep 04 05:06:26 PM UTC 24 |
Sep 04 05:08:21 PM UTC 24 |
9243570483 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3168289853 |
|
|
Sep 04 05:06:38 PM UTC 24 |
Sep 04 05:08:28 PM UTC 24 |
5688926118 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2183593898 |
|
|
Sep 04 05:08:23 PM UTC 24 |
Sep 04 05:08:33 PM UTC 24 |
47326364 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.334295893 |
|
|
Sep 04 05:00:56 PM UTC 24 |
Sep 04 05:08:38 PM UTC 24 |
10979049596 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.152176797 |
|
|
Sep 04 05:06:10 PM UTC 24 |
Sep 04 05:08:42 PM UTC 24 |
2857472725 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1790013310 |
|
|
Sep 04 05:08:40 PM UTC 24 |
Sep 04 05:08:49 PM UTC 24 |
51738191 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4162341115 |
|
|
Sep 04 05:01:04 PM UTC 24 |
Sep 04 05:08:52 PM UTC 24 |
31986481248 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.4179263659 |
|
|
Sep 04 05:05:32 PM UTC 24 |
Sep 04 05:09:11 PM UTC 24 |
3690209970 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.3094122328 |
|
|
Sep 04 05:01:21 PM UTC 24 |
Sep 04 05:09:23 PM UTC 24 |
5801262266 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3435412417 |
|
|
Sep 04 05:09:16 PM UTC 24 |
Sep 04 05:09:26 PM UTC 24 |
33145682 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.2323663481 |
|
|
Sep 04 05:01:02 PM UTC 24 |
Sep 04 05:09:32 PM UTC 24 |
35904358718 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1772293112 |
|
|
Sep 04 05:01:38 PM UTC 24 |
Sep 04 05:09:35 PM UTC 24 |
10238897409 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.633985501 |
|
|
Sep 04 05:03:01 PM UTC 24 |
Sep 04 05:09:38 PM UTC 24 |
11186726306 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2390434100 |
|
|
Sep 04 05:09:04 PM UTC 24 |
Sep 04 05:09:49 PM UTC 24 |
1057124221 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2741891832 |
|
|
Sep 04 05:07:04 PM UTC 24 |
Sep 04 05:10:06 PM UTC 24 |
9623178805 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.2616785809 |
|
|
Sep 04 05:09:56 PM UTC 24 |
Sep 04 05:10:07 PM UTC 24 |
99425753 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.870529602 |
|
|
Sep 04 05:08:58 PM UTC 24 |
Sep 04 05:10:07 PM UTC 24 |
4668167014 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2119127357 |
|
|
Sep 04 05:09:59 PM UTC 24 |
Sep 04 05:10:18 PM UTC 24 |
249046627 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.2370583414 |
|
|
Sep 04 05:09:37 PM UTC 24 |
Sep 04 05:10:21 PM UTC 24 |
483922371 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.3951475184 |
|
|
Sep 04 05:09:54 PM UTC 24 |
Sep 04 05:10:27 PM UTC 24 |
880001065 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.2316607107 |
|
|
Sep 04 05:07:34 PM UTC 24 |
Sep 04 05:10:29 PM UTC 24 |
5895477108 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.2758257440 |
|
|
Sep 04 05:01:33 PM UTC 24 |
Sep 04 05:10:30 PM UTC 24 |
5006170966 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1135871620 |
|
|
Sep 04 05:07:38 PM UTC 24 |
Sep 04 05:10:42 PM UTC 24 |
411322192 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.2269732451 |
|
|
Sep 04 05:08:22 PM UTC 24 |
Sep 04 05:10:42 PM UTC 24 |
3245374234 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1897225518 |
|
|
Sep 04 05:07:38 PM UTC 24 |
Sep 04 05:10:45 PM UTC 24 |
2396998743 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.4112622041 |
|
|
Sep 04 05:08:47 PM UTC 24 |
Sep 04 05:10:54 PM UTC 24 |
9618861464 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.416086296 |
|
|
Sep 04 05:10:57 PM UTC 24 |
Sep 04 05:11:06 PM UTC 24 |
42588655 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.583361290 |
|
|
Sep 04 05:10:53 PM UTC 24 |
Sep 04 05:11:07 PM UTC 24 |
226763844 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.113253419 |
|
|
Sep 04 05:11:13 PM UTC 24 |
Sep 04 05:11:25 PM UTC 24 |
95530071 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2374532501 |
|
|
Sep 04 05:03:15 PM UTC 24 |
Sep 04 05:11:33 PM UTC 24 |
5736112929 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.403025453 |
|
|
Sep 04 05:11:12 PM UTC 24 |
Sep 04 05:11:40 PM UTC 24 |
349669592 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.4059819400 |
|
|
Sep 04 05:11:35 PM UTC 24 |
Sep 04 05:11:56 PM UTC 24 |
118058207 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2276562244 |
|
|
Sep 04 05:07:52 PM UTC 24 |
Sep 04 05:12:05 PM UTC 24 |
5119542032 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.234903691 |
|
|
Sep 04 05:02:15 PM UTC 24 |
Sep 04 05:12:08 PM UTC 24 |
61371099980 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1336585848 |
|
|
Sep 04 05:11:01 PM UTC 24 |
Sep 04 05:12:25 PM UTC 24 |
5231405955 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2076179869 |
|
|
Sep 04 05:00:52 PM UTC 24 |
Sep 04 05:12:36 PM UTC 24 |
12417987720 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.2092509736 |
|
|
Sep 04 05:12:10 PM UTC 24 |
Sep 04 05:12:40 PM UTC 24 |
267455994 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.3286614382 |
|
|
Sep 04 05:11:52 PM UTC 24 |
Sep 04 05:12:40 PM UTC 24 |
464861832 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.324076843 |
|
|
Sep 04 05:10:01 PM UTC 24 |
Sep 04 05:12:44 PM UTC 24 |
1807281699 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3704170434 |
|
|
Sep 04 05:03:28 PM UTC 24 |
Sep 04 05:12:49 PM UTC 24 |
13399307795 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.748327511 |
|
|
Sep 04 05:05:07 PM UTC 24 |
Sep 04 05:12:51 PM UTC 24 |
5922986299 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.1128593415 |
|
|
Sep 04 05:12:04 PM UTC 24 |
Sep 04 05:12:59 PM UTC 24 |
1979899301 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.342686689 |
|
|
Sep 04 05:00:56 PM UTC 24 |
Sep 04 05:12:59 PM UTC 24 |
73938180302 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.1094031766 |
|
|
Sep 04 05:10:58 PM UTC 24 |
Sep 04 05:13:15 PM UTC 24 |
9720619420 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3176132691 |
|
|
Sep 04 05:04:18 PM UTC 24 |
Sep 04 05:13:17 PM UTC 24 |
30051201010 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2257467583 |
|
|
Sep 04 05:12:27 PM UTC 24 |
Sep 04 05:13:35 PM UTC 24 |
1430096008 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.735989366 |
|
|
Sep 04 05:13:28 PM UTC 24 |
Sep 04 05:13:35 PM UTC 24 |
40904351 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.3869214068 |
|
|
Sep 04 05:13:23 PM UTC 24 |
Sep 04 05:13:36 PM UTC 24 |
206341158 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.44631059 |
|
|
Sep 04 05:12:32 PM UTC 24 |
Sep 04 05:13:39 PM UTC 24 |
274631303 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2323284715 |
|
|
Sep 04 05:10:13 PM UTC 24 |
Sep 04 05:13:56 PM UTC 24 |
1813166520 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2060873402 |
|
|
Sep 04 05:07:43 PM UTC 24 |
Sep 04 05:14:25 PM UTC 24 |
3874325893 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.617688608 |
|
|
Sep 04 05:07:01 PM UTC 24 |
Sep 04 05:14:43 PM UTC 24 |
36909344969 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3559413703 |
|
|
Sep 04 05:13:29 PM UTC 24 |
Sep 04 05:14:53 PM UTC 24 |
5482326411 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.2635159766 |
|
|
Sep 04 05:13:45 PM UTC 24 |
Sep 04 05:14:58 PM UTC 24 |
1486924574 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3887096893 |
|
|
Sep 04 05:12:54 PM UTC 24 |
Sep 04 05:14:58 PM UTC 24 |
1858356223 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.2962239059 |
|
|
Sep 04 05:13:47 PM UTC 24 |
Sep 04 05:15:00 PM UTC 24 |
549569812 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3521793989 |
|
|
Sep 04 05:14:07 PM UTC 24 |
Sep 04 05:15:02 PM UTC 24 |
1343860549 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.2349440787 |
|
|
Sep 04 05:13:26 PM UTC 24 |
Sep 04 05:15:04 PM UTC 24 |
6330196938 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.1191225251 |
|
|
Sep 04 05:10:51 PM UTC 24 |
Sep 04 05:15:11 PM UTC 24 |
3826577798 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.671343210 |
|
|
Sep 04 05:14:28 PM UTC 24 |
Sep 04 05:15:14 PM UTC 24 |
1120173042 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2403214199 |
|
|
Sep 04 05:14:53 PM UTC 24 |
Sep 04 05:15:31 PM UTC 24 |
522572877 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.4155804501 |
|
|
Sep 04 05:13:21 PM UTC 24 |
Sep 04 05:15:46 PM UTC 24 |
3069664435 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.1409104416 |
|
|
Sep 04 05:04:13 PM UTC 24 |
Sep 04 05:15:48 PM UTC 24 |
61788968841 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2297546077 |
|
|
Sep 04 05:15:15 PM UTC 24 |
Sep 04 05:15:50 PM UTC 24 |
340843639 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3053975813 |
|
|
Sep 04 05:10:02 PM UTC 24 |
Sep 04 05:15:51 PM UTC 24 |
9453825424 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1874277356 |
|
|
Sep 04 05:15:12 PM UTC 24 |
Sep 04 05:16:04 PM UTC 24 |
289973330 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3881073524 |
|
|
Sep 04 05:15:57 PM UTC 24 |
Sep 04 05:16:05 PM UTC 24 |
163143478 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3945627135 |
|
|
Sep 04 05:16:15 PM UTC 24 |
Sep 04 05:16:24 PM UTC 24 |
45905692 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.479270394 |
|
|
Sep 04 05:14:05 PM UTC 24 |
Sep 04 05:16:26 PM UTC 24 |
10215150758 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3845985889 |
|
|
Sep 04 05:12:36 PM UTC 24 |
Sep 04 05:16:29 PM UTC 24 |
5935937538 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3811113609 |
|
|
Sep 04 05:05:45 PM UTC 24 |
Sep 04 05:16:32 PM UTC 24 |
5922192035 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1628723955 |
|
|
Sep 04 05:10:05 PM UTC 24 |
Sep 04 05:16:34 PM UTC 24 |
1292132001 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.684801735 |
|
|
Sep 04 05:10:37 PM UTC 24 |
Sep 04 05:16:51 PM UTC 24 |
7736244516 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1952018580 |
|
|
Sep 04 05:16:23 PM UTC 24 |
Sep 04 05:16:56 PM UTC 24 |
763954461 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2175209074 |
|
|
Sep 04 05:15:24 PM UTC 24 |
Sep 04 05:17:05 PM UTC 24 |
1254134163 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3083254974 |
|
|
Sep 04 05:10:34 PM UTC 24 |
Sep 04 05:17:28 PM UTC 24 |
4229218400 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.2048517573 |
|
|
Sep 04 05:16:15 PM UTC 24 |
Sep 04 05:17:29 PM UTC 24 |
7313993113 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4139134538 |
|
|
Sep 04 05:05:46 PM UTC 24 |
Sep 04 05:17:30 PM UTC 24 |
12280618454 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.3821034654 |
|
|
Sep 04 05:16:34 PM UTC 24 |
Sep 04 05:17:38 PM UTC 24 |
526035969 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.931482449 |
|
|
Sep 04 05:17:06 PM UTC 24 |
Sep 04 05:17:48 PM UTC 24 |
1163673518 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.718767383 |
|
|
Sep 04 05:16:21 PM UTC 24 |
Sep 04 05:17:56 PM UTC 24 |
4436713246 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2662061311 |
|
|
Sep 04 05:17:14 PM UTC 24 |
Sep 04 05:18:04 PM UTC 24 |
808390618 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.1861749901 |
|
|
Sep 04 05:17:02 PM UTC 24 |
Sep 04 05:18:17 PM UTC 24 |
2749982463 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3083638141 |
|
|
Sep 04 05:17:21 PM UTC 24 |
Sep 04 05:18:27 PM UTC 24 |
1359553458 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2271298776 |
|
|
Sep 04 05:08:05 PM UTC 24 |
Sep 04 05:18:30 PM UTC 24 |
5732832100 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.352606025 |
|
|
Sep 04 05:13:06 PM UTC 24 |
Sep 04 05:18:31 PM UTC 24 |
4122399763 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.2020771194 |
|
|
Sep 04 05:16:55 PM UTC 24 |
Sep 04 05:18:35 PM UTC 24 |
1557086625 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.901726116 |
|
|
Sep 04 05:15:28 PM UTC 24 |
Sep 04 05:18:41 PM UTC 24 |
5522505576 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1295540626 |
|
|
Sep 04 05:17:27 PM UTC 24 |
Sep 04 05:18:43 PM UTC 24 |
739045096 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.1000939228 |
|
|
Sep 04 05:18:34 PM UTC 24 |
Sep 04 05:18:44 PM UTC 24 |
41784291 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1641698140 |
|
|
Sep 04 05:18:47 PM UTC 24 |
Sep 04 05:18:56 PM UTC 24 |
38936730 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.4174210844 |
|
|
Sep 04 05:02:22 PM UTC 24 |
Sep 04 05:19:00 PM UTC 24 |
58388967635 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1238067616 |
|
|
Sep 04 05:19:31 PM UTC 24 |
Sep 04 05:19:44 PM UTC 24 |
180939128 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.1992555486 |
|
|
Sep 04 05:17:59 PM UTC 24 |
Sep 04 05:19:48 PM UTC 24 |
1438010550 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.2824738474 |
|
|
Sep 04 05:19:02 PM UTC 24 |
Sep 04 05:20:03 PM UTC 24 |
1252184197 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.4065753550 |
|
|
Sep 04 05:15:43 PM UTC 24 |
Sep 04 05:20:06 PM UTC 24 |
3624854128 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.1693093360 |
|
|
Sep 04 05:18:58 PM UTC 24 |
Sep 04 05:20:10 PM UTC 24 |
537151822 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.566562947 |
|
|
Sep 04 05:17:36 PM UTC 24 |
Sep 04 05:20:28 PM UTC 24 |
4213622731 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.25993934 |
|
|
Sep 04 05:04:15 PM UTC 24 |
Sep 04 05:20:28 PM UTC 24 |
68990870525 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3321993525 |
|
|
Sep 04 05:19:00 PM UTC 24 |
Sep 04 05:20:28 PM UTC 24 |
6212002612 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.959072340 |
|
|
Sep 04 05:20:14 PM UTC 24 |
Sep 04 05:20:31 PM UTC 24 |
141667485 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.3610989653 |
|
|
Sep 04 05:07:54 PM UTC 24 |
Sep 04 05:20:33 PM UTC 24 |
6563743062 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.2993197147 |
|
|
Sep 04 05:19:15 PM UTC 24 |
Sep 04 05:20:34 PM UTC 24 |
734924016 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1022002865 |
|
|
Sep 04 05:20:20 PM UTC 24 |
Sep 04 05:20:37 PM UTC 24 |
83301192 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.220490865 |
|
|
Sep 04 05:20:33 PM UTC 24 |
Sep 04 05:20:55 PM UTC 24 |
117738193 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2437185302 |
|
|
Sep 04 05:18:00 PM UTC 24 |
Sep 04 05:20:58 PM UTC 24 |
2768869848 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3307297047 |
|
|
Sep 04 05:15:29 PM UTC 24 |
Sep 04 05:21:04 PM UTC 24 |
6794922068 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1066902467 |
|
|
Sep 04 05:09:08 PM UTC 24 |
Sep 04 05:21:11 PM UTC 24 |
64862640487 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.3187971961 |
|
|
Sep 04 05:18:58 PM UTC 24 |
Sep 04 05:21:12 PM UTC 24 |
10461690733 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.464026697 |
|
|
Sep 04 05:21:08 PM UTC 24 |
Sep 04 05:21:22 PM UTC 24 |
220270574 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.969625553 |
|
|
Sep 04 05:05:15 PM UTC 24 |
Sep 04 05:21:28 PM UTC 24 |
22988088738 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1869654475 |
|
|
Sep 04 05:21:25 PM UTC 24 |
Sep 04 05:21:35 PM UTC 24 |
54382487 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.2567596510 |
|
|
Sep 04 05:15:33 PM UTC 24 |
Sep 04 05:21:48 PM UTC 24 |
4733496200 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.3385900691 |
|
|
Sep 04 05:21:43 PM UTC 24 |
Sep 04 05:21:57 PM UTC 24 |
279779325 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.303223934 |
|
|
Sep 04 05:21:44 PM UTC 24 |
Sep 04 05:22:02 PM UTC 24 |
187077273 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.2702544631 |
|
|
Sep 04 05:18:26 PM UTC 24 |
Sep 04 05:22:09 PM UTC 24 |
3121103732 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1743592102 |
|
|
Sep 04 05:09:20 PM UTC 24 |
Sep 04 05:22:10 PM UTC 24 |
48976050244 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.379590336 |
|
|
Sep 04 05:00:56 PM UTC 24 |
Sep 04 05:22:21 PM UTC 24 |
10811041305 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.3247080374 |
|
|
Sep 04 05:22:08 PM UTC 24 |
Sep 04 05:22:38 PM UTC 24 |
797015249 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2004051931 |
|
|
Sep 04 05:20:37 PM UTC 24 |
Sep 04 05:22:43 PM UTC 24 |
3381908763 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.942837246 |
|
|
Sep 04 05:22:29 PM UTC 24 |
Sep 04 05:22:45 PM UTC 24 |
229833222 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2843556203 |
|
|
Sep 04 05:21:27 PM UTC 24 |
Sep 04 05:22:50 PM UTC 24 |
8067331538 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.683007504 |
|
|
Sep 04 05:21:35 PM UTC 24 |
Sep 04 05:22:51 PM UTC 24 |
5087883773 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2305070500 |
|
|
Sep 04 05:22:40 PM UTC 24 |
Sep 04 05:22:51 PM UTC 24 |
43852775 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.1711953232 |
|
|
Sep 04 05:16:36 PM UTC 24 |
Sep 04 05:22:55 PM UTC 24 |
33831416990 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.1727789572 |
|
|
Sep 04 05:16:55 PM UTC 24 |
Sep 04 05:22:55 PM UTC 24 |
18753242081 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1167082974 |
|
|
Sep 04 05:03:16 PM UTC 24 |
Sep 04 05:23:00 PM UTC 24 |
9352642562 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.487401808 |
|
|
Sep 04 05:07:00 PM UTC 24 |
Sep 04 05:23:17 PM UTC 24 |
63896324490 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1462574568 |
|
|
Sep 04 05:15:28 PM UTC 24 |
Sep 04 05:23:20 PM UTC 24 |
2313483060 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.1885927858 |
|
|
Sep 04 05:22:24 PM UTC 24 |
Sep 04 05:23:21 PM UTC 24 |
2006586525 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3545394338 |
|
|
Sep 04 05:09:27 PM UTC 24 |
Sep 04 05:23:25 PM UTC 24 |
54228224254 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.3944259786 |
|
|
Sep 04 05:22:39 PM UTC 24 |
Sep 04 05:23:25 PM UTC 24 |
803647469 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3419246129 |
|
|
Sep 04 05:23:25 PM UTC 24 |
Sep 04 05:23:33 PM UTC 24 |
50961995 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.652010275 |
|
|
Sep 04 05:23:24 PM UTC 24 |
Sep 04 05:23:35 PM UTC 24 |
51952804 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.2489938868 |
|
|
Sep 04 05:08:11 PM UTC 24 |
Sep 04 05:23:56 PM UTC 24 |
10733770755 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.4134244641 |
|
|
Sep 04 05:20:57 PM UTC 24 |
Sep 04 05:23:58 PM UTC 24 |
2307552605 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.4195035732 |
|
|
Sep 04 05:13:11 PM UTC 24 |
Sep 04 05:24:05 PM UTC 24 |
6161881450 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1417602771 |
|
|
Sep 04 05:15:34 PM UTC 24 |
Sep 04 05:24:05 PM UTC 24 |
6103640744 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2028089672 |
|
|
Sep 04 05:11:23 PM UTC 24 |
Sep 04 05:24:09 PM UTC 24 |
41693769617 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1822513852 |
|
|
Sep 04 05:23:47 PM UTC 24 |
Sep 04 05:24:14 PM UTC 24 |
767860941 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.435032938 |
|
|
Sep 04 05:23:49 PM UTC 24 |
Sep 04 05:24:38 PM UTC 24 |
536330437 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.426383492 |
|
|
Sep 04 05:24:32 PM UTC 24 |
Sep 04 05:24:40 PM UTC 24 |
21078873 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.485306194 |
|
|
Sep 04 05:24:04 PM UTC 24 |
Sep 04 05:24:49 PM UTC 24 |
596237791 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2029711753 |
|
|
Sep 04 05:24:26 PM UTC 24 |
Sep 04 05:25:06 PM UTC 24 |
337147435 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3866965633 |
|
|
Sep 04 05:24:35 PM UTC 24 |
Sep 04 05:25:07 PM UTC 24 |
277300081 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.546547804 |
|
|
Sep 04 05:23:42 PM UTC 24 |
Sep 04 05:25:08 PM UTC 24 |
6049043878 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.1660120926 |
|
|
Sep 04 05:24:27 PM UTC 24 |
Sep 04 05:25:11 PM UTC 24 |
326507942 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2042415289 |
|
|
Sep 04 05:14:06 PM UTC 24 |
Sep 04 05:25:20 PM UTC 24 |
46345704042 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1721208585 |
|
|
Sep 04 05:24:03 PM UTC 24 |
Sep 04 05:25:25 PM UTC 24 |
1688386644 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.3861201753 |
|
|
Sep 04 05:23:29 PM UTC 24 |
Sep 04 05:25:33 PM UTC 24 |
9739824240 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.708839163 |
|
|
Sep 04 05:05:45 PM UTC 24 |
Sep 04 05:25:38 PM UTC 24 |
12624750104 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1740292506 |
|
|
Sep 04 05:25:37 PM UTC 24 |
Sep 04 05:25:46 PM UTC 24 |
43247289 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3511718533 |
|
|
Sep 04 05:25:39 PM UTC 24 |
Sep 04 05:25:53 PM UTC 24 |
199835976 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2812719409 |
|
|
Sep 04 05:18:01 PM UTC 24 |
Sep 04 05:25:55 PM UTC 24 |
4004728495 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2276607287 |
|
|
Sep 04 05:23:07 PM UTC 24 |
Sep 04 05:26:17 PM UTC 24 |
569032600 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3701311162 |
|
|
Sep 04 05:25:56 PM UTC 24 |
Sep 04 05:26:25 PM UTC 24 |
492552884 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.1013010008 |
|
|
Sep 04 05:26:02 PM UTC 24 |
Sep 04 05:26:32 PM UTC 24 |
204941501 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.432030935 |
|
|
Sep 04 05:21:05 PM UTC 24 |
Sep 04 05:26:37 PM UTC 24 |
4192314224 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1331732165 |
|
|
Sep 04 05:13:07 PM UTC 24 |
Sep 04 05:26:40 PM UTC 24 |
9267466006 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1824152977 |
|
|
Sep 04 05:25:08 PM UTC 24 |
Sep 04 05:26:49 PM UTC 24 |
450138380 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1559669574 |
|
|
Sep 04 05:25:50 PM UTC 24 |
Sep 04 05:27:09 PM UTC 24 |
4531943699 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1499848778 |
|
|
Sep 04 05:26:55 PM UTC 24 |
Sep 04 05:27:13 PM UTC 24 |
268107694 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3372033639 |
|
|
Sep 04 05:25:46 PM UTC 24 |
Sep 04 05:27:15 PM UTC 24 |
9995637887 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.2221590765 |
|
|
Sep 04 05:27:04 PM UTC 24 |
Sep 04 05:27:20 PM UTC 24 |
196877339 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1995857673 |
|
|
Sep 04 05:27:08 PM UTC 24 |
Sep 04 05:27:27 PM UTC 24 |
96876671 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2875179853 |
|
|
Sep 04 05:26:47 PM UTC 24 |
Sep 04 05:27:47 PM UTC 24 |
1781595426 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3370141790 |
|
|
Sep 04 05:27:19 PM UTC 24 |
Sep 04 05:27:47 PM UTC 24 |
11540663 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1110155096 |
|
|
Sep 04 05:10:38 PM UTC 24 |
Sep 04 05:27:55 PM UTC 24 |
10472898632 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.1038467289 |
|
|
Sep 04 05:26:24 PM UTC 24 |
Sep 04 05:27:55 PM UTC 24 |
1026338674 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3651960574 |
|
|
Sep 04 05:26:08 PM UTC 24 |
Sep 04 05:27:56 PM UTC 24 |
10265342881 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2972806862 |
|
|
Sep 04 05:25:36 PM UTC 24 |
Sep 04 05:28:16 PM UTC 24 |
3637366943 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.1564058472 |
|
|
Sep 04 05:21:48 PM UTC 24 |
Sep 04 05:28:18 PM UTC 24 |
37566433612 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2436971008 |
|
|
Sep 04 05:22:52 PM UTC 24 |
Sep 04 05:28:24 PM UTC 24 |
3651080215 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1261905371 |
|
|
Sep 04 05:28:14 PM UTC 24 |
Sep 04 05:28:24 PM UTC 24 |
54048252 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.705561810 |
|
|
Sep 04 05:28:18 PM UTC 24 |
Sep 04 05:28:26 PM UTC 24 |
132886552 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.937812707 |
|
|
Sep 04 05:21:03 PM UTC 24 |
Sep 04 05:28:33 PM UTC 24 |
6531798372 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_03/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.3073779806 |
|
|
Sep 04 05:24:42 PM UTC 24 |
Sep 04 05:28:45 PM UTC 24 |
5218189627 ps |