| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2699977328 |
|
|
Sep 25 02:58:46 AM UTC 24 |
Sep 25 04:20:22 AM UTC 24 |
14415337716 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1254820835 |
|
|
Sep 25 03:06:23 AM UTC 24 |
Sep 25 04:20:54 AM UTC 24 |
14855142693 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.646235735 |
|
|
Sep 25 04:15:47 AM UTC 24 |
Sep 25 04:21:59 AM UTC 24 |
3160196494 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2513165416 |
|
|
Sep 25 03:04:17 AM UTC 24 |
Sep 25 04:22:02 AM UTC 24 |
14606152338 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.817790232 |
|
|
Sep 25 03:02:17 AM UTC 24 |
Sep 25 04:22:21 AM UTC 24 |
15371746040 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2326667155 |
|
|
Sep 25 03:00:06 AM UTC 24 |
Sep 25 04:22:28 AM UTC 24 |
14861427308 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1218875151 |
|
|
Sep 25 03:06:36 AM UTC 24 |
Sep 25 04:22:38 AM UTC 24 |
14641663376 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3806926868 |
|
|
Sep 25 04:17:51 AM UTC 24 |
Sep 25 04:23:01 AM UTC 24 |
2970515519 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.917047111 |
|
|
Sep 25 04:18:58 AM UTC 24 |
Sep 25 04:23:34 AM UTC 24 |
3123017040 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.1657629254 |
|
|
Sep 25 04:18:42 AM UTC 24 |
Sep 25 04:23:41 AM UTC 24 |
3308915624 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.51603943 |
|
|
Sep 25 04:19:09 AM UTC 24 |
Sep 25 04:24:22 AM UTC 24 |
3402776680 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1941877891 |
|
|
Sep 25 03:00:42 AM UTC 24 |
Sep 25 04:25:04 AM UTC 24 |
14637032980 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1920550061 |
|
|
Sep 25 03:01:19 AM UTC 24 |
Sep 25 04:25:24 AM UTC 24 |
15573363620 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.4055238806 |
|
|
Sep 25 03:02:56 AM UTC 24 |
Sep 25 04:25:51 AM UTC 24 |
16144089848 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1643895890 |
|
|
Sep 25 03:00:06 AM UTC 24 |
Sep 25 04:25:55 AM UTC 24 |
15628644668 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1181646648 |
|
|
Sep 25 03:12:21 AM UTC 24 |
Sep 25 04:27:49 AM UTC 24 |
14093199830 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2545301857 |
|
|
Sep 25 04:23:36 AM UTC 24 |
Sep 25 04:28:22 AM UTC 24 |
2853597492 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.302023805 |
|
|
Sep 25 03:09:34 AM UTC 24 |
Sep 25 04:28:41 AM UTC 24 |
15257054101 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.2507168103 |
|
|
Sep 25 04:19:37 AM UTC 24 |
Sep 25 04:29:03 AM UTC 24 |
3985895610 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.761811638 |
|
|
Sep 25 04:21:01 AM UTC 24 |
Sep 25 04:30:13 AM UTC 24 |
3588451000 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.3541844388 |
|
|
Sep 25 04:16:21 AM UTC 24 |
Sep 25 04:30:37 AM UTC 24 |
4726120484 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.2720346422 |
|
|
Sep 25 04:19:32 AM UTC 24 |
Sep 25 04:31:00 AM UTC 24 |
4204727334 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.1630475199 |
|
|
Sep 25 04:23:19 AM UTC 24 |
Sep 25 04:31:10 AM UTC 24 |
3541284356 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2476247467 |
|
|
Sep 25 04:24:33 AM UTC 24 |
Sep 25 04:31:16 AM UTC 24 |
3370327239 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2869902529 |
|
|
Sep 25 04:17:18 AM UTC 24 |
Sep 25 04:31:38 AM UTC 24 |
6136067320 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1847113319 |
|
|
Sep 25 03:10:38 AM UTC 24 |
Sep 25 04:31:38 AM UTC 24 |
15161071193 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3312176032 |
|
|
Sep 25 03:23:58 AM UTC 24 |
Sep 25 04:31:48 AM UTC 24 |
20802996475 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.3958283690 |
|
|
Sep 25 04:17:51 AM UTC 24 |
Sep 25 04:32:50 AM UTC 24 |
5335903606 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.1485663430 |
|
|
Sep 25 04:19:33 AM UTC 24 |
Sep 25 04:33:55 AM UTC 24 |
4499958142 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.275317746 |
|
|
Sep 25 04:24:34 AM UTC 24 |
Sep 25 04:34:11 AM UTC 24 |
4646351904 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.223889382 |
|
|
Sep 25 04:23:18 AM UTC 24 |
Sep 25 04:34:15 AM UTC 24 |
3942786196 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.795209027 |
|
|
Sep 25 04:24:56 AM UTC 24 |
Sep 25 04:34:53 AM UTC 24 |
3851661733 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3900851628 |
|
|
Sep 25 04:26:35 AM UTC 24 |
Sep 25 04:34:54 AM UTC 24 |
4663726816 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2817341953 |
|
|
Sep 25 04:28:57 AM UTC 24 |
Sep 25 04:35:00 AM UTC 24 |
3495186060 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2312539229 |
|
|
Sep 25 04:31:11 AM UTC 24 |
Sep 25 04:35:19 AM UTC 24 |
3227609860 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.714472852 |
|
|
Sep 25 04:06:44 AM UTC 24 |
Sep 25 04:35:37 AM UTC 24 |
7758578800 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3291747647 |
|
|
Sep 25 04:23:18 AM UTC 24 |
Sep 25 04:35:57 AM UTC 24 |
4980850672 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.1118319214 |
|
|
Sep 25 03:20:13 AM UTC 24 |
Sep 25 04:36:09 AM UTC 24 |
15327803355 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3931887530 |
|
|
Sep 25 04:32:41 AM UTC 24 |
Sep 25 04:36:59 AM UTC 24 |
2700659619 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.201540177 |
|
|
Sep 25 04:32:44 AM UTC 24 |
Sep 25 04:37:23 AM UTC 24 |
3233156486 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.4095566945 |
|
|
Sep 25 04:24:29 AM UTC 24 |
Sep 25 04:37:37 AM UTC 24 |
6708863325 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3876082217 |
|
|
Sep 25 04:35:59 AM UTC 24 |
Sep 25 04:37:56 AM UTC 24 |
2600583273 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2469146511 |
|
|
Sep 25 04:35:59 AM UTC 24 |
Sep 25 04:38:18 AM UTC 24 |
3067863622 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2520992021 |
|
|
Sep 25 03:18:17 AM UTC 24 |
Sep 25 04:39:07 AM UTC 24 |
15896507312 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1039530279 |
|
|
Sep 25 04:32:39 AM UTC 24 |
Sep 25 04:39:11 AM UTC 24 |
2852904680 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1131149441 |
|
|
Sep 25 04:25:38 AM UTC 24 |
Sep 25 04:39:20 AM UTC 24 |
4106256976 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2205324321 |
|
|
Sep 25 04:23:11 AM UTC 24 |
Sep 25 04:39:34 AM UTC 24 |
5021599344 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1362137548 |
|
|
Sep 25 04:25:59 AM UTC 24 |
Sep 25 04:39:43 AM UTC 24 |
4670707831 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.4171878988 |
|
|
Sep 25 04:23:00 AM UTC 24 |
Sep 25 04:39:45 AM UTC 24 |
5011418100 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.205715166 |
|
|
Sep 25 03:17:50 AM UTC 24 |
Sep 25 04:39:59 AM UTC 24 |
15618169516 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4082902741 |
|
|
Sep 25 04:34:29 AM UTC 24 |
Sep 25 04:40:19 AM UTC 24 |
3453319831 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2513792715 |
|
|
Sep 25 04:21:30 AM UTC 24 |
Sep 25 04:40:38 AM UTC 24 |
8046009434 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2104423841 |
|
|
Sep 25 03:26:19 AM UTC 24 |
Sep 25 04:41:41 AM UTC 24 |
19291125669 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.560971015 |
|
|
Sep 25 04:36:39 AM UTC 24 |
Sep 25 04:41:50 AM UTC 24 |
3303781588 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.3492116689 |
|
|
Sep 25 04:36:44 AM UTC 24 |
Sep 25 04:43:11 AM UTC 24 |
2468754876 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.639834753 |
|
|
Sep 25 04:32:34 AM UTC 24 |
Sep 25 04:44:00 AM UTC 24 |
4022389368 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2181104302 |
|
|
Sep 25 04:38:31 AM UTC 24 |
Sep 25 04:44:23 AM UTC 24 |
4512433174 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.4021351646 |
|
|
Sep 25 04:33:26 AM UTC 24 |
Sep 25 04:44:40 AM UTC 24 |
7569808124 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.11879501 |
|
|
Sep 25 04:19:15 AM UTC 24 |
Sep 25 04:44:45 AM UTC 24 |
9335430360 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.3589669546 |
|
|
Sep 25 04:26:35 AM UTC 24 |
Sep 25 04:44:54 AM UTC 24 |
5763310940 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2969227893 |
|
|
Sep 25 03:01:55 AM UTC 24 |
Sep 25 04:45:31 AM UTC 24 |
18770739848 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1675911847 |
|
|
Sep 25 04:38:10 AM UTC 24 |
Sep 25 04:45:33 AM UTC 24 |
6344313656 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.2600108660 |
|
|
Sep 25 03:27:02 AM UTC 24 |
Sep 25 04:46:19 AM UTC 24 |
20420740671 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3463125372 |
|
|
Sep 25 03:17:50 AM UTC 24 |
Sep 25 04:46:50 AM UTC 24 |
15131840051 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1746038432 |
|
|
Sep 25 04:28:26 AM UTC 24 |
Sep 25 04:46:55 AM UTC 24 |
5646610648 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3622766419 |
|
|
Sep 25 04:42:27 AM UTC 24 |
Sep 25 04:47:12 AM UTC 24 |
2839957756 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3071184230 |
|
|
Sep 25 04:30:46 AM UTC 24 |
Sep 25 04:48:06 AM UTC 24 |
6168049265 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3581779797 |
|
|
Sep 25 02:02:10 AM UTC 24 |
Sep 25 04:49:12 AM UTC 24 |
32178912562 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.342539283 |
|
|
Sep 25 04:43:46 AM UTC 24 |
Sep 25 04:49:36 AM UTC 24 |
3222591992 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3999963444 |
|
|
Sep 25 04:42:28 AM UTC 24 |
Sep 25 04:50:01 AM UTC 24 |
4316490360 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.596367819 |
|
|
Sep 25 04:44:58 AM UTC 24 |
Sep 25 04:50:41 AM UTC 24 |
3555174262 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1042090360 |
|
|
Sep 25 04:37:56 AM UTC 24 |
Sep 25 04:51:07 AM UTC 24 |
5548909560 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.379890274 |
|
|
Sep 25 03:03:17 AM UTC 24 |
Sep 25 04:51:14 AM UTC 24 |
18456927169 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3738817609 |
|
|
Sep 25 04:32:36 AM UTC 24 |
Sep 25 04:51:29 AM UTC 24 |
6630549094 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4230847786 |
|
|
Sep 25 04:32:49 AM UTC 24 |
Sep 25 04:52:44 AM UTC 24 |
7235828060 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.2309584087 |
|
|
Sep 25 04:46:23 AM UTC 24 |
Sep 25 04:52:52 AM UTC 24 |
3810674836 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.251419845 |
|
|
Sep 25 04:41:13 AM UTC 24 |
Sep 25 04:52:57 AM UTC 24 |
7757567392 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2316542652 |
|
|
Sep 25 04:46:24 AM UTC 24 |
Sep 25 04:53:39 AM UTC 24 |
3844078910 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2357150967 |
|
|
Sep 25 04:40:57 AM UTC 24 |
Sep 25 04:54:23 AM UTC 24 |
7912985156 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3968281585 |
|
|
Sep 25 04:32:49 AM UTC 24 |
Sep 25 04:54:49 AM UTC 24 |
8155990542 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2897774860 |
|
|
Sep 25 04:45:37 AM UTC 24 |
Sep 25 04:55:25 AM UTC 24 |
6079687784 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3682178984 |
|
|
Sep 25 04:46:54 AM UTC 24 |
Sep 25 04:55:33 AM UTC 24 |
6164224376 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3181579176 |
|
|
Sep 25 04:41:18 AM UTC 24 |
Sep 25 04:55:44 AM UTC 24 |
7714874040 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.935479172 |
|
|
Sep 25 04:38:53 AM UTC 24 |
Sep 25 04:55:45 AM UTC 24 |
6505144216 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.3170372149 |
|
|
Sep 25 04:35:58 AM UTC 24 |
Sep 25 04:56:20 AM UTC 24 |
11942316389 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1315359109 |
|
|
Sep 25 04:53:41 AM UTC 24 |
Sep 25 04:58:07 AM UTC 24 |
2095012860 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1367442572 |
|
|
Sep 25 04:45:38 AM UTC 24 |
Sep 25 04:58:17 AM UTC 24 |
4667615068 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.3815965777 |
|
|
Sep 25 04:52:05 AM UTC 24 |
Sep 25 04:58:40 AM UTC 24 |
2957546188 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3883497256 |
|
|
Sep 25 04:48:43 AM UTC 24 |
Sep 25 04:58:59 AM UTC 24 |
17919575292 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.1205066730 |
|
|
Sep 25 04:53:40 AM UTC 24 |
Sep 25 04:59:18 AM UTC 24 |
3216768445 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4065745878 |
|
|
Sep 25 04:47:48 AM UTC 24 |
Sep 25 04:59:30 AM UTC 24 |
5083774840 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.740185804 |
|
|
Sep 25 04:54:16 AM UTC 24 |
Sep 25 05:00:05 AM UTC 24 |
3285490956 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2752383112 |
|
|
Sep 25 04:47:43 AM UTC 24 |
Sep 25 05:00:19 AM UTC 24 |
5417211220 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1354820531 |
|
|
Sep 25 05:00:41 AM UTC 24 |
Sep 25 05:11:29 AM UTC 24 |
3559590760 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3578412406 |
|
|
Sep 25 04:53:40 AM UTC 24 |
Sep 25 05:01:12 AM UTC 24 |
2959159637 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.3043223797 |
|
|
Sep 25 04:51:15 AM UTC 24 |
Sep 25 05:01:37 AM UTC 24 |
4035266648 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.929209916 |
|
|
Sep 25 04:54:57 AM UTC 24 |
Sep 25 05:02:05 AM UTC 24 |
5641468470 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.182507869 |
|
|
Sep 25 03:39:33 AM UTC 24 |
Sep 25 05:02:17 AM UTC 24 |
15161538700 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1379191720 |
|
|
Sep 25 04:56:40 AM UTC 24 |
Sep 25 05:02:37 AM UTC 24 |
3645049656 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.4236833099 |
|
|
Sep 25 04:58:54 AM UTC 24 |
Sep 25 05:02:45 AM UTC 24 |
2774669581 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.838491735 |
|
|
Sep 25 04:59:34 AM UTC 24 |
Sep 25 05:03:28 AM UTC 24 |
2576678342 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2131017298 |
|
|
Sep 25 04:40:44 AM UTC 24 |
Sep 25 05:03:40 AM UTC 24 |
14989745670 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3693522105 |
|
|
Sep 25 04:59:13 AM UTC 24 |
Sep 25 05:03:55 AM UTC 24 |
2793285450 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1543355075 |
|
|
Sep 25 04:55:25 AM UTC 24 |
Sep 25 05:04:15 AM UTC 24 |
4801081604 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.591608492 |
|
|
Sep 25 04:47:35 AM UTC 24 |
Sep 25 05:04:17 AM UTC 24 |
10400884568 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2181779819 |
|
|
Sep 25 04:40:24 AM UTC 24 |
Sep 25 05:05:54 AM UTC 24 |
12642422815 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.621242813 |
|
|
Sep 25 04:52:02 AM UTC 24 |
Sep 25 05:06:08 AM UTC 24 |
4859963220 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.2146053670 |
|
|
Sep 25 04:49:48 AM UTC 24 |
Sep 25 05:06:27 AM UTC 24 |
5913605704 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1416667642 |
|
|
Sep 25 03:39:38 AM UTC 24 |
Sep 25 05:07:13 AM UTC 24 |
15214799856 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1420528531 |
|
|
Sep 25 05:02:37 AM UTC 24 |
Sep 25 05:07:57 AM UTC 24 |
3051851152 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2763556686 |
|
|
Sep 25 04:40:56 AM UTC 24 |
Sep 25 05:08:31 AM UTC 24 |
12414434234 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4043692248 |
|
|
Sep 25 05:03:19 AM UTC 24 |
Sep 25 05:09:00 AM UTC 24 |
2966067860 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.4207290329 |
|
|
Sep 25 04:29:09 AM UTC 24 |
Sep 25 05:09:02 AM UTC 24 |
19747890755 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3071523323 |
|
|
Sep 25 03:42:41 AM UTC 24 |
Sep 25 05:09:07 AM UTC 24 |
15643534980 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.2790043254 |
|
|
Sep 25 05:04:30 AM UTC 24 |
Sep 25 05:09:32 AM UTC 24 |
2782514696 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3150591256 |
|
|
Sep 25 05:04:59 AM UTC 24 |
Sep 25 05:09:50 AM UTC 24 |
2236985194 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1318467154 |
|
|
Sep 25 05:05:00 AM UTC 24 |
Sep 25 05:10:03 AM UTC 24 |
2944708912 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.4275024538 |
|
|
Sep 25 04:52:00 AM UTC 24 |
Sep 25 05:10:11 AM UTC 24 |
5764803398 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.2448550466 |
|
|
Sep 25 03:35:53 AM UTC 24 |
Sep 25 05:10:27 AM UTC 24 |
61481594814 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3460901598 |
|
|
Sep 25 03:28:33 AM UTC 24 |
Sep 25 05:10:52 AM UTC 24 |
57095512895 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.186172126 |
|
|
Sep 25 05:00:07 AM UTC 24 |
Sep 25 05:11:12 AM UTC 24 |
3388925712 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3059266272 |
|
|
Sep 25 04:37:35 AM UTC 24 |
Sep 25 05:11:30 AM UTC 24 |
12237922600 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3177453731 |
|
|
Sep 25 05:02:52 AM UTC 24 |
Sep 25 05:11:41 AM UTC 24 |
3575294898 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3837435717 |
|
|
Sep 25 03:03:58 AM UTC 24 |
Sep 25 05:11:50 AM UTC 24 |
23368856961 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.1582003486 |
|
|
Sep 25 03:38:48 AM UTC 24 |
Sep 25 05:12:21 AM UTC 24 |
16809888230 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3093093945 |
|
|
Sep 25 05:01:48 AM UTC 24 |
Sep 25 05:12:48 AM UTC 24 |
7423267107 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.4244457333 |
|
|
Sep 25 05:06:41 AM UTC 24 |
Sep 25 05:13:02 AM UTC 24 |
2720972098 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.4026450882 |
|
|
Sep 25 05:10:46 AM UTC 24 |
Sep 25 05:15:22 AM UTC 24 |
3073744258 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.185380462 |
|
|
Sep 25 05:10:08 AM UTC 24 |
Sep 25 05:15:29 AM UTC 24 |
2885925420 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.3801504934 |
|
|
Sep 25 04:45:37 AM UTC 24 |
Sep 25 05:15:36 AM UTC 24 |
24228849992 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3894994630 |
|
|
Sep 25 05:10:31 AM UTC 24 |
Sep 25 05:16:09 AM UTC 24 |
3103953726 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3724076273 |
|
|
Sep 25 05:10:43 AM UTC 24 |
Sep 25 05:16:21 AM UTC 24 |
2544063078 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.3549349482 |
|
|
Sep 25 05:10:10 AM UTC 24 |
Sep 25 05:16:26 AM UTC 24 |
3096962142 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.2242398231 |
|
|
Sep 25 05:00:03 AM UTC 24 |
Sep 25 05:18:10 AM UTC 24 |
4463222842 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.610871019 |
|
|
Sep 25 05:12:54 AM UTC 24 |
Sep 25 05:18:12 AM UTC 24 |
3122608824 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.681940232 |
|
|
Sep 25 03:03:47 AM UTC 24 |
Sep 25 05:19:04 AM UTC 24 |
23102451608 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3016961633 |
|
|
Sep 25 03:03:26 AM UTC 24 |
Sep 25 05:19:09 AM UTC 24 |
23452012512 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1152850086 |
|
|
Sep 25 04:21:01 AM UTC 24 |
Sep 25 05:19:56 AM UTC 24 |
13600733002 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4226440803 |
|
|
Sep 25 03:04:17 AM UTC 24 |
Sep 25 05:20:23 AM UTC 24 |
23283144440 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3969107497 |
|
|
Sep 25 05:04:16 AM UTC 24 |
Sep 25 05:20:28 AM UTC 24 |
6018185739 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1930170545 |
|
|
Sep 25 03:02:10 AM UTC 24 |
Sep 25 05:20:44 AM UTC 24 |
24459484116 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3070313884 |
|
|
Sep 25 05:11:01 AM UTC 24 |
Sep 25 05:21:12 AM UTC 24 |
9140286468 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.920991750 |
|
|
Sep 25 05:13:24 AM UTC 24 |
Sep 25 05:21:42 AM UTC 24 |
4831547560 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2364522230 |
|
|
Sep 25 05:11:22 AM UTC 24 |
Sep 25 05:22:04 AM UTC 24 |
5472499992 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.1841950527 |
|
|
Sep 25 05:17:00 AM UTC 24 |
Sep 25 05:22:12 AM UTC 24 |
3347639564 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1673118392 |
|
|
Sep 25 03:03:53 AM UTC 24 |
Sep 25 05:22:27 AM UTC 24 |
23365265685 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.961370059 |
|
|
Sep 25 05:12:36 AM UTC 24 |
Sep 25 05:22:27 AM UTC 24 |
4602631078 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.606116541 |
|
|
Sep 25 05:11:48 AM UTC 24 |
Sep 25 05:23:42 AM UTC 24 |
5663450184 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.4151542693 |
|
|
Sep 25 05:12:35 AM UTC 24 |
Sep 25 05:23:52 AM UTC 24 |
6965754946 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4074225680 |
|
|
Sep 25 04:56:54 AM UTC 24 |
Sep 25 05:23:53 AM UTC 24 |
7677256674 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2463453067 |
|
|
Sep 25 04:36:15 AM UTC 24 |
Sep 25 05:24:18 AM UTC 24 |
30777523291 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2601582191 |
|
|
Sep 25 05:17:07 AM UTC 24 |
Sep 25 05:24:35 AM UTC 24 |
3749753006 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.3590658668 |
|
|
Sep 25 05:16:19 AM UTC 24 |
Sep 25 05:24:37 AM UTC 24 |
3933339224 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.2277786503 |
|
|
Sep 25 04:56:37 AM UTC 24 |
Sep 25 05:25:17 AM UTC 24 |
7730093676 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.731503096 |
|
|
Sep 25 03:02:19 AM UTC 24 |
Sep 25 05:25:24 AM UTC 24 |
24298951748 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.118190560 |
|
|
Sep 25 05:08:34 AM UTC 24 |
Sep 25 05:25:38 AM UTC 24 |
6274023328 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.843649977 |
|
|
Sep 25 05:18:56 AM UTC 24 |
Sep 25 05:25:51 AM UTC 24 |
4130468220 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3804963213 |
|
|
Sep 25 05:12:37 AM UTC 24 |
Sep 25 05:26:27 AM UTC 24 |
7591273500 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1522530208 |
|
|
Sep 25 05:19:49 AM UTC 24 |
Sep 25 05:26:58 AM UTC 24 |
4403589476 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.3975482252 |
|
|
Sep 25 05:04:13 AM UTC 24 |
Sep 25 05:27:37 AM UTC 24 |
7134696424 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1198027651 |
|
|
Sep 25 04:56:36 AM UTC 24 |
Sep 25 05:27:38 AM UTC 24 |
13263081560 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2905640626 |
|
|
Sep 25 05:23:10 AM UTC 24 |
Sep 25 05:28:07 AM UTC 24 |
3051312314 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.2063916476 |
|
|
Sep 25 05:03:22 AM UTC 24 |
Sep 25 05:28:31 AM UTC 24 |
6159111332 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1215305011 |
|
|
Sep 25 05:12:32 AM UTC 24 |
Sep 25 05:28:14 AM UTC 24 |
7165284640 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3634899293 |
|
|
Sep 25 05:19:49 AM UTC 24 |
Sep 25 05:28:47 AM UTC 24 |
7395986623 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2655122713 |
|
|
Sep 25 04:58:53 AM UTC 24 |
Sep 25 05:28:55 AM UTC 24 |
8040332898 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3986395061 |
|
|
Sep 25 03:02:48 AM UTC 24 |
Sep 25 05:29:10 AM UTC 24 |
23902170120 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.910882144 |
|
|
Sep 25 05:18:56 AM UTC 24 |
Sep 25 05:29:13 AM UTC 24 |
5652042232 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.2328229543 |
|
|
Sep 25 05:22:46 AM UTC 24 |
Sep 25 05:29:55 AM UTC 24 |
3728322976 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1393152235 |
|
|
Sep 25 05:22:46 AM UTC 24 |
Sep 25 05:30:05 AM UTC 24 |
2987906088 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2706406097 |
|
|
Sep 25 05:21:16 AM UTC 24 |
Sep 25 05:30:54 AM UTC 24 |
4154058580 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2260170795 |
|
|
Sep 25 05:21:19 AM UTC 24 |
Sep 25 05:31:30 AM UTC 24 |
3986968536 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1116979277 |
|
|
Sep 25 05:16:23 AM UTC 24 |
Sep 25 05:31:42 AM UTC 24 |
4535934402 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1600189158 |
|
|
Sep 25 05:20:30 AM UTC 24 |
Sep 25 05:32:01 AM UTC 24 |
4662833860 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1496833871 |
|
|
Sep 25 05:21:20 AM UTC 24 |
Sep 25 05:32:01 AM UTC 24 |
4143265544 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2936950509 |
|
|
Sep 25 04:40:24 AM UTC 24 |
Sep 25 05:32:11 AM UTC 24 |
25749044133 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2120323894 |
|
|
Sep 25 05:25:21 AM UTC 24 |
Sep 25 05:32:11 AM UTC 24 |
4551811098 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.2374730271 |
|
|
Sep 25 05:28:33 AM UTC 24 |
Sep 25 05:32:31 AM UTC 24 |
3068730096 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3751224747 |
|
|
Sep 25 05:21:45 AM UTC 24 |
Sep 25 05:32:55 AM UTC 24 |
4568715010 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1620078587 |
|
|
Sep 25 05:22:17 AM UTC 24 |
Sep 25 05:33:00 AM UTC 24 |
5008072212 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.3013365262 |
|
|
Sep 25 05:27:03 AM UTC 24 |
Sep 25 05:33:01 AM UTC 24 |
4445846228 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1946055433 |
|
|
Sep 25 05:26:30 AM UTC 24 |
Sep 25 05:33:05 AM UTC 24 |
6066250168 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3290040497 |
|
|
Sep 25 05:29:14 AM UTC 24 |
Sep 25 05:33:15 AM UTC 24 |
3704881902 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.1690204717 |
|
|
Sep 25 05:24:53 AM UTC 24 |
Sep 25 05:33:17 AM UTC 24 |
3850981350 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3995524234 |
|
|
Sep 25 05:23:11 AM UTC 24 |
Sep 25 05:33:32 AM UTC 24 |
4577830724 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2629940593 |
|
|
Sep 25 05:29:51 AM UTC 24 |
Sep 25 05:33:44 AM UTC 24 |
2863988403 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3071716874 |
|
|
Sep 25 05:06:41 AM UTC 24 |
Sep 25 05:34:21 AM UTC 24 |
7465024828 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4029272871 |
|
|
Sep 25 05:25:21 AM UTC 24 |
Sep 25 05:34:23 AM UTC 24 |
7862590380 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.193564380 |
|
|
Sep 25 05:29:27 AM UTC 24 |
Sep 25 05:34:58 AM UTC 24 |
3190557640 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1930487163 |
|
|
Sep 25 05:31:32 AM UTC 24 |
Sep 25 05:35:12 AM UTC 24 |
2601364183 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3594383750 |
|
|
Sep 25 05:16:18 AM UTC 24 |
Sep 25 05:36:04 AM UTC 24 |
6215495926 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3513121965 |
|
|
Sep 25 05:27:29 AM UTC 24 |
Sep 25 05:36:31 AM UTC 24 |
4983282488 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3376975237 |
|
|
Sep 25 05:28:22 AM UTC 24 |
Sep 25 05:36:36 AM UTC 24 |
4625579171 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2343754983 |
|
|
Sep 25 05:26:31 AM UTC 24 |
Sep 25 05:36:58 AM UTC 24 |
6125285050 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4127972890 |
|
|
Sep 25 05:33:20 AM UTC 24 |
Sep 25 05:37:05 AM UTC 24 |
3023489796 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.182299766 |
|
|
Sep 25 05:32:58 AM UTC 24 |
Sep 25 05:37:24 AM UTC 24 |
3511960191 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2862167410 |
|
|
Sep 25 05:33:21 AM UTC 24 |
Sep 25 05:37:34 AM UTC 24 |
2514008787 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.2702419907 |
|
|
Sep 25 05:30:42 AM UTC 24 |
Sep 25 05:37:48 AM UTC 24 |
3553434418 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3575696894 |
|
|
Sep 25 05:28:22 AM UTC 24 |
Sep 25 05:38:24 AM UTC 24 |
6339578708 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3795179222 |
|
|
Sep 25 05:28:58 AM UTC 24 |
Sep 25 05:39:33 AM UTC 24 |
6643571378 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.583191828 |
|
|
Sep 25 05:17:07 AM UTC 24 |
Sep 25 05:40:14 AM UTC 24 |
10241082746 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.295211847 |
|
|
Sep 25 05:35:56 AM UTC 24 |
Sep 25 05:40:34 AM UTC 24 |
2970441644 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.306157030 |
|
|
Sep 25 05:38:42 AM UTC 24 |
Sep 25 05:40:52 AM UTC 24 |
2503997272 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.1111127022 |
|
|
Sep 25 05:24:29 AM UTC 24 |
Sep 25 05:40:54 AM UTC 24 |
8888245928 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1670897433 |
|
|
Sep 25 05:00:54 AM UTC 24 |
Sep 25 05:41:47 AM UTC 24 |
9383338820 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.2332369722 |
|
|
Sep 25 05:07:03 AM UTC 24 |
Sep 25 05:41:50 AM UTC 24 |
10010915332 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2361315764 |
|
|
Sep 25 05:39:10 AM UTC 24 |
Sep 25 05:42:58 AM UTC 24 |
4003910725 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3002988577 |
|
|
Sep 25 05:31:32 AM UTC 24 |
Sep 25 05:43:31 AM UTC 24 |
5108305597 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.938159016 |
|
|
Sep 25 05:33:52 AM UTC 24 |
Sep 25 05:43:41 AM UTC 24 |
5372853800 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.2201590293 |
|
|
Sep 25 05:30:42 AM UTC 24 |
Sep 25 05:44:21 AM UTC 24 |
5702530234 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.702729383 |
|
|
Sep 25 05:35:15 AM UTC 24 |
Sep 25 05:44:27 AM UTC 24 |
11409634300 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.3108305563 |
|
|
Sep 25 05:10:05 AM UTC 24 |
Sep 25 05:45:14 AM UTC 24 |
9398829464 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.311395623 |
|
|
Sep 25 05:41:08 AM UTC 24 |
Sep 25 05:45:41 AM UTC 24 |
2379770876 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2029902208 |
|
|
Sep 25 05:41:36 AM UTC 24 |
Sep 25 05:46:02 AM UTC 24 |
2789419742 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.812332363 |
|
|
Sep 25 05:41:37 AM UTC 24 |
Sep 25 05:46:09 AM UTC 24 |
2849710376 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2579523599 |
|
|
Sep 25 05:35:17 AM UTC 24 |
Sep 25 05:46:39 AM UTC 24 |
5019533960 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2672832907 |
|
|
Sep 25 05:40:47 AM UTC 24 |
Sep 25 05:46:52 AM UTC 24 |
2699556880 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2096645281 |
|
|
Sep 25 05:42:30 AM UTC 24 |
Sep 25 05:47:17 AM UTC 24 |
2906052685 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1912086172 |
|
|
Sep 25 05:07:47 AM UTC 24 |
Sep 25 05:47:43 AM UTC 24 |
11816285884 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.18541554 |
|
|
Sep 25 05:09:06 AM UTC 24 |
Sep 25 05:49:11 AM UTC 24 |
10470654568 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1615648612 |
|
|
Sep 25 05:40:09 AM UTC 24 |
Sep 25 05:49:44 AM UTC 24 |
4944989950 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.4225862041 |
|
|
Sep 25 05:45:06 AM UTC 24 |
Sep 25 05:49:45 AM UTC 24 |
2732451988 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3345356920 |
|
|
Sep 25 05:46:15 AM UTC 24 |
Sep 25 05:49:47 AM UTC 24 |
2735376664 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.3522051966 |
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Sep 25 05:43:32 AM UTC 24 |
Sep 25 05:50:24 AM UTC 24 |
3378834090 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.3429928462 |
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|
Sep 25 05:45:06 AM UTC 24 |
Sep 25 05:50:40 AM UTC 24 |
6148129400 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.2067893853 |
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Sep 25 05:28:41 AM UTC 24 |
Sep 25 05:50:53 AM UTC 24 |
13070162628 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.2080845186 |
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Sep 25 05:44:17 AM UTC 24 |
Sep 25 05:51:00 AM UTC 24 |
3544850328 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.3837723237 |
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Sep 25 05:48:08 AM UTC 24 |
Sep 25 05:51:08 AM UTC 24 |
2123433170 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2155537930 |
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Sep 25 04:46:28 AM UTC 24 |
Sep 25 05:51:31 AM UTC 24 |
20882863650 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3163749806 |
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Sep 25 05:32:14 AM UTC 24 |
Sep 25 05:51:38 AM UTC 24 |
7607116810 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.521855713 |
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Sep 25 05:46:46 AM UTC 24 |
Sep 25 05:51:41 AM UTC 24 |
2848277250 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.1252453192 |
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Sep 25 05:47:12 AM UTC 24 |
Sep 25 05:52:03 AM UTC 24 |
3098241572 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.2191159303 |
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Sep 25 05:46:46 AM UTC 24 |
Sep 25 05:52:04 AM UTC 24 |
3085990472 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.3247764822 |
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Sep 25 05:42:30 AM UTC 24 |
Sep 25 05:52:09 AM UTC 24 |
4360651280 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2411785749 |
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Sep 25 03:28:19 AM UTC 24 |
Sep 25 05:52:11 AM UTC 24 |
63457951228 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1172121001 |
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Sep 25 05:45:48 AM UTC 24 |
Sep 25 05:52:19 AM UTC 24 |
5230635000 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.1371954695 |
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Sep 25 05:47:51 AM UTC 24 |
Sep 25 05:52:20 AM UTC 24 |
2981936240 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2888054789 |
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Sep 25 05:26:28 AM UTC 24 |
Sep 25 05:52:23 AM UTC 24 |
22419368720 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.842607900 |
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Sep 25 05:47:25 AM UTC 24 |
Sep 25 05:52:28 AM UTC 24 |
3241152168 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3699894394 |
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Sep 25 05:49:45 AM UTC 24 |
Sep 25 05:53:01 AM UTC 24 |
2725984500 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.298922778 |
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Sep 25 05:50:41 AM UTC 24 |
Sep 25 05:54:20 AM UTC 24 |
2909445480 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.551610109 |
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Sep 25 05:13:38 AM UTC 24 |
Sep 25 05:55:18 AM UTC 24 |
29454988958 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.3440337005 |
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Sep 25 05:51:50 AM UTC 24 |
Sep 25 05:55:39 AM UTC 24 |
3236072300 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.2479031861 |
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Sep 25 05:50:42 AM UTC 24 |
Sep 25 05:56:05 AM UTC 24 |
3349838882 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2729696478 |
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Sep 25 05:35:31 AM UTC 24 |
Sep 25 05:56:17 AM UTC 24 |
5642032128 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2883003305 |
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Sep 25 05:53:04 AM UTC 24 |
Sep 25 05:56:50 AM UTC 24 |
2233864890 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.1441476537 |
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Sep 25 05:51:50 AM UTC 24 |
Sep 25 05:58:06 AM UTC 24 |
3781261448 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4198707868 |
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Sep 25 05:51:49 AM UTC 24 |
Sep 25 05:58:17 AM UTC 24 |
3611469441 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.2820881283 |
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Sep 25 05:36:03 AM UTC 24 |
Sep 25 05:59:35 AM UTC 24 |
5871658630 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.2219967164 |
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Sep 25 05:24:02 AM UTC 24 |
Sep 25 05:59:43 AM UTC 24 |
17160404171 ps |