| T1412 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.2314020521 |
|
|
Sep 24 11:42:40 PM UTC 24 |
Sep 24 11:43:11 PM UTC 24 |
537997844 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1217948997 |
|
|
Sep 24 11:40:52 PM UTC 24 |
Sep 24 11:43:17 PM UTC 24 |
539897111 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1418727260 |
|
|
Sep 24 11:43:11 PM UTC 24 |
Sep 24 11:43:20 PM UTC 24 |
36658684 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.225372568 |
|
|
Sep 24 11:40:51 PM UTC 24 |
Sep 24 11:43:26 PM UTC 24 |
1894650270 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.335621255 |
|
|
Sep 24 11:43:01 PM UTC 24 |
Sep 24 11:43:31 PM UTC 24 |
143212306 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1575166910 |
|
|
Sep 24 11:42:41 PM UTC 24 |
Sep 24 11:43:39 PM UTC 24 |
1426417178 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.3069828555 |
|
|
Sep 24 11:41:55 PM UTC 24 |
Sep 24 11:43:43 PM UTC 24 |
10618858274 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.876108358 |
|
|
Sep 24 11:42:22 PM UTC 24 |
Sep 24 11:43:43 PM UTC 24 |
1190402836 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1884851359 |
|
|
Sep 24 11:41:58 PM UTC 24 |
Sep 24 11:44:00 PM UTC 24 |
5414311425 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3412552251 |
|
|
Sep 24 11:44:05 PM UTC 24 |
Sep 24 11:44:16 PM UTC 24 |
38577174 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3519231519 |
|
|
Sep 24 11:44:05 PM UTC 24 |
Sep 24 11:44:16 PM UTC 24 |
46006532 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3031560647 |
|
|
Sep 24 11:44:38 PM UTC 24 |
Sep 24 11:44:50 PM UTC 24 |
107069635 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.4067884279 |
|
|
Sep 24 11:44:40 PM UTC 24 |
Sep 24 11:45:14 PM UTC 24 |
348112177 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.2040285569 |
|
|
Sep 24 11:41:37 PM UTC 24 |
Sep 24 11:45:48 PM UTC 24 |
3055246232 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1185694270 |
|
|
Sep 24 11:38:14 PM UTC 24 |
Sep 24 11:45:52 PM UTC 24 |
5867444606 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2518408509 |
|
|
Sep 24 11:27:33 PM UTC 24 |
Sep 24 11:45:53 PM UTC 24 |
56747147269 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.926200496 |
|
|
Sep 24 11:28:40 PM UTC 24 |
Sep 24 11:45:56 PM UTC 24 |
6415118048 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.2630870701 |
|
|
Sep 24 11:34:13 PM UTC 24 |
Sep 24 11:45:59 PM UTC 24 |
61969129683 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2568765052 |
|
|
Sep 24 11:38:12 PM UTC 24 |
Sep 24 11:46:02 PM UTC 24 |
3872629867 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.2920410307 |
|
|
Sep 24 11:45:13 PM UTC 24 |
Sep 24 11:46:06 PM UTC 24 |
3456913786 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1191531788 |
|
|
Sep 24 11:38:09 PM UTC 24 |
Sep 24 11:46:08 PM UTC 24 |
8565866076 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1746191025 |
|
|
Sep 24 11:43:32 PM UTC 24 |
Sep 24 11:46:13 PM UTC 24 |
625342608 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.542818139 |
|
|
Sep 24 11:28:46 PM UTC 24 |
Sep 24 11:46:14 PM UTC 24 |
10516206435 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.4056629184 |
|
|
Sep 24 11:43:24 PM UTC 24 |
Sep 24 11:46:29 PM UTC 24 |
4294799127 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.284765222 |
|
|
Sep 24 11:46:11 PM UTC 24 |
Sep 24 11:46:32 PM UTC 24 |
284544688 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.163544043 |
|
|
Sep 24 11:44:23 PM UTC 24 |
Sep 24 11:46:37 PM UTC 24 |
9335648822 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1629466217 |
|
|
Sep 24 11:44:34 PM UTC 24 |
Sep 24 11:46:37 PM UTC 24 |
4792818614 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.367791950 |
|
|
Sep 24 11:46:15 PM UTC 24 |
Sep 24 11:46:42 PM UTC 24 |
321601335 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.753561847 |
|
|
Sep 24 11:46:20 PM UTC 24 |
Sep 24 11:47:02 PM UTC 24 |
613037984 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3936894789 |
|
|
Sep 24 11:46:23 PM UTC 24 |
Sep 24 11:47:04 PM UTC 24 |
803075168 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.2533562506 |
|
|
Sep 24 11:46:15 PM UTC 24 |
Sep 24 11:47:07 PM UTC 24 |
1012865069 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3558353907 |
|
|
Sep 24 11:47:03 PM UTC 24 |
Sep 24 11:47:14 PM UTC 24 |
44627214 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.532537776 |
|
|
Sep 24 11:47:00 PM UTC 24 |
Sep 24 11:47:17 PM UTC 24 |
272836001 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3958404004 |
|
|
Sep 24 11:47:34 PM UTC 24 |
Sep 24 11:48:08 PM UTC 24 |
202154084 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3913857694 |
|
|
Sep 24 11:37:10 PM UTC 24 |
Sep 24 11:48:25 PM UTC 24 |
48934673309 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3038972180 |
|
|
Sep 24 11:35:18 PM UTC 24 |
Sep 24 11:48:35 PM UTC 24 |
13523226614 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1232963768 |
|
|
Sep 24 11:47:25 PM UTC 24 |
Sep 24 11:48:44 PM UTC 24 |
3793811286 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3174984376 |
|
|
Sep 24 11:44:05 PM UTC 24 |
Sep 24 11:48:50 PM UTC 24 |
3272003360 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3455010078 |
|
|
Sep 24 11:43:42 PM UTC 24 |
Sep 24 11:48:51 PM UTC 24 |
3919665986 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.3202602356 |
|
|
Sep 24 11:47:28 PM UTC 24 |
Sep 24 11:49:12 PM UTC 24 |
2096517599 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.2086761473 |
|
|
Sep 24 11:47:25 PM UTC 24 |
Sep 24 11:49:12 PM UTC 24 |
7931080753 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1658606763 |
|
|
Sep 24 11:49:12 PM UTC 24 |
Sep 24 11:49:24 PM UTC 24 |
35068246 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.2449613859 |
|
|
Sep 24 11:49:06 PM UTC 24 |
Sep 24 11:49:31 PM UTC 24 |
165450706 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2862117053 |
|
|
Sep 24 11:49:14 PM UTC 24 |
Sep 24 11:49:40 PM UTC 24 |
121607009 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4270507977 |
|
|
Sep 24 11:40:50 PM UTC 24 |
Sep 24 11:49:42 PM UTC 24 |
2841680084 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3348567839 |
|
|
Sep 24 11:39:27 PM UTC 24 |
Sep 24 11:50:07 PM UTC 24 |
56944475564 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.814134615 |
|
|
Sep 24 11:35:33 PM UTC 24 |
Sep 24 11:50:07 PM UTC 24 |
5249183512 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.2029004760 |
|
|
Sep 24 11:48:30 PM UTC 24 |
Sep 24 11:50:08 PM UTC 24 |
1871550624 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.2823210820 |
|
|
Sep 24 11:39:52 PM UTC 24 |
Sep 24 11:50:19 PM UTC 24 |
35436544949 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.2204226353 |
|
|
Sep 24 11:48:57 PM UTC 24 |
Sep 24 11:50:25 PM UTC 24 |
1892842779 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.673488528 |
|
|
Sep 24 11:43:38 PM UTC 24 |
Sep 24 11:50:30 PM UTC 24 |
8186198795 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.1067333076 |
|
|
Sep 24 11:50:29 PM UTC 24 |
Sep 24 11:50:40 PM UTC 24 |
50473659 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1299451011 |
|
|
Sep 24 11:50:41 PM UTC 24 |
Sep 24 11:50:51 PM UTC 24 |
35176226 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3758730649 |
|
|
Sep 24 11:49:34 PM UTC 24 |
Sep 24 11:51:16 PM UTC 24 |
727004194 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1791652703 |
|
|
Sep 24 11:49:54 PM UTC 24 |
Sep 24 11:51:17 PM UTC 24 |
212964218 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2146421336 |
|
|
Sep 24 11:46:24 PM UTC 24 |
Sep 24 11:51:22 PM UTC 24 |
6467048963 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3173122529 |
|
|
Sep 24 11:51:02 PM UTC 24 |
Sep 24 11:51:41 PM UTC 24 |
1020404098 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.786539783 |
|
|
Sep 24 11:33:43 PM UTC 24 |
Sep 24 11:51:51 PM UTC 24 |
9642317752 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1761094345 |
|
|
Sep 24 11:51:12 PM UTC 24 |
Sep 24 11:52:08 PM UTC 24 |
394708224 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2577925854 |
|
|
Sep 24 11:52:13 PM UTC 24 |
Sep 24 11:52:25 PM UTC 24 |
46330454 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3257333446 |
|
|
Sep 24 11:20:02 PM UTC 24 |
Sep 24 11:52:30 PM UTC 24 |
15836054125 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1184405651 |
|
|
Sep 24 11:51:44 PM UTC 24 |
Sep 24 11:52:38 PM UTC 24 |
1106524963 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.2545300629 |
|
|
Sep 24 11:50:45 PM UTC 24 |
Sep 24 11:52:39 PM UTC 24 |
8625320734 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1933823591 |
|
|
Sep 24 11:46:28 PM UTC 24 |
Sep 24 11:52:42 PM UTC 24 |
8447588230 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3978347922 |
|
|
Sep 24 11:46:35 PM UTC 24 |
Sep 24 11:52:48 PM UTC 24 |
4497363763 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.4106033037 |
|
|
Sep 24 11:41:19 PM UTC 24 |
Sep 24 11:52:50 PM UTC 24 |
5625615373 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.469037432 |
|
|
Sep 24 11:49:45 PM UTC 24 |
Sep 24 11:52:50 PM UTC 24 |
1799239489 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2423513481 |
|
|
Sep 24 11:50:52 PM UTC 24 |
Sep 24 11:52:51 PM UTC 24 |
5243010163 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1258818326 |
|
|
Sep 24 11:52:51 PM UTC 24 |
Sep 24 11:53:00 PM UTC 24 |
21190625 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3086478353 |
|
|
Sep 24 11:43:53 PM UTC 24 |
Sep 24 11:53:17 PM UTC 24 |
5514791128 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.403994678 |
|
|
Sep 24 11:52:31 PM UTC 24 |
Sep 24 11:53:18 PM UTC 24 |
1277446167 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3154199184 |
|
|
Sep 24 11:18:28 PM UTC 24 |
Sep 24 11:53:25 PM UTC 24 |
128766385141 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.784450694 |
|
|
Sep 24 11:52:48 PM UTC 24 |
Sep 24 11:53:26 PM UTC 24 |
181204036 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3287696977 |
|
|
Sep 24 11:53:22 PM UTC 24 |
Sep 24 11:53:36 PM UTC 24 |
199496475 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.760836750 |
|
|
Sep 24 11:46:58 PM UTC 24 |
Sep 24 11:53:43 PM UTC 24 |
3575211968 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3622767629 |
|
|
Sep 24 11:53:38 PM UTC 24 |
Sep 24 11:53:50 PM UTC 24 |
45186252 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1855896316 |
|
|
Sep 24 11:25:00 PM UTC 24 |
Sep 24 11:53:56 PM UTC 24 |
107288589689 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1389038224 |
|
|
Sep 24 11:16:57 PM UTC 24 |
Sep 24 11:53:56 PM UTC 24 |
15481758506 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1461936210 |
|
|
Sep 24 11:42:12 PM UTC 24 |
Sep 24 11:53:58 PM UTC 24 |
47421540042 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1534448049 |
|
|
Sep 24 11:53:48 PM UTC 24 |
Sep 24 11:54:02 PM UTC 24 |
60572426 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.3533632060 |
|
|
Sep 24 11:42:10 PM UTC 24 |
Sep 24 11:54:09 PM UTC 24 |
66364201190 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2539448417 |
|
|
Sep 24 11:53:56 PM UTC 24 |
Sep 24 11:54:27 PM UTC 24 |
200184322 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3394567916 |
|
|
Sep 24 11:53:02 PM UTC 24 |
Sep 24 11:54:31 PM UTC 24 |
145991333 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2837979415 |
|
|
Sep 24 11:54:22 PM UTC 24 |
Sep 24 11:54:34 PM UTC 24 |
119035263 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.3070191607 |
|
|
Sep 24 11:54:16 PM UTC 24 |
Sep 24 11:54:36 PM UTC 24 |
121605987 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.4223446851 |
|
|
Sep 24 11:54:29 PM UTC 24 |
Sep 24 11:54:53 PM UTC 24 |
104168474 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1184366318 |
|
|
Sep 24 11:54:49 PM UTC 24 |
Sep 24 11:55:02 PM UTC 24 |
138676178 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.259837639 |
|
|
Sep 24 11:54:19 PM UTC 24 |
Sep 24 11:55:07 PM UTC 24 |
1319981590 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1864312456 |
|
|
Sep 24 11:37:02 PM UTC 24 |
Sep 24 11:55:12 PM UTC 24 |
60936555987 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3819502191 |
|
|
Sep 24 11:46:24 PM UTC 24 |
Sep 24 11:55:19 PM UTC 24 |
4461221312 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.361033598 |
|
|
Sep 24 11:53:04 PM UTC 24 |
Sep 24 11:55:24 PM UTC 24 |
1341176887 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.211723894 |
|
|
Sep 24 11:50:29 PM UTC 24 |
Sep 24 11:55:33 PM UTC 24 |
3470564488 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4246490398 |
|
|
Sep 24 11:38:08 PM UTC 24 |
Sep 24 11:55:35 PM UTC 24 |
14617957212 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3985739122 |
|
|
Sep 24 11:53:40 PM UTC 24 |
Sep 24 11:55:35 PM UTC 24 |
10009348779 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3636447873 |
|
|
Sep 24 11:54:56 PM UTC 24 |
Sep 24 11:55:44 PM UTC 24 |
9850723 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2086101844 |
|
|
Sep 24 11:35:40 PM UTC 24 |
Sep 24 11:55:49 PM UTC 24 |
11654421160 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1376020706 |
|
|
Sep 24 11:53:47 PM UTC 24 |
Sep 24 11:55:56 PM UTC 24 |
6607832026 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2982668766 |
|
|
Sep 24 11:55:45 PM UTC 24 |
Sep 24 11:56:00 PM UTC 24 |
213152646 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2179667210 |
|
|
Sep 24 11:55:54 PM UTC 24 |
Sep 24 11:56:04 PM UTC 24 |
47008466 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1701412839 |
|
|
Sep 24 11:46:51 PM UTC 24 |
Sep 24 11:56:21 PM UTC 24 |
7454373930 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1254658933 |
|
|
Sep 24 11:48:45 PM UTC 24 |
Sep 24 11:57:00 PM UTC 24 |
25896829654 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2126627017 |
|
|
Sep 24 11:43:47 PM UTC 24 |
Sep 24 11:57:09 PM UTC 24 |
5764747325 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.3718958934 |
|
|
Sep 24 11:56:10 PM UTC 24 |
Sep 24 11:57:28 PM UTC 24 |
553460940 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.1980732608 |
|
|
Sep 24 11:52:59 PM UTC 24 |
Sep 24 11:57:29 PM UTC 24 |
5840267461 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.1201043403 |
|
|
Sep 24 11:47:37 PM UTC 24 |
Sep 24 11:57:38 PM UTC 24 |
56163290301 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3818546287 |
|
|
Sep 24 11:55:54 PM UTC 24 |
Sep 24 11:57:40 PM UTC 24 |
7168214791 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.3077857584 |
|
|
Sep 24 11:57:21 PM UTC 24 |
Sep 24 11:57:41 PM UTC 24 |
143566347 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3736307014 |
|
|
Sep 24 11:55:56 PM UTC 24 |
Sep 24 11:57:42 PM UTC 24 |
4320260630 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.3814085553 |
|
|
Sep 24 11:56:05 PM UTC 24 |
Sep 24 11:57:45 PM UTC 24 |
2044889235 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.4177479261 |
|
|
Sep 24 11:57:31 PM UTC 24 |
Sep 24 11:58:11 PM UTC 24 |
927439460 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.886978696 |
|
|
Sep 24 11:56:25 PM UTC 24 |
Sep 24 11:58:15 PM UTC 24 |
2074147661 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.3270604613 |
|
|
Sep 24 11:28:52 PM UTC 24 |
Sep 24 11:58:44 PM UTC 24 |
16555515385 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2956462598 |
|
|
Sep 24 11:57:50 PM UTC 24 |
Sep 24 11:58:57 PM UTC 24 |
1343718717 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.775904702 |
|
|
Sep 24 11:53:10 PM UTC 24 |
Sep 24 11:58:59 PM UTC 24 |
4163039272 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3109309317 |
|
|
Sep 24 11:57:50 PM UTC 24 |
Sep 24 11:59:01 PM UTC 24 |
1048137117 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2463327512 |
|
|
Sep 24 11:53:07 PM UTC 24 |
Sep 24 11:59:05 PM UTC 24 |
1906619421 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3059066624 |
|
|
Sep 24 11:41:30 PM UTC 24 |
Sep 24 11:59:07 PM UTC 24 |
11194819088 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1820060788 |
|
|
Sep 24 11:59:19 PM UTC 24 |
Sep 24 11:59:27 PM UTC 24 |
41070350 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.3623526690 |
|
|
Sep 24 11:59:18 PM UTC 24 |
Sep 24 11:59:31 PM UTC 24 |
155803389 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.583580123 |
|
|
Sep 24 11:50:04 PM UTC 24 |
Sep 24 11:59:33 PM UTC 24 |
6333441966 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3483097606 |
|
|
Sep 24 11:48:27 PM UTC 24 |
Sep 24 11:59:53 PM UTC 24 |
37288511074 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1685573322 |
|
|
Sep 24 11:50:01 PM UTC 24 |
Sep 25 12:00:04 AM UTC 24 |
5555866881 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.1753784332 |
|
|
Sep 24 11:46:35 PM UTC 24 |
Sep 25 12:00:04 AM UTC 24 |
6085907475 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1463154239 |
|
|
Sep 24 11:53:13 PM UTC 24 |
Sep 25 12:00:04 AM UTC 24 |
4417515841 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2886073550 |
|
|
Sep 24 11:54:58 PM UTC 24 |
Sep 25 12:00:04 AM UTC 24 |
6077707236 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.2139321553 |
|
|
Sep 24 11:59:46 PM UTC 24 |
Sep 25 12:00:08 AM UTC 24 |
153380740 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1955267920 |
|
|
Sep 24 11:49:35 PM UTC 24 |
Sep 25 12:00:10 AM UTC 24 |
6894380903 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.3686128244 |
|
|
Sep 24 11:59:28 PM UTC 24 |
Sep 25 12:00:25 AM UTC 24 |
1819264609 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.281378306 |
|
|
Sep 24 11:45:37 PM UTC 24 |
Sep 25 12:00:33 AM UTC 24 |
48996144158 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2291152413 |
|
|
Sep 25 12:00:29 AM UTC 24 |
Sep 25 12:00:49 AM UTC 24 |
288795066 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3421968261 |
|
|
Sep 24 11:59:27 PM UTC 24 |
Sep 25 12:00:50 AM UTC 24 |
4152324655 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.495873912 |
|
|
Sep 24 11:59:21 PM UTC 24 |
Sep 25 12:01:04 AM UTC 24 |
7494244175 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.4126182983 |
|
|
Sep 25 12:00:13 AM UTC 24 |
Sep 25 12:01:08 AM UTC 24 |
601092495 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.3089852199 |
|
|
Sep 25 12:00:26 AM UTC 24 |
Sep 25 12:01:15 AM UTC 24 |
250742954 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.4005555113 |
|
|
Sep 25 12:00:28 AM UTC 24 |
Sep 25 12:01:15 AM UTC 24 |
436816076 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1233367961 |
|
|
Sep 25 12:00:28 AM UTC 24 |
Sep 25 12:01:15 AM UTC 24 |
916560901 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3673565160 |
|
|
Sep 24 11:58:00 PM UTC 24 |
Sep 25 12:01:22 AM UTC 24 |
2768823281 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.3036880209 |
|
|
Sep 25 12:01:35 AM UTC 24 |
Sep 25 12:01:47 AM UTC 24 |
155927534 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.302048361 |
|
|
Sep 25 12:01:36 AM UTC 24 |
Sep 25 12:01:47 AM UTC 24 |
53993543 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.1555752057 |
|
|
Sep 24 11:51:36 PM UTC 24 |
Sep 25 12:01:58 AM UTC 24 |
45714194047 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3460824565 |
|
|
Sep 24 11:54:53 PM UTC 24 |
Sep 25 12:02:10 AM UTC 24 |
9222582855 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1148828615 |
|
|
Sep 25 12:01:11 AM UTC 24 |
Sep 25 12:02:19 AM UTC 24 |
260150658 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.298093470 |
|
|
Sep 24 11:56:18 PM UTC 24 |
Sep 25 12:02:19 AM UTC 24 |
24138144859 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.821965254 |
|
|
Sep 25 12:02:20 AM UTC 24 |
Sep 25 12:02:42 AM UTC 24 |
156098533 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1024496552 |
|
|
Sep 24 11:58:03 PM UTC 24 |
Sep 25 12:02:47 AM UTC 24 |
2383651882 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.2967578208 |
|
|
Sep 25 12:00:31 AM UTC 24 |
Sep 25 12:02:52 AM UTC 24 |
3443315633 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.3147558489 |
|
|
Sep 24 11:22:56 PM UTC 24 |
Sep 25 12:02:57 AM UTC 24 |
15905091752 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.3299004899 |
|
|
Sep 25 12:01:43 AM UTC 24 |
Sep 25 12:03:07 AM UTC 24 |
7660943257 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3360875205 |
|
|
Sep 24 11:55:13 PM UTC 24 |
Sep 25 12:03:17 AM UTC 24 |
4019834220 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2303340805 |
|
|
Sep 25 12:02:08 AM UTC 24 |
Sep 25 12:03:34 AM UTC 24 |
5906879574 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3277893538 |
|
|
Sep 25 12:02:07 AM UTC 24 |
Sep 25 12:03:34 AM UTC 24 |
2193835664 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.3948109116 |
|
|
Sep 25 12:02:40 AM UTC 24 |
Sep 25 12:03:37 AM UTC 24 |
1047829671 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.1854323174 |
|
|
Sep 25 12:03:07 AM UTC 24 |
Sep 25 12:03:38 AM UTC 24 |
340590739 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.918829408 |
|
|
Sep 25 12:03:17 AM UTC 24 |
Sep 25 12:03:41 AM UTC 24 |
98432012 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.2128911014 |
|
|
Sep 24 11:51:39 PM UTC 24 |
Sep 25 12:03:45 AM UTC 24 |
46617493191 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.1823347104 |
|
|
Sep 24 11:54:03 PM UTC 24 |
Sep 25 12:03:48 AM UTC 24 |
53316547471 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3587665880 |
|
|
Sep 25 12:03:13 AM UTC 24 |
Sep 25 12:03:56 AM UTC 24 |
1522121191 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3258738956 |
|
|
Sep 25 12:02:32 AM UTC 24 |
Sep 25 12:04:14 AM UTC 24 |
7802933235 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.362604462 |
|
|
Sep 24 11:29:38 PM UTC 24 |
Sep 25 12:04:19 AM UTC 24 |
109650420470 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3803919257 |
|
|
Sep 25 12:04:09 AM UTC 24 |
Sep 25 12:04:20 AM UTC 24 |
174589142 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4063731421 |
|
|
Sep 25 12:03:29 AM UTC 24 |
Sep 25 12:04:21 AM UTC 24 |
1306993159 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4239784237 |
|
|
Sep 25 12:04:16 AM UTC 24 |
Sep 25 12:04:27 AM UTC 24 |
42084179 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2439798266 |
|
|
Sep 24 11:55:37 PM UTC 24 |
Sep 25 12:04:32 AM UTC 24 |
4828820398 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.503035505 |
|
|
Sep 25 12:03:59 AM UTC 24 |
Sep 25 12:04:46 AM UTC 24 |
144355772 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.2841290708 |
|
|
Sep 25 12:02:40 AM UTC 24 |
Sep 25 12:04:52 AM UTC 24 |
6135909470 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3127949177 |
|
|
Sep 25 12:00:54 AM UTC 24 |
Sep 25 12:05:00 AM UTC 24 |
2930286541 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.1444777250 |
|
|
Sep 25 12:04:42 AM UTC 24 |
Sep 25 12:05:10 AM UTC 24 |
208633772 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.1587610946 |
|
|
Sep 24 11:58:00 PM UTC 24 |
Sep 25 12:05:36 AM UTC 24 |
4584294632 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.1997271545 |
|
|
Sep 25 12:04:43 AM UTC 24 |
Sep 25 12:05:40 AM UTC 24 |
1076446467 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2909278887 |
|
|
Sep 25 12:05:18 AM UTC 24 |
Sep 25 12:05:44 AM UTC 24 |
208028732 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3856438198 |
|
|
Sep 25 12:03:53 AM UTC 24 |
Sep 25 12:05:52 AM UTC 24 |
167000741 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2145729715 |
|
|
Sep 25 12:04:41 AM UTC 24 |
Sep 25 12:06:02 AM UTC 24 |
4722011373 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.222860954 |
|
|
Sep 24 11:11:44 PM UTC 24 |
Sep 25 12:06:06 AM UTC 24 |
29787717070 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3965260697 |
|
|
Sep 25 12:03:55 AM UTC 24 |
Sep 25 12:06:13 AM UTC 24 |
3537202456 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2831590428 |
|
|
Sep 25 12:06:01 AM UTC 24 |
Sep 25 12:06:23 AM UTC 24 |
114727409 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3104187736 |
|
|
Sep 25 12:05:58 AM UTC 24 |
Sep 25 12:06:26 AM UTC 24 |
167973336 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.4237784828 |
|
|
Sep 25 12:04:34 AM UTC 24 |
Sep 25 12:06:33 AM UTC 24 |
7240067523 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3486766316 |
|
|
Sep 25 12:05:08 AM UTC 24 |
Sep 25 12:06:35 AM UTC 24 |
756158099 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.832392871 |
|
|
Sep 25 12:06:41 AM UTC 24 |
Sep 25 12:06:51 AM UTC 24 |
179288989 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3292196210 |
|
|
Sep 25 12:06:45 AM UTC 24 |
Sep 25 12:06:54 AM UTC 24 |
50329272 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.1961384213 |
|
|
Sep 25 12:03:33 AM UTC 24 |
Sep 25 12:07:01 AM UTC 24 |
1969089558 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.719395109 |
|
|
Sep 24 11:58:01 PM UTC 24 |
Sep 25 12:07:09 AM UTC 24 |
4418641630 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.864846283 |
|
|
Sep 25 12:05:32 AM UTC 24 |
Sep 25 12:07:22 AM UTC 24 |
2332594988 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.3807040837 |
|
|
Sep 25 12:04:48 AM UTC 24 |
Sep 25 12:07:30 AM UTC 24 |
18898431703 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.93437184 |
|
|
Sep 24 11:58:33 PM UTC 24 |
Sep 25 12:07:51 AM UTC 24 |
5788034336 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.2745054942 |
|
|
Sep 24 11:58:05 PM UTC 24 |
Sep 25 12:07:51 AM UTC 24 |
4887611030 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.3619909424 |
|
|
Sep 25 12:01:12 AM UTC 24 |
Sep 25 12:08:01 AM UTC 24 |
4551502658 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.3954750967 |
|
|
Sep 24 11:59:05 PM UTC 24 |
Sep 25 12:08:04 AM UTC 24 |
4601935230 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2848479988 |
|
|
Sep 24 11:55:22 PM UTC 24 |
Sep 25 12:08:05 AM UTC 24 |
5737279865 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3225328586 |
|
|
Sep 24 11:34:32 PM UTC 24 |
Sep 25 12:08:08 AM UTC 24 |
134898844043 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4092459048 |
|
|
Sep 25 12:07:14 AM UTC 24 |
Sep 25 12:08:10 AM UTC 24 |
471146953 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3992573199 |
|
|
Sep 25 12:07:13 AM UTC 24 |
Sep 25 12:08:11 AM UTC 24 |
1387044274 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.132158846 |
|
|
Sep 25 12:06:13 AM UTC 24 |
Sep 25 12:08:26 AM UTC 24 |
321667893 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.453049196 |
|
|
Sep 25 12:06:05 AM UTC 24 |
Sep 25 12:08:27 AM UTC 24 |
2682153233 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.583546820 |
|
|
Sep 25 12:06:52 AM UTC 24 |
Sep 25 12:08:32 AM UTC 24 |
9614775547 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3287478835 |
|
|
Sep 25 12:08:12 AM UTC 24 |
Sep 25 12:08:46 AM UTC 24 |
328417364 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1780325637 |
|
|
Sep 25 12:06:55 AM UTC 24 |
Sep 25 12:08:47 AM UTC 24 |
5985413459 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1667121498 |
|
|
Sep 25 12:08:11 AM UTC 24 |
Sep 25 12:08:51 AM UTC 24 |
480481144 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3929849590 |
|
|
Sep 25 12:08:51 AM UTC 24 |
Sep 25 12:08:58 AM UTC 24 |
41802256 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.2929641847 |
|
|
Sep 25 12:08:23 AM UTC 24 |
Sep 25 12:08:58 AM UTC 24 |
242457359 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.3894045667 |
|
|
Sep 25 12:08:49 AM UTC 24 |
Sep 25 12:09:01 AM UTC 24 |
194880940 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3446533924 |
|
|
Sep 25 12:08:25 AM UTC 24 |
Sep 25 12:09:07 AM UTC 24 |
253524393 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.336427762 |
|
|
Sep 24 11:54:11 PM UTC 24 |
Sep 25 12:09:29 AM UTC 24 |
58132639221 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1945621347 |
|
|
Sep 25 12:04:04 AM UTC 24 |
Sep 25 12:09:30 AM UTC 24 |
4264263409 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.1677924875 |
|
|
Sep 25 12:01:34 AM UTC 24 |
Sep 25 12:09:32 AM UTC 24 |
4829511138 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.3939143717 |
|
|
Sep 25 12:09:19 AM UTC 24 |
Sep 25 12:09:41 AM UTC 24 |
269781026 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.3137808332 |
|
|
Sep 25 12:09:11 AM UTC 24 |
Sep 25 12:09:45 AM UTC 24 |
297613466 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3683195318 |
|
|
Sep 25 12:03:58 AM UTC 24 |
Sep 25 12:10:03 AM UTC 24 |
4468397660 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2159900423 |
|
|
Sep 25 12:09:12 AM UTC 24 |
Sep 25 12:10:04 AM UTC 24 |
393986263 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1506431819 |
|
|
Sep 24 11:55:29 PM UTC 24 |
Sep 25 12:10:05 AM UTC 24 |
11041134456 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.2697377925 |
|
|
Sep 25 12:08:30 AM UTC 24 |
Sep 25 12:10:08 AM UTC 24 |
2314423281 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1104355285 |
|
|
Sep 24 11:59:54 PM UTC 24 |
Sep 25 12:10:16 AM UTC 24 |
33924491333 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3843482817 |
|
|
Sep 25 12:10:06 AM UTC 24 |
Sep 25 12:10:32 AM UTC 24 |
190294295 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3437462121 |
|
|
Sep 25 12:08:31 AM UTC 24 |
Sep 25 12:10:33 AM UTC 24 |
405998768 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.863736930 |
|
|
Sep 24 11:32:26 PM UTC 24 |
Sep 25 12:10:34 AM UTC 24 |
118455791701 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.768985626 |
|
|
Sep 25 12:09:53 AM UTC 24 |
Sep 25 12:10:35 AM UTC 24 |
249411406 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3972151475 |
|
|
Sep 25 12:00:27 AM UTC 24 |
Sep 25 12:10:43 AM UTC 24 |
33040432162 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.2404837791 |
|
|
Sep 25 12:10:02 AM UTC 24 |
Sep 25 12:10:46 AM UTC 24 |
995741176 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.317721420 |
|
|
Sep 25 12:09:52 AM UTC 24 |
Sep 25 12:10:49 AM UTC 24 |
1625026038 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.1503589051 |
|
|
Sep 25 12:07:42 AM UTC 24 |
Sep 25 12:10:52 AM UTC 24 |
3455906519 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1399966626 |
|
|
Sep 25 12:09:05 AM UTC 24 |
Sep 25 12:10:52 AM UTC 24 |
9860048100 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.961016709 |
|
|
Sep 25 12:10:38 AM UTC 24 |
Sep 25 12:10:54 AM UTC 24 |
247380429 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1859666407 |
|
|
Sep 25 12:10:52 AM UTC 24 |
Sep 25 12:11:02 AM UTC 24 |
38283405 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.2712385824 |
|
|
Sep 25 12:10:54 AM UTC 24 |
Sep 25 12:11:03 AM UTC 24 |
132147314 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3192519945 |
|
|
Sep 25 12:03:03 AM UTC 24 |
Sep 25 12:11:07 AM UTC 24 |
32594096379 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2316047618 |
|
|
Sep 25 12:09:07 AM UTC 24 |
Sep 25 12:11:12 AM UTC 24 |
6134539637 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.23674362 |
|
|
Sep 25 12:10:25 AM UTC 24 |
Sep 25 12:11:13 AM UTC 24 |
866004285 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2767066821 |
|
|
Sep 25 12:06:27 AM UTC 24 |
Sep 25 12:11:22 AM UTC 24 |
908100872 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1289647564 |
|
|
Sep 25 12:09:50 AM UTC 24 |
Sep 25 12:11:24 AM UTC 24 |
2437355208 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.213076405 |
|
|
Sep 25 12:11:12 AM UTC 24 |
Sep 25 12:11:25 AM UTC 24 |
71256026 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1703165057 |
|
|
Sep 25 12:01:25 AM UTC 24 |
Sep 25 12:11:26 AM UTC 24 |
6921604508 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.3701337496 |
|
|
Sep 25 12:06:34 AM UTC 24 |
Sep 25 12:11:46 AM UTC 24 |
3434184520 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1649274298 |
|
|
Sep 25 12:06:23 AM UTC 24 |
Sep 25 12:11:54 AM UTC 24 |
8398146321 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1581010141 |
|
|
Sep 25 12:11:23 AM UTC 24 |
Sep 25 12:11:56 AM UTC 24 |
254935903 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.3298569870 |
|
|
Sep 25 12:11:44 AM UTC 24 |
Sep 25 12:11:58 AM UTC 24 |
196256950 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2793433112 |
|
|
Sep 25 12:11:03 AM UTC 24 |
Sep 25 12:11:59 AM UTC 24 |
513040421 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.348754243 |
|
|
Sep 25 12:11:28 AM UTC 24 |
Sep 25 12:12:07 AM UTC 24 |
285782998 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3001007118 |
|
|
Sep 24 11:42:32 PM UTC 24 |
Sep 25 12:12:12 AM UTC 24 |
100347333095 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.3962316139 |
|
|
Sep 25 12:12:08 AM UTC 24 |
Sep 25 12:12:19 AM UTC 24 |
45325955 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.4161569117 |
|
|
Sep 25 12:11:23 AM UTC 24 |
Sep 25 12:12:20 AM UTC 24 |
1266620179 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1992931681 |
|
|
Sep 25 12:10:53 AM UTC 24 |
Sep 25 12:12:23 AM UTC 24 |
5619911275 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1713638933 |
|
|
Sep 25 12:11:12 AM UTC 24 |
Sep 25 12:12:29 AM UTC 24 |
1347440560 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3981541115 |
|
|
Sep 25 12:12:20 AM UTC 24 |
Sep 25 12:12:40 AM UTC 24 |
126710313 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.4130019874 |
|
|
Sep 25 12:08:27 AM UTC 24 |
Sep 25 12:12:56 AM UTC 24 |
5479797343 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1148161896 |
|
|
Sep 25 12:20:35 AM UTC 24 |
Sep 25 12:20:48 AM UTC 24 |
143770941 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.657498588 |
|
|
Sep 25 12:07:22 AM UTC 24 |
Sep 25 12:12:56 AM UTC 24 |
29862134407 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.717011772 |
|
|
Sep 25 12:12:40 AM UTC 24 |
Sep 25 12:13:07 AM UTC 24 |
139076657 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.207000263 |
|
|
Sep 24 11:59:53 PM UTC 24 |
Sep 25 12:13:11 AM UTC 24 |
82866295968 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1410489132 |
|
|
Sep 25 12:10:55 AM UTC 24 |
Sep 25 12:13:12 AM UTC 24 |
8166361326 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3717485581 |
|
|
Sep 25 12:12:19 AM UTC 24 |
Sep 25 12:13:17 AM UTC 24 |
3574287523 ps |