| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.1660955309 |
|
|
Sep 25 07:42:25 AM UTC 24 |
Sep 25 07:54:15 AM UTC 24 |
4709974644 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1239893744 |
|
|
Sep 25 07:45:47 AM UTC 24 |
Sep 25 07:54:26 AM UTC 24 |
3854529546 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1413323016 |
|
|
Sep 25 07:45:48 AM UTC 24 |
Sep 25 07:54:29 AM UTC 24 |
4520684640 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.606810699 |
|
|
Sep 25 07:43:30 AM UTC 24 |
Sep 25 07:54:55 AM UTC 24 |
4322994320 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.603738150 |
|
|
Sep 25 07:43:30 AM UTC 24 |
Sep 25 07:55:04 AM UTC 24 |
3840413040 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2840310295 |
|
|
Sep 25 05:39:19 AM UTC 24 |
Sep 25 07:56:09 AM UTC 24 |
26592383052 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.2120244174 |
|
|
Sep 25 07:45:37 AM UTC 24 |
Sep 25 07:56:17 AM UTC 24 |
5857941196 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.3896383993 |
|
|
Sep 25 07:03:00 AM UTC 24 |
Sep 25 07:56:18 AM UTC 24 |
26605954304 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.612745841 |
|
|
Sep 25 07:44:20 AM UTC 24 |
Sep 25 07:57:14 AM UTC 24 |
5063029982 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1492789753 |
|
|
Sep 25 07:45:48 AM UTC 24 |
Sep 25 07:57:20 AM UTC 24 |
7727703848 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.2211151594 |
|
|
Sep 25 06:40:39 AM UTC 24 |
Sep 25 07:57:25 AM UTC 24 |
16441886316 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1414044838 |
|
|
Sep 25 06:29:35 AM UTC 24 |
Sep 25 07:57:42 AM UTC 24 |
19852785110 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1305073095 |
|
|
Sep 25 07:48:32 AM UTC 24 |
Sep 25 07:59:23 AM UTC 24 |
4907414000 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.604248378 |
|
|
Sep 25 07:26:27 AM UTC 24 |
Sep 25 07:59:38 AM UTC 24 |
8311580064 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.2567569151 |
|
|
Sep 25 07:50:46 AM UTC 24 |
Sep 25 08:00:39 AM UTC 24 |
3994683990 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2095317252 |
|
|
Sep 25 07:52:57 AM UTC 24 |
Sep 25 08:01:25 AM UTC 24 |
4257985608 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3873399483 |
|
|
Sep 25 07:52:50 AM UTC 24 |
Sep 25 08:01:51 AM UTC 24 |
6460546521 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.2672470935 |
|
|
Sep 25 07:38:13 AM UTC 24 |
Sep 25 08:02:07 AM UTC 24 |
12359034511 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.2446405044 |
|
|
Sep 25 07:47:12 AM UTC 24 |
Sep 25 08:02:17 AM UTC 24 |
8695168761 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.811552527 |
|
|
Sep 25 06:10:46 AM UTC 24 |
Sep 25 08:03:03 AM UTC 24 |
50030870176 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590957260 |
|
|
Sep 25 07:55:15 AM UTC 24 |
Sep 25 08:03:38 AM UTC 24 |
3463897024 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2757278118 |
|
|
Sep 25 07:57:07 AM UTC 24 |
Sep 25 08:03:47 AM UTC 24 |
4061300408 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.2086699946 |
|
|
Sep 25 07:50:08 AM UTC 24 |
Sep 25 08:04:01 AM UTC 24 |
6200699560 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.4207598063 |
|
|
Sep 25 07:55:08 AM UTC 24 |
Sep 25 08:05:26 AM UTC 24 |
6055927224 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.1789101718 |
|
|
Sep 25 07:52:58 AM UTC 24 |
Sep 25 08:05:33 AM UTC 24 |
5707998328 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2592504244 |
|
|
Sep 25 07:45:40 AM UTC 24 |
Sep 25 08:06:00 AM UTC 24 |
9690218500 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.936936704 |
|
|
Sep 25 06:11:51 AM UTC 24 |
Sep 25 08:06:10 AM UTC 24 |
48125923660 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2634760030 |
|
|
Sep 25 07:55:42 AM UTC 24 |
Sep 25 08:06:42 AM UTC 24 |
4454780266 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.3380773322 |
|
|
Sep 25 07:55:43 AM UTC 24 |
Sep 25 08:07:22 AM UTC 24 |
4846321280 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.3790702504 |
|
|
Sep 25 06:09:59 AM UTC 24 |
Sep 25 08:07:29 AM UTC 24 |
47732711540 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.361010995 |
|
|
Sep 25 08:00:29 AM UTC 24 |
Sep 25 08:07:46 AM UTC 24 |
3750264994 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.2837372189 |
|
|
Sep 25 07:58:19 AM UTC 24 |
Sep 25 08:07:48 AM UTC 24 |
4640073918 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4278641746 |
|
|
Sep 25 07:34:37 AM UTC 24 |
Sep 25 08:07:51 AM UTC 24 |
13474324555 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1299621421 |
|
|
Sep 25 07:58:26 AM UTC 24 |
Sep 25 08:07:57 AM UTC 24 |
4332426414 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.4522365 |
|
|
Sep 25 07:47:30 AM UTC 24 |
Sep 25 08:09:36 AM UTC 24 |
13246504394 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3783272039 |
|
|
Sep 25 08:01:14 AM UTC 24 |
Sep 25 08:10:22 AM UTC 24 |
5581325465 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1198235677 |
|
|
Sep 25 08:01:59 AM UTC 24 |
Sep 25 08:11:21 AM UTC 24 |
4062256340 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.756238834 |
|
|
Sep 25 07:57:08 AM UTC 24 |
Sep 25 08:12:13 AM UTC 24 |
10093817780 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3845750450 |
|
|
Sep 25 08:04:35 AM UTC 24 |
Sep 25 08:12:27 AM UTC 24 |
4311569000 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.479677165 |
|
|
Sep 25 08:00:26 AM UTC 24 |
Sep 25 08:12:28 AM UTC 24 |
5673946824 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2865636894 |
|
|
Sep 25 07:58:25 AM UTC 24 |
Sep 25 08:13:10 AM UTC 24 |
5933326816 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.1375490932 |
|
|
Sep 25 08:02:57 AM UTC 24 |
Sep 25 08:13:23 AM UTC 24 |
4583959956 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.59286699 |
|
|
Sep 25 08:06:12 AM UTC 24 |
Sep 25 08:13:47 AM UTC 24 |
3777263748 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.1581239652 |
|
|
Sep 25 08:04:38 AM UTC 24 |
Sep 25 08:13:48 AM UTC 24 |
5140088976 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.1881207646 |
|
|
Sep 25 08:02:57 AM UTC 24 |
Sep 25 08:14:30 AM UTC 24 |
4957017064 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1794470463 |
|
|
Sep 25 02:00:15 AM UTC 24 |
Sep 25 08:15:55 AM UTC 24 |
80481037070 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.2905107832 |
|
|
Sep 25 08:04:39 AM UTC 24 |
Sep 25 08:16:14 AM UTC 24 |
4678602798 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.1659746465 |
|
|
Sep 25 06:50:17 AM UTC 24 |
Sep 25 08:17:21 AM UTC 24 |
15255664712 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2852398407 |
|
|
Sep 25 07:58:18 AM UTC 24 |
Sep 25 08:17:38 AM UTC 24 |
10731282038 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.3202182201 |
|
|
Sep 25 08:08:58 AM UTC 24 |
Sep 25 08:18:11 AM UTC 24 |
7174818013 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3309901774 |
|
|
Sep 25 08:06:48 AM UTC 24 |
Sep 25 08:18:18 AM UTC 24 |
4309800792 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.551144337 |
|
|
Sep 25 08:08:48 AM UTC 24 |
Sep 25 08:18:37 AM UTC 24 |
4056819148 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.1684591915 |
|
|
Sep 25 08:06:48 AM UTC 24 |
Sep 25 08:19:11 AM UTC 24 |
5744005000 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3465525696 |
|
|
Sep 25 08:08:53 AM UTC 24 |
Sep 25 08:19:25 AM UTC 24 |
5460803080 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.342082499 |
|
|
Sep 25 07:44:34 AM UTC 24 |
Sep 25 08:19:47 AM UTC 24 |
13854928333 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.3162115064 |
|
|
Sep 25 08:08:18 AM UTC 24 |
Sep 25 08:20:31 AM UTC 24 |
5485394000 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909588533 |
|
|
Sep 25 08:11:57 AM UTC 24 |
Sep 25 08:20:51 AM UTC 24 |
3344329084 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.3994802354 |
|
|
Sep 25 08:08:52 AM UTC 24 |
Sep 25 08:20:55 AM UTC 24 |
3974513360 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1157904286 |
|
|
Sep 25 07:17:39 AM UTC 24 |
Sep 25 08:21:25 AM UTC 24 |
12042887588 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.3175851418 |
|
|
Sep 25 08:10:57 AM UTC 24 |
Sep 25 08:21:44 AM UTC 24 |
6752555534 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.1634817610 |
|
|
Sep 25 08:03:37 AM UTC 24 |
Sep 25 08:21:59 AM UTC 24 |
10888773490 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2424931686 |
|
|
Sep 25 08:10:13 AM UTC 24 |
Sep 25 08:22:11 AM UTC 24 |
4224944580 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137872765 |
|
|
Sep 25 08:16:33 AM UTC 24 |
Sep 25 08:24:28 AM UTC 24 |
3529951000 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2277402590 |
|
|
Sep 25 08:14:34 AM UTC 24 |
Sep 25 08:24:40 AM UTC 24 |
4041252756 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3795479191 |
|
|
Sep 25 08:06:12 AM UTC 24 |
Sep 25 08:25:14 AM UTC 24 |
13218182359 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.3183511803 |
|
|
Sep 25 08:13:57 AM UTC 24 |
Sep 25 08:25:17 AM UTC 24 |
5088443992 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1829610927 |
|
|
Sep 25 08:20:01 AM UTC 24 |
Sep 25 08:26:16 AM UTC 24 |
2936462448 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3660479761 |
|
|
Sep 25 08:18:23 AM UTC 24 |
Sep 25 08:26:19 AM UTC 24 |
4052212082 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1482413288 |
|
|
Sep 25 08:19:22 AM UTC 24 |
Sep 25 08:26:22 AM UTC 24 |
4348604392 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336172109 |
|
|
Sep 25 08:21:07 AM UTC 24 |
Sep 25 08:26:27 AM UTC 24 |
3610302132 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.572321782 |
|
|
Sep 25 07:33:51 AM UTC 24 |
Sep 25 08:26:30 AM UTC 24 |
13091403060 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.3421242471 |
|
|
Sep 25 08:16:51 AM UTC 24 |
Sep 25 08:27:01 AM UTC 24 |
5240347128 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.947431723 |
|
|
Sep 25 08:21:40 AM UTC 24 |
Sep 25 08:27:39 AM UTC 24 |
3862193384 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.1889352425 |
|
|
Sep 25 08:07:15 AM UTC 24 |
Sep 25 08:27:46 AM UTC 24 |
11358675768 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.768018501 |
|
|
Sep 25 08:19:17 AM UTC 24 |
Sep 25 08:27:56 AM UTC 24 |
4310231768 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.54447153 |
|
|
Sep 25 08:18:54 AM UTC 24 |
Sep 25 08:28:08 AM UTC 24 |
3840068192 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.746600883 |
|
|
Sep 25 08:14:33 AM UTC 24 |
Sep 25 08:28:21 AM UTC 24 |
6156915672 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1451455306 |
|
|
Sep 25 08:18:18 AM UTC 24 |
Sep 25 08:28:25 AM UTC 24 |
4251277048 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.830260241 |
|
|
Sep 25 07:17:43 AM UTC 24 |
Sep 25 08:29:31 AM UTC 24 |
25713269757 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.3699951481 |
|
|
Sep 25 07:17:24 AM UTC 24 |
Sep 25 08:30:23 AM UTC 24 |
14972937746 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655259804 |
|
|
Sep 25 08:23:12 AM UTC 24 |
Sep 25 08:30:47 AM UTC 24 |
3978980448 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.18404547 |
|
|
Sep 25 08:18:23 AM UTC 24 |
Sep 25 08:31:06 AM UTC 24 |
4578827014 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.1986622484 |
|
|
Sep 25 08:20:24 AM UTC 24 |
Sep 25 08:31:07 AM UTC 24 |
4452400896 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.2014244340 |
|
|
Sep 25 08:19:23 AM UTC 24 |
Sep 25 08:31:21 AM UTC 24 |
5469506048 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455462176 |
|
|
Sep 25 08:23:13 AM UTC 24 |
Sep 25 08:31:42 AM UTC 24 |
4292148998 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.127971002 |
|
|
Sep 25 08:22:00 AM UTC 24 |
Sep 25 08:31:49 AM UTC 24 |
5286047128 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3780075033 |
|
|
Sep 25 08:19:46 AM UTC 24 |
Sep 25 08:32:00 AM UTC 24 |
5207385740 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.779925250 |
|
|
Sep 25 08:21:39 AM UTC 24 |
Sep 25 08:32:28 AM UTC 24 |
4308540192 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1275272487 |
|
|
Sep 25 08:23:04 AM UTC 24 |
Sep 25 08:32:40 AM UTC 24 |
4144040760 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.2478407156 |
|
|
Sep 25 07:48:10 AM UTC 24 |
Sep 25 08:32:54 AM UTC 24 |
24476154141 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.1837445073 |
|
|
Sep 25 07:18:48 AM UTC 24 |
Sep 25 08:32:55 AM UTC 24 |
15521636336 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3779235341 |
|
|
Sep 25 08:25:18 AM UTC 24 |
Sep 25 08:33:51 AM UTC 24 |
4372745482 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2829138405 |
|
|
Sep 25 08:23:11 AM UTC 24 |
Sep 25 08:34:12 AM UTC 24 |
4882105820 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.147242104 |
|
|
Sep 25 08:26:03 AM UTC 24 |
Sep 25 08:34:19 AM UTC 24 |
3692960664 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.485771158 |
|
|
Sep 25 07:44:19 AM UTC 24 |
Sep 25 08:34:45 AM UTC 24 |
12658410360 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205070145 |
|
|
Sep 25 08:27:55 AM UTC 24 |
Sep 25 08:34:47 AM UTC 24 |
4306383820 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.1063500475 |
|
|
Sep 25 08:25:14 AM UTC 24 |
Sep 25 08:34:54 AM UTC 24 |
4060244276 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052382618 |
|
|
Sep 25 08:27:58 AM UTC 24 |
Sep 25 08:35:17 AM UTC 24 |
3311304368 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.639004380 |
|
|
Sep 25 08:27:50 AM UTC 24 |
Sep 25 08:36:01 AM UTC 24 |
4414494832 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1750373960 |
|
|
Sep 25 08:23:03 AM UTC 24 |
Sep 25 08:36:36 AM UTC 24 |
5040072360 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563506976 |
|
|
Sep 25 08:29:17 AM UTC 24 |
Sep 25 08:36:44 AM UTC 24 |
3921225984 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3716709741 |
|
|
Sep 25 08:29:06 AM UTC 24 |
Sep 25 08:36:49 AM UTC 24 |
3756240232 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3672315935 |
|
|
Sep 25 07:19:25 AM UTC 24 |
Sep 25 08:37:17 AM UTC 24 |
15604018216 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4283962359 |
|
|
Sep 25 07:14:26 AM UTC 24 |
Sep 25 08:37:38 AM UTC 24 |
21683744398 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3017403895 |
|
|
Sep 25 08:29:13 AM UTC 24 |
Sep 25 08:37:49 AM UTC 24 |
3686012808 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.1415171829 |
|
|
Sep 25 08:26:02 AM UTC 24 |
Sep 25 08:38:37 AM UTC 24 |
5243506600 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.547747212 |
|
|
Sep 25 08:32:04 AM UTC 24 |
Sep 25 08:38:53 AM UTC 24 |
3924074920 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.491437028 |
|
|
Sep 25 08:29:12 AM UTC 24 |
Sep 25 08:39:01 AM UTC 24 |
5131436860 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.4052389872 |
|
|
Sep 25 08:27:53 AM UTC 24 |
Sep 25 08:39:17 AM UTC 24 |
5883642862 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4005309187 |
|
|
Sep 25 07:19:23 AM UTC 24 |
Sep 25 08:39:20 AM UTC 24 |
14596014088 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531799385 |
|
|
Sep 25 08:32:40 AM UTC 24 |
Sep 25 08:39:22 AM UTC 24 |
3723587736 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309997317 |
|
|
Sep 25 08:30:59 AM UTC 24 |
Sep 25 08:39:24 AM UTC 24 |
4241748672 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.2461995057 |
|
|
Sep 25 07:17:50 AM UTC 24 |
Sep 25 08:39:29 AM UTC 24 |
14607725050 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1549737210 |
|
|
Sep 25 08:27:58 AM UTC 24 |
Sep 25 08:40:15 AM UTC 24 |
4462389604 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2717835738 |
|
|
Sep 25 08:33:41 AM UTC 24 |
Sep 25 08:40:31 AM UTC 24 |
3802889522 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.2395179146 |
|
|
Sep 25 08:27:54 AM UTC 24 |
Sep 25 08:40:34 AM UTC 24 |
5512846208 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3037643196 |
|
|
Sep 25 08:29:13 AM UTC 24 |
Sep 25 08:40:53 AM UTC 24 |
5981161124 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.3281170470 |
|
|
Sep 25 08:14:00 AM UTC 24 |
Sep 25 08:40:58 AM UTC 24 |
7512120790 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1135382280 |
|
|
Sep 25 07:53:55 AM UTC 24 |
Sep 25 08:41:02 AM UTC 24 |
13572695992 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.151170522 |
|
|
Sep 25 08:33:14 AM UTC 24 |
Sep 25 08:41:11 AM UTC 24 |
3618858914 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.437440869 |
|
|
Sep 25 08:32:44 AM UTC 24 |
Sep 25 08:41:29 AM UTC 24 |
3782337040 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.2631069371 |
|
|
Sep 25 08:29:17 AM UTC 24 |
Sep 25 08:41:44 AM UTC 24 |
4938179672 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391725901 |
|
|
Sep 25 08:34:27 AM UTC 24 |
Sep 25 08:41:44 AM UTC 24 |
3942468360 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3319114355 |
|
|
Sep 25 08:30:08 AM UTC 24 |
Sep 25 08:42:01 AM UTC 24 |
5645285960 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413507885 |
|
|
Sep 25 08:35:01 AM UTC 24 |
Sep 25 08:42:05 AM UTC 24 |
4133245650 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.4262043697 |
|
|
Sep 25 08:31:23 AM UTC 24 |
Sep 25 08:42:15 AM UTC 24 |
5449807312 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.316625115 |
|
|
Sep 25 07:19:08 AM UTC 24 |
Sep 25 08:42:17 AM UTC 24 |
15210104537 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.4245266961 |
|
|
Sep 25 07:52:57 AM UTC 24 |
Sep 25 08:42:36 AM UTC 24 |
11038224540 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2510933129 |
|
|
Sep 25 08:32:49 AM UTC 24 |
Sep 25 08:42:55 AM UTC 24 |
5774947448 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1843449143 |
|
|
Sep 25 08:35:53 AM UTC 24 |
Sep 25 08:43:36 AM UTC 24 |
4144307980 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.763719469 |
|
|
Sep 25 07:12:07 AM UTC 24 |
Sep 25 08:43:47 AM UTC 24 |
23948766234 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1350641990 |
|
|
Sep 25 08:35:57 AM UTC 24 |
Sep 25 08:43:58 AM UTC 24 |
4021703360 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.4089045780 |
|
|
Sep 25 08:32:27 AM UTC 24 |
Sep 25 08:44:35 AM UTC 24 |
5260850328 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2436058178 |
|
|
Sep 25 08:37:38 AM UTC 24 |
Sep 25 08:44:49 AM UTC 24 |
3751972956 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1114672700 |
|
|
Sep 25 08:32:49 AM UTC 24 |
Sep 25 08:44:54 AM UTC 24 |
5577124670 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.4152597923 |
|
|
Sep 25 08:35:01 AM UTC 24 |
Sep 25 08:44:56 AM UTC 24 |
5455880528 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.2375357949 |
|
|
Sep 25 08:35:56 AM UTC 24 |
Sep 25 08:45:18 AM UTC 24 |
4881976406 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.147077736 |
|
|
Sep 25 08:35:51 AM UTC 24 |
Sep 25 08:45:23 AM UTC 24 |
4627998904 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2561417379 |
|
|
Sep 25 07:19:22 AM UTC 24 |
Sep 25 08:45:28 AM UTC 24 |
14924438002 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2234606062 |
|
|
Sep 25 07:18:29 AM UTC 24 |
Sep 25 08:45:44 AM UTC 24 |
15474622591 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673533531 |
|
|
Sep 25 08:38:26 AM UTC 24 |
Sep 25 08:45:47 AM UTC 24 |
3499252992 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2504978252 |
|
|
Sep 25 07:19:24 AM UTC 24 |
Sep 25 08:45:55 AM UTC 24 |
16115632688 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327929118 |
|
|
Sep 25 08:37:38 AM UTC 24 |
Sep 25 08:46:14 AM UTC 24 |
3806173248 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157024635 |
|
|
Sep 25 08:39:23 AM UTC 24 |
Sep 25 08:46:15 AM UTC 24 |
3315476092 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1644675401 |
|
|
Sep 25 08:33:43 AM UTC 24 |
Sep 25 08:46:27 AM UTC 24 |
6551859154 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2103571422 |
|
|
Sep 25 08:33:28 AM UTC 24 |
Sep 25 08:46:31 AM UTC 24 |
4809795300 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3083021585 |
|
|
Sep 25 08:36:40 AM UTC 24 |
Sep 25 08:46:49 AM UTC 24 |
4580510882 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366496711 |
|
|
Sep 25 08:40:18 AM UTC 24 |
Sep 25 08:47:13 AM UTC 24 |
4492773964 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2617505751 |
|
|
Sep 25 08:40:52 AM UTC 24 |
Sep 25 08:48:01 AM UTC 24 |
3972832042 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.358108778 |
|
|
Sep 25 08:40:37 AM UTC 24 |
Sep 25 08:48:24 AM UTC 24 |
4133615144 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.471008817 |
|
|
Sep 25 08:41:17 AM UTC 24 |
Sep 25 08:48:44 AM UTC 24 |
3931558100 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1255806199 |
|
|
Sep 25 08:39:36 AM UTC 24 |
Sep 25 08:48:45 AM UTC 24 |
5383775568 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.60917355 |
|
|
Sep 25 08:37:54 AM UTC 24 |
Sep 25 08:49:02 AM UTC 24 |
6037485656 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411578574 |
|
|
Sep 25 08:42:10 AM UTC 24 |
Sep 25 08:49:42 AM UTC 24 |
3669841560 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.72244244 |
|
|
Sep 25 08:37:36 AM UTC 24 |
Sep 25 08:49:57 AM UTC 24 |
5246998916 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3059243173 |
|
|
Sep 25 08:40:52 AM UTC 24 |
Sep 25 08:49:59 AM UTC 24 |
4515641128 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.805074085 |
|
|
Sep 25 08:38:26 AM UTC 24 |
Sep 25 08:50:50 AM UTC 24 |
5488573814 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870328278 |
|
|
Sep 25 08:44:16 AM UTC 24 |
Sep 25 08:50:55 AM UTC 24 |
3977284456 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.171201303 |
|
|
Sep 25 07:19:32 AM UTC 24 |
Sep 25 08:50:59 AM UTC 24 |
17560847588 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3628517585 |
|
|
Sep 25 08:45:12 AM UTC 24 |
Sep 25 08:51:04 AM UTC 24 |
3994597016 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276817468 |
|
|
Sep 25 08:43:49 AM UTC 24 |
Sep 25 08:51:08 AM UTC 24 |
4186273618 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3795755815 |
|
|
Sep 25 08:45:30 AM UTC 24 |
Sep 25 08:51:45 AM UTC 24 |
3459907400 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1497657387 |
|
|
Sep 25 08:43:47 AM UTC 24 |
Sep 25 08:51:56 AM UTC 24 |
4004812704 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2611914452 |
|
|
Sep 25 08:44:17 AM UTC 24 |
Sep 25 08:52:04 AM UTC 24 |
3767179536 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.300473145 |
|
|
Sep 25 08:46:35 AM UTC 24 |
Sep 25 08:52:13 AM UTC 24 |
3485917320 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4260075988 |
|
|
Sep 25 08:44:18 AM UTC 24 |
Sep 25 08:52:14 AM UTC 24 |
3975653976 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.821051811 |
|
|
Sep 25 08:45:08 AM UTC 24 |
Sep 25 08:52:20 AM UTC 24 |
3658162246 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2819519162 |
|
|
Sep 25 08:43:45 AM UTC 24 |
Sep 25 08:52:36 AM UTC 24 |
5131244916 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.4048584676 |
|
|
Sep 25 08:40:45 AM UTC 24 |
Sep 25 08:53:00 AM UTC 24 |
5139372908 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3291047207 |
|
|
Sep 25 08:42:41 AM UTC 24 |
Sep 25 08:53:25 AM UTC 24 |
5440195336 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.1690480229 |
|
|
Sep 25 08:43:52 AM UTC 24 |
Sep 25 08:53:31 AM UTC 24 |
4265412360 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1242794429 |
|
|
Sep 25 08:42:58 AM UTC 24 |
Sep 25 08:54:05 AM UTC 24 |
5220730588 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.519969800 |
|
|
Sep 25 08:46:32 AM UTC 24 |
Sep 25 08:54:28 AM UTC 24 |
3992593790 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700285038 |
|
|
Sep 25 08:47:49 AM UTC 24 |
Sep 25 08:54:35 AM UTC 24 |
3747396100 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2158072031 |
|
|
Sep 25 08:42:09 AM UTC 24 |
Sep 25 08:54:36 AM UTC 24 |
5790265444 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3221041522 |
|
|
Sep 25 08:48:18 AM UTC 24 |
Sep 25 08:54:40 AM UTC 24 |
3354389220 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672152933 |
|
|
Sep 25 08:47:50 AM UTC 24 |
Sep 25 08:55:06 AM UTC 24 |
4449953890 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.745330837 |
|
|
Sep 25 08:48:18 AM UTC 24 |
Sep 25 08:55:19 AM UTC 24 |
3411616416 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103206650 |
|
|
Sep 25 08:48:15 AM UTC 24 |
Sep 25 08:55:20 AM UTC 24 |
3994236520 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3510197962 |
|
|
Sep 25 08:45:13 AM UTC 24 |
Sep 25 08:55:23 AM UTC 24 |
5059281440 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.160545752 |
|
|
Sep 25 08:44:57 AM UTC 24 |
Sep 25 08:55:32 AM UTC 24 |
4288634500 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547557385 |
|
|
Sep 25 08:48:43 AM UTC 24 |
Sep 25 08:55:48 AM UTC 24 |
3685094394 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.701375818 |
|
|
Sep 25 08:48:39 AM UTC 24 |
Sep 25 08:56:13 AM UTC 24 |
3588551528 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1439351163 |
|
|
Sep 25 08:50:47 AM UTC 24 |
Sep 25 08:56:23 AM UTC 24 |
3745174462 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.4182591309 |
|
|
Sep 25 08:44:13 AM UTC 24 |
Sep 25 08:56:27 AM UTC 24 |
5523256840 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1098618417 |
|
|
Sep 25 08:44:18 AM UTC 24 |
Sep 25 08:56:36 AM UTC 24 |
4593667660 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.267768940 |
|
|
Sep 25 08:49:01 AM UTC 24 |
Sep 25 08:56:44 AM UTC 24 |
3423634432 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797558499 |
|
|
Sep 25 08:50:20 AM UTC 24 |
Sep 25 08:56:56 AM UTC 24 |
4345735138 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.701766749 |
|
|
Sep 25 08:49:49 AM UTC 24 |
Sep 25 08:57:25 AM UTC 24 |
3865153156 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3842727071 |
|
|
Sep 25 08:48:26 AM UTC 24 |
Sep 25 08:57:40 AM UTC 24 |
5638581180 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1975339432 |
|
|
Sep 25 08:45:22 AM UTC 24 |
Sep 25 08:58:04 AM UTC 24 |
5472868330 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2459241657 |
|
|
Sep 25 08:48:56 AM UTC 24 |
Sep 25 08:58:38 AM UTC 24 |
4413383354 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2737061351 |
|
|
Sep 25 08:48:43 AM UTC 24 |
Sep 25 08:58:48 AM UTC 24 |
4844307270 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.278624896 |
|
|
Sep 25 08:48:12 AM UTC 24 |
Sep 25 08:58:59 AM UTC 24 |
4982883314 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2701660121 |
|
|
Sep 25 08:13:17 AM UTC 24 |
Sep 25 08:59:12 AM UTC 24 |
13191656176 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883580446 |
|
|
Sep 25 08:54:23 AM UTC 24 |
Sep 25 08:59:20 AM UTC 24 |
3207914400 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2315381631 |
|
|
Sep 25 08:46:57 AM UTC 24 |
Sep 25 08:59:27 AM UTC 24 |
5857846388 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1774626146 |
|
|
Sep 25 08:48:19 AM UTC 24 |
Sep 25 08:59:30 AM UTC 24 |
5268610176 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.2568982711 |
|
|
Sep 25 08:47:49 AM UTC 24 |
Sep 25 08:59:32 AM UTC 24 |
5819031256 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.667196710 |
|
|
Sep 25 08:52:59 AM UTC 24 |
Sep 25 08:59:43 AM UTC 24 |
3399584402 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.3110662186 |
|
|
Sep 25 08:52:34 AM UTC 24 |
Sep 25 09:00:00 AM UTC 24 |
4817376806 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2722710913 |
|
|
Sep 25 08:54:04 AM UTC 24 |
Sep 25 09:00:08 AM UTC 24 |
3602961992 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.1955136396 |
|
|
Sep 25 08:49:47 AM UTC 24 |
Sep 25 09:00:11 AM UTC 24 |
5907003384 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.207077245 |
|
|
Sep 25 08:54:08 AM UTC 24 |
Sep 25 09:00:16 AM UTC 24 |
3752614906 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2750904972 |
|
|
Sep 25 08:48:15 AM UTC 24 |
Sep 25 09:00:25 AM UTC 24 |
5301397896 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.387785118 |
|
|
Sep 25 08:51:59 AM UTC 24 |
Sep 25 09:00:35 AM UTC 24 |
4081707716 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2904873034 |
|
|
Sep 25 08:54:25 AM UTC 24 |
Sep 25 09:00:36 AM UTC 24 |
3839746512 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.3224218568 |
|
|
Sep 25 08:49:50 AM UTC 24 |
Sep 25 09:00:50 AM UTC 24 |
5714791000 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.1012395488 |
|
|
Sep 25 08:15:07 AM UTC 24 |
Sep 25 09:01:01 AM UTC 24 |
13362547992 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.128925084 |
|
|
Sep 25 08:48:42 AM UTC 24 |
Sep 25 09:01:05 AM UTC 24 |
5818457516 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024942952 |
|
|
Sep 25 08:54:43 AM UTC 24 |
Sep 25 09:01:08 AM UTC 24 |
3886808136 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2794403753 |
|
|
Sep 25 08:50:47 AM UTC 24 |
Sep 25 09:01:13 AM UTC 24 |
4738412860 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.551533424 |
|
|
Sep 25 08:54:24 AM UTC 24 |
Sep 25 09:01:39 AM UTC 24 |
3385149236 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.1872813740 |
|
|
Sep 25 08:52:37 AM UTC 24 |
Sep 25 09:01:57 AM UTC 24 |
4612670552 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.3701814030 |
|
|
Sep 25 08:54:07 AM UTC 24 |
Sep 25 09:02:48 AM UTC 24 |
5650884060 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1692738402 |
|
|
Sep 25 08:53:08 AM UTC 24 |
Sep 25 09:03:10 AM UTC 24 |
5111019576 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2195044648 |
|
|
Sep 25 08:54:38 AM UTC 24 |
Sep 25 09:03:12 AM UTC 24 |
4643163224 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533063330 |
|
|
Sep 25 08:56:33 AM UTC 24 |
Sep 25 09:03:12 AM UTC 24 |
3725702322 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.1817177630 |
|
|
Sep 25 08:54:42 AM UTC 24 |
Sep 25 09:03:26 AM UTC 24 |
4172048936 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.2888665079 |
|
|
Sep 25 08:53:24 AM UTC 24 |
Sep 25 09:03:29 AM UTC 24 |
4969769782 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984179345 |
|
|
Sep 25 08:58:26 AM UTC 24 |
Sep 25 09:03:31 AM UTC 24 |
3272733448 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830221852 |
|
|
Sep 25 08:56:51 AM UTC 24 |
Sep 25 09:03:32 AM UTC 24 |
3709247916 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770420707 |
|
|
Sep 25 08:58:05 AM UTC 24 |
Sep 25 09:04:24 AM UTC 24 |
3489034672 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381825368 |
|
|
Sep 25 08:58:30 AM UTC 24 |
Sep 25 09:04:25 AM UTC 24 |
3133279500 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.591883999 |
|
|
Sep 25 08:58:22 AM UTC 24 |
Sep 25 09:04:36 AM UTC 24 |
3816668880 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1239590999 |
|
|
Sep 25 08:58:22 AM UTC 24 |
Sep 25 09:04:49 AM UTC 24 |
4053736546 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.1039620291 |
|
|
Sep 25 08:53:59 AM UTC 24 |
Sep 25 09:04:54 AM UTC 24 |
6316819508 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2095717318 |
|
|
Sep 25 08:57:52 AM UTC 24 |
Sep 25 09:05:11 AM UTC 24 |
3997594000 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.1050639046 |
|
|
Sep 25 08:58:06 AM UTC 24 |
Sep 25 09:05:14 AM UTC 24 |
5519158648 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.3661876863 |
|
|
Sep 25 08:55:42 AM UTC 24 |
Sep 25 09:05:44 AM UTC 24 |
5293168872 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.2680678987 |
|
|
Sep 25 08:58:21 AM UTC 24 |
Sep 25 09:06:11 AM UTC 24 |
5631122868 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3023687313 |
|
|
Sep 25 08:58:17 AM UTC 24 |
Sep 25 09:06:30 AM UTC 24 |
4624761650 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.964766053 |
|
|
Sep 25 08:58:17 AM UTC 24 |
Sep 25 09:06:30 AM UTC 24 |
6048222600 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.4082065797 |
|
|
Sep 25 08:59:37 AM UTC 24 |
Sep 25 09:06:57 AM UTC 24 |
4746068834 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3271931824 |
|
|
Sep 25 08:58:48 AM UTC 24 |
Sep 25 09:07:02 AM UTC 24 |
4432252748 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3393805354 |
|
|
Sep 25 08:58:03 AM UTC 24 |
Sep 25 09:07:07 AM UTC 24 |
5629305412 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3601962661 |
|
|
Sep 25 08:58:42 AM UTC 24 |
Sep 25 09:07:20 AM UTC 24 |
5191386230 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2963654391 |
|
|
Sep 25 08:58:44 AM UTC 24 |
Sep 25 09:07:24 AM UTC 24 |
4920902848 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.681378087 |
|
|
Sep 25 08:58:25 AM UTC 24 |
Sep 25 09:08:12 AM UTC 24 |
5502453210 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1459408739 |
|
|
Sep 25 08:58:50 AM UTC 24 |
Sep 25 09:08:15 AM UTC 24 |
4930487978 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2652799055 |
|
|
Sep 25 08:59:54 AM UTC 24 |
Sep 25 09:08:32 AM UTC 24 |
5382173280 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.406684781 |
|
|
Sep 25 08:59:51 AM UTC 24 |
Sep 25 09:08:42 AM UTC 24 |
4730265520 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1356806993 |
|
|
Sep 25 08:58:49 AM UTC 24 |
Sep 25 09:08:50 AM UTC 24 |
5227352370 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.272985058 |
|
|
Sep 25 08:59:50 AM UTC 24 |
Sep 25 09:10:26 AM UTC 24 |
6329309000 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.2962439973 |
|
|
Sep 25 07:45:38 AM UTC 24 |
Sep 25 09:14:49 AM UTC 24 |
18632314632 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.2431225421 |
|
|
Sep 25 04:20:24 AM UTC 24 |
Sep 25 09:14:59 AM UTC 24 |
67692935029 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.901221658 |
|
|
Sep 25 07:55:14 AM UTC 24 |
Sep 25 09:20:11 AM UTC 24 |
18105466930 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.643537832 |
|
|
Sep 25 07:20:14 AM UTC 24 |
Sep 25 09:27:27 AM UTC 24 |
25960120596 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.103073860 |
|
|
Sep 25 07:59:58 AM UTC 24 |
Sep 25 09:37:16 AM UTC 24 |
22208104760 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.4145461243 |
|
|
Sep 25 08:02:25 AM UTC 24 |
Sep 25 09:38:05 AM UTC 24 |
22239025872 ps |