| T2272 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.757503535 |
|
|
Sep 25 12:59:04 AM UTC 24 |
Sep 25 01:10:40 AM UTC 24 |
43212866109 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1407487999 |
|
|
Sep 25 01:10:02 AM UTC 24 |
Sep 25 01:10:46 AM UTC 24 |
467593478 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3005119465 |
|
|
Sep 25 01:09:45 AM UTC 24 |
Sep 25 01:10:51 AM UTC 24 |
1159478941 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.4133645931 |
|
|
Sep 25 01:09:08 AM UTC 24 |
Sep 25 01:10:53 AM UTC 24 |
300413302 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3538537941 |
|
|
Sep 25 01:09:20 AM UTC 24 |
Sep 25 01:10:59 AM UTC 24 |
4180913036 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.3128701337 |
|
|
Sep 25 01:09:16 AM UTC 24 |
Sep 25 01:11:02 AM UTC 24 |
9622588730 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4145009052 |
|
|
Sep 25 12:43:36 AM UTC 24 |
Sep 25 01:11:09 AM UTC 24 |
95062245456 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3589355174 |
|
|
Sep 25 01:09:41 AM UTC 24 |
Sep 25 01:11:12 AM UTC 24 |
2152284790 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.4203014406 |
|
|
Sep 25 01:08:48 AM UTC 24 |
Sep 25 01:11:14 AM UTC 24 |
3551935420 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3125299676 |
|
|
Sep 25 01:10:52 AM UTC 24 |
Sep 25 01:11:23 AM UTC 24 |
285534888 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1000105740 |
|
|
Sep 25 01:11:14 AM UTC 24 |
Sep 25 01:11:29 AM UTC 24 |
94997957 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.728217264 |
|
|
Sep 25 01:11:14 AM UTC 24 |
Sep 25 01:11:31 AM UTC 24 |
167799863 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.662975355 |
|
|
Sep 25 01:11:21 AM UTC 24 |
Sep 25 01:11:42 AM UTC 24 |
235716056 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3129858743 |
|
|
Sep 25 01:10:32 AM UTC 24 |
Sep 25 01:11:47 AM UTC 24 |
3857270255 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2442850685 |
|
|
Sep 25 01:11:03 AM UTC 24 |
Sep 25 01:11:52 AM UTC 24 |
326781104 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2228860099 |
|
|
Sep 25 01:11:25 AM UTC 24 |
Sep 25 01:11:54 AM UTC 24 |
740690656 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.209343286 |
|
|
Sep 25 01:10:30 AM UTC 24 |
Sep 25 01:11:55 AM UTC 24 |
7910875247 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1557581146 |
|
|
Sep 25 01:09:34 AM UTC 24 |
Sep 25 01:11:56 AM UTC 24 |
2555013652 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1902639045 |
|
|
Sep 25 12:55:44 AM UTC 24 |
Sep 25 01:11:59 AM UTC 24 |
60420453392 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.618915206 |
|
|
Sep 25 01:10:50 AM UTC 24 |
Sep 25 01:12:00 AM UTC 24 |
1249281872 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3615050626 |
|
|
Sep 25 01:11:53 AM UTC 24 |
Sep 25 01:12:04 AM UTC 24 |
47892235 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.2143386324 |
|
|
Sep 25 01:11:52 AM UTC 24 |
Sep 25 01:12:06 AM UTC 24 |
176342316 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3744906717 |
|
|
Sep 25 01:05:03 AM UTC 24 |
Sep 25 01:12:06 AM UTC 24 |
7683953189 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.2984563709 |
|
|
Sep 25 01:11:32 AM UTC 24 |
Sep 25 01:12:07 AM UTC 24 |
366936668 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2906221624 |
|
|
Sep 25 01:06:13 AM UTC 24 |
Sep 25 01:12:08 AM UTC 24 |
10210646192 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2118671478 |
|
|
Sep 25 12:35:45 AM UTC 24 |
Sep 25 01:12:30 AM UTC 24 |
141020626185 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.4116066034 |
|
|
Sep 25 01:04:34 AM UTC 24 |
Sep 25 01:12:39 AM UTC 24 |
39280359718 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.773546727 |
|
|
Sep 25 01:12:11 AM UTC 24 |
Sep 25 01:12:40 AM UTC 24 |
211202368 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2408984150 |
|
|
Sep 25 01:12:28 AM UTC 24 |
Sep 25 01:13:03 AM UTC 24 |
475325326 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3844436610 |
|
|
Sep 25 01:12:13 AM UTC 24 |
Sep 25 01:13:03 AM UTC 24 |
384477712 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.1501936519 |
|
|
Sep 25 01:12:27 AM UTC 24 |
Sep 25 01:13:10 AM UTC 24 |
403114649 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.2317385075 |
|
|
Sep 25 01:12:24 AM UTC 24 |
Sep 25 01:13:14 AM UTC 24 |
443726808 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2211094586 |
|
|
Sep 25 01:13:03 AM UTC 24 |
Sep 25 01:13:18 AM UTC 24 |
216811413 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2537577081 |
|
|
Sep 25 01:04:46 AM UTC 24 |
Sep 25 01:13:30 AM UTC 24 |
32705328518 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.3615719015 |
|
|
Sep 25 01:00:08 AM UTC 24 |
Sep 25 01:13:35 AM UTC 24 |
53973631861 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.3294318066 |
|
|
Sep 25 01:03:38 AM UTC 24 |
Sep 25 01:13:35 AM UTC 24 |
35682171490 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2343268629 |
|
|
Sep 25 01:13:26 AM UTC 24 |
Sep 25 01:13:35 AM UTC 24 |
45547906 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.3593357709 |
|
|
Sep 25 01:12:05 AM UTC 24 |
Sep 25 01:13:37 AM UTC 24 |
9143752596 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.548197032 |
|
|
Sep 25 01:12:29 AM UTC 24 |
Sep 25 01:13:46 AM UTC 24 |
1313869202 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.2385370779 |
|
|
Sep 25 01:13:37 AM UTC 24 |
Sep 25 01:13:54 AM UTC 24 |
124813398 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1186499798 |
|
|
Sep 25 01:13:39 AM UTC 24 |
Sep 25 01:14:01 AM UTC 24 |
127338524 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.1401382178 |
|
|
Sep 25 01:12:18 AM UTC 24 |
Sep 25 01:14:15 AM UTC 24 |
2973217868 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3977890550 |
|
|
Sep 25 01:12:10 AM UTC 24 |
Sep 25 01:14:19 AM UTC 24 |
5658299503 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.4084274648 |
|
|
Sep 25 01:13:33 AM UTC 24 |
Sep 25 01:14:32 AM UTC 24 |
3528361716 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3765500591 |
|
|
Sep 25 01:13:26 AM UTC 24 |
Sep 25 01:14:33 AM UTC 24 |
6330520629 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.3362587420 |
|
|
Sep 25 01:00:02 AM UTC 24 |
Sep 25 01:14:43 AM UTC 24 |
90163946941 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.1548472871 |
|
|
Sep 25 12:01:27 AM UTC 24 |
Sep 25 01:14:43 AM UTC 24 |
30633939884 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2359555367 |
|
|
Sep 25 01:14:08 AM UTC 24 |
Sep 25 01:14:46 AM UTC 24 |
422838880 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.2474287042 |
|
|
Sep 25 01:14:16 AM UTC 24 |
Sep 25 01:14:46 AM UTC 24 |
158728374 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.942744339 |
|
|
Sep 25 12:57:18 AM UTC 24 |
Sep 25 01:15:04 AM UTC 24 |
103771454487 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1583573219 |
|
|
Sep 25 01:02:17 AM UTC 24 |
Sep 25 01:15:11 AM UTC 24 |
45660337691 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3458136219 |
|
|
Sep 25 01:15:06 AM UTC 24 |
Sep 25 01:15:17 AM UTC 24 |
49538034 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.4076911987 |
|
|
Sep 25 01:15:05 AM UTC 24 |
Sep 25 01:15:17 AM UTC 24 |
183267806 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1007743560 |
|
|
Sep 25 01:14:24 AM UTC 24 |
Sep 25 01:15:22 AM UTC 24 |
1183335925 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.1441416859 |
|
|
Sep 25 01:13:56 AM UTC 24 |
Sep 25 01:15:23 AM UTC 24 |
739662642 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4253323028 |
|
|
Sep 25 01:12:21 AM UTC 24 |
Sep 25 01:15:26 AM UTC 24 |
10564888135 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1751354785 |
|
|
Sep 25 01:05:45 AM UTC 24 |
Sep 25 01:15:33 AM UTC 24 |
39873242117 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2417866590 |
|
|
Sep 25 12:37:56 AM UTC 24 |
Sep 25 01:15:39 AM UTC 24 |
135357650816 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.1058380772 |
|
|
Sep 25 01:13:59 AM UTC 24 |
Sep 25 01:15:43 AM UTC 24 |
2295478018 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2968806914 |
|
|
Sep 25 01:11:08 AM UTC 24 |
Sep 25 01:15:53 AM UTC 24 |
14630215339 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.3240514302 |
|
|
Sep 25 01:15:33 AM UTC 24 |
Sep 25 01:15:53 AM UTC 24 |
171004657 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1364089033 |
|
|
Sep 25 01:09:01 AM UTC 24 |
Sep 25 01:16:06 AM UTC 24 |
7893204184 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1766135125 |
|
|
Sep 25 01:15:09 AM UTC 24 |
Sep 25 01:16:21 AM UTC 24 |
4786758602 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.1285677960 |
|
|
Sep 25 01:16:02 AM UTC 24 |
Sep 25 01:16:26 AM UTC 24 |
315084111 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.3319575542 |
|
|
Sep 25 01:15:45 AM UTC 24 |
Sep 25 01:16:27 AM UTC 24 |
732111964 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1138269583 |
|
|
Sep 25 01:15:25 AM UTC 24 |
Sep 25 01:16:28 AM UTC 24 |
1255474453 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.220939706 |
|
|
Sep 25 01:01:34 AM UTC 24 |
Sep 25 01:16:28 AM UTC 24 |
7250757495 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.2690553297 |
|
|
Sep 25 01:15:49 AM UTC 24 |
Sep 25 01:16:38 AM UTC 24 |
443233751 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.3262435607 |
|
|
Sep 25 01:15:56 AM UTC 24 |
Sep 25 01:16:38 AM UTC 24 |
474349636 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2799444039 |
|
|
Sep 25 01:16:49 AM UTC 24 |
Sep 25 01:17:00 AM UTC 24 |
50711139 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.2202259842 |
|
|
Sep 25 01:16:48 AM UTC 24 |
Sep 25 01:17:01 AM UTC 24 |
189860578 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.368220916 |
|
|
Sep 25 01:03:00 AM UTC 24 |
Sep 25 01:17:02 AM UTC 24 |
7373624588 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3090184469 |
|
|
Sep 25 01:16:06 AM UTC 24 |
Sep 25 01:17:04 AM UTC 24 |
1182823462 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.1030093867 |
|
|
Sep 25 01:15:09 AM UTC 24 |
Sep 25 01:17:04 AM UTC 24 |
8369639648 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1066833570 |
|
|
Sep 25 01:10:00 AM UTC 24 |
Sep 25 01:17:05 AM UTC 24 |
11281288928 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2401729593 |
|
|
Sep 25 01:12:32 AM UTC 24 |
Sep 25 01:17:11 AM UTC 24 |
2989752527 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.3845456250 |
|
|
Sep 25 01:11:37 AM UTC 24 |
Sep 25 01:17:30 AM UTC 24 |
9869912577 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.968340577 |
|
|
Sep 25 01:16:16 AM UTC 24 |
Sep 25 01:17:39 AM UTC 24 |
891621068 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.1542205545 |
|
|
Sep 25 01:17:25 AM UTC 24 |
Sep 25 01:17:40 AM UTC 24 |
38725442 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.588797859 |
|
|
Sep 25 01:17:27 AM UTC 24 |
Sep 25 01:17:43 AM UTC 24 |
92458729 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.4128683432 |
|
|
Sep 25 01:17:00 AM UTC 24 |
Sep 25 01:17:44 AM UTC 24 |
1113722106 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3564709084 |
|
|
Sep 25 01:17:00 AM UTC 24 |
Sep 25 01:17:45 AM UTC 24 |
455482253 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3997224680 |
|
|
Sep 25 01:11:47 AM UTC 24 |
Sep 25 01:17:47 AM UTC 24 |
4806054167 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.1186214125 |
|
|
Sep 25 01:14:54 AM UTC 24 |
Sep 25 01:17:55 AM UTC 24 |
4289253076 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.4079069629 |
|
|
Sep 25 01:17:27 AM UTC 24 |
Sep 25 01:18:02 AM UTC 24 |
342590196 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.583909500 |
|
|
Sep 25 01:12:17 AM UTC 24 |
Sep 25 01:18:11 AM UTC 24 |
21894680765 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2594565916 |
|
|
Sep 25 01:18:09 AM UTC 24 |
Sep 25 01:18:20 AM UTC 24 |
225454134 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2726275203 |
|
|
Sep 25 01:18:08 AM UTC 24 |
Sep 25 01:18:20 AM UTC 24 |
54989826 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1869457325 |
|
|
Sep 25 01:16:51 AM UTC 24 |
Sep 25 01:18:28 AM UTC 24 |
4644726913 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2615603765 |
|
|
Sep 25 01:17:34 AM UTC 24 |
Sep 25 01:18:29 AM UTC 24 |
1073166100 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2726010683 |
|
|
Sep 25 01:17:51 AM UTC 24 |
Sep 25 01:18:37 AM UTC 24 |
1024276138 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.3995880498 |
|
|
Sep 25 01:10:06 AM UTC 24 |
Sep 25 01:18:46 AM UTC 24 |
11562767928 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.1030100070 |
|
|
Sep 25 01:02:15 AM UTC 24 |
Sep 25 01:18:51 AM UTC 24 |
89475055963 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3622321303 |
|
|
Sep 25 12:42:06 AM UTC 24 |
Sep 25 01:19:04 AM UTC 24 |
136815497029 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1543908225 |
|
|
Sep 25 01:18:33 AM UTC 24 |
Sep 25 01:19:05 AM UTC 24 |
294410462 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2657367387 |
|
|
Sep 25 01:18:19 AM UTC 24 |
Sep 25 01:19:27 AM UTC 24 |
7143839577 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.2232178951 |
|
|
Sep 25 01:01:17 AM UTC 24 |
Sep 25 01:19:30 AM UTC 24 |
95284471260 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1495128164 |
|
|
Sep 25 01:18:26 AM UTC 24 |
Sep 25 01:19:34 AM UTC 24 |
4358240302 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1271226926 |
|
|
Sep 25 01:18:41 AM UTC 24 |
Sep 25 01:19:36 AM UTC 24 |
595725033 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.532124431 |
|
|
Sep 25 01:09:35 AM UTC 24 |
Sep 25 01:19:43 AM UTC 24 |
35825317619 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2727306347 |
|
|
Sep 25 01:19:27 AM UTC 24 |
Sep 25 01:19:48 AM UTC 24 |
107008017 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.2784910253 |
|
|
Sep 25 01:19:24 AM UTC 24 |
Sep 25 01:19:56 AM UTC 24 |
465952818 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.80068409 |
|
|
Sep 25 01:14:56 AM UTC 24 |
Sep 25 01:19:56 AM UTC 24 |
6201059281 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.3986499604 |
|
|
Sep 25 01:19:08 AM UTC 24 |
Sep 25 01:19:58 AM UTC 24 |
1175804907 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.4024475640 |
|
|
Sep 25 01:19:13 AM UTC 24 |
Sep 25 01:20:05 AM UTC 24 |
467775470 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.66363807 |
|
|
Sep 25 01:16:51 AM UTC 24 |
Sep 25 01:20:08 AM UTC 24 |
10573771252 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.545516979 |
|
|
Sep 25 01:12:52 AM UTC 24 |
Sep 25 01:20:11 AM UTC 24 |
4359782609 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.3138444155 |
|
|
Sep 25 01:20:05 AM UTC 24 |
Sep 25 01:20:16 AM UTC 24 |
47023010 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.4263628658 |
|
|
Sep 25 01:20:08 AM UTC 24 |
Sep 25 01:20:19 AM UTC 24 |
39036863 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.619067371 |
|
|
Sep 25 01:04:39 AM UTC 24 |
Sep 25 01:20:28 AM UTC 24 |
56086256812 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1683391611 |
|
|
Sep 25 01:18:50 AM UTC 24 |
Sep 25 01:20:31 AM UTC 24 |
1813143790 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.27887040 |
|
|
Sep 25 01:19:59 AM UTC 24 |
Sep 25 01:20:36 AM UTC 24 |
10133983 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.194959966 |
|
|
Sep 25 01:14:42 AM UTC 24 |
Sep 25 01:20:36 AM UTC 24 |
1030183896 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.2970571263 |
|
|
Sep 25 01:12:30 AM UTC 24 |
Sep 25 01:20:40 AM UTC 24 |
11769145463 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1350472942 |
|
|
Sep 25 01:06:59 AM UTC 24 |
Sep 25 01:20:41 AM UTC 24 |
50687774301 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.1476442887 |
|
|
Sep 25 01:20:38 AM UTC 24 |
Sep 25 01:21:02 AM UTC 24 |
446419953 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3766670539 |
|
|
Sep 25 01:16:29 AM UTC 24 |
Sep 25 01:21:07 AM UTC 24 |
3655993100 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1964502085 |
|
|
Sep 25 01:10:16 AM UTC 24 |
Sep 25 01:21:19 AM UTC 24 |
16049612314 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.2452721887 |
|
|
Sep 25 01:18:01 AM UTC 24 |
Sep 25 01:21:20 AM UTC 24 |
5147270531 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2885343480 |
|
|
Sep 25 01:20:28 AM UTC 24 |
Sep 25 01:21:22 AM UTC 24 |
493987269 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.1179303145 |
|
|
Sep 25 01:20:54 AM UTC 24 |
Sep 25 01:21:26 AM UTC 24 |
965740202 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.2996486127 |
|
|
Sep 25 01:20:58 AM UTC 24 |
Sep 25 01:21:29 AM UTC 24 |
224667295 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.3999590426 |
|
|
Sep 25 01:20:20 AM UTC 24 |
Sep 25 01:21:32 AM UTC 24 |
1521185756 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1362921251 |
|
|
Sep 25 01:21:03 AM UTC 24 |
Sep 25 01:21:40 AM UTC 24 |
20244071 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3241108558 |
|
|
Sep 25 01:18:05 AM UTC 24 |
Sep 25 01:21:41 AM UTC 24 |
2509985816 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2740854941 |
|
|
Sep 25 01:20:59 AM UTC 24 |
Sep 25 01:21:43 AM UTC 24 |
695085255 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1012744317 |
|
|
Sep 25 01:20:18 AM UTC 24 |
Sep 25 01:21:47 AM UTC 24 |
6492671799 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1473468979 |
|
|
Sep 25 01:21:42 AM UTC 24 |
Sep 25 01:21:52 AM UTC 24 |
155368268 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1793466929 |
|
|
Sep 25 01:21:42 AM UTC 24 |
Sep 25 01:21:52 AM UTC 24 |
44752883 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.1645532913 |
|
|
Sep 25 01:20:48 AM UTC 24 |
Sep 25 01:22:01 AM UTC 24 |
1970107271 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.2720304277 |
|
|
Sep 25 01:19:48 AM UTC 24 |
Sep 25 01:22:03 AM UTC 24 |
1480705417 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.1894172681 |
|
|
Sep 25 01:17:22 AM UTC 24 |
Sep 25 01:22:06 AM UTC 24 |
20426933028 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1430287409 |
|
|
Sep 25 01:20:18 AM UTC 24 |
Sep 25 01:22:21 AM UTC 24 |
8132768463 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2861347697 |
|
|
Sep 25 01:22:11 AM UTC 24 |
Sep 25 01:22:27 AM UTC 24 |
473545271 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3016880220 |
|
|
Sep 25 01:07:01 AM UTC 24 |
Sep 25 01:22:28 AM UTC 24 |
83759723889 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.922341267 |
|
|
Sep 25 01:21:54 AM UTC 24 |
Sep 25 01:22:41 AM UTC 24 |
378566128 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.905431457 |
|
|
Sep 25 01:11:35 AM UTC 24 |
Sep 25 01:22:50 AM UTC 24 |
11196529348 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.2223276606 |
|
|
Sep 25 01:21:52 AM UTC 24 |
Sep 25 01:22:51 AM UTC 24 |
1522240863 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.837414301 |
|
|
Sep 25 01:22:24 AM UTC 24 |
Sep 25 01:22:54 AM UTC 24 |
147796630 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1411385959 |
|
|
Sep 25 01:22:15 AM UTC 24 |
Sep 25 01:23:02 AM UTC 24 |
548612540 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.530840936 |
|
|
Sep 25 01:22:27 AM UTC 24 |
Sep 25 01:23:02 AM UTC 24 |
303280856 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1235806972 |
|
|
Sep 25 01:22:26 AM UTC 24 |
Sep 25 01:23:02 AM UTC 24 |
268326359 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3937375928 |
|
|
Sep 25 01:15:45 AM UTC 24 |
Sep 25 01:23:06 AM UTC 24 |
26261574534 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.2162187191 |
|
|
Sep 25 01:23:02 AM UTC 24 |
Sep 25 01:23:15 AM UTC 24 |
50341553 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1120189031 |
|
|
Sep 25 01:21:39 AM UTC 24 |
Sep 25 01:23:15 AM UTC 24 |
7787419580 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1774850797 |
|
|
Sep 25 01:22:05 AM UTC 24 |
Sep 25 01:23:19 AM UTC 24 |
1213262445 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.979708 |
|
|
Sep 25 01:23:12 AM UTC 24 |
Sep 25 01:23:20 AM UTC 24 |
36040935 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2962082109 |
|
|
Sep 25 01:22:43 AM UTC 24 |
Sep 25 01:23:26 AM UTC 24 |
111425991 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1768953991 |
|
|
Sep 25 01:08:00 AM UTC 24 |
Sep 25 01:23:30 AM UTC 24 |
7995758916 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3779593990 |
|
|
Sep 25 01:23:26 AM UTC 24 |
Sep 25 01:23:43 AM UTC 24 |
234096578 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1723237705 |
|
|
Sep 25 01:19:57 AM UTC 24 |
Sep 25 01:23:44 AM UTC 24 |
2355558034 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.449176192 |
|
|
Sep 25 01:12:18 AM UTC 24 |
Sep 25 01:23:46 AM UTC 24 |
65234012403 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.4131572514 |
|
|
Sep 25 01:21:48 AM UTC 24 |
Sep 25 01:23:47 AM UTC 24 |
4603764781 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.206893663 |
|
|
Sep 25 01:23:35 AM UTC 24 |
Sep 25 01:23:52 AM UTC 24 |
225187006 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3126888770 |
|
|
Sep 25 01:22:03 AM UTC 24 |
Sep 25 01:24:01 AM UTC 24 |
6181267483 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2179895160 |
|
|
Sep 25 01:23:25 AM UTC 24 |
Sep 25 01:24:07 AM UTC 24 |
382315367 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.3356346067 |
|
|
Sep 25 01:22:49 AM UTC 24 |
Sep 25 01:24:10 AM UTC 24 |
1038734208 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1090715069 |
|
|
Sep 25 01:23:38 AM UTC 24 |
Sep 25 01:24:13 AM UTC 24 |
682765429 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1085736876 |
|
|
Sep 25 01:23:17 AM UTC 24 |
Sep 25 01:24:24 AM UTC 24 |
3275289853 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.2950715335 |
|
|
Sep 25 01:24:12 AM UTC 24 |
Sep 25 01:24:25 AM UTC 24 |
221385568 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.3984427513 |
|
|
Sep 25 01:23:47 AM UTC 24 |
Sep 25 01:24:31 AM UTC 24 |
676843777 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3112689814 |
|
|
Sep 25 01:24:22 AM UTC 24 |
Sep 25 01:24:32 AM UTC 24 |
48390046 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.286919268 |
|
|
Sep 25 01:23:14 AM UTC 24 |
Sep 25 01:24:39 AM UTC 24 |
6541609168 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2021032215 |
|
|
Sep 25 01:23:42 AM UTC 24 |
Sep 25 01:24:41 AM UTC 24 |
529290356 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.3265869172 |
|
|
Sep 25 01:05:45 AM UTC 24 |
Sep 25 01:24:50 AM UTC 24 |
99641195586 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.234980888 |
|
|
Sep 25 01:13:02 AM UTC 24 |
Sep 25 01:24:50 AM UTC 24 |
13422627229 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3245788753 |
|
|
Sep 25 12:54:17 AM UTC 24 |
Sep 25 01:24:51 AM UTC 24 |
105125255380 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2394219501 |
|
|
Sep 25 01:13:51 AM UTC 24 |
Sep 25 01:24:52 AM UTC 24 |
60087001212 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3906055303 |
|
|
Sep 25 01:24:41 AM UTC 24 |
Sep 25 01:24:52 AM UTC 24 |
34280859 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1926413299 |
|
|
Sep 25 01:16:43 AM UTC 24 |
Sep 25 01:24:56 AM UTC 24 |
3825792629 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3057461152 |
|
|
Sep 25 01:23:52 AM UTC 24 |
Sep 25 01:25:00 AM UTC 24 |
1209024568 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.753553763 |
|
|
Sep 25 01:03:35 AM UTC 24 |
Sep 25 01:25:09 AM UTC 24 |
113127730013 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2863492111 |
|
|
Sep 25 01:21:25 AM UTC 24 |
Sep 25 01:25:14 AM UTC 24 |
6380220721 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2500922780 |
|
|
Sep 25 01:19:53 AM UTC 24 |
Sep 25 01:25:19 AM UTC 24 |
3105357212 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.4044275370 |
|
|
Sep 25 01:24:35 AM UTC 24 |
Sep 25 01:25:22 AM UTC 24 |
1172886010 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1296274616 |
|
|
Sep 25 01:21:28 AM UTC 24 |
Sep 25 01:25:27 AM UTC 24 |
885209493 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.1001191999 |
|
|
Sep 25 01:25:12 AM UTC 24 |
Sep 25 01:25:34 AM UTC 24 |
294569340 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3317995005 |
|
|
Sep 25 01:24:30 AM UTC 24 |
Sep 25 01:25:34 AM UTC 24 |
3447068715 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3371933890 |
|
|
Sep 25 01:25:01 AM UTC 24 |
Sep 25 01:25:36 AM UTC 24 |
287622289 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1417871628 |
|
|
Sep 25 01:25:32 AM UTC 24 |
Sep 25 01:25:43 AM UTC 24 |
215608826 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.351650805 |
|
|
Sep 25 01:25:37 AM UTC 24 |
Sep 25 01:25:47 AM UTC 24 |
48737046 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.433278086 |
|
|
Sep 25 01:09:32 AM UTC 24 |
Sep 25 01:25:48 AM UTC 24 |
61504501773 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.642604115 |
|
|
Sep 25 01:25:12 AM UTC 24 |
Sep 25 01:25:52 AM UTC 24 |
255264738 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1074768693 |
|
|
Sep 25 01:25:20 AM UTC 24 |
Sep 25 01:25:57 AM UTC 24 |
482863093 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.2168390962 |
|
|
Sep 25 01:08:26 AM UTC 24 |
Sep 25 01:25:59 AM UTC 24 |
63731804899 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.4159325977 |
|
|
Sep 25 01:25:48 AM UTC 24 |
Sep 25 01:26:00 AM UTC 24 |
143381090 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3580682707 |
|
|
Sep 25 12:49:40 AM UTC 24 |
Sep 25 01:26:04 AM UTC 24 |
128862768876 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2486431441 |
|
|
Sep 25 01:25:56 AM UTC 24 |
Sep 25 01:26:07 AM UTC 24 |
32564557 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2557033292 |
|
|
Sep 25 01:25:11 AM UTC 24 |
Sep 25 01:26:11 AM UTC 24 |
583066351 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2221832383 |
|
|
Sep 25 01:17:23 AM UTC 24 |
Sep 25 01:26:16 AM UTC 24 |
32471369602 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1497324378 |
|
|
Sep 25 01:18:04 AM UTC 24 |
Sep 25 01:26:23 AM UTC 24 |
3792479621 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3857718960 |
|
|
Sep 25 01:26:15 AM UTC 24 |
Sep 25 01:26:24 AM UTC 24 |
31948472 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.286561320 |
|
|
Sep 25 01:24:26 AM UTC 24 |
Sep 25 01:26:24 AM UTC 24 |
9648576593 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.3402043544 |
|
|
Sep 25 01:14:37 AM UTC 24 |
Sep 25 01:26:32 AM UTC 24 |
16547549742 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.838032083 |
|
|
Sep 25 01:26:27 AM UTC 24 |
Sep 25 01:26:33 AM UTC 24 |
6402570 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.4270039118 |
|
|
Sep 25 01:24:54 AM UTC 24 |
Sep 25 01:26:38 AM UTC 24 |
2432190992 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2817399490 |
|
|
Sep 25 01:26:11 AM UTC 24 |
Sep 25 01:26:47 AM UTC 24 |
363499594 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.56988243 |
|
|
Sep 25 01:17:27 AM UTC 24 |
Sep 25 01:26:47 AM UTC 24 |
31524001264 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.3369887533 |
|
|
Sep 25 01:26:37 AM UTC 24 |
Sep 25 01:26:48 AM UTC 24 |
52737721 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.298102357 |
|
|
Sep 25 01:09:29 AM UTC 24 |
Sep 25 01:26:48 AM UTC 24 |
82463100252 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.4030718626 |
|
|
Sep 25 01:26:21 AM UTC 24 |
Sep 25 01:26:53 AM UTC 24 |
236109881 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2423726783 |
|
|
Sep 25 01:26:45 AM UTC 24 |
Sep 25 01:26:54 AM UTC 24 |
44555180 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.745100316 |
|
|
Sep 25 01:15:40 AM UTC 24 |
Sep 25 01:27:00 AM UTC 24 |
38808511280 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.2538301759 |
|
|
Sep 25 01:25:57 AM UTC 24 |
Sep 25 01:27:04 AM UTC 24 |
4730987997 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.461002134 |
|
|
Sep 25 01:26:54 AM UTC 24 |
Sep 25 01:27:05 AM UTC 24 |
75446566 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.3263068100 |
|
|
Sep 25 01:26:18 AM UTC 24 |
Sep 25 01:27:10 AM UTC 24 |
1096863636 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3901589012 |
|
|
Sep 25 01:02:23 AM UTC 24 |
Sep 25 01:27:11 AM UTC 24 |
91374469706 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2091219451 |
|
|
Sep 25 01:22:08 AM UTC 24 |
Sep 25 01:27:18 AM UTC 24 |
19244710008 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.2690371270 |
|
|
Sep 25 01:26:04 AM UTC 24 |
Sep 25 01:27:22 AM UTC 24 |
1446247705 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.110576760 |
|
|
Sep 25 01:18:50 AM UTC 24 |
Sep 25 01:27:25 AM UTC 24 |
32309785648 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.246122507 |
|
|
Sep 25 01:25:45 AM UTC 24 |
Sep 25 01:27:25 AM UTC 24 |
4981136149 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.917071036 |
|
|
Sep 25 01:25:42 AM UTC 24 |
Sep 25 01:27:29 AM UTC 24 |
9904490479 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1680174651 |
|
|
Sep 25 01:25:13 AM UTC 24 |
Sep 25 01:27:30 AM UTC 24 |
150215329 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.4042529576 |
|
|
Sep 25 01:24:05 AM UTC 24 |
Sep 25 01:27:32 AM UTC 24 |
5137713460 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.3723234519 |
|
|
Sep 25 01:27:10 AM UTC 24 |
Sep 25 01:27:39 AM UTC 24 |
370431654 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1375845666 |
|
|
Sep 25 01:27:34 AM UTC 24 |
Sep 25 01:27:47 AM UTC 24 |
12695636 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.2035705224 |
|
|
Sep 25 01:10:56 AM UTC 24 |
Sep 25 01:27:48 AM UTC 24 |
65788925255 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.3502926857 |
|
|
Sep 25 01:27:32 AM UTC 24 |
Sep 25 01:27:51 AM UTC 24 |
218555314 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.241284907 |
|
|
Sep 25 01:27:40 AM UTC 24 |
Sep 25 01:27:54 AM UTC 24 |
162987288 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.1573089109 |
|
|
Sep 25 01:27:12 AM UTC 24 |
Sep 25 01:27:55 AM UTC 24 |
1030924712 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.543528753 |
|
|
Sep 25 01:27:45 AM UTC 24 |
Sep 25 01:27:56 AM UTC 24 |
50831336 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.228418380 |
|
|
Sep 25 01:26:55 AM UTC 24 |
Sep 25 01:27:56 AM UTC 24 |
507035215 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3590731543 |
|
|
Sep 25 01:08:24 AM UTC 24 |
Sep 25 01:27:57 AM UTC 24 |
90940050202 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.145855177 |
|
|
Sep 25 01:27:14 AM UTC 24 |
Sep 25 01:27:58 AM UTC 24 |
322914098 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.632864352 |
|
|
Sep 25 01:21:00 AM UTC 24 |
Sep 25 01:28:01 AM UTC 24 |
4392345399 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.348441707 |
|
|
Sep 25 01:26:45 AM UTC 24 |
Sep 25 01:28:01 AM UTC 24 |
7168091296 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3442117738 |
|
|
Sep 25 01:27:23 AM UTC 24 |
Sep 25 01:28:08 AM UTC 24 |
906658951 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.2812971159 |
|
|
Sep 25 01:25:58 AM UTC 24 |
Sep 25 01:28:11 AM UTC 24 |
7572499567 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1750778181 |
|
|
Sep 25 01:27:25 AM UTC 24 |
Sep 25 01:28:13 AM UTC 24 |
1278922456 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.979133220 |
|
|
Sep 25 01:26:22 AM UTC 24 |
Sep 25 01:28:13 AM UTC 24 |
1045476560 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2585820020 |
|
|
Sep 25 01:10:58 AM UTC 24 |
Sep 25 01:28:13 AM UTC 24 |
97655195166 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.1420355293 |
|
|
Sep 25 01:27:50 AM UTC 24 |
Sep 25 01:28:20 AM UTC 24 |
582584673 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1618736788 |
|
|
Sep 25 01:28:23 AM UTC 24 |
Sep 25 01:28:33 AM UTC 24 |
46205037 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.1645190469 |
|
|
Sep 25 01:27:51 AM UTC 24 |
Sep 25 01:28:36 AM UTC 24 |
457701697 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2438593962 |
|
|
Sep 25 01:28:21 AM UTC 24 |
Sep 25 01:28:36 AM UTC 24 |
232376601 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2889445734 |
|
|
Sep 25 01:28:12 AM UTC 24 |
Sep 25 01:28:51 AM UTC 24 |
317052195 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.525493239 |
|
|
Sep 25 01:27:08 AM UTC 24 |
Sep 25 01:28:54 AM UTC 24 |
1892473240 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3124753070 |
|
|
Sep 25 01:28:16 AM UTC 24 |
Sep 25 01:28:55 AM UTC 24 |
884638074 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.3739223847 |
|
|
Sep 25 01:28:13 AM UTC 24 |
Sep 25 01:28:56 AM UTC 24 |
1395118867 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.1727118143 |
|
|
Sep 25 01:28:13 AM UTC 24 |
Sep 25 01:28:57 AM UTC 24 |
329410477 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2997782819 |
|
|
Sep 25 01:26:48 AM UTC 24 |
Sep 25 01:29:05 AM UTC 24 |
5727978602 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3282781872 |
|
|
Sep 25 01:03:40 AM UTC 24 |
Sep 25 01:29:08 AM UTC 24 |
99929482702 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1857804171 |
|
|
Sep 25 01:28:20 AM UTC 24 |
Sep 25 01:29:14 AM UTC 24 |
144355496 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1369995916 |
|
|
Sep 25 12:59:07 AM UTC 24 |
Sep 25 01:29:17 AM UTC 24 |
108718835967 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2345233522 |
|
|
Sep 25 01:28:35 AM UTC 24 |
Sep 25 01:29:23 AM UTC 24 |
536397015 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.277443238 |
|
|
Sep 25 01:13:57 AM UTC 24 |
Sep 25 01:29:37 AM UTC 24 |
58026315813 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3242799418 |
|
|
Sep 25 01:24:06 AM UTC 24 |
Sep 25 01:29:38 AM UTC 24 |
3863395335 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1740458460 |
|
|
Sep 25 01:29:15 AM UTC 24 |
Sep 25 01:29:39 AM UTC 24 |
738004848 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3062981887 |
|
|
Sep 25 01:29:18 AM UTC 24 |
Sep 25 01:29:44 AM UTC 24 |
211923726 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2889067474 |
|
|
Sep 25 01:28:07 AM UTC 24 |
Sep 25 01:29:51 AM UTC 24 |
1091787361 ps |