| T2027 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.850187324 |
|
|
Sep 25 12:51:37 AM UTC 24 |
Sep 25 12:52:21 AM UTC 24 |
275278945 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1350425466 |
|
|
Sep 25 12:51:04 AM UTC 24 |
Sep 25 12:52:24 AM UTC 24 |
629342105 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.3654234168 |
|
|
Sep 25 12:52:01 AM UTC 24 |
Sep 25 12:52:26 AM UTC 24 |
183098636 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.1960830365 |
|
|
Sep 25 12:52:02 AM UTC 24 |
Sep 25 12:52:47 AM UTC 24 |
482274470 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.33612708 |
|
|
Sep 25 12:44:01 AM UTC 24 |
Sep 25 12:52:50 AM UTC 24 |
12427543775 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1309000679 |
|
|
Sep 25 12:52:01 AM UTC 24 |
Sep 25 12:53:01 AM UTC 24 |
3840331741 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2614298882 |
|
|
Sep 25 12:51:38 AM UTC 24 |
Sep 25 12:53:03 AM UTC 24 |
1441967941 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2300762095 |
|
|
Sep 25 12:50:01 AM UTC 24 |
Sep 25 12:53:06 AM UTC 24 |
4780445152 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.3902856426 |
|
|
Sep 25 12:51:59 AM UTC 24 |
Sep 25 12:53:27 AM UTC 24 |
5856769399 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.4033700012 |
|
|
Sep 25 12:52:47 AM UTC 24 |
Sep 25 12:53:29 AM UTC 24 |
233774198 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1808423169 |
|
|
Sep 25 12:53:25 AM UTC 24 |
Sep 25 12:53:31 AM UTC 24 |
5778363 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3181974626 |
|
|
Sep 25 12:52:49 AM UTC 24 |
Sep 25 12:53:32 AM UTC 24 |
987127247 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.3004776016 |
|
|
Sep 25 12:53:27 AM UTC 24 |
Sep 25 12:53:40 AM UTC 24 |
226362018 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.2227142474 |
|
|
Sep 25 12:52:43 AM UTC 24 |
Sep 25 12:53:50 AM UTC 24 |
1754461803 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.437316611 |
|
|
Sep 25 12:52:28 AM UTC 24 |
Sep 25 12:53:52 AM UTC 24 |
2200901810 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.413595542 |
|
|
Sep 25 12:42:40 AM UTC 24 |
Sep 25 12:53:54 AM UTC 24 |
16307087790 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3818028449 |
|
|
Sep 25 12:53:48 AM UTC 24 |
Sep 25 12:53:55 AM UTC 24 |
46262807 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.3643048344 |
|
|
Sep 25 12:52:18 AM UTC 24 |
Sep 25 12:54:00 AM UTC 24 |
2038328161 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.586725048 |
|
|
Sep 25 12:53:14 AM UTC 24 |
Sep 25 12:54:03 AM UTC 24 |
128261581 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2740890046 |
|
|
Sep 25 12:51:43 AM UTC 24 |
Sep 25 12:54:08 AM UTC 24 |
1183636731 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.910398005 |
|
|
Sep 25 12:51:44 AM UTC 24 |
Sep 25 12:54:16 AM UTC 24 |
274699935 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3802055218 |
|
|
Sep 25 12:53:25 AM UTC 24 |
Sep 25 12:54:24 AM UTC 24 |
253986230 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3557983934 |
|
|
Sep 25 12:48:39 AM UTC 24 |
Sep 25 12:54:25 AM UTC 24 |
1218126965 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.15415363 |
|
|
Sep 25 12:47:43 AM UTC 24 |
Sep 25 12:54:26 AM UTC 24 |
3899499963 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1030620380 |
|
|
Sep 25 12:53:54 AM UTC 24 |
Sep 25 12:54:38 AM UTC 24 |
442344751 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2549045627 |
|
|
Sep 25 12:54:23 AM UTC 24 |
Sep 25 12:54:46 AM UTC 24 |
744117745 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.1578743353 |
|
|
Sep 25 12:54:02 AM UTC 24 |
Sep 25 12:54:52 AM UTC 24 |
593781020 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.4284480252 |
|
|
Sep 25 12:53:51 AM UTC 24 |
Sep 25 12:54:53 AM UTC 24 |
5337410782 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.638123492 |
|
|
Sep 25 12:54:16 AM UTC 24 |
Sep 25 12:54:55 AM UTC 24 |
455240980 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.511769083 |
|
|
Sep 25 12:54:31 AM UTC 24 |
Sep 25 12:55:05 AM UTC 24 |
713211194 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.1316427381 |
|
|
Sep 25 12:54:25 AM UTC 24 |
Sep 25 12:55:17 AM UTC 24 |
959188953 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3446929812 |
|
|
Sep 25 12:46:56 AM UTC 24 |
Sep 25 12:55:22 AM UTC 24 |
28732184421 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.4242302542 |
|
|
Sep 25 12:55:07 AM UTC 24 |
Sep 25 12:55:23 AM UTC 24 |
217777984 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2870274877 |
|
|
Sep 25 12:55:15 AM UTC 24 |
Sep 25 12:55:25 AM UTC 24 |
42799369 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3190695736 |
|
|
Sep 25 12:54:38 AM UTC 24 |
Sep 25 12:55:26 AM UTC 24 |
933573323 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2294852517 |
|
|
Sep 25 12:54:59 AM UTC 24 |
Sep 25 12:55:28 AM UTC 24 |
70569683 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2037807790 |
|
|
Sep 25 12:47:18 AM UTC 24 |
Sep 25 12:55:35 AM UTC 24 |
10913312863 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.557167200 |
|
|
Sep 25 12:48:01 AM UTC 24 |
Sep 25 12:55:35 AM UTC 24 |
44873964362 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.205139717 |
|
|
Sep 25 12:53:53 AM UTC 24 |
Sep 25 12:55:40 AM UTC 24 |
5508549330 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.3994392212 |
|
|
Sep 25 12:55:57 AM UTC 24 |
Sep 25 12:56:09 AM UTC 24 |
58832137 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.339166862 |
|
|
Sep 25 12:55:40 AM UTC 24 |
Sep 25 12:56:15 AM UTC 24 |
281512669 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1196655722 |
|
|
Sep 25 12:50:09 AM UTC 24 |
Sep 25 12:56:17 AM UTC 24 |
3250387488 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.493982370 |
|
|
Sep 25 12:34:20 AM UTC 24 |
Sep 25 12:56:23 AM UTC 24 |
111879690118 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.1948940175 |
|
|
Sep 25 12:55:59 AM UTC 24 |
Sep 25 12:56:26 AM UTC 24 |
316448077 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1465931257 |
|
|
Sep 25 12:56:02 AM UTC 24 |
Sep 25 12:56:38 AM UTC 24 |
273969527 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1721377984 |
|
|
Sep 25 12:55:45 AM UTC 24 |
Sep 25 12:56:41 AM UTC 24 |
1330636781 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.1459139475 |
|
|
Sep 25 12:44:53 AM UTC 24 |
Sep 25 01:01:04 AM UTC 24 |
87182019552 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.3370389485 |
|
|
Sep 25 12:55:28 AM UTC 24 |
Sep 25 12:56:42 AM UTC 24 |
2038734578 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.1742933486 |
|
|
Sep 25 12:55:51 AM UTC 24 |
Sep 25 12:56:54 AM UTC 24 |
1410181100 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.4125865754 |
|
|
Sep 25 12:54:50 AM UTC 24 |
Sep 25 12:56:56 AM UTC 24 |
3240507748 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3209102305 |
|
|
Sep 25 12:56:44 AM UTC 24 |
Sep 25 12:56:57 AM UTC 24 |
192020092 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3223032005 |
|
|
Sep 25 12:50:03 AM UTC 24 |
Sep 25 12:57:02 AM UTC 24 |
1287637437 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2958514442 |
|
|
Sep 25 12:57:01 AM UTC 24 |
Sep 25 12:57:09 AM UTC 24 |
49939650 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1104475365 |
|
|
Sep 25 12:55:18 AM UTC 24 |
Sep 25 12:57:17 AM UTC 24 |
5521717041 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.3084308793 |
|
|
Sep 25 12:57:17 AM UTC 24 |
Sep 25 12:57:31 AM UTC 24 |
61662184 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.3095432912 |
|
|
Sep 25 12:51:49 AM UTC 24 |
Sep 25 12:57:35 AM UTC 24 |
4308214721 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.1813825876 |
|
|
Sep 24 11:55:34 PM UTC 24 |
Sep 25 12:57:35 AM UTC 24 |
31243033048 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.3391031765 |
|
|
Sep 25 12:55:16 AM UTC 24 |
Sep 25 12:57:36 AM UTC 24 |
10684121929 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3420700301 |
|
|
Sep 25 12:53:10 AM UTC 24 |
Sep 25 12:57:40 AM UTC 24 |
2983233467 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.2283252704 |
|
|
Sep 24 11:53:12 PM UTC 24 |
Sep 25 12:57:47 AM UTC 24 |
30022843936 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.44152685 |
|
|
Sep 25 12:57:17 AM UTC 24 |
Sep 25 12:57:49 AM UTC 24 |
253375784 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.425501394 |
|
|
Sep 25 12:46:22 AM UTC 24 |
Sep 25 12:57:49 AM UTC 24 |
17626440974 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2904127501 |
|
|
Sep 25 12:38:52 AM UTC 24 |
Sep 25 12:57:54 AM UTC 24 |
71016263934 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3567836232 |
|
|
Sep 25 12:50:46 AM UTC 24 |
Sep 25 12:58:01 AM UTC 24 |
45280425635 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.3990679659 |
|
|
Sep 25 12:54:14 AM UTC 24 |
Sep 25 12:58:02 AM UTC 24 |
16885193157 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.3260044618 |
|
|
Sep 25 12:57:58 AM UTC 24 |
Sep 25 12:58:24 AM UTC 24 |
233036467 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2434770269 |
|
|
Sep 25 12:58:17 AM UTC 24 |
Sep 25 12:58:28 AM UTC 24 |
33705882 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2062191372 |
|
|
Sep 25 12:58:26 AM UTC 24 |
Sep 25 12:58:38 AM UTC 24 |
59045650 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.3717947027 |
|
|
Sep 25 12:51:01 AM UTC 24 |
Sep 25 12:58:39 AM UTC 24 |
23034965996 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1043165636 |
|
|
Sep 25 12:57:38 AM UTC 24 |
Sep 25 12:58:42 AM UTC 24 |
2801268615 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1059331865 |
|
|
Sep 25 12:54:48 AM UTC 24 |
Sep 25 12:58:43 AM UTC 24 |
602481273 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1280878929 |
|
|
Sep 25 12:58:13 AM UTC 24 |
Sep 25 12:58:44 AM UTC 24 |
85027346 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.631874489 |
|
|
Sep 25 12:57:59 AM UTC 24 |
Sep 25 12:58:46 AM UTC 24 |
808995139 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.2247702045 |
|
|
Sep 25 12:57:58 AM UTC 24 |
Sep 25 12:58:57 AM UTC 24 |
901966033 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.130006828 |
|
|
Sep 25 12:51:48 AM UTC 24 |
Sep 25 12:58:59 AM UTC 24 |
2468714210 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2181208990 |
|
|
Sep 25 12:42:41 AM UTC 24 |
Sep 25 12:58:59 AM UTC 24 |
10460960697 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.3089206272 |
|
|
Sep 25 12:46:04 AM UTC 24 |
Sep 25 12:59:01 AM UTC 24 |
53599112963 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.552687544 |
|
|
Sep 25 12:57:04 AM UTC 24 |
Sep 25 12:59:04 AM UTC 24 |
9152212477 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3017639089 |
|
|
Sep 25 12:57:04 AM UTC 24 |
Sep 25 12:59:10 AM UTC 24 |
6120701710 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.3121046075 |
|
|
Sep 25 12:57:53 AM UTC 24 |
Sep 25 12:59:12 AM UTC 24 |
1965402295 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2656193077 |
|
|
Sep 25 12:47:09 AM UTC 24 |
Sep 25 12:59:14 AM UTC 24 |
47876136954 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3596189795 |
|
|
Sep 25 12:56:44 AM UTC 24 |
Sep 25 12:59:19 AM UTC 24 |
610403878 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.1242488603 |
|
|
Sep 25 12:59:08 AM UTC 24 |
Sep 25 12:59:21 AM UTC 24 |
326027188 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.620225620 |
|
|
Sep 25 12:59:19 AM UTC 24 |
Sep 25 12:59:27 AM UTC 24 |
25915955 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.3880699690 |
|
|
Sep 25 12:58:52 AM UTC 24 |
Sep 25 12:59:30 AM UTC 24 |
760567425 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.141223805 |
|
|
Sep 25 12:59:02 AM UTC 24 |
Sep 25 12:59:32 AM UTC 24 |
274906517 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.1569385708 |
|
|
Sep 25 12:58:25 AM UTC 24 |
Sep 25 12:59:42 AM UTC 24 |
6486318718 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3251187445 |
|
|
Sep 25 12:59:34 AM UTC 24 |
Sep 25 12:59:47 AM UTC 24 |
217337626 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3989164234 |
|
|
Sep 25 12:59:41 AM UTC 24 |
Sep 25 12:59:51 AM UTC 24 |
52402801 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1738679130 |
|
|
Sep 25 12:49:40 AM UTC 24 |
Sep 25 12:59:54 AM UTC 24 |
42212971714 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.4275436766 |
|
|
Sep 25 12:40:59 AM UTC 24 |
Sep 25 12:59:59 AM UTC 24 |
70557204857 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2158553679 |
|
|
Sep 25 12:59:19 AM UTC 24 |
Sep 25 01:00:03 AM UTC 24 |
698355528 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1559843137 |
|
|
Sep 25 12:58:45 AM UTC 24 |
Sep 25 01:00:05 AM UTC 24 |
4800036241 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2610091963 |
|
|
Sep 25 12:48:52 AM UTC 24 |
Sep 25 01:00:09 AM UTC 24 |
10458920095 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3254939722 |
|
|
Sep 25 12:57:24 AM UTC 24 |
Sep 25 01:00:17 AM UTC 24 |
10275337824 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2263613557 |
|
|
Sep 25 12:59:53 AM UTC 24 |
Sep 25 01:00:18 AM UTC 24 |
169988883 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.513692079 |
|
|
Sep 25 12:39:45 AM UTC 24 |
Sep 25 01:00:20 AM UTC 24 |
100264929179 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.64507887 |
|
|
Sep 25 12:57:30 AM UTC 24 |
Sep 25 01:00:22 AM UTC 24 |
3478621094 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2576370958 |
|
|
Sep 25 12:54:12 AM UTC 24 |
Sep 25 01:00:29 AM UTC 24 |
31721748358 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.3032669460 |
|
|
Sep 25 12:54:46 AM UTC 24 |
Sep 25 01:00:31 AM UTC 24 |
4175353065 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.318063528 |
|
|
Sep 25 12:59:19 AM UTC 24 |
Sep 25 01:00:32 AM UTC 24 |
1780979676 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.304302036 |
|
|
Sep 25 12:59:52 AM UTC 24 |
Sep 25 01:00:37 AM UTC 24 |
423908731 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3845798895 |
|
|
Sep 25 01:00:21 AM UTC 24 |
Sep 25 01:00:54 AM UTC 24 |
306544112 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.3504111260 |
|
|
Sep 25 01:00:29 AM UTC 24 |
Sep 25 01:00:56 AM UTC 24 |
770781592 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1617674378 |
|
|
Sep 25 12:40:57 AM UTC 24 |
Sep 25 01:00:57 AM UTC 24 |
63262411207 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.3668514579 |
|
|
Sep 25 12:59:30 AM UTC 24 |
Sep 25 01:00:59 AM UTC 24 |
1079053650 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3566904937 |
|
|
Sep 25 12:59:06 AM UTC 24 |
Sep 25 01:01:01 AM UTC 24 |
2301375611 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.666651824 |
|
|
Sep 25 01:00:49 AM UTC 24 |
Sep 25 01:01:02 AM UTC 24 |
169441735 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3723076062 |
|
|
Sep 25 01:00:52 AM UTC 24 |
Sep 25 01:01:02 AM UTC 24 |
56685885 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1398442443 |
|
|
Sep 25 01:00:31 AM UTC 24 |
Sep 25 01:01:03 AM UTC 24 |
699754663 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2857581739 |
|
|
Sep 25 01:00:13 AM UTC 24 |
Sep 25 01:01:07 AM UTC 24 |
555244837 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.770506071 |
|
|
Sep 25 12:59:44 AM UTC 24 |
Sep 25 01:01:07 AM UTC 24 |
6167889126 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.1716792767 |
|
|
Sep 25 01:00:28 AM UTC 24 |
Sep 25 01:01:16 AM UTC 24 |
895939045 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1930863775 |
|
|
Sep 25 12:43:29 AM UTC 24 |
Sep 25 01:01:16 AM UTC 24 |
63683284169 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1968565840 |
|
|
Sep 25 12:56:33 AM UTC 24 |
Sep 25 01:01:17 AM UTC 24 |
7947838484 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3589000018 |
|
|
Sep 25 12:55:45 AM UTC 24 |
Sep 25 01:01:25 AM UTC 24 |
30486749272 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3644286946 |
|
|
Sep 25 12:56:37 AM UTC 24 |
Sep 25 01:01:27 AM UTC 24 |
488171994 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.3537069143 |
|
|
Sep 25 12:59:51 AM UTC 24 |
Sep 25 01:01:32 AM UTC 24 |
6231896260 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3254025349 |
|
|
Sep 25 12:46:06 AM UTC 24 |
Sep 25 01:01:35 AM UTC 24 |
56274470954 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.477800571 |
|
|
Sep 25 01:01:25 AM UTC 24 |
Sep 25 01:01:38 AM UTC 24 |
56380519 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2238404471 |
|
|
Sep 25 12:41:59 AM UTC 24 |
Sep 25 01:01:45 AM UTC 24 |
108367471594 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3412668410 |
|
|
Sep 25 01:01:46 AM UTC 24 |
Sep 25 01:01:54 AM UTC 24 |
53955157 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.3611767605 |
|
|
Sep 25 01:01:46 AM UTC 24 |
Sep 25 01:01:59 AM UTC 24 |
218235103 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.1706990143 |
|
|
Sep 25 01:01:21 AM UTC 24 |
Sep 25 01:02:01 AM UTC 24 |
857334067 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.192960906 |
|
|
Sep 25 01:01:21 AM UTC 24 |
Sep 25 01:02:03 AM UTC 24 |
934004056 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.486518821 |
|
|
Sep 25 01:01:22 AM UTC 24 |
Sep 25 01:02:05 AM UTC 24 |
1021848454 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.585455192 |
|
|
Sep 25 01:00:52 AM UTC 24 |
Sep 25 01:02:18 AM UTC 24 |
6757712084 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.354891471 |
|
|
Sep 25 01:01:15 AM UTC 24 |
Sep 25 01:02:20 AM UTC 24 |
577527339 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2161741701 |
|
|
Sep 25 01:00:57 AM UTC 24 |
Sep 25 01:02:25 AM UTC 24 |
5205946983 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1715763041 |
|
|
Sep 25 01:01:27 AM UTC 24 |
Sep 25 01:02:30 AM UTC 24 |
1171244329 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2252106488 |
|
|
Sep 25 01:01:26 AM UTC 24 |
Sep 25 01:02:30 AM UTC 24 |
1198748698 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.4027945075 |
|
|
Sep 25 12:59:32 AM UTC 24 |
Sep 25 01:02:37 AM UTC 24 |
473218948 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1622958532 |
|
|
Sep 25 12:45:06 AM UTC 24 |
Sep 25 01:02:37 AM UTC 24 |
65404014365 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.2152888564 |
|
|
Sep 25 01:01:16 AM UTC 24 |
Sep 25 01:02:42 AM UTC 24 |
2150889784 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.2072938411 |
|
|
Sep 25 01:01:58 AM UTC 24 |
Sep 25 01:02:53 AM UTC 24 |
603871818 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.2685801708 |
|
|
Sep 25 01:02:38 AM UTC 24 |
Sep 25 01:02:57 AM UTC 24 |
189024701 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4286164959 |
|
|
Sep 25 12:55:48 AM UTC 24 |
Sep 25 01:03:04 AM UTC 24 |
26717616282 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3584982992 |
|
|
Sep 25 01:02:06 AM UTC 24 |
Sep 25 01:03:08 AM UTC 24 |
587123497 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3245055507 |
|
|
Sep 25 01:02:26 AM UTC 24 |
Sep 25 01:03:10 AM UTC 24 |
1599216951 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.50852539 |
|
|
Sep 25 01:03:04 AM UTC 24 |
Sep 25 01:03:14 AM UTC 24 |
161371106 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.45587842 |
|
|
Sep 25 12:49:32 AM UTC 24 |
Sep 25 01:03:16 AM UTC 24 |
78020791398 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.2309553748 |
|
|
Sep 25 12:59:01 AM UTC 24 |
Sep 25 01:03:16 AM UTC 24 |
24769334465 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3601341354 |
|
|
Sep 25 01:02:45 AM UTC 24 |
Sep 25 01:03:17 AM UTC 24 |
493730744 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.2319344771 |
|
|
Sep 25 12:59:20 AM UTC 24 |
Sep 25 01:03:23 AM UTC 24 |
2763549015 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1440810617 |
|
|
Sep 25 12:59:24 AM UTC 24 |
Sep 25 01:03:26 AM UTC 24 |
2339374084 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3883894222 |
|
|
Sep 25 01:03:15 AM UTC 24 |
Sep 25 01:03:26 AM UTC 24 |
43953030 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3514490360 |
|
|
Sep 25 12:43:28 AM UTC 24 |
Sep 25 01:03:31 AM UTC 24 |
114300244634 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.545133745 |
|
|
Sep 25 01:01:51 AM UTC 24 |
Sep 25 01:03:32 AM UTC 24 |
4930290187 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.1261276300 |
|
|
Sep 25 01:01:50 AM UTC 24 |
Sep 25 01:03:33 AM UTC 24 |
8408285822 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1412531661 |
|
|
Sep 25 01:00:16 AM UTC 24 |
Sep 25 01:03:38 AM UTC 24 |
10891470884 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.75696250 |
|
|
Sep 25 01:00:39 AM UTC 24 |
Sep 25 01:03:38 AM UTC 24 |
4245979967 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1137264357 |
|
|
Sep 25 01:02:40 AM UTC 24 |
Sep 25 01:03:43 AM UTC 24 |
1263078087 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3059899119 |
|
|
Sep 25 01:02:20 AM UTC 24 |
Sep 25 01:03:44 AM UTC 24 |
1646125744 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.2696303065 |
|
|
Sep 25 01:03:33 AM UTC 24 |
Sep 25 01:03:46 AM UTC 24 |
62570434 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.2080711876 |
|
|
Sep 25 01:03:45 AM UTC 24 |
Sep 25 01:03:57 AM UTC 24 |
107823927 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.3708497350 |
|
|
Sep 25 01:03:43 AM UTC 24 |
Sep 25 01:04:07 AM UTC 24 |
241451598 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3114646661 |
|
|
Sep 25 01:04:03 AM UTC 24 |
Sep 25 01:04:13 AM UTC 24 |
47072633 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.4011434844 |
|
|
Sep 25 01:04:01 AM UTC 24 |
Sep 25 01:04:14 AM UTC 24 |
175537605 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.517069218 |
|
|
Sep 25 01:03:46 AM UTC 24 |
Sep 25 01:04:17 AM UTC 24 |
168698010 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.693385006 |
|
|
Sep 25 12:39:57 AM UTC 24 |
Sep 25 01:04:21 AM UTC 24 |
71995800266 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.2504973136 |
|
|
Sep 25 01:00:40 AM UTC 24 |
Sep 25 01:04:25 AM UTC 24 |
7049466488 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1789078405 |
|
|
Sep 25 01:03:56 AM UTC 24 |
Sep 25 01:04:25 AM UTC 24 |
143916192 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.3324702339 |
|
|
Sep 25 01:03:28 AM UTC 24 |
Sep 25 01:04:26 AM UTC 24 |
1146121925 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2497326599 |
|
|
Sep 25 01:03:52 AM UTC 24 |
Sep 25 01:04:30 AM UTC 24 |
340855311 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1150046296 |
|
|
Sep 25 01:00:38 AM UTC 24 |
Sep 25 01:04:36 AM UTC 24 |
390271364 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1372297864 |
|
|
Sep 25 01:03:20 AM UTC 24 |
Sep 25 01:04:42 AM UTC 24 |
7967644151 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.1829845532 |
|
|
Sep 25 01:04:32 AM UTC 24 |
Sep 25 01:04:42 AM UTC 24 |
40945937 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3551836804 |
|
|
Sep 25 12:58:01 AM UTC 24 |
Sep 25 01:04:46 AM UTC 24 |
4550113060 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2637488674 |
|
|
Sep 25 01:03:26 AM UTC 24 |
Sep 25 01:04:52 AM UTC 24 |
5294923587 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.2147237037 |
|
|
Sep 25 01:04:48 AM UTC 24 |
Sep 25 01:05:00 AM UTC 24 |
98813219 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.272100227 |
|
|
Sep 25 01:04:48 AM UTC 24 |
Sep 25 01:05:03 AM UTC 24 |
120047271 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1475111440 |
|
|
Sep 25 01:03:59 AM UTC 24 |
Sep 25 01:05:11 AM UTC 24 |
1855249368 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.2787977876 |
|
|
Sep 25 01:04:49 AM UTC 24 |
Sep 25 01:05:14 AM UTC 24 |
118125894 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1219362039 |
|
|
Sep 25 12:58:10 AM UTC 24 |
Sep 25 01:05:17 AM UTC 24 |
4175601220 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.831307695 |
|
|
Sep 24 11:19:46 PM UTC 24 |
Sep 25 01:05:23 AM UTC 24 |
56804955496 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.1058573959 |
|
|
Sep 25 01:04:43 AM UTC 24 |
Sep 25 01:05:23 AM UTC 24 |
847377807 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2007432848 |
|
|
Sep 25 01:04:28 AM UTC 24 |
Sep 25 01:05:24 AM UTC 24 |
560844569 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.1479980628 |
|
|
Sep 25 12:56:38 AM UTC 24 |
Sep 25 01:05:29 AM UTC 24 |
13069826489 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.952749609 |
|
|
Sep 25 01:05:23 AM UTC 24 |
Sep 25 01:05:32 AM UTC 24 |
44751392 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1448969050 |
|
|
Sep 25 01:01:31 AM UTC 24 |
Sep 25 01:05:34 AM UTC 24 |
5839534863 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.871472691 |
|
|
Sep 25 12:28:52 AM UTC 24 |
Sep 25 01:05:35 AM UTC 24 |
121095417222 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3699670700 |
|
|
Sep 25 01:05:26 AM UTC 24 |
Sep 25 01:05:37 AM UTC 24 |
48150125 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3508582414 |
|
|
Sep 25 01:04:59 AM UTC 24 |
Sep 25 01:05:46 AM UTC 24 |
1074889272 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2439185347 |
|
|
Sep 25 01:04:06 AM UTC 24 |
Sep 25 01:05:48 AM UTC 24 |
7385729601 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.709529965 |
|
|
Sep 25 01:04:18 AM UTC 24 |
Sep 25 01:05:49 AM UTC 24 |
6310763086 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.2340599813 |
|
|
Sep 25 01:03:39 AM UTC 24 |
Sep 25 01:05:53 AM UTC 24 |
3155225674 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.717687401 |
|
|
Sep 25 12:52:09 AM UTC 24 |
Sep 25 01:11:49 AM UTC 24 |
61977366047 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.301036435 |
|
|
Sep 25 12:36:45 AM UTC 24 |
Sep 25 01:05:54 AM UTC 24 |
106981901679 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.93483591 |
|
|
Sep 25 01:02:52 AM UTC 24 |
Sep 25 01:06:01 AM UTC 24 |
2055449077 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.4220905840 |
|
|
Sep 25 01:05:57 AM UTC 24 |
Sep 25 01:06:18 AM UTC 24 |
266698566 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1188918448 |
|
|
Sep 25 12:51:09 AM UTC 24 |
Sep 25 01:06:20 AM UTC 24 |
56513453812 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.748764089 |
|
|
Sep 25 01:05:41 AM UTC 24 |
Sep 25 01:06:23 AM UTC 24 |
861330195 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.3396085698 |
|
|
Sep 25 12:58:11 AM UTC 24 |
Sep 25 01:06:31 AM UTC 24 |
14252573900 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.1596056339 |
|
|
Sep 25 01:06:24 AM UTC 24 |
Sep 25 01:06:34 AM UTC 24 |
44532309 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3767358407 |
|
|
Sep 25 01:02:50 AM UTC 24 |
Sep 25 01:06:38 AM UTC 24 |
388004092 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.1902594895 |
|
|
Sep 25 01:02:58 AM UTC 24 |
Sep 25 01:06:39 AM UTC 24 |
2784043568 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1843605416 |
|
|
Sep 25 01:06:07 AM UTC 24 |
Sep 25 01:06:40 AM UTC 24 |
277960046 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2536114002 |
|
|
Sep 25 01:05:43 AM UTC 24 |
Sep 25 01:06:40 AM UTC 24 |
441104294 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.1679391259 |
|
|
Sep 25 01:05:49 AM UTC 24 |
Sep 25 01:06:44 AM UTC 24 |
541004432 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.81277869 |
|
|
Sep 25 01:06:41 AM UTC 24 |
Sep 25 01:06:52 AM UTC 24 |
55639744 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.1442255048 |
|
|
Sep 25 01:05:58 AM UTC 24 |
Sep 25 01:07:02 AM UTC 24 |
1529434266 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.2567951694 |
|
|
Sep 25 01:05:31 AM UTC 24 |
Sep 25 01:07:04 AM UTC 24 |
8389005358 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.2396428266 |
|
|
Sep 25 01:06:54 AM UTC 24 |
Sep 25 01:07:21 AM UTC 24 |
232783711 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.825297994 |
|
|
Sep 25 01:06:12 AM UTC 24 |
Sep 25 01:07:25 AM UTC 24 |
195357831 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.105363035 |
|
|
Sep 25 01:05:55 AM UTC 24 |
Sep 25 01:07:29 AM UTC 24 |
2459793175 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1491343801 |
|
|
Sep 25 01:03:52 AM UTC 24 |
Sep 25 01:07:36 AM UTC 24 |
2144489338 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.912106480 |
|
|
Sep 25 01:07:00 AM UTC 24 |
Sep 25 01:07:40 AM UTC 24 |
284994415 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.4105956699 |
|
|
Sep 25 01:05:36 AM UTC 24 |
Sep 25 01:07:43 AM UTC 24 |
6658748240 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.159113653 |
|
|
Sep 25 12:48:21 AM UTC 24 |
Sep 25 01:07:45 AM UTC 24 |
73750926024 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.4127785156 |
|
|
Sep 25 01:06:54 AM UTC 24 |
Sep 25 01:07:48 AM UTC 24 |
399722861 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2235984657 |
|
|
Sep 25 01:03:53 AM UTC 24 |
Sep 25 01:07:48 AM UTC 24 |
3317098617 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.4247907759 |
|
|
Sep 25 01:07:24 AM UTC 24 |
Sep 25 01:07:49 AM UTC 24 |
357919588 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.306138582 |
|
|
Sep 25 01:05:09 AM UTC 24 |
Sep 25 01:08:01 AM UTC 24 |
4576098878 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1347630950 |
|
|
Sep 25 01:07:28 AM UTC 24 |
Sep 25 01:08:04 AM UTC 24 |
293726552 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2263069624 |
|
|
Sep 25 01:05:13 AM UTC 24 |
Sep 25 01:08:05 AM UTC 24 |
399751525 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2060950518 |
|
|
Sep 25 01:08:02 AM UTC 24 |
Sep 25 01:08:12 AM UTC 24 |
50061445 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1196759616 |
|
|
Sep 25 01:07:06 AM UTC 24 |
Sep 25 01:08:13 AM UTC 24 |
598499794 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2765198640 |
|
|
Sep 25 01:01:37 AM UTC 24 |
Sep 25 01:08:15 AM UTC 24 |
7881757837 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1023929830 |
|
|
Sep 25 01:08:02 AM UTC 24 |
Sep 25 01:08:16 AM UTC 24 |
189883915 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.2463791020 |
|
|
Sep 25 01:07:15 AM UTC 24 |
Sep 25 01:08:26 AM UTC 24 |
1842860329 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3260908572 |
|
|
Sep 25 01:08:11 AM UTC 24 |
Sep 25 01:08:27 AM UTC 24 |
126091539 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1698587474 |
|
|
Sep 25 01:06:10 AM UTC 24 |
Sep 25 01:08:37 AM UTC 24 |
1127802864 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.848617338 |
|
|
Sep 25 01:08:12 AM UTC 24 |
Sep 25 01:08:39 AM UTC 24 |
423468521 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.1473153701 |
|
|
Sep 25 01:06:43 AM UTC 24 |
Sep 25 01:08:46 AM UTC 24 |
10441047528 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3384358130 |
|
|
Sep 25 01:06:14 AM UTC 24 |
Sep 25 01:08:53 AM UTC 24 |
322180635 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.2064169609 |
|
|
Sep 25 01:08:39 AM UTC 24 |
Sep 25 01:08:55 AM UTC 24 |
73348218 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1070243271 |
|
|
Sep 25 01:07:46 AM UTC 24 |
Sep 25 01:08:55 AM UTC 24 |
147299339 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.92775732 |
|
|
Sep 25 01:08:28 AM UTC 24 |
Sep 25 01:08:58 AM UTC 24 |
579818400 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.34335625 |
|
|
Sep 25 01:06:44 AM UTC 24 |
Sep 25 01:09:03 AM UTC 24 |
5748409719 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.1321894269 |
|
|
Sep 25 01:08:35 AM UTC 24 |
Sep 25 01:09:07 AM UTC 24 |
375507084 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2167572405 |
|
|
Sep 25 01:07:44 AM UTC 24 |
Sep 25 01:09:09 AM UTC 24 |
630727528 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1784888566 |
|
|
Sep 25 12:52:04 AM UTC 24 |
Sep 25 01:09:11 AM UTC 24 |
97087649812 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2021384900 |
|
|
Sep 25 01:08:46 AM UTC 24 |
Sep 25 01:09:12 AM UTC 24 |
228205167 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.3420988041 |
|
|
Sep 25 01:08:36 AM UTC 24 |
Sep 25 01:09:13 AM UTC 24 |
805911873 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1452715923 |
|
|
Sep 25 01:09:14 AM UTC 24 |
Sep 25 01:09:21 AM UTC 24 |
42667427 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2138272846 |
|
|
Sep 25 01:09:11 AM UTC 24 |
Sep 25 01:09:22 AM UTC 24 |
44150693 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.216174424 |
|
|
Sep 25 01:01:18 AM UTC 24 |
Sep 25 01:09:28 AM UTC 24 |
27913099460 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.1463443541 |
|
|
Sep 25 01:07:52 AM UTC 24 |
Sep 25 01:09:37 AM UTC 24 |
1216911298 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2135435350 |
|
|
Sep 25 01:00:43 AM UTC 24 |
Sep 25 01:09:37 AM UTC 24 |
4687691523 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1028693136 |
|
|
Sep 25 01:09:26 AM UTC 24 |
Sep 25 01:09:39 AM UTC 24 |
67920937 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2691327316 |
|
|
Sep 25 01:08:59 AM UTC 24 |
Sep 25 01:09:43 AM UTC 24 |
66567079 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.3454947842 |
|
|
Sep 25 01:08:08 AM UTC 24 |
Sep 25 01:09:57 AM UTC 24 |
9331457941 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2084998057 |
|
|
Sep 25 01:05:03 AM UTC 24 |
Sep 25 01:09:58 AM UTC 24 |
3080972088 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3817835480 |
|
|
Sep 25 01:08:09 AM UTC 24 |
Sep 25 01:09:58 AM UTC 24 |
5551373669 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2742846722 |
|
|
Sep 25 01:09:22 AM UTC 24 |
Sep 25 01:10:07 AM UTC 24 |
535013412 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2233725823 |
|
|
Sep 25 12:34:33 AM UTC 24 |
Sep 25 01:10:10 AM UTC 24 |
148337690132 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2320441732 |
|
|
Sep 25 01:10:18 AM UTC 24 |
Sep 25 01:10:28 AM UTC 24 |
46619659 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2746577453 |
|
|
Sep 25 01:10:18 AM UTC 24 |
Sep 25 01:10:31 AM UTC 24 |
155506459 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1114183 |
|
|
Sep 25 01:10:00 AM UTC 24 |
Sep 25 01:10:35 AM UTC 24 |
644183304 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.556716691 |
|
|
Sep 25 01:09:43 AM UTC 24 |
Sep 25 01:10:35 AM UTC 24 |
1818662286 ps |