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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.41 93.73 95.49 94.54 97.40 99.54


Total test records in report: 2925
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T2515 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.937860141 Sep 25 01:29:38 AM UTC 24 Sep 25 01:29:53 AM UTC 24 223401965 ps
T2516 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3113001963 Sep 25 01:29:17 AM UTC 24 Sep 25 01:29:53 AM UTC 24 800599775 ps
T2517 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.633132882 Sep 25 01:25:13 AM UTC 24 Sep 25 01:29:54 AM UTC 24 3293998094 ps
T2518 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3118372335 Sep 25 01:29:45 AM UTC 24 Sep 25 01:29:54 AM UTC 24 44472992 ps
T2519 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1041024046 Sep 25 01:27:46 AM UTC 24 Sep 25 01:29:56 AM UTC 24 5953718907 ps
T2520 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3381176735 Sep 25 01:28:14 AM UTC 24 Sep 25 01:29:56 AM UTC 24 261020066 ps
T2521 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.2757396405 Sep 25 01:27:47 AM UTC 24 Sep 25 01:29:57 AM UTC 24 8262883066 ps
T2522 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2207721056 Sep 25 01:25:23 AM UTC 24 Sep 25 01:29:57 AM UTC 24 6429172965 ps
T2523 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.608855325 Sep 25 01:28:32 AM UTC 24 Sep 25 01:29:59 AM UTC 24 2184943608 ps
T2524 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.1415286887 Sep 25 01:24:55 AM UTC 24 Sep 25 01:30:04 AM UTC 24 20041034838 ps
T2525 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.3981594752 Sep 25 01:30:02 AM UTC 24 Sep 25 01:30:10 AM UTC 24 41410210 ps
T2526 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1738095858 Sep 25 01:29:13 AM UTC 24 Sep 25 01:30:15 AM UTC 24 1409297543 ps
T2527 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.16090285 Sep 25 01:28:58 AM UTC 24 Sep 25 01:30:15 AM UTC 24 1439540651 ps
T2528 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.581885037 Sep 25 01:28:32 AM UTC 24 Sep 25 01:30:21 AM UTC 24 7624583047 ps
T2529 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.3503761827 Sep 25 01:22:00 AM UTC 24 Sep 25 01:30:22 AM UTC 24 40210745378 ps
T2530 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3765660074 Sep 25 01:30:06 AM UTC 24 Sep 25 01:30:22 AM UTC 24 130090952 ps
T2531 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.384288833 Sep 25 01:24:10 AM UTC 24 Sep 25 01:30:26 AM UTC 24 4269934983 ps
T2532 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1278622460 Sep 25 01:16:16 AM UTC 24 Sep 25 01:30:31 AM UTC 24 16639306251 ps
T2533 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3002585548 Sep 25 01:28:31 AM UTC 24 Sep 25 01:30:34 AM UTC 24 5296549969 ps
T2534 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2933757730 Sep 25 01:30:16 AM UTC 24 Sep 25 01:30:34 AM UTC 24 337340198 ps
T2535 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4214981282 Sep 25 01:26:25 AM UTC 24 Sep 25 01:30:38 AM UTC 24 872609248 ps
T2536 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2311261083 Sep 25 01:24:45 AM UTC 24 Sep 25 01:30:38 AM UTC 24 31853874888 ps
T2537 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.145770359 Sep 25 01:30:16 AM UTC 24 Sep 25 01:30:38 AM UTC 24 232061421 ps
T2538 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.2263126232 Sep 25 01:20:33 AM UTC 24 Sep 25 01:30:38 AM UTC 24 39731298200 ps
T2539 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.544196030 Sep 25 01:30:17 AM UTC 24 Sep 25 01:30:43 AM UTC 24 218333538 ps
T2540 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.1351370595 Sep 25 01:30:37 AM UTC 24 Sep 25 01:30:48 AM UTC 24 34609223 ps
T2541 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3901513926 Sep 25 01:30:38 AM UTC 24 Sep 25 01:30:50 AM UTC 24 56222983 ps
T2542 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.92970415 Sep 25 01:30:15 AM UTC 24 Sep 25 01:31:03 AM UTC 24 456366580 ps
T2543 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2036816678 Sep 25 01:30:17 AM UTC 24 Sep 25 01:31:04 AM UTC 24 842735775 ps
T2544 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2603841377 Sep 25 01:30:45 AM UTC 24 Sep 25 01:31:07 AM UTC 24 186191089 ps
T2545 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2856634827 Sep 25 01:22:51 AM UTC 24 Sep 25 01:31:07 AM UTC 24 9277588742 ps
T2546 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2657241685 Sep 25 01:29:58 AM UTC 24 Sep 25 01:31:19 AM UTC 24 4962140364 ps
T2547 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.3421352139 Sep 25 01:30:48 AM UTC 24 Sep 25 01:31:26 AM UTC 24 278683495 ps
T2548 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.2707862882 Sep 25 01:31:01 AM UTC 24 Sep 25 01:31:33 AM UTC 24 167587345 ps
T2549 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.862787809 Sep 25 01:31:28 AM UTC 24 Sep 25 01:31:41 AM UTC 24 58173877 ps
T2550 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3389983000 Sep 25 01:31:31 AM UTC 24 Sep 25 01:31:41 AM UTC 24 45928461 ps
T2551 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.4272461405 Sep 25 01:13:58 AM UTC 24 Sep 25 01:31:42 AM UTC 24 61676987413 ps
T2552 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.3627269627 Sep 25 01:30:00 AM UTC 24 Sep 25 01:31:42 AM UTC 24 9495830046 ps
T2553 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.55473901 Sep 25 01:29:34 AM UTC 24 Sep 25 01:31:46 AM UTC 24 312217187 ps
T2554 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2281057758 Sep 25 01:30:44 AM UTC 24 Sep 25 01:31:46 AM UTC 24 3937048917 ps
T2555 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.193234478 Sep 25 01:29:17 AM UTC 24 Sep 25 01:31:56 AM UTC 24 3436464622 ps
T2556 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.1108288235 Sep 25 01:31:02 AM UTC 24 Sep 25 01:31:57 AM UTC 24 1739677527 ps
T2557 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.506089202 Sep 25 01:30:59 AM UTC 24 Sep 25 01:32:02 AM UTC 24 1910146107 ps
T2558 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2307800948 Sep 25 01:29:26 AM UTC 24 Sep 25 01:32:04 AM UTC 24 2757632271 ps
T2559 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.1517101882 Sep 25 01:30:56 AM UTC 24 Sep 25 01:32:07 AM UTC 24 1248040613 ps
T2560 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.892346831 Sep 25 01:30:41 AM UTC 24 Sep 25 01:32:27 AM UTC 24 9147606878 ps
T2561 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3610035861 Sep 25 01:31:06 AM UTC 24 Sep 25 01:32:29 AM UTC 24 1350310688 ps
T2562 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.1622415935 Sep 25 01:23:25 AM UTC 24 Sep 25 01:32:39 AM UTC 24 49190712849 ps
T2563 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.3920635812 Sep 25 01:31:56 AM UTC 24 Sep 25 01:32:41 AM UTC 24 725332238 ps
T2564 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3544516222 Sep 25 01:32:29 AM UTC 24 Sep 25 01:32:46 AM UTC 24 62803709 ps
T2565 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.3936500428 Sep 25 01:28:15 AM UTC 24 Sep 25 01:32:47 AM UTC 24 7608637287 ps
T2566 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3873668326 Sep 25 01:32:19 AM UTC 24 Sep 25 01:32:56 AM UTC 24 321635144 ps
T2567 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1294847554 Sep 25 01:32:25 AM UTC 24 Sep 25 01:33:01 AM UTC 24 567398018 ps
T2568 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2079576769 Sep 25 01:32:58 AM UTC 24 Sep 25 01:33:09 AM UTC 24 158824398 ps
T2569 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2768463275 Sep 25 01:33:05 AM UTC 24 Sep 25 01:33:16 AM UTC 24 49830470 ps
T2570 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3963986257 Sep 25 01:20:42 AM UTC 24 Sep 25 01:33:16 AM UTC 24 48790904489 ps
T2571 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2996159464 Sep 25 01:31:49 AM UTC 24 Sep 25 01:33:17 AM UTC 24 5231106631 ps
T2572 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.2922448720 Sep 25 01:32:21 AM UTC 24 Sep 25 01:33:18 AM UTC 24 343467501 ps
T2573 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.3526094324 Sep 25 01:32:03 AM UTC 24 Sep 25 01:33:18 AM UTC 24 603332352 ps
T2574 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2971256933 Sep 25 01:18:04 AM UTC 24 Sep 25 01:33:23 AM UTC 24 19272791223 ps
T2575 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2921127197 Sep 25 01:31:40 AM UTC 24 Sep 25 01:33:28 AM UTC 24 9322308062 ps
T2576 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.4091998811 Sep 25 01:30:19 AM UTC 24 Sep 25 01:33:32 AM UTC 24 2283189347 ps
T2577 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.361918429 Sep 25 01:32:04 AM UTC 24 Sep 25 01:33:35 AM UTC 24 1044514785 ps
T2578 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.840847022 Sep 25 01:32:09 AM UTC 24 Sep 25 01:33:36 AM UTC 24 1854440830 ps
T2579 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.683201182 Sep 25 01:26:32 AM UTC 24 Sep 25 01:33:43 AM UTC 24 8781363384 ps
T2580 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.4210217861 Sep 25 01:29:29 AM UTC 24 Sep 25 01:33:51 AM UTC 24 2971160095 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.111358234 Sep 25 01:32:47 AM UTC 24 Sep 25 01:33:55 AM UTC 24 804133891 ps
T2581 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.2187541262 Sep 25 01:33:19 AM UTC 24 Sep 25 01:33:57 AM UTC 24 388983537 ps
T2582 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1488953251 Sep 25 01:33:46 AM UTC 24 Sep 25 01:34:03 AM UTC 24 66920872 ps
T2583 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1225648169 Sep 25 12:52:29 AM UTC 24 Sep 25 01:34:17 AM UTC 24 147422164241 ps
T2584 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.2341635055 Sep 25 01:33:24 AM UTC 24 Sep 25 01:34:24 AM UTC 24 623272044 ps
T2585 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1746071182 Sep 25 01:34:14 AM UTC 24 Sep 25 01:34:25 AM UTC 24 50712563 ps
T2586 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3461504364 Sep 25 01:33:09 AM UTC 24 Sep 25 01:34:27 AM UTC 24 4632685838 ps
T2587 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.3203281016 Sep 25 01:34:15 AM UTC 24 Sep 25 01:34:27 AM UTC 24 55558529 ps
T2588 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.1056030480 Sep 25 01:33:37 AM UTC 24 Sep 25 01:34:29 AM UTC 24 1245635235 ps
T2589 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2478614078 Sep 25 01:33:39 AM UTC 24 Sep 25 01:34:42 AM UTC 24 1149705550 ps
T2590 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2302516862 Sep 25 01:33:50 AM UTC 24 Sep 25 01:34:42 AM UTC 24 798052708 ps
T2591 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1233695044 Sep 25 01:30:23 AM UTC 24 Sep 25 01:34:48 AM UTC 24 7105094712 ps
T2592 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.680485772 Sep 25 01:31:23 AM UTC 24 Sep 25 01:34:52 AM UTC 24 2603276815 ps
T2593 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.514524793 Sep 25 01:30:20 AM UTC 24 Sep 25 01:34:53 AM UTC 24 5068644528 ps
T2594 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.2500341593 Sep 25 01:28:17 AM UTC 24 Sep 25 01:35:06 AM UTC 24 10693866757 ps
T2595 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.2845026982 Sep 25 01:31:09 AM UTC 24 Sep 25 01:35:17 AM UTC 24 2906750085 ps
T2596 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1140341975 Sep 25 01:33:08 AM UTC 24 Sep 25 01:35:17 AM UTC 24 9169935103 ps
T2597 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3598847521 Sep 25 01:34:06 AM UTC 24 Sep 25 01:35:18 AM UTC 24 103515116 ps
T2598 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1520356975 Sep 25 01:18:42 AM UTC 24 Sep 25 01:35:21 AM UTC 24 87496207386 ps
T2599 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3930811845 Sep 25 01:35:05 AM UTC 24 Sep 25 01:35:30 AM UTC 24 285242048 ps
T2600 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.366365326 Sep 25 01:34:45 AM UTC 24 Sep 25 01:35:35 AM UTC 24 428357261 ps
T2601 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.992748081 Sep 25 01:35:02 AM UTC 24 Sep 25 01:35:42 AM UTC 24 400632376 ps
T2602 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.1834925384 Sep 25 01:35:14 AM UTC 24 Sep 25 01:35:50 AM UTC 24 296637674 ps
T2603 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3401122195 Sep 25 01:35:39 AM UTC 24 Sep 25 01:35:51 AM UTC 24 49335969 ps
T2604 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.66330933 Sep 25 01:33:30 AM UTC 24 Sep 25 01:35:53 AM UTC 24 10909325029 ps
T2605 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.1213467423 Sep 25 01:34:41 AM UTC 24 Sep 25 01:35:54 AM UTC 24 1764838091 ps
T2606 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2903617746 Sep 25 01:35:43 AM UTC 24 Sep 25 01:35:55 AM UTC 24 48980761 ps
T2607 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1684063817 Sep 25 01:35:15 AM UTC 24 Sep 25 01:35:55 AM UTC 24 834860914 ps
T2608 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3586667744 Sep 25 01:33:40 AM UTC 24 Sep 25 01:35:56 AM UTC 24 2704398965 ps
T2609 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.4010040297 Sep 25 01:33:55 AM UTC 24 Sep 25 01:35:59 AM UTC 24 1376617002 ps
T2610 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3564700803 Sep 25 01:34:47 AM UTC 24 Sep 25 01:36:04 AM UTC 24 594547256 ps
T2611 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.2775705758 Sep 25 01:35:11 AM UTC 24 Sep 25 01:36:06 AM UTC 24 1120948903 ps
T2612 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.772702387 Sep 25 01:34:25 AM UTC 24 Sep 25 01:36:09 AM UTC 24 4486947382 ps
T2613 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.3459350559 Sep 25 01:15:37 AM UTC 24 Sep 25 01:36:15 AM UTC 24 95767337471 ps
T2614 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.2775416991 Sep 25 01:34:20 AM UTC 24 Sep 25 01:36:33 AM UTC 24 9509949378 ps
T2615 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.465184775 Sep 25 01:36:25 AM UTC 24 Sep 25 01:36:35 AM UTC 24 55593750 ps
T2616 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.3851048073 Sep 25 01:36:06 AM UTC 24 Sep 25 01:36:43 AM UTC 24 283434706 ps
T2617 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.4076256628 Sep 25 01:36:19 AM UTC 24 Sep 25 01:36:45 AM UTC 24 186288602 ps
T2618 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.1722876479 Sep 25 01:36:11 AM UTC 24 Sep 25 01:36:50 AM UTC 24 301499387 ps
T2619 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.1415423273 Sep 25 01:32:05 AM UTC 24 Sep 25 01:36:53 AM UTC 24 17926656569 ps
T2620 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2645752429 Sep 25 01:36:17 AM UTC 24 Sep 25 01:36:56 AM UTC 24 357327889 ps
T2621 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.380749097 Sep 25 01:36:20 AM UTC 24 Sep 25 01:36:56 AM UTC 24 190177472 ps
T2622 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3815739239 Sep 25 01:26:09 AM UTC 24 Sep 25 01:37:01 AM UTC 24 37476244016 ps
T2623 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1226042445 Sep 25 01:35:39 AM UTC 24 Sep 25 01:37:02 AM UTC 24 266503658 ps
T2624 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3941735579 Sep 25 01:24:08 AM UTC 24 Sep 25 01:37:04 AM UTC 24 20211887869 ps
T2625 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.2590479933 Sep 25 01:36:17 AM UTC 24 Sep 25 01:37:05 AM UTC 24 419062292 ps
T2626 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1652751857 Sep 25 01:31:26 AM UTC 24 Sep 25 01:37:06 AM UTC 24 957628244 ps
T2627 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.340369549 Sep 25 01:36:57 AM UTC 24 Sep 25 01:37:09 AM UTC 24 157350040 ps
T2628 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.624106001 Sep 25 01:35:56 AM UTC 24 Sep 25 01:37:09 AM UTC 24 4288483462 ps
T2629 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3390464496 Sep 25 01:37:04 AM UTC 24 Sep 25 01:37:16 AM UTC 24 55988821 ps
T2630 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.25936395 Sep 25 01:27:27 AM UTC 24 Sep 25 01:37:19 AM UTC 24 5016851842 ps
T2631 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3323924654 Sep 25 01:32:47 AM UTC 24 Sep 25 01:37:24 AM UTC 24 4295577917 ps
T2632 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3231885615 Sep 25 01:30:13 AM UTC 24 Sep 25 01:37:25 AM UTC 24 21467574416 ps
T2633 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.1389949119 Sep 25 01:35:52 AM UTC 24 Sep 25 01:37:34 AM UTC 24 9201607091 ps
T2634 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.2420650321 Sep 25 01:27:08 AM UTC 24 Sep 25 01:37:36 AM UTC 24 39377533085 ps
T2635 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3687486398 Sep 25 01:31:10 AM UTC 24 Sep 25 01:37:40 AM UTC 24 1692172312 ps
T2636 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3296214668 Sep 25 01:37:32 AM UTC 24 Sep 25 01:37:44 AM UTC 24 37148129 ps
T2637 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1306465325 Sep 25 01:37:23 AM UTC 24 Sep 25 01:37:45 AM UTC 24 494267546 ps
T2638 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.910275896 Sep 25 01:35:39 AM UTC 24 Sep 25 01:37:46 AM UTC 24 3241366485 ps
T2639 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.956053561 Sep 25 01:37:14 AM UTC 24 Sep 25 01:37:48 AM UTC 24 326300699 ps
T2640 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.785059220 Sep 25 01:37:20 AM UTC 24 Sep 25 01:37:55 AM UTC 24 375408392 ps
T2641 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.784490970 Sep 25 01:37:17 AM UTC 24 Sep 25 01:37:58 AM UTC 24 358381531 ps
T2642 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2249192491 Sep 25 01:37:13 AM UTC 24 Sep 25 01:38:02 AM UTC 24 2862152252 ps
T2643 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1525877882 Sep 25 01:38:00 AM UTC 24 Sep 25 01:38:10 AM UTC 24 48717845 ps
T2644 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.3266320356 Sep 25 01:37:56 AM UTC 24 Sep 25 01:38:10 AM UTC 24 189667848 ps
T2645 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.494853217 Sep 25 01:36:39 AM UTC 24 Sep 25 01:38:12 AM UTC 24 961816135 ps
T2646 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3607986818 Sep 25 01:01:20 AM UTC 24 Sep 25 01:38:15 AM UTC 24 139925225657 ps
T2647 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.2398774921 Sep 25 01:37:27 AM UTC 24 Sep 25 01:38:28 AM UTC 24 604859353 ps
T2648 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.3731285710 Sep 25 01:38:08 AM UTC 24 Sep 25 01:38:29 AM UTC 24 198294880 ps
T2649 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1718402892 Sep 25 01:30:32 AM UTC 24 Sep 25 01:38:30 AM UTC 24 4201593781 ps
T2650 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1456799127 Sep 25 01:37:32 AM UTC 24 Sep 25 01:38:30 AM UTC 24 1272009846 ps
T2651 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.2439895710 Sep 25 01:30:54 AM UTC 24 Sep 25 01:38:36 AM UTC 24 27096171260 ps
T2652 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.237961532 Sep 25 01:37:07 AM UTC 24 Sep 25 01:38:40 AM UTC 24 8987838175 ps
T2653 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2312180556 Sep 25 01:38:37 AM UTC 24 Sep 25 01:38:46 AM UTC 24 25428935 ps
T2654 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.3757329803 Sep 25 01:38:21 AM UTC 24 Sep 25 01:38:46 AM UTC 24 362965377 ps
T2655 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1470549978 Sep 25 01:07:02 AM UTC 24 Sep 25 01:38:47 AM UTC 24 114697268693 ps
T2656 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1500371487 Sep 25 01:38:34 AM UTC 24 Sep 25 01:38:49 AM UTC 24 241443472 ps
T2657 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.4251016633 Sep 25 01:37:21 AM UTC 24 Sep 25 01:39:05 AM UTC 24 5925257932 ps
T2658 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3525223775 Sep 25 01:38:57 AM UTC 24 Sep 25 01:39:08 AM UTC 24 56883878 ps
T2659 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2750323303 Sep 25 01:38:08 AM UTC 24 Sep 25 01:39:11 AM UTC 24 1700511180 ps
T2660 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.1766256864 Sep 25 01:38:56 AM UTC 24 Sep 25 01:39:12 AM UTC 24 236550259 ps
T2661 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.234922217 Sep 25 01:37:46 AM UTC 24 Sep 25 01:39:14 AM UTC 24 2617733020 ps
T2662 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3719520620 Sep 25 01:38:33 AM UTC 24 Sep 25 01:39:20 AM UTC 24 629102874 ps
T2663 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.1979552916 Sep 25 01:30:15 AM UTC 24 Sep 25 01:39:26 AM UTC 24 31219312977 ps
T2664 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.559022177 Sep 25 01:38:07 AM UTC 24 Sep 25 01:39:27 AM UTC 24 4760386822 ps
T2665 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.1939947684 Sep 25 01:38:32 AM UTC 24 Sep 25 01:39:32 AM UTC 24 1314929360 ps
T2666 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.34513303 Sep 25 01:38:00 AM UTC 24 Sep 25 01:39:33 AM UTC 24 8813516739 ps
T2667 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1164216244 Sep 25 01:39:11 AM UTC 24 Sep 25 01:39:47 AM UTC 24 271694646 ps
T2668 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2000881972 Sep 25 01:28:00 AM UTC 24 Sep 25 01:39:52 AM UTC 24 38890166607 ps
T2669 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1413175608 Sep 25 01:08:36 AM UTC 24 Sep 25 01:39:52 AM UTC 24 118917761804 ps
T2670 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.3989999959 Sep 25 01:39:07 AM UTC 24 Sep 25 01:40:03 AM UTC 24 981924448 ps
T2671 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.2321905027 Sep 25 01:34:48 AM UTC 24 Sep 25 01:40:07 AM UTC 24 33049009690 ps
T2672 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.301990857 Sep 25 01:39:07 AM UTC 24 Sep 25 01:40:12 AM UTC 24 4407927265 ps
T2673 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1155001157 Sep 25 01:37:48 AM UTC 24 Sep 25 01:40:13 AM UTC 24 324677418 ps
T2674 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.291616255 Sep 25 01:24:59 AM UTC 24 Sep 25 01:40:18 AM UTC 24 64263167399 ps
T2675 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1849564410 Sep 25 01:39:48 AM UTC 24 Sep 25 01:40:22 AM UTC 24 209694925 ps
T2676 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.2264723903 Sep 25 01:39:42 AM UTC 24 Sep 25 01:40:23 AM UTC 24 395276963 ps
T2677 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3367485606 Sep 25 01:20:29 AM UTC 24 Sep 25 01:40:24 AM UTC 24 111152861765 ps
T2678 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.2878371692 Sep 25 01:40:14 AM UTC 24 Sep 25 01:40:25 AM UTC 24 46259105 ps
T2679 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1229101318 Sep 25 01:36:56 AM UTC 24 Sep 25 01:40:28 AM UTC 24 2243963570 ps
T2680 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2003027144 Sep 25 01:40:24 AM UTC 24 Sep 25 01:40:35 AM UTC 24 42441136 ps
T2681 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.2901312071 Sep 25 01:39:28 AM UTC 24 Sep 25 01:40:36 AM UTC 24 3638044310 ps
T2682 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.882583007 Sep 25 01:39:46 AM UTC 24 Sep 25 01:40:38 AM UTC 24 971480855 ps
T2683 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.3193077600 Sep 25 01:39:37 AM UTC 24 Sep 25 01:40:38 AM UTC 24 2098676730 ps
T2684 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3287537573 Sep 25 01:40:35 AM UTC 24 Sep 25 01:40:53 AM UTC 24 104374832 ps
T2685 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2129584704 Sep 25 01:39:04 AM UTC 24 Sep 25 01:40:56 AM UTC 24 8205721068 ps
T2686 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.2337928789 Sep 25 01:36:27 AM UTC 24 Sep 25 01:40:57 AM UTC 24 6501163293 ps
T2687 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1293937369 Sep 25 01:23:29 AM UTC 24 Sep 25 01:41:05 AM UTC 24 56567909476 ps
T2688 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.3032413760 Sep 25 01:40:40 AM UTC 24 Sep 25 01:41:07 AM UTC 24 178783634 ps
T2689 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1535886974 Sep 25 01:39:55 AM UTC 24 Sep 25 01:41:11 AM UTC 24 327811969 ps
T2690 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.2455949456 Sep 25 01:40:49 AM UTC 24 Sep 25 01:41:11 AM UTC 24 528514658 ps
T2691 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3218501438 Sep 25 01:28:55 AM UTC 24 Sep 25 01:41:14 AM UTC 24 44335122413 ps
T2692 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.215453455 Sep 25 01:33:40 AM UTC 24 Sep 25 01:41:19 AM UTC 24 25252176421 ps
T2693 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.441234401 Sep 25 01:40:59 AM UTC 24 Sep 25 01:41:23 AM UTC 24 280138445 ps
T2694 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.2045254706 Sep 25 01:38:09 AM UTC 24 Sep 25 01:41:25 AM UTC 24 17096198269 ps
T2695 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.490135228 Sep 25 01:41:02 AM UTC 24 Sep 25 01:41:29 AM UTC 24 631828866 ps
T2696 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.879946253 Sep 25 01:39:32 AM UTC 24 Sep 25 01:41:31 AM UTC 24 2530124824 ps
T2697 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1572705651 Sep 25 01:40:58 AM UTC 24 Sep 25 01:41:38 AM UTC 24 1030089806 ps
T2698 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.4253573499 Sep 25 01:41:26 AM UTC 24 Sep 25 01:41:39 AM UTC 24 180298613 ps
T2699 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3791726667 Sep 25 01:41:29 AM UTC 24 Sep 25 01:41:40 AM UTC 24 45453078 ps
T2700 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.100400739 Sep 25 01:41:16 AM UTC 24 Sep 25 01:41:45 AM UTC 24 9826062 ps
T2701 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1700568995 Sep 25 01:41:40 AM UTC 24 Sep 25 01:41:53 AM UTC 24 88164000 ps
T2702 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3091930592 Sep 25 01:36:11 AM UTC 24 Sep 25 01:41:57 AM UTC 24 20543240146 ps
T2703 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.619191439 Sep 25 01:40:33 AM UTC 24 Sep 25 01:41:59 AM UTC 24 5186621604 ps
T2704 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.3008751727 Sep 25 01:40:27 AM UTC 24 Sep 25 01:42:05 AM UTC 24 7539079519 ps
T2705 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.4135251899 Sep 25 01:40:48 AM UTC 24 Sep 25 01:42:06 AM UTC 24 1393790520 ps
T2706 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.1189717441 Sep 25 01:41:58 AM UTC 24 Sep 25 01:42:12 AM UTC 24 102525971 ps
T2707 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3939877285 Sep 25 01:37:42 AM UTC 24 Sep 25 01:42:19 AM UTC 24 2175223067 ps
T2708 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.1820437973 Sep 25 01:34:00 AM UTC 24 Sep 25 01:42:20 AM UTC 24 15153881107 ps
T2709 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1161771858 Sep 25 01:41:36 AM UTC 24 Sep 25 01:42:28 AM UTC 24 459921995 ps
T2710 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2348439350 Sep 25 01:42:05 AM UTC 24 Sep 25 01:42:34 AM UTC 24 173562894 ps
T2711 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.2672718494 Sep 25 01:41:01 AM UTC 24 Sep 25 01:42:36 AM UTC 24 2361311183 ps
T2712 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2227368297 Sep 25 01:42:28 AM UTC 24 Sep 25 01:42:39 AM UTC 24 48030576 ps
T2713 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.3419668218 Sep 25 01:42:01 AM UTC 24 Sep 25 01:42:43 AM UTC 24 807881400 ps
T2714 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1077829479 Sep 25 01:41:32 AM UTC 24 Sep 25 01:42:43 AM UTC 24 6136670365 ps
T2715 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.695862739 Sep 25 01:38:53 AM UTC 24 Sep 25 01:42:44 AM UTC 24 462524628 ps
T2716 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.372955723 Sep 25 01:42:34 AM UTC 24 Sep 25 01:42:44 AM UTC 24 43299268 ps
T2717 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2032739556 Sep 25 01:36:31 AM UTC 24 Sep 25 01:42:47 AM UTC 24 2974290629 ps
T2718 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.2894453717 Sep 25 01:40:44 AM UTC 24 Sep 25 01:42:53 AM UTC 24 8315914659 ps
T2719 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.335852773 Sep 25 01:41:31 AM UTC 24 Sep 25 01:43:02 AM UTC 24 4548061824 ps
T2720 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.1226544460 Sep 25 01:42:00 AM UTC 24 Sep 25 01:43:04 AM UTC 24 1357155943 ps
T2721 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.457952354 Sep 25 01:32:27 AM UTC 24 Sep 25 01:43:09 AM UTC 24 15478860729 ps
T2722 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1911904861 Sep 25 01:38:53 AM UTC 24 Sep 25 01:43:09 AM UTC 24 6955711977 ps
T2723 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.4203276593 Sep 25 01:37:38 AM UTC 24 Sep 25 01:43:17 AM UTC 24 8397134777 ps
T2724 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.774783786 Sep 25 01:42:54 AM UTC 24 Sep 25 01:43:20 AM UTC 24 223049898 ps
T2725 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2433650286 Sep 25 01:35:27 AM UTC 24 Sep 25 01:43:24 AM UTC 24 1812370154 ps
T2726 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.149620349 Sep 25 01:43:07 AM UTC 24 Sep 25 01:43:33 AM UTC 24 431331165 ps
T2727 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.657415179 Sep 25 01:23:38 AM UTC 24 Sep 25 01:43:38 AM UTC 24 71126435464 ps
T2728 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2194804060 Sep 25 01:32:09 AM UTC 24 Sep 25 01:43:39 AM UTC 24 42001821087 ps
T2729 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3442911379 Sep 25 01:43:16 AM UTC 24 Sep 25 01:43:44 AM UTC 24 245075389 ps
T2730 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3222269495 Sep 25 01:39:55 AM UTC 24 Sep 25 01:43:44 AM UTC 24 5441951571 ps
T2731 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2469022932 Sep 25 01:43:09 AM UTC 24 Sep 25 01:43:44 AM UTC 24 679331908 ps
T2732 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.4197554647 Sep 25 01:43:40 AM UTC 24 Sep 25 01:43:50 AM UTC 24 58603748 ps
T2733 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1899741919 Sep 25 01:43:40 AM UTC 24 Sep 25 01:43:51 AM UTC 24 48376372 ps
T2734 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.3668799530 Sep 25 01:41:49 AM UTC 24 Sep 25 01:44:00 AM UTC 24 3136414427 ps
T2735 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.2004696928 Sep 25 01:38:47 AM UTC 24 Sep 25 01:44:18 AM UTC 24 3527138332 ps
T2736 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.3438812890 Sep 25 01:42:43 AM UTC 24 Sep 25 01:44:20 AM UTC 24 5696025728 ps
T2737 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2560044513 Sep 25 01:42:51 AM UTC 24 Sep 25 01:44:21 AM UTC 24 2189931962 ps
T2738 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3396006705 Sep 25 01:44:01 AM UTC 24 Sep 25 01:44:27 AM UTC 24 240746311 ps
T2739 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.243656417 Sep 25 01:43:07 AM UTC 24 Sep 25 01:44:43 AM UTC 24 2449976982 ps
T2740 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.3740008345 Sep 25 01:27:01 AM UTC 24 Sep 25 01:44:45 AM UTC 24 95726449675 ps
T2741 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2818374797 Sep 25 01:44:06 AM UTC 24 Sep 25 01:44:45 AM UTC 24 516396854 ps
T2742 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.597064159 Sep 25 01:42:43 AM UTC 24 Sep 25 01:44:46 AM UTC 24 8637632183 ps
T2743 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.3107546205 Sep 25 01:42:57 AM UTC 24 Sep 25 01:44:50 AM UTC 24 9494467601 ps
T2744 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.151148944 Sep 25 01:33:59 AM UTC 24 Sep 25 01:44:51 AM UTC 24 4017949233 ps
T2745 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.3208019724 Sep 25 01:43:59 AM UTC 24 Sep 25 01:44:55 AM UTC 24 1112110168 ps
T2746 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.3509039786 Sep 25 01:44:41 AM UTC 24 Sep 25 01:44:58 AM UTC 24 98238627 ps
T2747 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.64698391 Sep 25 01:40:10 AM UTC 24 Sep 25 01:45:01 AM UTC 24 7171489949 ps
T2748 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.1611118496 Sep 25 01:44:22 AM UTC 24 Sep 25 01:45:04 AM UTC 24 1067464189 ps
T2749 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.3910930514 Sep 25 01:41:45 AM UTC 24 Sep 25 01:45:07 AM UTC 24 12644501045 ps
T2750 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.3695215799 Sep 25 01:36:09 AM UTC 24 Sep 25 01:45:08 AM UTC 24 33653287943 ps
T2751 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3426417976 Sep 25 01:49:48 AM UTC 24 Sep 25 01:50:29 AM UTC 24 285946593 ps
T2752 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.844684401 Sep 25 01:44:43 AM UTC 24 Sep 25 01:45:11 AM UTC 24 235962655 ps
T2753 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.3732985684 Sep 25 01:45:06 AM UTC 24 Sep 25 01:45:15 AM UTC 24 43733169 ps
T2754 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3701667442 Sep 25 01:45:05 AM UTC 24 Sep 25 01:45:15 AM UTC 24 43483481 ps
T2755 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1580579799 Sep 25 01:43:47 AM UTC 24 Sep 25 01:45:26 AM UTC 24 7981408843 ps
T2756 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.1178567863 Sep 25 01:43:06 AM UTC 24 Sep 25 01:45:28 AM UTC 24 3220492333 ps
T2757 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3543531562 Sep 25 01:43:30 AM UTC 24 Sep 25 01:45:33 AM UTC 24 2756393735 ps
T2758 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.131214941 Sep 25 01:45:16 AM UTC 24 Sep 25 01:45:35 AM UTC 24 114303948 ps
T2759 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.3025046707 Sep 25 01:45:18 AM UTC 24 Sep 25 01:45:36 AM UTC 24 166496467 ps
T2760 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.713733635 Sep 25 01:45:26 AM UTC 24 Sep 25 01:45:39 AM UTC 24 233792041 ps
T2761 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3056572230 Sep 25 01:43:56 AM UTC 24 Sep 25 01:45:41 AM UTC 24 5901221779 ps
T2762 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.890389787 Sep 25 01:45:36 AM UTC 24 Sep 25 01:45:49 AM UTC 24 240870936 ps
T2763 /workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.300919517 Sep 25 01:44:13 AM UTC 24 Sep 25 01:45:58 AM UTC 24 2369391852 ps
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