| T1788 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2123120018 |
|
|
Sep 25 12:35:22 AM UTC 24 |
Sep 25 12:35:30 AM UTC 24 |
53505140 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1281963738 |
|
|
Sep 25 12:35:21 AM UTC 24 |
Sep 25 12:35:32 AM UTC 24 |
50817824 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.48650310 |
|
|
Sep 25 12:18:25 AM UTC 24 |
Sep 25 12:35:35 AM UTC 24 |
67980960894 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.467472441 |
|
|
Sep 25 12:34:06 AM UTC 24 |
Sep 25 12:35:41 AM UTC 24 |
8080364008 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4083963156 |
|
|
Sep 25 12:35:08 AM UTC 24 |
Sep 25 12:35:54 AM UTC 24 |
96731151 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.1650518545 |
|
|
Sep 25 12:34:55 AM UTC 24 |
Sep 25 12:36:00 AM UTC 24 |
705864451 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.3044091936 |
|
|
Sep 25 12:24:05 AM UTC 24 |
Sep 25 12:36:01 AM UTC 24 |
64436617865 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.965774507 |
|
|
Sep 25 12:33:12 AM UTC 24 |
Sep 25 12:36:04 AM UTC 24 |
9876366148 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1716347312 |
|
|
Sep 25 12:35:20 AM UTC 24 |
Sep 25 12:36:05 AM UTC 24 |
97550100 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1689920816 |
|
|
Sep 25 12:35:52 AM UTC 24 |
Sep 25 12:36:05 AM UTC 24 |
113914045 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1945230784 |
|
|
Sep 25 12:35:38 AM UTC 24 |
Sep 25 12:36:09 AM UTC 24 |
521434738 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.358486449 |
|
|
Sep 25 12:35:38 AM UTC 24 |
Sep 25 12:36:17 AM UTC 24 |
274912455 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2192452481 |
|
|
Sep 25 12:28:02 AM UTC 24 |
Sep 25 12:36:17 AM UTC 24 |
9067761426 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3138648722 |
|
|
Sep 25 12:34:11 AM UTC 24 |
Sep 25 12:36:24 AM UTC 24 |
7476756297 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2790055696 |
|
|
Sep 25 12:35:54 AM UTC 24 |
Sep 25 12:36:24 AM UTC 24 |
203453998 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1365405583 |
|
|
Sep 25 12:32:40 AM UTC 24 |
Sep 25 12:36:24 AM UTC 24 |
2929296472 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3832786271 |
|
|
Sep 25 12:35:54 AM UTC 24 |
Sep 25 12:36:25 AM UTC 24 |
175478873 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.1700551314 |
|
|
Sep 25 12:35:44 AM UTC 24 |
Sep 25 12:36:29 AM UTC 24 |
1432449246 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1095955751 |
|
|
Sep 25 12:36:24 AM UTC 24 |
Sep 25 12:36:33 AM UTC 24 |
43447938 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2334137576 |
|
|
Sep 25 12:36:23 AM UTC 24 |
Sep 25 12:36:39 AM UTC 24 |
225522236 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.3994503051 |
|
|
Sep 25 12:36:02 AM UTC 24 |
Sep 25 12:36:53 AM UTC 24 |
1374302799 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2007138896 |
|
|
Sep 25 12:36:35 AM UTC 24 |
Sep 25 12:36:53 AM UTC 24 |
291883579 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.2636820978 |
|
|
Sep 25 12:35:35 AM UTC 24 |
Sep 25 12:37:01 AM UTC 24 |
8342219917 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1718763770 |
|
|
Sep 25 12:27:59 AM UTC 24 |
Sep 25 12:37:01 AM UTC 24 |
14645465283 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.2048735369 |
|
|
Sep 25 12:36:45 AM UTC 24 |
Sep 25 12:37:19 AM UTC 24 |
2408930756 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3056395149 |
|
|
Sep 25 12:35:37 AM UTC 24 |
Sep 25 12:37:25 AM UTC 24 |
4640000994 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.2354553206 |
|
|
Sep 25 12:32:21 AM UTC 24 |
Sep 25 12:37:26 AM UTC 24 |
6749193439 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3604677323 |
|
|
Sep 25 12:36:48 AM UTC 24 |
Sep 25 12:37:26 AM UTC 24 |
321208588 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2618755257 |
|
|
Sep 25 12:12:41 AM UTC 24 |
Sep 25 12:37:28 AM UTC 24 |
95069672009 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.2750668888 |
|
|
Sep 25 12:37:01 AM UTC 24 |
Sep 25 12:37:34 AM UTC 24 |
440676094 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.2693543880 |
|
|
Sep 25 12:36:36 AM UTC 24 |
Sep 25 12:37:34 AM UTC 24 |
560941735 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3592061515 |
|
|
Sep 25 12:36:28 AM UTC 24 |
Sep 25 12:37:34 AM UTC 24 |
4596221779 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1335320121 |
|
|
Sep 25 12:24:49 AM UTC 24 |
Sep 25 12:37:35 AM UTC 24 |
15710716623 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.4292241251 |
|
|
Sep 25 12:35:44 AM UTC 24 |
Sep 25 12:37:35 AM UTC 24 |
10656990553 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.4059779901 |
|
|
Sep 25 12:07:51 AM UTC 24 |
Sep 25 12:37:37 AM UTC 24 |
109372734147 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.102068200 |
|
|
Sep 25 12:36:25 AM UTC 24 |
Sep 25 12:37:40 AM UTC 24 |
6648948507 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2375864531 |
|
|
Sep 25 12:36:50 AM UTC 24 |
Sep 25 12:37:44 AM UTC 24 |
1512204579 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1666404413 |
|
|
Sep 25 12:35:48 AM UTC 24 |
Sep 25 12:37:48 AM UTC 24 |
2794295354 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1808775202 |
|
|
Sep 25 12:37:45 AM UTC 24 |
Sep 25 12:37:53 AM UTC 24 |
41439507 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2840405896 |
|
|
Sep 25 12:37:15 AM UTC 24 |
Sep 25 12:37:55 AM UTC 24 |
1040339161 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.89367367 |
|
|
Sep 25 12:27:12 AM UTC 24 |
Sep 25 12:37:57 AM UTC 24 |
58753353324 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3117094378 |
|
|
Sep 25 12:35:13 AM UTC 24 |
Sep 25 12:37:57 AM UTC 24 |
4237973066 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2252382571 |
|
|
Sep 25 12:38:20 AM UTC 24 |
Sep 25 12:38:29 AM UTC 24 |
191058786 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.4184131048 |
|
|
Sep 25 12:37:46 AM UTC 24 |
Sep 25 12:37:57 AM UTC 24 |
203394413 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.183339311 |
|
|
Sep 25 12:31:48 AM UTC 24 |
Sep 25 12:38:01 AM UTC 24 |
34053978571 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.3695275500 |
|
|
Sep 25 12:36:45 AM UTC 24 |
Sep 25 12:38:01 AM UTC 24 |
2021126406 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1387540836 |
|
|
Sep 25 12:33:05 AM UTC 24 |
Sep 25 12:38:03 AM UTC 24 |
31300742404 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3707480320 |
|
|
Sep 25 12:37:53 AM UTC 24 |
Sep 25 12:38:15 AM UTC 24 |
233356400 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2231225156 |
|
|
Sep 25 12:38:07 AM UTC 24 |
Sep 25 12:38:26 AM UTC 24 |
187646098 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.986733551 |
|
|
Sep 25 12:42:20 AM UTC 24 |
Sep 25 12:43:30 AM UTC 24 |
1122379783 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.4070950884 |
|
|
Sep 25 12:36:22 AM UTC 24 |
Sep 25 12:38:30 AM UTC 24 |
404528924 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3774255314 |
|
|
Sep 25 12:38:21 AM UTC 24 |
Sep 25 12:38:31 AM UTC 24 |
45700325 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.444116779 |
|
|
Sep 25 12:36:21 AM UTC 24 |
Sep 25 12:38:32 AM UTC 24 |
2897748314 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.205537428 |
|
|
Sep 25 12:32:40 AM UTC 24 |
Sep 25 12:38:32 AM UTC 24 |
2650710827 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1469457423 |
|
|
Sep 25 12:38:12 AM UTC 24 |
Sep 25 12:38:33 AM UTC 24 |
127102904 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.993105411 |
|
|
Sep 25 12:31:05 AM UTC 24 |
Sep 25 12:38:35 AM UTC 24 |
11664867166 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.3947486771 |
|
|
Sep 25 12:38:01 AM UTC 24 |
Sep 25 12:38:37 AM UTC 24 |
903129424 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.4059165636 |
|
|
Sep 25 12:37:54 AM UTC 24 |
Sep 25 12:38:41 AM UTC 24 |
958715079 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1970904842 |
|
|
Sep 25 12:37:56 AM UTC 24 |
Sep 25 12:38:42 AM UTC 24 |
1227116652 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.583616774 |
|
|
Sep 25 12:33:49 AM UTC 24 |
Sep 25 12:38:43 AM UTC 24 |
863438331 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.3474939545 |
|
|
Sep 25 12:38:02 AM UTC 24 |
Sep 25 12:38:47 AM UTC 24 |
775114308 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2637034455 |
|
|
Sep 25 12:31:15 AM UTC 24 |
Sep 25 12:38:50 AM UTC 24 |
7846383867 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2796676222 |
|
|
Sep 25 12:30:29 AM UTC 24 |
Sep 25 12:38:58 AM UTC 24 |
37086557578 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.1564660407 |
|
|
Sep 25 12:38:50 AM UTC 24 |
Sep 25 12:39:03 AM UTC 24 |
66542700 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.874476360 |
|
|
Sep 25 12:38:55 AM UTC 24 |
Sep 25 12:39:04 AM UTC 24 |
34277377 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3837718624 |
|
|
Sep 25 12:37:47 AM UTC 24 |
Sep 25 12:39:05 AM UTC 24 |
7467004088 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2210850477 |
|
|
Sep 25 12:38:45 AM UTC 24 |
Sep 25 12:39:15 AM UTC 24 |
297773406 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.2270648489 |
|
|
Sep 25 12:38:52 AM UTC 24 |
Sep 25 12:39:17 AM UTC 24 |
273434438 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4030082676 |
|
|
Sep 25 12:39:00 AM UTC 24 |
Sep 25 12:39:23 AM UTC 24 |
282661040 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.452045911 |
|
|
Sep 25 12:37:47 AM UTC 24 |
Sep 25 12:39:28 AM UTC 24 |
6700805051 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2321233893 |
|
|
Sep 25 12:38:15 AM UTC 24 |
Sep 25 12:39:28 AM UTC 24 |
163335437 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.1254176308 |
|
|
Sep 25 12:39:19 AM UTC 24 |
Sep 25 12:39:36 AM UTC 24 |
245890263 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.2983830940 |
|
|
Sep 25 12:38:51 AM UTC 24 |
Sep 25 12:39:37 AM UTC 24 |
511591081 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2267130766 |
|
|
Sep 25 12:39:25 AM UTC 24 |
Sep 25 12:39:37 AM UTC 24 |
54959496 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2806696058 |
|
|
Sep 25 12:27:27 AM UTC 24 |
Sep 25 12:39:43 AM UTC 24 |
41881356305 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.260821336 |
|
|
Sep 25 12:20:42 AM UTC 24 |
Sep 25 12:39:49 AM UTC 24 |
108479285891 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3111265021 |
|
|
Sep 25 12:39:03 AM UTC 24 |
Sep 25 12:39:53 AM UTC 24 |
143808656 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.322516146 |
|
|
Sep 25 12:38:34 AM UTC 24 |
Sep 25 12:39:57 AM UTC 24 |
5442647082 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2632978490 |
|
|
Sep 25 12:38:22 AM UTC 24 |
Sep 25 12:39:59 AM UTC 24 |
8820019808 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.807366579 |
|
|
Sep 25 12:38:55 AM UTC 24 |
Sep 25 12:40:01 AM UTC 24 |
984046453 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.2816182305 |
|
|
Sep 25 12:24:08 AM UTC 24 |
Sep 25 12:40:05 AM UTC 24 |
54047865567 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.948971631 |
|
|
Sep 25 12:32:18 AM UTC 24 |
Sep 25 12:40:05 AM UTC 24 |
1985066064 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1874091379 |
|
|
Sep 25 12:39:56 AM UTC 24 |
Sep 25 12:40:09 AM UTC 24 |
152564394 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.1576173868 |
|
|
Sep 25 12:39:58 AM UTC 24 |
Sep 25 12:40:11 AM UTC 24 |
65900848 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3483720121 |
|
|
Sep 25 12:39:01 AM UTC 24 |
Sep 25 12:40:24 AM UTC 24 |
1419168240 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.465876958 |
|
|
Sep 24 11:16:52 PM UTC 24 |
Sep 25 12:40:26 AM UTC 24 |
35541393100 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.1032384396 |
|
|
Sep 25 12:39:39 AM UTC 24 |
Sep 25 12:40:32 AM UTC 24 |
488918647 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.3701345347 |
|
|
Sep 25 12:33:53 AM UTC 24 |
Sep 25 12:40:36 AM UTC 24 |
10926675113 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2548078275 |
|
|
Sep 25 12:40:26 AM UTC 24 |
Sep 25 12:40:37 AM UTC 24 |
44469209 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.2193420779 |
|
|
Sep 25 12:38:16 AM UTC 24 |
Sep 25 12:40:37 AM UTC 24 |
3105759098 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2102169391 |
|
|
Sep 25 12:40:08 AM UTC 24 |
Sep 25 12:40:38 AM UTC 24 |
431759531 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.3624004554 |
|
|
Sep 25 12:40:26 AM UTC 24 |
Sep 25 12:40:39 AM UTC 24 |
168661807 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.4094769722 |
|
|
Sep 24 11:30:51 PM UTC 24 |
Sep 25 12:40:45 AM UTC 24 |
27418853996 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1916249958 |
|
|
Sep 25 12:40:13 AM UTC 24 |
Sep 25 12:40:50 AM UTC 24 |
239634758 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2576913445 |
|
|
Sep 25 12:37:15 AM UTC 24 |
Sep 25 12:40:52 AM UTC 24 |
2538762973 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.2784816680 |
|
|
Sep 25 12:38:15 AM UTC 24 |
Sep 25 12:40:53 AM UTC 24 |
2256820337 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3798276755 |
|
|
Sep 25 12:39:26 AM UTC 24 |
Sep 25 12:40:54 AM UTC 24 |
4042957131 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1598257068 |
|
|
Sep 25 12:39:36 AM UTC 24 |
Sep 25 12:40:57 AM UTC 24 |
1769830601 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.1555592769 |
|
|
Sep 25 12:40:04 AM UTC 24 |
Sep 25 12:40:58 AM UTC 24 |
837689389 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.3234928519 |
|
|
Sep 25 12:39:50 AM UTC 24 |
Sep 25 12:41:03 AM UTC 24 |
1206913932 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.2206925850 |
|
|
Sep 25 12:40:48 AM UTC 24 |
Sep 25 12:41:11 AM UTC 24 |
174949192 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.1535080736 |
|
|
Sep 25 12:39:25 AM UTC 24 |
Sep 25 12:41:27 AM UTC 24 |
8872307222 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2571270361 |
|
|
Sep 25 12:41:20 AM UTC 24 |
Sep 25 12:41:30 AM UTC 24 |
118867538 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.257009498 |
|
|
Sep 25 12:41:01 AM UTC 24 |
Sep 25 12:41:32 AM UTC 24 |
925702152 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.2687276969 |
|
|
Sep 25 12:37:23 AM UTC 24 |
Sep 25 12:41:36 AM UTC 24 |
3636559125 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.130368011 |
|
|
Sep 25 12:41:26 AM UTC 24 |
Sep 25 12:41:37 AM UTC 24 |
55890723 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.904417044 |
|
|
Sep 25 12:40:19 AM UTC 24 |
Sep 25 12:41:39 AM UTC 24 |
2250064136 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1915041306 |
|
|
Sep 25 12:41:07 AM UTC 24 |
Sep 25 12:41:44 AM UTC 24 |
201043871 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3061047863 |
|
|
Sep 25 12:41:11 AM UTC 24 |
Sep 25 12:41:44 AM UTC 24 |
571936873 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3381869576 |
|
|
Sep 25 12:36:11 AM UTC 24 |
Sep 25 12:41:44 AM UTC 24 |
709251294 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.3492837392 |
|
|
Sep 25 12:41:15 AM UTC 24 |
Sep 25 12:41:56 AM UTC 24 |
716281809 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.2014139758 |
|
|
Sep 25 12:41:01 AM UTC 24 |
Sep 25 12:41:59 AM UTC 24 |
1504121294 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.4017372346 |
|
|
Sep 25 12:41:53 AM UTC 24 |
Sep 25 12:42:01 AM UTC 24 |
28930691 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.1058646406 |
|
|
Sep 25 12:40:56 AM UTC 24 |
Sep 25 12:42:02 AM UTC 24 |
1080462110 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.2944139315 |
|
|
Sep 25 12:40:46 AM UTC 24 |
Sep 25 12:42:17 AM UTC 24 |
2407827369 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.3734052022 |
|
|
Sep 25 12:41:12 AM UTC 24 |
Sep 25 12:42:19 AM UTC 24 |
670368153 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.3116648461 |
|
|
Sep 25 12:41:59 AM UTC 24 |
Sep 25 12:42:30 AM UTC 24 |
403638498 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.346068820 |
|
|
Sep 25 12:40:32 AM UTC 24 |
Sep 25 12:42:43 AM UTC 24 |
5482536342 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2862374211 |
|
|
Sep 25 12:40:30 AM UTC 24 |
Sep 25 12:42:43 AM UTC 24 |
7397586749 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.637000410 |
|
|
Sep 25 12:41:54 AM UTC 24 |
Sep 25 12:42:55 AM UTC 24 |
606543377 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1658132301 |
|
|
Sep 25 12:41:59 AM UTC 24 |
Sep 25 12:43:02 AM UTC 24 |
3668533725 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1733625319 |
|
|
Sep 25 12:42:53 AM UTC 24 |
Sep 25 12:43:04 AM UTC 24 |
148237423 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1895454286 |
|
|
Sep 25 12:42:21 AM UTC 24 |
Sep 25 12:43:05 AM UTC 24 |
269694825 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1514179566 |
|
|
Sep 25 12:41:34 AM UTC 24 |
Sep 25 12:43:06 AM UTC 24 |
8460351559 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3645042009 |
|
|
Sep 25 12:43:03 AM UTC 24 |
Sep 25 12:43:14 AM UTC 24 |
43510344 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3178312847 |
|
|
Sep 25 12:41:50 AM UTC 24 |
Sep 25 12:43:14 AM UTC 24 |
4582967442 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.4141680129 |
|
|
Sep 25 12:42:06 AM UTC 24 |
Sep 25 12:43:16 AM UTC 24 |
1586458638 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3622925053 |
|
|
Sep 25 12:42:06 AM UTC 24 |
Sep 25 12:43:16 AM UTC 24 |
1615140978 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1816457466 |
|
|
Sep 25 12:33:09 AM UTC 24 |
Sep 25 12:43:41 AM UTC 24 |
38388610742 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3392654122 |
|
|
Sep 25 12:40:23 AM UTC 24 |
Sep 25 12:43:52 AM UTC 24 |
1264846787 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2550372150 |
|
|
Sep 25 12:35:48 AM UTC 24 |
Sep 25 12:43:58 AM UTC 24 |
30173890230 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3981167832 |
|
|
Sep 25 12:09:28 AM UTC 24 |
Sep 25 12:44:06 AM UTC 24 |
126232005844 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2013369277 |
|
|
Sep 25 12:43:23 AM UTC 24 |
Sep 25 12:44:17 AM UTC 24 |
589976690 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.609409249 |
|
|
Sep 25 12:43:37 AM UTC 24 |
Sep 25 12:44:20 AM UTC 24 |
582820825 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.1885721034 |
|
|
Sep 25 12:43:37 AM UTC 24 |
Sep 25 12:44:21 AM UTC 24 |
1010324309 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3564088889 |
|
|
Sep 25 12:37:23 AM UTC 24 |
Sep 25 12:44:23 AM UTC 24 |
2286126116 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1216017486 |
|
|
Sep 25 12:43:58 AM UTC 24 |
Sep 25 12:44:31 AM UTC 24 |
838845378 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2414991692 |
|
|
Sep 25 12:43:17 AM UTC 24 |
Sep 25 12:44:33 AM UTC 24 |
3583100908 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.4091128425 |
|
|
Sep 25 12:43:54 AM UTC 24 |
Sep 25 12:44:34 AM UTC 24 |
855710708 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.2014288288 |
|
|
Sep 25 12:44:25 AM UTC 24 |
Sep 25 12:44:38 AM UTC 24 |
234722232 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3134903245 |
|
|
Sep 25 12:44:38 AM UTC 24 |
Sep 25 12:44:45 AM UTC 24 |
35178446 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.1572604658 |
|
|
Sep 25 12:37:54 AM UTC 24 |
Sep 25 12:44:47 AM UTC 24 |
39971858126 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3157256776 |
|
|
Sep 25 12:37:55 AM UTC 24 |
Sep 25 12:44:47 AM UTC 24 |
22717931105 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3833961973 |
|
|
Sep 25 12:38:15 AM UTC 24 |
Sep 25 12:44:50 AM UTC 24 |
740482399 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.4052667601 |
|
|
Sep 25 12:44:20 AM UTC 24 |
Sep 25 12:44:59 AM UTC 24 |
132879755 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.3701115891 |
|
|
Sep 25 12:38:49 AM UTC 24 |
Sep 25 12:45:08 AM UTC 24 |
31348406831 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2945817129 |
|
|
Sep 25 12:43:05 AM UTC 24 |
Sep 25 12:45:13 AM UTC 24 |
7776450673 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2127328407 |
|
|
Sep 25 12:37:39 AM UTC 24 |
Sep 25 12:45:14 AM UTC 24 |
6170827593 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2768033418 |
|
|
Sep 25 12:24:14 AM UTC 24 |
Sep 25 12:45:15 AM UTC 24 |
83514854223 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.3143632518 |
|
|
Sep 25 12:44:52 AM UTC 24 |
Sep 25 12:45:17 AM UTC 24 |
218870515 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.557801598 |
|
|
Sep 25 12:44:45 AM UTC 24 |
Sep 25 12:45:32 AM UTC 24 |
1306351238 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2993756445 |
|
|
Sep 25 12:32:00 AM UTC 24 |
Sep 25 12:45:33 AM UTC 24 |
48189508058 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.1266912340 |
|
|
Sep 25 12:43:36 AM UTC 24 |
Sep 25 12:45:36 AM UTC 24 |
3071589907 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.2582428782 |
|
|
Sep 25 12:45:12 AM UTC 24 |
Sep 25 12:45:36 AM UTC 24 |
546478920 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.136095274 |
|
|
Sep 25 12:28:10 AM UTC 24 |
Sep 25 12:45:39 AM UTC 24 |
19276457210 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.3433509370 |
|
|
Sep 25 12:45:09 AM UTC 24 |
Sep 25 12:45:40 AM UTC 24 |
482666253 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3327898038 |
|
|
Sep 25 12:44:42 AM UTC 24 |
Sep 25 12:45:41 AM UTC 24 |
3302416782 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3796477208 |
|
|
Sep 25 12:45:20 AM UTC 24 |
Sep 25 12:45:45 AM UTC 24 |
348660364 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2221151720 |
|
|
Sep 25 12:44:03 AM UTC 24 |
Sep 25 12:45:46 AM UTC 24 |
166224965 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.120078790 |
|
|
Sep 25 12:45:38 AM UTC 24 |
Sep 25 12:45:49 AM UTC 24 |
58106934 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2179608505 |
|
|
Sep 25 12:45:50 AM UTC 24 |
Sep 25 12:45:57 AM UTC 24 |
42881416 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3607049860 |
|
|
Sep 25 12:41:16 AM UTC 24 |
Sep 25 12:45:59 AM UTC 24 |
625082602 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.898954702 |
|
|
Sep 25 12:42:23 AM UTC 24 |
Sep 25 12:46:01 AM UTC 24 |
4832302195 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3022142262 |
|
|
Sep 25 12:45:07 AM UTC 24 |
Sep 25 12:46:04 AM UTC 24 |
550900256 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.3681346056 |
|
|
Sep 25 12:45:00 AM UTC 24 |
Sep 25 12:46:05 AM UTC 24 |
1441564222 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.451062861 |
|
|
Sep 25 12:36:46 AM UTC 24 |
Sep 25 12:46:04 AM UTC 24 |
46679595867 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.1584821263 |
|
|
Sep 25 12:39:03 AM UTC 24 |
Sep 25 12:46:17 AM UTC 24 |
12070850791 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.4282609612 |
|
|
Sep 25 12:45:38 AM UTC 24 |
Sep 25 12:46:17 AM UTC 24 |
76577120 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.251388585 |
|
|
Sep 25 12:41:12 AM UTC 24 |
Sep 25 12:46:18 AM UTC 24 |
6172841553 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2629884506 |
|
|
Sep 25 12:40:53 AM UTC 24 |
Sep 25 12:46:23 AM UTC 24 |
27019013064 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.1353893657 |
|
|
Sep 25 12:46:10 AM UTC 24 |
Sep 25 12:46:25 AM UTC 24 |
226362262 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3004928537 |
|
|
Sep 25 12:44:41 AM UTC 24 |
Sep 25 12:46:26 AM UTC 24 |
7272678921 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.381834330 |
|
|
Sep 24 11:38:13 PM UTC 24 |
Sep 25 12:46:28 AM UTC 24 |
29473495249 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.4213242154 |
|
|
Sep 24 11:35:56 PM UTC 24 |
Sep 25 12:46:34 AM UTC 24 |
28268527622 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.103104833 |
|
|
Sep 25 12:27:18 AM UTC 24 |
Sep 25 12:46:35 AM UTC 24 |
62146040235 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2606763129 |
|
|
Sep 25 12:40:18 AM UTC 24 |
Sep 25 12:46:39 AM UTC 24 |
6699175374 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1065469086 |
|
|
Sep 25 12:45:58 AM UTC 24 |
Sep 25 12:46:47 AM UTC 24 |
419605111 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3105610122 |
|
|
Sep 25 12:46:39 AM UTC 24 |
Sep 25 12:46:49 AM UTC 24 |
39589033 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.312841600 |
|
|
Sep 25 12:46:18 AM UTC 24 |
Sep 25 12:46:50 AM UTC 24 |
214893172 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2753500364 |
|
|
Sep 25 12:46:39 AM UTC 24 |
Sep 25 12:46:51 AM UTC 24 |
201005612 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.733274268 |
|
|
Sep 25 12:39:08 AM UTC 24 |
Sep 25 12:46:51 AM UTC 24 |
3214040569 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.1943846997 |
|
|
Sep 25 12:30:29 AM UTC 24 |
Sep 25 12:46:55 AM UTC 24 |
98709395913 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1513051698 |
|
|
Sep 25 12:46:20 AM UTC 24 |
Sep 25 12:46:56 AM UTC 24 |
222604953 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.2368024225 |
|
|
Sep 25 12:46:00 AM UTC 24 |
Sep 25 12:47:01 AM UTC 24 |
468535918 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.475084101 |
|
|
Sep 25 12:45:53 AM UTC 24 |
Sep 25 12:47:21 AM UTC 24 |
6574640316 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.3103669302 |
|
|
Sep 25 12:46:04 AM UTC 24 |
Sep 25 12:47:25 AM UTC 24 |
929893661 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.875144463 |
|
|
Sep 25 12:46:17 AM UTC 24 |
Sep 25 12:47:28 AM UTC 24 |
1779368933 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.417861101 |
|
|
Sep 25 12:46:48 AM UTC 24 |
Sep 25 12:47:31 AM UTC 24 |
758000027 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.223640624 |
|
|
Sep 25 12:45:57 AM UTC 24 |
Sep 25 12:47:33 AM UTC 24 |
5540969856 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.3196247033 |
|
|
Sep 25 12:34:26 AM UTC 24 |
Sep 25 12:47:35 AM UTC 24 |
44882553933 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.573709470 |
|
|
Sep 25 12:47:13 AM UTC 24 |
Sep 25 12:47:36 AM UTC 24 |
140669757 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2697011509 |
|
|
Sep 25 12:47:13 AM UTC 24 |
Sep 25 12:47:39 AM UTC 24 |
214027281 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3476390941 |
|
|
Sep 25 12:46:50 AM UTC 24 |
Sep 25 12:47:50 AM UTC 24 |
473251571 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3173552914 |
|
|
Sep 25 12:47:49 AM UTC 24 |
Sep 25 12:47:56 AM UTC 24 |
36440142 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1522701501 |
|
|
Sep 25 12:47:47 AM UTC 24 |
Sep 25 12:47:59 AM UTC 24 |
170722496 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.1421249743 |
|
|
Sep 25 12:45:31 AM UTC 24 |
Sep 25 12:48:02 AM UTC 24 |
1654640032 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1680133201 |
|
|
Sep 25 12:45:37 AM UTC 24 |
Sep 25 12:48:07 AM UTC 24 |
3589387110 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4139371821 |
|
|
Sep 25 12:46:46 AM UTC 24 |
Sep 25 12:48:09 AM UTC 24 |
5035357695 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3629416640 |
|
|
Sep 25 12:47:11 AM UTC 24 |
Sep 25 12:48:11 AM UTC 24 |
1691215297 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.4258400636 |
|
|
Sep 25 12:47:57 AM UTC 24 |
Sep 25 12:48:17 AM UTC 24 |
174763419 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.3676917444 |
|
|
Sep 25 12:47:10 AM UTC 24 |
Sep 25 12:48:17 AM UTC 24 |
1456334244 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.3490905398 |
|
|
Sep 25 12:46:45 AM UTC 24 |
Sep 25 12:48:18 AM UTC 24 |
8641762465 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2137220155 |
|
|
Sep 25 12:46:25 AM UTC 24 |
Sep 25 12:48:34 AM UTC 24 |
255592503 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.3192667366 |
|
|
Sep 25 12:47:01 AM UTC 24 |
Sep 25 12:48:44 AM UTC 24 |
2899916800 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.2581389235 |
|
|
Sep 25 12:48:24 AM UTC 24 |
Sep 25 12:48:48 AM UTC 24 |
500744173 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2883296029 |
|
|
Sep 25 12:47:52 AM UTC 24 |
Sep 25 12:48:59 AM UTC 24 |
6112155254 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3142007253 |
|
|
Sep 25 12:48:32 AM UTC 24 |
Sep 25 12:49:00 AM UTC 24 |
377529202 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.923262988 |
|
|
Sep 25 12:47:57 AM UTC 24 |
Sep 25 12:49:01 AM UTC 24 |
1453553971 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4170515167 |
|
|
Sep 25 12:48:33 AM UTC 24 |
Sep 25 12:49:10 AM UTC 24 |
205255504 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.3761001037 |
|
|
Sep 24 11:19:51 PM UTC 24 |
Sep 25 12:49:10 AM UTC 24 |
30440401832 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2709426065 |
|
|
Sep 25 12:45:35 AM UTC 24 |
Sep 25 12:49:15 AM UTC 24 |
242033902 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.2727774977 |
|
|
Sep 25 12:44:55 AM UTC 24 |
Sep 25 12:49:16 AM UTC 24 |
16687852606 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.523305896 |
|
|
Sep 25 12:49:09 AM UTC 24 |
Sep 25 12:49:18 AM UTC 24 |
41171191 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2523648540 |
|
|
Sep 25 12:49:03 AM UTC 24 |
Sep 25 12:49:22 AM UTC 24 |
225483569 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2547967369 |
|
|
Sep 25 12:46:37 AM UTC 24 |
Sep 25 12:49:27 AM UTC 24 |
3138883683 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1750697484 |
|
|
Sep 25 12:47:55 AM UTC 24 |
Sep 25 12:49:32 AM UTC 24 |
6050681326 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.666178393 |
|
|
Sep 25 12:47:23 AM UTC 24 |
Sep 25 12:49:35 AM UTC 24 |
1964323306 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.3535439414 |
|
|
Sep 25 12:38:51 AM UTC 24 |
Sep 25 12:49:39 AM UTC 24 |
45755955209 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2244392435 |
|
|
Sep 25 12:42:25 AM UTC 24 |
Sep 25 12:49:39 AM UTC 24 |
514254817 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1966589179 |
|
|
Sep 25 12:45:59 AM UTC 24 |
Sep 25 12:49:40 AM UTC 24 |
21991249601 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1883885110 |
|
|
Sep 25 12:46:22 AM UTC 24 |
Sep 25 12:49:46 AM UTC 24 |
5044856793 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.1386936220 |
|
|
Sep 25 12:48:19 AM UTC 24 |
Sep 25 12:49:46 AM UTC 24 |
790053532 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.4273848013 |
|
|
Sep 25 12:48:28 AM UTC 24 |
Sep 25 12:49:50 AM UTC 24 |
2330208646 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.1161382853 |
|
|
Sep 25 12:49:21 AM UTC 24 |
Sep 25 12:49:55 AM UTC 24 |
777545498 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.253925710 |
|
|
Sep 25 12:49:58 AM UTC 24 |
Sep 25 12:50:06 AM UTC 24 |
21874037 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1115791404 |
|
|
Sep 25 12:49:52 AM UTC 24 |
Sep 25 12:50:17 AM UTC 24 |
556689947 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1747549620 |
|
|
Sep 25 12:50:09 AM UTC 24 |
Sep 25 12:50:22 AM UTC 24 |
193879783 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.415629042 |
|
|
Sep 25 12:50:12 AM UTC 24 |
Sep 25 12:50:23 AM UTC 24 |
41750215 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1651610601 |
|
|
Sep 25 12:49:50 AM UTC 24 |
Sep 25 12:50:39 AM UTC 24 |
479739830 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2618677616 |
|
|
Sep 25 12:49:44 AM UTC 24 |
Sep 25 12:50:42 AM UTC 24 |
497426049 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.2982678927 |
|
|
Sep 25 12:49:32 AM UTC 24 |
Sep 25 12:50:46 AM UTC 24 |
598589574 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.2223639899 |
|
|
Sep 25 12:46:57 AM UTC 24 |
Sep 25 12:50:50 AM UTC 24 |
18264337431 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2440945117 |
|
|
Sep 25 12:50:01 AM UTC 24 |
Sep 25 12:50:57 AM UTC 24 |
335239424 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.1497583638 |
|
|
Sep 25 12:49:20 AM UTC 24 |
Sep 25 12:51:14 AM UTC 24 |
9452807442 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.969102638 |
|
|
Sep 25 12:48:12 AM UTC 24 |
Sep 25 12:51:16 AM UTC 24 |
9540551074 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3613075340 |
|
|
Sep 25 12:49:22 AM UTC 24 |
Sep 25 12:51:22 AM UTC 24 |
6037621198 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3703494080 |
|
|
Sep 25 12:44:14 AM UTC 24 |
Sep 25 12:51:23 AM UTC 24 |
9255197415 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.3171608430 |
|
|
Sep 25 12:48:39 AM UTC 24 |
Sep 25 12:51:28 AM UTC 24 |
3733630604 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2739285778 |
|
|
Sep 25 12:49:38 AM UTC 24 |
Sep 25 12:51:28 AM UTC 24 |
1068267460 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.3720370137 |
|
|
Sep 25 12:50:41 AM UTC 24 |
Sep 25 12:51:32 AM UTC 24 |
848089309 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.4048225455 |
|
|
Sep 24 11:44:01 PM UTC 24 |
Sep 25 12:51:35 AM UTC 24 |
27702248109 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.4073223831 |
|
|
Sep 25 12:50:45 AM UTC 24 |
Sep 25 12:51:37 AM UTC 24 |
501603718 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4215848757 |
|
|
Sep 25 12:47:17 AM UTC 24 |
Sep 25 12:51:39 AM UTC 24 |
459074647 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.1433076371 |
|
|
Sep 25 12:51:13 AM UTC 24 |
Sep 25 12:51:40 AM UTC 24 |
220678349 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.3505703755 |
|
|
Sep 25 12:48:39 AM UTC 24 |
Sep 25 12:51:40 AM UTC 24 |
2272865877 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1240938499 |
|
|
Sep 25 12:51:18 AM UTC 24 |
Sep 25 12:51:41 AM UTC 24 |
552067600 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.565911906 |
|
|
Sep 25 12:50:17 AM UTC 24 |
Sep 25 12:51:46 AM UTC 24 |
6612131273 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3968585555 |
|
|
Sep 25 12:50:30 AM UTC 24 |
Sep 25 12:51:57 AM UTC 24 |
3857203553 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2121340081 |
|
|
Sep 25 12:51:58 AM UTC 24 |
Sep 25 12:52:06 AM UTC 24 |
45212651 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3809856322 |
|
|
Sep 25 12:51:53 AM UTC 24 |
Sep 25 12:52:08 AM UTC 24 |
219406911 ps |