| T431 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2914657453 |
|
|
Sep 25 05:26:12 AM UTC 24 |
Sep 25 06:01:46 AM UTC 24 |
26411672040 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.587437030 |
|
|
Sep 25 05:57:24 AM UTC 24 |
Sep 25 06:02:28 AM UTC 24 |
2373473672 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.2058413347 |
|
|
Sep 25 05:44:18 AM UTC 24 |
Sep 25 06:02:36 AM UTC 24 |
5905816920 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1255512020 |
|
|
Sep 25 05:54:19 AM UTC 24 |
Sep 25 06:02:56 AM UTC 24 |
3909135663 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.4080837213 |
|
|
Sep 25 05:51:24 AM UTC 24 |
Sep 25 06:02:57 AM UTC 24 |
4896503048 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.160324171 |
|
|
Sep 25 05:50:42 AM UTC 24 |
Sep 25 06:03:00 AM UTC 24 |
5574225534 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.26573734 |
|
|
Sep 25 05:50:59 AM UTC 24 |
Sep 25 06:03:12 AM UTC 24 |
6103401624 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1011230644 |
|
|
Sep 25 05:58:54 AM UTC 24 |
Sep 25 06:04:18 AM UTC 24 |
3330437046 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.4194673931 |
|
|
Sep 25 05:54:19 AM UTC 24 |
Sep 25 06:04:31 AM UTC 24 |
4446293480 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.2364877597 |
|
|
Sep 25 05:56:50 AM UTC 24 |
Sep 25 06:05:24 AM UTC 24 |
3569064447 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.1127782366 |
|
|
Sep 25 05:56:49 AM UTC 24 |
Sep 25 06:06:00 AM UTC 24 |
3447283416 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.701052305 |
|
|
Sep 25 05:54:56 AM UTC 24 |
Sep 25 06:06:47 AM UTC 24 |
5348874128 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.321762186 |
|
|
Sep 25 05:24:12 AM UTC 24 |
Sep 25 06:06:50 AM UTC 24 |
22376671880 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.3373953719 |
|
|
Sep 25 05:53:44 AM UTC 24 |
Sep 25 06:07:17 AM UTC 24 |
3806675710 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.3050208408 |
|
|
Sep 25 05:54:13 AM UTC 24 |
Sep 25 06:07:19 AM UTC 24 |
4771565514 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.4244239829 |
|
|
Sep 25 06:00:21 AM UTC 24 |
Sep 25 06:07:23 AM UTC 24 |
3671023816 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.2769052257 |
|
|
Sep 25 05:54:18 AM UTC 24 |
Sep 25 06:07:41 AM UTC 24 |
4353070644 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.480129927 |
|
|
Sep 25 05:33:13 AM UTC 24 |
Sep 25 06:08:07 AM UTC 24 |
11543056660 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3746510451 |
|
|
Sep 25 05:55:54 AM UTC 24 |
Sep 25 06:08:41 AM UTC 24 |
4460061180 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1073410013 |
|
|
Sep 25 04:50:11 AM UTC 24 |
Sep 25 06:09:24 AM UTC 24 |
17560274420 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.347669383 |
|
|
Sep 25 05:56:13 AM UTC 24 |
Sep 25 06:10:04 AM UTC 24 |
5680315992 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.3802455477 |
|
|
Sep 25 06:00:20 AM UTC 24 |
Sep 25 06:10:15 AM UTC 24 |
4334468226 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3463949723 |
|
|
Sep 25 04:50:36 AM UTC 24 |
Sep 25 06:10:29 AM UTC 24 |
18467269953 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.453517681 |
|
|
Sep 25 06:05:58 AM UTC 24 |
Sep 25 06:10:36 AM UTC 24 |
2500369862 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3017612370 |
|
|
Sep 25 06:08:26 AM UTC 24 |
Sep 25 06:11:16 AM UTC 24 |
2911603721 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3872420672 |
|
|
Sep 25 06:03:54 AM UTC 24 |
Sep 25 06:11:56 AM UTC 24 |
3772489120 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1718369671 |
|
|
Sep 25 06:08:24 AM UTC 24 |
Sep 25 06:12:29 AM UTC 24 |
2975269346 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1140798465 |
|
|
Sep 25 06:06:35 AM UTC 24 |
Sep 25 06:12:46 AM UTC 24 |
2899608756 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1552975516 |
|
|
Sep 25 05:35:30 AM UTC 24 |
Sep 25 06:12:49 AM UTC 24 |
16058306482 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.116429859 |
|
|
Sep 25 06:11:12 AM UTC 24 |
Sep 25 06:12:59 AM UTC 24 |
2124391321 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2683589862 |
|
|
Sep 25 06:11:11 AM UTC 24 |
Sep 25 06:13:17 AM UTC 24 |
2620659253 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.1202957333 |
|
|
Sep 25 06:02:22 AM UTC 24 |
Sep 25 06:13:17 AM UTC 24 |
3664267864 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.3867766295 |
|
|
Sep 25 05:58:55 AM UTC 24 |
Sep 25 06:13:41 AM UTC 24 |
6954734833 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.58200645 |
|
|
Sep 25 05:02:12 AM UTC 24 |
Sep 25 06:14:22 AM UTC 24 |
13992139112 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.540727342 |
|
|
Sep 25 06:03:12 AM UTC 24 |
Sep 25 06:14:42 AM UTC 24 |
4809772234 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3277967940 |
|
|
Sep 25 06:09:16 AM UTC 24 |
Sep 25 06:14:48 AM UTC 24 |
3146541442 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.4292288370 |
|
|
Sep 25 05:33:40 AM UTC 24 |
Sep 25 06:15:06 AM UTC 24 |
23550269169 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3038604952 |
|
|
Sep 25 06:03:11 AM UTC 24 |
Sep 25 06:15:13 AM UTC 24 |
4581369517 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.3892966340 |
|
|
Sep 25 04:29:30 AM UTC 24 |
Sep 25 06:16:37 AM UTC 24 |
43043729483 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.494959793 |
|
|
Sep 25 05:52:25 AM UTC 24 |
Sep 25 06:17:21 AM UTC 24 |
9656353156 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.1266068149 |
|
|
Sep 25 06:13:48 AM UTC 24 |
Sep 25 06:18:25 AM UTC 24 |
3079031116 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.189882454 |
|
|
Sep 25 03:56:14 AM UTC 24 |
Sep 25 06:19:13 AM UTC 24 |
26479581768 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1215938479 |
|
|
Sep 25 06:13:03 AM UTC 24 |
Sep 25 06:19:33 AM UTC 24 |
4045020344 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1985100459 |
|
|
Sep 25 06:07:35 AM UTC 24 |
Sep 25 06:20:41 AM UTC 24 |
4218797032 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.3559546692 |
|
|
Sep 25 06:03:55 AM UTC 24 |
Sep 25 06:22:09 AM UTC 24 |
5264138180 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.64995271 |
|
|
Sep 25 06:14:15 AM UTC 24 |
Sep 25 06:22:38 AM UTC 24 |
8292051379 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3146615228 |
|
|
Sep 25 05:54:13 AM UTC 24 |
Sep 25 06:23:00 AM UTC 24 |
8289912106 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1129848738 |
|
|
Sep 25 06:03:54 AM UTC 24 |
Sep 25 06:23:39 AM UTC 24 |
6206148667 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.829491935 |
|
|
Sep 25 06:20:06 AM UTC 24 |
Sep 25 06:24:08 AM UTC 24 |
2566533940 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.924331697 |
|
|
Sep 25 06:14:14 AM UTC 24 |
Sep 25 06:24:21 AM UTC 24 |
5171732086 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.3176405390 |
|
|
Sep 25 06:08:40 AM UTC 24 |
Sep 25 06:25:03 AM UTC 24 |
10627481812 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1920530303 |
|
|
Sep 25 06:05:05 AM UTC 24 |
Sep 25 06:25:23 AM UTC 24 |
5894337213 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.4210680138 |
|
|
Sep 25 06:14:13 AM UTC 24 |
Sep 25 06:26:22 AM UTC 24 |
5005273608 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.2559030977 |
|
|
Sep 25 04:36:11 AM UTC 24 |
Sep 25 06:26:46 AM UTC 24 |
47650217192 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3996181805 |
|
|
Sep 25 06:21:16 AM UTC 24 |
Sep 25 06:27:25 AM UTC 24 |
2449325950 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.623458267 |
|
|
Sep 25 06:08:19 AM UTC 24 |
Sep 25 06:27:32 AM UTC 24 |
7576595336 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2334600458 |
|
|
Sep 25 06:17:10 AM UTC 24 |
Sep 25 06:27:43 AM UTC 24 |
5664788624 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.3826986088 |
|
|
Sep 25 06:10:50 AM UTC 24 |
Sep 25 06:27:44 AM UTC 24 |
8172104404 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3964737968 |
|
|
Sep 25 06:20:42 AM UTC 24 |
Sep 25 06:28:40 AM UTC 24 |
3804946160 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.602007362 |
|
|
Sep 25 06:15:51 AM UTC 24 |
Sep 25 06:28:52 AM UTC 24 |
10093498084 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2437439201 |
|
|
Sep 25 06:07:35 AM UTC 24 |
Sep 25 06:28:59 AM UTC 24 |
8212287808 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2519441562 |
|
|
Sep 25 06:08:26 AM UTC 24 |
Sep 25 06:29:19 AM UTC 24 |
7677307630 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4128523675 |
|
|
Sep 25 06:18:59 AM UTC 24 |
Sep 25 06:29:33 AM UTC 24 |
5417477450 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2638685328 |
|
|
Sep 25 06:23:14 AM UTC 24 |
Sep 25 06:29:46 AM UTC 24 |
3561745858 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4242062874 |
|
|
Sep 25 06:14:19 AM UTC 24 |
Sep 25 06:30:47 AM UTC 24 |
6727213865 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3650388452 |
|
|
Sep 25 06:24:52 AM UTC 24 |
Sep 25 06:31:26 AM UTC 24 |
3498551061 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1680656293 |
|
|
Sep 25 06:25:38 AM UTC 24 |
Sep 25 06:32:05 AM UTC 24 |
3738173120 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.680303752 |
|
|
Sep 25 06:25:56 AM UTC 24 |
Sep 25 06:32:55 AM UTC 24 |
6698016560 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.951192693 |
|
|
Sep 25 04:34:55 AM UTC 24 |
Sep 25 06:33:31 AM UTC 24 |
49705221628 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1663303275 |
|
|
Sep 25 06:30:07 AM UTC 24 |
Sep 25 06:34:47 AM UTC 24 |
3382834012 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3014875063 |
|
|
Sep 25 06:23:52 AM UTC 24 |
Sep 25 06:34:49 AM UTC 24 |
6490725296 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.2616956722 |
|
|
Sep 25 05:10:09 AM UTC 24 |
Sep 25 06:35:40 AM UTC 24 |
17639208148 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3063877593 |
|
|
Sep 25 05:36:19 AM UTC 24 |
Sep 25 06:35:50 AM UTC 24 |
11998098750 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.3314321194 |
|
|
Sep 25 06:30:18 AM UTC 24 |
Sep 25 06:36:02 AM UTC 24 |
3555746566 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2942357116 |
|
|
Sep 25 06:23:34 AM UTC 24 |
Sep 25 06:36:22 AM UTC 24 |
5315683062 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.4001313013 |
|
|
Sep 25 06:31:22 AM UTC 24 |
Sep 25 06:38:08 AM UTC 24 |
3466501254 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.1353941538 |
|
|
Sep 25 06:29:37 AM UTC 24 |
Sep 25 06:38:09 AM UTC 24 |
3485272220 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3778523819 |
|
|
Sep 25 04:34:54 AM UTC 24 |
Sep 25 06:38:18 AM UTC 24 |
49048413005 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2617424389 |
|
|
Sep 25 06:28:28 AM UTC 24 |
Sep 25 06:38:57 AM UTC 24 |
18358593400 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.434945918 |
|
|
Sep 25 06:14:58 AM UTC 24 |
Sep 25 06:38:58 AM UTC 24 |
11987475231 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.3334984986 |
|
|
Sep 25 06:32:41 AM UTC 24 |
Sep 25 06:39:03 AM UTC 24 |
2927819400 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1354675213 |
|
|
Sep 25 06:27:20 AM UTC 24 |
Sep 25 06:39:27 AM UTC 24 |
5496203852 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4155269260 |
|
|
Sep 25 05:54:15 AM UTC 24 |
Sep 25 06:39:47 AM UTC 24 |
13319473254 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2492552792 |
|
|
Sep 25 06:31:58 AM UTC 24 |
Sep 25 06:40:05 AM UTC 24 |
2758171933 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.279590527 |
|
|
Sep 25 06:34:06 AM UTC 24 |
Sep 25 06:40:58 AM UTC 24 |
4853924464 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2389871113 |
|
|
Sep 25 06:28:34 AM UTC 24 |
Sep 25 06:41:06 AM UTC 24 |
5488274850 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3592735794 |
|
|
Sep 25 06:26:56 AM UTC 24 |
Sep 25 06:41:35 AM UTC 24 |
7410275000 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.1578357472 |
|
|
Sep 25 06:03:46 AM UTC 24 |
Sep 25 06:41:38 AM UTC 24 |
19585711256 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.173533956 |
|
|
Sep 25 06:33:29 AM UTC 24 |
Sep 25 06:41:42 AM UTC 24 |
5190084272 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.734456059 |
|
|
Sep 25 06:15:51 AM UTC 24 |
Sep 25 06:42:02 AM UTC 24 |
11040475432 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.579848930 |
|
|
Sep 25 06:15:27 AM UTC 24 |
Sep 25 06:43:03 AM UTC 24 |
18093805777 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3346738394 |
|
|
Sep 25 06:39:03 AM UTC 24 |
Sep 25 06:43:28 AM UTC 24 |
2781570304 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.3160616444 |
|
|
Sep 25 06:39:02 AM UTC 24 |
Sep 25 06:44:15 AM UTC 24 |
3001483541 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.2037238316 |
|
|
Sep 25 06:28:34 AM UTC 24 |
Sep 25 06:45:41 AM UTC 24 |
5927647250 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.2357859429 |
|
|
Sep 25 06:39:07 AM UTC 24 |
Sep 25 06:45:56 AM UTC 24 |
3478738840 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.254637920 |
|
|
Sep 25 06:36:25 AM UTC 24 |
Sep 25 06:46:17 AM UTC 24 |
3930927344 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3699705152 |
|
|
Sep 25 06:29:51 AM UTC 24 |
Sep 25 06:46:39 AM UTC 24 |
5161488372 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.209473925 |
|
|
Sep 25 06:41:43 AM UTC 24 |
Sep 25 06:47:52 AM UTC 24 |
3423504260 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3021068858 |
|
|
Sep 25 06:42:38 AM UTC 24 |
Sep 25 06:48:03 AM UTC 24 |
2720590256 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.1993881623 |
|
|
Sep 25 06:43:40 AM UTC 24 |
Sep 25 06:49:27 AM UTC 24 |
2852296718 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.2503277120 |
|
|
Sep 25 06:44:03 AM UTC 24 |
Sep 25 06:49:39 AM UTC 24 |
3318190850 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2586362901 |
|
|
Sep 25 06:44:35 AM UTC 24 |
Sep 25 06:49:42 AM UTC 24 |
2664201798 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1374057347 |
|
|
Sep 25 06:39:59 AM UTC 24 |
Sep 25 06:50:00 AM UTC 24 |
2754369960 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.1540591689 |
|
|
Sep 25 06:29:37 AM UTC 24 |
Sep 25 06:50:19 AM UTC 24 |
5204330740 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.1917204867 |
|
|
Sep 25 05:36:08 AM UTC 24 |
Sep 25 06:50:41 AM UTC 24 |
22799950884 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.353593638 |
|
|
Sep 25 06:41:43 AM UTC 24 |
Sep 25 06:51:33 AM UTC 24 |
5346862168 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3072896168 |
|
|
Sep 25 06:44:48 AM UTC 24 |
Sep 25 06:51:34 AM UTC 24 |
3472704712 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.2112419066 |
|
|
Sep 25 06:40:03 AM UTC 24 |
Sep 25 06:51:36 AM UTC 24 |
3915073784 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1241984008 |
|
|
Sep 25 06:40:21 AM UTC 24 |
Sep 25 06:51:50 AM UTC 24 |
6035044912 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3163738878 |
|
|
Sep 25 06:39:59 AM UTC 24 |
Sep 25 06:52:33 AM UTC 24 |
3651068008 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.3519549448 |
|
|
Sep 25 06:13:59 AM UTC 24 |
Sep 25 06:53:08 AM UTC 24 |
13735991928 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.4181231985 |
|
|
Sep 25 05:36:11 AM UTC 24 |
Sep 25 06:53:29 AM UTC 24 |
14915059330 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.2923271336 |
|
|
Sep 25 06:50:34 AM UTC 24 |
Sep 25 06:55:05 AM UTC 24 |
2516703836 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2195904204 |
|
|
Sep 25 06:50:52 AM UTC 24 |
Sep 25 06:55:14 AM UTC 24 |
2531638202 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.6683658 |
|
|
Sep 25 05:38:54 AM UTC 24 |
Sep 25 06:55:31 AM UTC 24 |
14984055120 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3265703023 |
|
|
Sep 25 06:50:29 AM UTC 24 |
Sep 25 06:55:45 AM UTC 24 |
3036788948 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.711888951 |
|
|
Sep 25 05:38:58 AM UTC 24 |
Sep 25 06:55:58 AM UTC 24 |
15043320968 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.2983656406 |
|
|
Sep 25 06:51:16 AM UTC 24 |
Sep 25 06:56:05 AM UTC 24 |
2418286044 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.3770083557 |
|
|
Sep 25 05:36:02 AM UTC 24 |
Sep 25 06:56:06 AM UTC 24 |
14884190121 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3707398210 |
|
|
Sep 25 06:50:34 AM UTC 24 |
Sep 25 06:56:09 AM UTC 24 |
2977922070 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.4155207826 |
|
|
Sep 25 05:37:45 AM UTC 24 |
Sep 25 06:56:22 AM UTC 24 |
15526120469 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.236455290 |
|
|
Sep 25 05:36:22 AM UTC 24 |
Sep 25 06:56:32 AM UTC 24 |
15358042772 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1480645788 |
|
|
Sep 25 06:12:29 AM UTC 24 |
Sep 25 06:57:09 AM UTC 24 |
31454403741 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2304494896 |
|
|
Sep 25 05:38:58 AM UTC 24 |
Sep 25 06:58:42 AM UTC 24 |
15209010392 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.708481648 |
|
|
Sep 25 06:40:06 AM UTC 24 |
Sep 25 06:59:42 AM UTC 24 |
5753800180 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.626111612 |
|
|
Sep 25 05:36:43 AM UTC 24 |
Sep 25 06:59:51 AM UTC 24 |
15084949313 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2741047531 |
|
|
Sep 25 06:15:26 AM UTC 24 |
Sep 25 07:00:21 AM UTC 24 |
28722675033 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.980899122 |
|
|
Sep 25 06:35:32 AM UTC 24 |
Sep 25 07:00:26 AM UTC 24 |
8282209700 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.814830561 |
|
|
Sep 25 06:55:52 AM UTC 24 |
Sep 25 07:00:59 AM UTC 24 |
2415906720 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.4021897353 |
|
|
Sep 25 06:42:26 AM UTC 24 |
Sep 25 07:00:59 AM UTC 24 |
5680342380 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.598719191 |
|
|
Sep 25 06:36:25 AM UTC 24 |
Sep 25 07:01:13 AM UTC 24 |
10588516834 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.2672984842 |
|
|
Sep 25 06:24:12 AM UTC 24 |
Sep 25 07:02:05 AM UTC 24 |
23099874208 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.846668377 |
|
|
Sep 25 05:37:46 AM UTC 24 |
Sep 25 07:02:26 AM UTC 24 |
14746419032 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3041553292 |
|
|
Sep 25 06:42:44 AM UTC 24 |
Sep 25 07:02:38 AM UTC 24 |
7266867624 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1693028300 |
|
|
Sep 25 06:52:41 AM UTC 24 |
Sep 25 07:02:40 AM UTC 24 |
4639495884 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.1494205365 |
|
|
Sep 25 06:57:31 AM UTC 24 |
Sep 25 07:02:43 AM UTC 24 |
3336388936 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3884972428 |
|
|
Sep 25 06:55:52 AM UTC 24 |
Sep 25 07:04:04 AM UTC 24 |
5198049900 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.257351266 |
|
|
Sep 25 06:46:52 AM UTC 24 |
Sep 25 07:04:11 AM UTC 24 |
6198927858 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.160793397 |
|
|
Sep 25 06:57:27 AM UTC 24 |
Sep 25 07:05:00 AM UTC 24 |
3942947480 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.2158780413 |
|
|
Sep 25 06:46:31 AM UTC 24 |
Sep 25 07:05:01 AM UTC 24 |
6389728210 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3721479859 |
|
|
Sep 25 06:52:41 AM UTC 24 |
Sep 25 07:05:04 AM UTC 24 |
9748954652 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3661089662 |
|
|
Sep 25 06:52:43 AM UTC 24 |
Sep 25 07:05:09 AM UTC 24 |
4686835992 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.458963578 |
|
|
Sep 25 05:32:17 AM UTC 24 |
Sep 25 07:05:31 AM UTC 24 |
24735444330 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.3203611918 |
|
|
Sep 25 07:03:00 AM UTC 24 |
Sep 25 07:06:33 AM UTC 24 |
2248178378 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2256639821 |
|
|
Sep 25 06:57:47 AM UTC 24 |
Sep 25 07:06:48 AM UTC 24 |
3995996872 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1620573749 |
|
|
Sep 25 06:36:39 AM UTC 24 |
Sep 25 07:07:24 AM UTC 24 |
8295244818 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1316514839 |
|
|
Sep 25 06:59:17 AM UTC 24 |
Sep 25 07:07:24 AM UTC 24 |
6625221719 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.4020946389 |
|
|
Sep 25 06:58:51 AM UTC 24 |
Sep 25 07:07:33 AM UTC 24 |
4616603628 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1944464382 |
|
|
Sep 25 06:53:09 AM UTC 24 |
Sep 25 07:07:35 AM UTC 24 |
6983072152 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1178447222 |
|
|
Sep 25 06:57:32 AM UTC 24 |
Sep 25 07:07:35 AM UTC 24 |
3530506020 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3988388793 |
|
|
Sep 25 06:57:19 AM UTC 24 |
Sep 25 07:07:53 AM UTC 24 |
5040624456 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.563101385 |
|
|
Sep 25 05:38:36 AM UTC 24 |
Sep 25 07:08:15 AM UTC 24 |
17644731912 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3085755318 |
|
|
Sep 25 06:54:05 AM UTC 24 |
Sep 25 07:08:38 AM UTC 24 |
7043738988 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1088649329 |
|
|
Sep 25 06:47:14 AM UTC 24 |
Sep 25 07:08:51 AM UTC 24 |
7124383413 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3666976284 |
|
|
Sep 25 06:36:56 AM UTC 24 |
Sep 25 07:08:58 AM UTC 24 |
8391187864 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.74300273 |
|
|
Sep 25 06:53:46 AM UTC 24 |
Sep 25 07:09:39 AM UTC 24 |
9757509760 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2517637299 |
|
|
Sep 25 07:02:40 AM UTC 24 |
Sep 25 07:09:51 AM UTC 24 |
3549189932 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.786872123 |
|
|
Sep 25 06:57:27 AM UTC 24 |
Sep 25 07:10:33 AM UTC 24 |
4019008584 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.2422336130 |
|
|
Sep 25 06:52:42 AM UTC 24 |
Sep 25 07:10:58 AM UTC 24 |
9407854694 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3901987629 |
|
|
Sep 25 07:00:28 AM UTC 24 |
Sep 25 07:11:03 AM UTC 24 |
4475620700 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3504521683 |
|
|
Sep 25 07:01:51 AM UTC 24 |
Sep 25 07:11:06 AM UTC 24 |
3413014601 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2545358629 |
|
|
Sep 25 07:00:24 AM UTC 24 |
Sep 25 07:11:12 AM UTC 24 |
4389620348 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3956023019 |
|
|
Sep 25 07:08:15 AM UTC 24 |
Sep 25 07:11:44 AM UTC 24 |
3188439445 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2328766336 |
|
|
Sep 25 07:01:06 AM UTC 24 |
Sep 25 07:11:53 AM UTC 24 |
4333227384 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1837825517 |
|
|
Sep 25 07:01:05 AM UTC 24 |
Sep 25 07:12:42 AM UTC 24 |
3972286976 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2998373031 |
|
|
Sep 25 07:01:55 AM UTC 24 |
Sep 25 07:13:19 AM UTC 24 |
5320552776 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4291271948 |
|
|
Sep 25 07:09:32 AM UTC 24 |
Sep 25 07:13:23 AM UTC 24 |
3042790408 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.1664850699 |
|
|
Sep 25 07:08:31 AM UTC 24 |
Sep 25 07:13:27 AM UTC 24 |
3502870732 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3621946328 |
|
|
Sep 25 07:06:18 AM UTC 24 |
Sep 25 07:13:38 AM UTC 24 |
3994823332 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1728042635 |
|
|
Sep 25 07:07:22 AM UTC 24 |
Sep 25 07:14:07 AM UTC 24 |
3953001156 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1864661664 |
|
|
Sep 25 07:09:32 AM UTC 24 |
Sep 25 07:14:16 AM UTC 24 |
2416817384 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3792401556 |
|
|
Sep 25 07:07:08 AM UTC 24 |
Sep 25 07:14:16 AM UTC 24 |
5685414510 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.278304993 |
|
|
Sep 25 07:01:51 AM UTC 24 |
Sep 25 07:14:21 AM UTC 24 |
4413011632 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.3129873800 |
|
|
Sep 25 07:04:52 AM UTC 24 |
Sep 25 07:14:31 AM UTC 24 |
5541586248 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.3424064793 |
|
|
Sep 25 06:46:16 AM UTC 24 |
Sep 25 07:14:38 AM UTC 24 |
7331833508 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.915243569 |
|
|
Sep 25 07:06:24 AM UTC 24 |
Sep 25 07:14:41 AM UTC 24 |
7294074914 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4019044051 |
|
|
Sep 25 07:03:16 AM UTC 24 |
Sep 25 07:14:43 AM UTC 24 |
4582866538 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.833172756 |
|
|
Sep 25 07:09:12 AM UTC 24 |
Sep 25 07:15:29 AM UTC 24 |
3102937126 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2806493862 |
|
|
Sep 25 07:11:08 AM UTC 24 |
Sep 25 07:15:39 AM UTC 24 |
2599488726 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3604792378 |
|
|
Sep 25 07:08:34 AM UTC 24 |
Sep 25 07:16:05 AM UTC 24 |
4675408037 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2643556483 |
|
|
Sep 25 07:08:36 AM UTC 24 |
Sep 25 07:16:07 AM UTC 24 |
3788755160 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.938861825 |
|
|
Sep 25 07:06:21 AM UTC 24 |
Sep 25 07:16:08 AM UTC 24 |
5990327212 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2516369862 |
|
|
Sep 25 07:10:26 AM UTC 24 |
Sep 25 07:17:25 AM UTC 24 |
3080297112 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1577748290 |
|
|
Sep 25 07:08:35 AM UTC 24 |
Sep 25 07:17:25 AM UTC 24 |
5595636686 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3790318763 |
|
|
Sep 25 07:12:33 AM UTC 24 |
Sep 25 07:17:29 AM UTC 24 |
2862904667 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3415703732 |
|
|
Sep 25 07:13:18 AM UTC 24 |
Sep 25 07:17:45 AM UTC 24 |
2956738963 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2300383653 |
|
|
Sep 25 07:12:27 AM UTC 24 |
Sep 25 07:18:22 AM UTC 24 |
2947215808 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.556453027 |
|
|
Sep 25 06:57:13 AM UTC 24 |
Sep 25 07:19:22 AM UTC 24 |
6980536298 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.1531264248 |
|
|
Sep 25 06:42:43 AM UTC 24 |
Sep 25 07:19:28 AM UTC 24 |
8357916560 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.4043241765 |
|
|
Sep 25 06:57:43 AM UTC 24 |
Sep 25 07:20:16 AM UTC 24 |
10198120040 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.1416363186 |
|
|
Sep 25 07:19:29 AM UTC 24 |
Sep 25 07:21:36 AM UTC 24 |
1938246024 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4106797715 |
|
|
Sep 25 07:17:25 AM UTC 24 |
Sep 25 07:22:32 AM UTC 24 |
2431955830 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.2447927430 |
|
|
Sep 25 06:48:41 AM UTC 24 |
Sep 25 07:22:42 AM UTC 24 |
8959616310 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2938472126 |
|
|
Sep 25 07:14:24 AM UTC 24 |
Sep 25 07:23:09 AM UTC 24 |
4832752624 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3640320611 |
|
|
Sep 25 07:10:26 AM UTC 24 |
Sep 25 07:23:11 AM UTC 24 |
5480420580 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.3820413737 |
|
|
Sep 25 07:04:51 AM UTC 24 |
Sep 25 07:23:53 AM UTC 24 |
7216467442 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2818931543 |
|
|
Sep 25 07:12:00 AM UTC 24 |
Sep 25 07:24:40 AM UTC 24 |
5122318481 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.2279136086 |
|
|
Sep 25 07:20:11 AM UTC 24 |
Sep 25 07:25:29 AM UTC 24 |
4765353079 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1381138329 |
|
|
Sep 25 07:14:25 AM UTC 24 |
Sep 25 07:25:52 AM UTC 24 |
4109790768 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.4051721915 |
|
|
Sep 25 07:17:18 AM UTC 24 |
Sep 25 07:27:28 AM UTC 24 |
10985536986 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.320205892 |
|
|
Sep 25 07:22:11 AM UTC 24 |
Sep 25 07:27:57 AM UTC 24 |
2962543120 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.396471488 |
|
|
Sep 25 07:23:18 AM UTC 24 |
Sep 25 07:27:59 AM UTC 24 |
2718813924 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.3353438956 |
|
|
Sep 25 07:23:52 AM UTC 24 |
Sep 25 07:28:02 AM UTC 24 |
2426293370 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.1568802044 |
|
|
Sep 25 07:20:52 AM UTC 24 |
Sep 25 07:28:17 AM UTC 24 |
4898350558 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.4218569221 |
|
|
Sep 25 07:24:26 AM UTC 24 |
Sep 25 07:28:52 AM UTC 24 |
2767305659 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.1535759347 |
|
|
Sep 25 07:23:15 AM UTC 24 |
Sep 25 07:29:36 AM UTC 24 |
3284589380 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1841284453 |
|
|
Sep 25 07:06:25 AM UTC 24 |
Sep 25 07:29:47 AM UTC 24 |
23561855920 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3402488273 |
|
|
Sep 25 07:08:30 AM UTC 24 |
Sep 25 07:29:50 AM UTC 24 |
13427043903 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2756513615 |
|
|
Sep 25 06:24:56 AM UTC 24 |
Sep 25 07:31:07 AM UTC 24 |
20444084241 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.1576375323 |
|
|
Sep 25 07:26:03 AM UTC 24 |
Sep 25 07:31:08 AM UTC 24 |
3034741064 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1993721235 |
|
|
Sep 25 07:12:01 AM UTC 24 |
Sep 25 07:31:35 AM UTC 24 |
7208564593 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2835406174 |
|
|
Sep 25 07:23:53 AM UTC 24 |
Sep 25 07:31:46 AM UTC 24 |
3813927888 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.2895112575 |
|
|
Sep 25 07:25:13 AM UTC 24 |
Sep 25 07:33:18 AM UTC 24 |
3242091232 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.174182596 |
|
|
Sep 25 07:29:26 AM UTC 24 |
Sep 25 07:33:36 AM UTC 24 |
2701351270 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3871540297 |
|
|
Sep 25 07:29:02 AM UTC 24 |
Sep 25 07:34:00 AM UTC 24 |
2738861152 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.3991772048 |
|
|
Sep 25 07:30:30 AM UTC 24 |
Sep 25 07:34:15 AM UTC 24 |
2948588086 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2726641534 |
|
|
Sep 25 07:28:58 AM UTC 24 |
Sep 25 07:34:24 AM UTC 24 |
2674069380 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.4245406003 |
|
|
Sep 25 07:28:03 AM UTC 24 |
Sep 25 07:34:41 AM UTC 24 |
3385159206 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.3119376147 |
|
|
Sep 25 06:48:38 AM UTC 24 |
Sep 25 07:35:02 AM UTC 24 |
11654491808 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.341065062 |
|
|
Sep 25 07:15:51 AM UTC 24 |
Sep 25 07:35:59 AM UTC 24 |
5947433576 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.529352219 |
|
|
Sep 25 06:56:17 AM UTC 24 |
Sep 25 07:36:42 AM UTC 24 |
31493215296 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.2147417469 |
|
|
Sep 25 07:30:36 AM UTC 24 |
Sep 25 07:36:43 AM UTC 24 |
2752345518 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1060764735 |
|
|
Sep 25 07:06:22 AM UTC 24 |
Sep 25 07:37:41 AM UTC 24 |
22622480328 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.2925227307 |
|
|
Sep 25 07:29:03 AM UTC 24 |
Sep 25 07:37:43 AM UTC 24 |
6013540004 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1303819529 |
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Sep 25 07:12:34 AM UTC 24 |
Sep 25 07:37:53 AM UTC 24 |
8005548044 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1590993924 |
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|
Sep 25 07:29:04 AM UTC 24 |
Sep 25 07:38:09 AM UTC 24 |
5365171328 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.3190981009 |
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|
Sep 25 07:08:42 AM UTC 24 |
Sep 25 07:39:46 AM UTC 24 |
15669587777 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.2789593944 |
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|
Sep 25 07:38:13 AM UTC 24 |
Sep 25 07:41:48 AM UTC 24 |
3405146209 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1891436646 |
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|
Sep 25 07:35:01 AM UTC 24 |
Sep 25 07:42:41 AM UTC 24 |
6006099090 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.792910807 |
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|
Sep 25 07:31:56 AM UTC 24 |
Sep 25 07:42:42 AM UTC 24 |
3890482816 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.316480276 |
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|
Sep 25 07:32:23 AM UTC 24 |
Sep 25 07:43:32 AM UTC 24 |
4434755280 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.4260711363 |
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|
Sep 25 07:30:36 AM UTC 24 |
Sep 25 07:43:39 AM UTC 24 |
4882107940 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.2756556429 |
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|
Sep 25 07:37:14 AM UTC 24 |
Sep 25 07:43:55 AM UTC 24 |
4801987684 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.4280400371 |
|
|
Sep 25 07:33:36 AM UTC 24 |
Sep 25 07:44:19 AM UTC 24 |
4702913802 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2075933308 |
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|
Sep 25 07:34:12 AM UTC 24 |
Sep 25 07:44:23 AM UTC 24 |
3872594949 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.3349401975 |
|
|
Sep 25 07:32:24 AM UTC 24 |
Sep 25 07:44:31 AM UTC 24 |
4765522852 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177130920 |
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|
Sep 25 07:35:15 AM UTC 24 |
Sep 25 07:44:34 AM UTC 24 |
3980804338 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.4096391579 |
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|
Sep 25 07:18:02 AM UTC 24 |
Sep 25 07:44:40 AM UTC 24 |
5991771050 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.2854715127 |
|
|
Sep 25 07:31:55 AM UTC 24 |
Sep 25 07:44:47 AM UTC 24 |
6111327714 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.1416204721 |
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|
Sep 25 07:36:32 AM UTC 24 |
Sep 25 07:46:46 AM UTC 24 |
5067305688 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1688341500 |
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|
Sep 25 06:19:49 AM UTC 24 |
Sep 25 07:47:01 AM UTC 24 |
37112234896 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.625541755 |
|
|
Sep 25 07:37:15 AM UTC 24 |
Sep 25 07:47:42 AM UTC 24 |
6914065785 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.1592422194 |
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|
Sep 25 07:03:04 AM UTC 24 |
Sep 25 07:47:55 AM UTC 24 |
22582251400 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2292940579 |
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|
Sep 25 06:04:45 AM UTC 24 |
Sep 25 07:49:31 AM UTC 24 |
44118838950 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4272289255 |
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|
Sep 25 06:28:35 AM UTC 24 |
Sep 25 07:50:12 AM UTC 24 |
16721064000 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.4218883525 |
|
|
Sep 25 07:14:05 AM UTC 24 |
Sep 25 07:51:51 AM UTC 24 |
17501888639 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.3458394962 |
|
|
Sep 25 07:38:44 AM UTC 24 |
Sep 25 07:51:59 AM UTC 24 |
5493756408 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.986954134 |
|
|
Sep 25 07:40:22 AM UTC 24 |
Sep 25 07:51:59 AM UTC 24 |
4036929242 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.4056504349 |
|
|
Sep 25 07:38:26 AM UTC 24 |
Sep 25 07:52:08 AM UTC 24 |
6266092976 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2129193237 |
|
|
Sep 25 07:35:01 AM UTC 24 |
Sep 25 07:53:19 AM UTC 24 |
13227568190 ps |