| T1339 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3641946693 |
|
|
Sep 25 07:57:07 AM UTC 24 |
Sep 25 09:39:23 AM UTC 24 |
25925463018 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.882447543 |
|
|
Sep 25 04:19:55 AM UTC 24 |
Sep 25 09:51:36 AM UTC 24 |
81855190050 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2824228913 |
|
|
Sep 25 07:35:37 AM UTC 24 |
Sep 25 09:52:00 AM UTC 24 |
32906677464 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2475994657 |
|
|
Sep 25 05:54:13 AM UTC 24 |
Sep 25 10:08:44 AM UTC 24 |
67567443697 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1220187654 |
|
|
Sep 25 05:36:08 AM UTC 24 |
Sep 25 10:12:16 AM UTC 24 |
90771886899 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.712294541 |
|
|
Sep 25 05:54:12 AM UTC 24 |
Sep 25 10:37:03 AM UTC 24 |
81702064230 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.240360964 |
|
|
Sep 24 11:11:42 PM UTC 24 |
Sep 24 11:11:50 PM UTC 24 |
47140739 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2545221185 |
|
|
Sep 24 11:11:44 PM UTC 24 |
Sep 24 11:11:53 PM UTC 24 |
42071125 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3360355390 |
|
|
Sep 24 11:11:50 PM UTC 24 |
Sep 24 11:12:17 PM UTC 24 |
312470126 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.766408528 |
|
|
Sep 24 11:11:55 PM UTC 24 |
Sep 24 11:12:20 PM UTC 24 |
189671138 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3119612532 |
|
|
Sep 24 11:11:57 PM UTC 24 |
Sep 24 11:12:28 PM UTC 24 |
250710232 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3801929827 |
|
|
Sep 24 11:11:58 PM UTC 24 |
Sep 24 11:12:43 PM UTC 24 |
421891142 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.2681253316 |
|
|
Sep 24 11:11:51 PM UTC 24 |
Sep 24 11:12:43 PM UTC 24 |
553240330 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2221577054 |
|
|
Sep 24 11:11:59 PM UTC 24 |
Sep 24 11:12:54 PM UTC 24 |
1348469030 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.705633775 |
|
|
Sep 24 11:11:47 PM UTC 24 |
Sep 24 11:13:04 PM UTC 24 |
4112007601 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.447068115 |
|
|
Sep 24 11:12:09 PM UTC 24 |
Sep 24 11:13:04 PM UTC 24 |
459649265 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.282427207 |
|
|
Sep 24 11:12:52 PM UTC 24 |
Sep 24 11:13:06 PM UTC 24 |
190229281 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3649575192 |
|
|
Sep 24 11:11:45 PM UTC 24 |
Sep 24 11:13:10 PM UTC 24 |
8160879353 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3322676766 |
|
|
Sep 24 11:13:02 PM UTC 24 |
Sep 24 11:13:11 PM UTC 24 |
42821529 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2325271433 |
|
|
Sep 24 11:13:12 PM UTC 24 |
Sep 24 11:13:29 PM UTC 24 |
231315214 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2741402623 |
|
|
Sep 24 11:11:50 PM UTC 24 |
Sep 24 11:13:39 PM UTC 24 |
1047733718 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1773534741 |
|
|
Sep 24 11:11:42 PM UTC 24 |
Sep 24 11:13:50 PM UTC 24 |
3989154904 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2914699978 |
|
|
Sep 24 11:13:13 PM UTC 24 |
Sep 24 11:13:53 PM UTC 24 |
455946383 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.759828536 |
|
|
Sep 24 11:13:31 PM UTC 24 |
Sep 24 11:14:02 PM UTC 24 |
552749402 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3192775804 |
|
|
Sep 24 11:13:42 PM UTC 24 |
Sep 24 11:14:06 PM UTC 24 |
514324695 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.2045317665 |
|
|
Sep 24 11:13:30 PM UTC 24 |
Sep 24 11:14:08 PM UTC 24 |
428961465 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1044391473 |
|
|
Sep 24 11:13:27 PM UTC 24 |
Sep 24 11:14:17 PM UTC 24 |
341669805 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1744344337 |
|
|
Sep 24 11:13:41 PM UTC 24 |
Sep 24 11:14:33 PM UTC 24 |
765354151 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3010420593 |
|
|
Sep 24 11:13:12 PM UTC 24 |
Sep 24 11:14:59 PM UTC 24 |
5891089438 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3903868221 |
|
|
Sep 24 11:13:03 PM UTC 24 |
Sep 24 11:15:03 PM UTC 24 |
7558563170 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2769884004 |
|
|
Sep 24 11:12:11 PM UTC 24 |
Sep 24 11:15:05 PM UTC 24 |
506482457 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1078247041 |
|
|
Sep 24 11:14:57 PM UTC 24 |
Sep 24 11:15:07 PM UTC 24 |
47319970 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1171337149 |
|
|
Sep 24 11:14:57 PM UTC 24 |
Sep 24 11:15:10 PM UTC 24 |
166788961 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3540017163 |
|
|
Sep 24 11:13:50 PM UTC 24 |
Sep 24 11:15:36 PM UTC 24 |
173223553 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1455977449 |
|
|
Sep 24 11:15:27 PM UTC 24 |
Sep 24 11:15:59 PM UTC 24 |
216854675 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.1552816813 |
|
|
Sep 24 11:15:23 PM UTC 24 |
Sep 24 11:16:01 PM UTC 24 |
686453766 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2633369915 |
|
|
Sep 24 11:11:42 PM UTC 24 |
Sep 24 11:16:12 PM UTC 24 |
3278018530 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2004648127 |
|
|
Sep 24 11:16:01 PM UTC 24 |
Sep 24 11:16:15 PM UTC 24 |
128841969 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.1719066387 |
|
|
Sep 24 11:12:43 PM UTC 24 |
Sep 24 11:16:20 PM UTC 24 |
3899106104 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.1830489472 |
|
|
Sep 24 11:15:55 PM UTC 24 |
Sep 24 11:16:20 PM UTC 24 |
196762931 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.3868987385 |
|
|
Sep 24 11:15:53 PM UTC 24 |
Sep 24 11:16:26 PM UTC 24 |
715556526 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.1672409385 |
|
|
Sep 24 11:12:14 PM UTC 24 |
Sep 24 11:16:31 PM UTC 24 |
4473667369 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1979632356 |
|
|
Sep 24 11:14:28 PM UTC 24 |
Sep 24 11:16:36 PM UTC 24 |
2868017132 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.988872969 |
|
|
Sep 24 11:16:38 PM UTC 24 |
Sep 24 11:16:59 PM UTC 24 |
8211845 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1678855350 |
|
|
Sep 24 11:16:01 PM UTC 24 |
Sep 24 11:17:04 PM UTC 24 |
1126449945 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.1500172556 |
|
|
Sep 24 11:12:43 PM UTC 24 |
Sep 24 11:17:11 PM UTC 24 |
8200667868 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2671519426 |
|
|
Sep 24 11:15:23 PM UTC 24 |
Sep 24 11:17:14 PM UTC 24 |
6198051463 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3141998976 |
|
|
Sep 24 11:15:20 PM UTC 24 |
Sep 24 11:17:15 PM UTC 24 |
7854029102 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1922578030 |
|
|
Sep 24 11:12:01 PM UTC 24 |
Sep 24 11:17:17 PM UTC 24 |
8788237670 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.2141481847 |
|
|
Sep 24 11:17:18 PM UTC 24 |
Sep 24 11:17:29 PM UTC 24 |
56238372 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2668590510 |
|
|
Sep 24 11:17:25 PM UTC 24 |
Sep 24 11:17:36 PM UTC 24 |
55075075 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.522659143 |
|
|
Sep 24 11:17:37 PM UTC 24 |
Sep 24 11:18:07 PM UTC 24 |
272969895 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.975271681 |
|
|
Sep 24 11:15:51 PM UTC 24 |
Sep 24 11:18:11 PM UTC 24 |
2275866300 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2144107812 |
|
|
Sep 24 11:12:04 PM UTC 24 |
Sep 24 11:18:18 PM UTC 24 |
944165629 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.1086073548 |
|
|
Sep 24 11:17:36 PM UTC 24 |
Sep 24 11:18:38 PM UTC 24 |
1531480448 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.832129663 |
|
|
Sep 24 11:13:49 PM UTC 24 |
Sep 24 11:18:38 PM UTC 24 |
7323003718 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2760701594 |
|
|
Sep 24 11:13:58 PM UTC 24 |
Sep 24 11:18:45 PM UTC 24 |
2440533890 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1759397972 |
|
|
Sep 24 11:14:08 PM UTC 24 |
Sep 24 11:18:56 PM UTC 24 |
5079324832 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.740243422 |
|
|
Sep 24 11:17:30 PM UTC 24 |
Sep 24 11:18:59 PM UTC 24 |
5952228409 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.978856327 |
|
|
Sep 24 11:18:57 PM UTC 24 |
Sep 24 11:19:10 PM UTC 24 |
156746733 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.1493905373 |
|
|
Sep 24 11:18:39 PM UTC 24 |
Sep 24 11:19:19 PM UTC 24 |
459813820 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.1484299095 |
|
|
Sep 24 11:18:32 PM UTC 24 |
Sep 24 11:19:24 PM UTC 24 |
1400293984 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.697304886 |
|
|
Sep 24 11:11:53 PM UTC 24 |
Sep 24 11:19:29 PM UTC 24 |
25763584246 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.1915676425 |
|
|
Sep 24 11:18:57 PM UTC 24 |
Sep 24 11:19:31 PM UTC 24 |
242851676 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3058555798 |
|
|
Sep 24 11:16:58 PM UTC 24 |
Sep 24 11:19:33 PM UTC 24 |
2810458001 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3020820556 |
|
|
Sep 24 11:17:33 PM UTC 24 |
Sep 24 11:19:41 PM UTC 24 |
5557318172 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.531353622 |
|
|
Sep 24 11:16:18 PM UTC 24 |
Sep 24 11:19:55 PM UTC 24 |
2512174905 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.4173258138 |
|
|
Sep 24 11:16:32 PM UTC 24 |
Sep 24 11:20:29 PM UTC 24 |
2466250589 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.529557631 |
|
|
Sep 24 11:17:56 PM UTC 24 |
Sep 24 11:20:37 PM UTC 24 |
2672498776 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2557405713 |
|
|
Sep 24 11:20:32 PM UTC 24 |
Sep 24 11:20:43 PM UTC 24 |
54206282 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3410215846 |
|
|
Sep 24 11:12:20 PM UTC 24 |
Sep 24 11:20:46 PM UTC 24 |
5667018308 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2731929830 |
|
|
Sep 24 11:20:35 PM UTC 24 |
Sep 24 11:20:47 PM UTC 24 |
59438385 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2856974321 |
|
|
Sep 24 11:14:12 PM UTC 24 |
Sep 24 11:20:48 PM UTC 24 |
4663960480 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.231458916 |
|
|
Sep 24 11:19:02 PM UTC 24 |
Sep 24 11:21:03 PM UTC 24 |
1013539744 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.869759593 |
|
|
Sep 24 11:19:17 PM UTC 24 |
Sep 24 11:21:04 PM UTC 24 |
1003396986 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3893443509 |
|
|
Sep 24 11:19:16 PM UTC 24 |
Sep 24 11:21:35 PM UTC 24 |
298412547 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.1534714504 |
|
|
Sep 24 11:21:05 PM UTC 24 |
Sep 24 11:21:53 PM UTC 24 |
1022997077 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.2218120491 |
|
|
Sep 24 11:13:55 PM UTC 24 |
Sep 24 11:21:53 PM UTC 24 |
11773408373 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.1351160798 |
|
|
Sep 24 11:21:08 PM UTC 24 |
Sep 24 11:21:56 PM UTC 24 |
379270341 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3099177025 |
|
|
Sep 24 11:17:51 PM UTC 24 |
Sep 24 11:22:05 PM UTC 24 |
13359334248 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.2605727336 |
|
|
Sep 24 11:21:10 PM UTC 24 |
Sep 24 11:22:08 PM UTC 24 |
3370689173 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.335074577 |
|
|
Sep 24 11:21:25 PM UTC 24 |
Sep 24 11:22:09 PM UTC 24 |
482606205 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.2767832912 |
|
|
Sep 24 11:20:50 PM UTC 24 |
Sep 24 11:22:16 PM UTC 24 |
8623979348 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3991240656 |
|
|
Sep 24 11:21:57 PM UTC 24 |
Sep 24 11:22:25 PM UTC 24 |
458407799 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.242461065 |
|
|
Sep 24 11:21:26 PM UTC 24 |
Sep 24 11:22:35 PM UTC 24 |
1864000874 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2721394035 |
|
|
Sep 24 11:21:00 PM UTC 24 |
Sep 24 11:22:55 PM UTC 24 |
5618856808 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3814425141 |
|
|
Sep 24 11:16:42 PM UTC 24 |
Sep 24 11:22:58 PM UTC 24 |
7448959830 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1863470782 |
|
|
Sep 24 11:22:14 PM UTC 24 |
Sep 24 11:23:02 PM UTC 24 |
272754114 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.4189249148 |
|
|
Sep 24 11:16:22 PM UTC 24 |
Sep 24 11:23:10 PM UTC 24 |
1020318945 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.1595232191 |
|
|
Sep 24 11:21:52 PM UTC 24 |
Sep 24 11:23:23 PM UTC 24 |
2367813167 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3236559871 |
|
|
Sep 24 11:23:23 PM UTC 24 |
Sep 24 11:23:34 PM UTC 24 |
41247409 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2376370889 |
|
|
Sep 24 11:23:19 PM UTC 24 |
Sep 24 11:23:35 PM UTC 24 |
224464729 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.1174560194 |
|
|
Sep 24 11:14:39 PM UTC 24 |
Sep 24 11:24:08 PM UTC 24 |
8360044332 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1389145539 |
|
|
Sep 24 11:11:43 PM UTC 24 |
Sep 24 11:24:24 PM UTC 24 |
13297173898 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3883873409 |
|
|
Sep 24 11:12:17 PM UTC 24 |
Sep 24 11:24:33 PM UTC 24 |
5695405455 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.923836948 |
|
|
Sep 24 11:22:17 PM UTC 24 |
Sep 24 11:24:40 PM UTC 24 |
747303020 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2797093756 |
|
|
Sep 24 11:12:49 PM UTC 24 |
Sep 24 11:24:40 PM UTC 24 |
11872623160 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.75057478 |
|
|
Sep 24 11:23:43 PM UTC 24 |
Sep 24 11:24:46 PM UTC 24 |
2796750342 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3710577995 |
|
|
Sep 24 11:23:31 PM UTC 24 |
Sep 24 11:24:47 PM UTC 24 |
5799145378 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1302220145 |
|
|
Sep 24 11:23:57 PM UTC 24 |
Sep 24 11:25:00 PM UTC 24 |
498452281 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1286891524 |
|
|
Sep 24 11:11:49 PM UTC 24 |
Sep 24 11:25:18 PM UTC 24 |
65977886502 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.3295653865 |
|
|
Sep 24 11:25:07 PM UTC 24 |
Sep 24 11:25:21 PM UTC 24 |
63523774 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.790465080 |
|
|
Sep 24 11:23:54 PM UTC 24 |
Sep 24 11:25:30 PM UTC 24 |
2096644688 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3139284172 |
|
|
Sep 24 11:25:06 PM UTC 24 |
Sep 24 11:25:41 PM UTC 24 |
399397494 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2069183063 |
|
|
Sep 24 11:22:26 PM UTC 24 |
Sep 24 11:25:43 PM UTC 24 |
2167357299 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.1723540133 |
|
|
Sep 24 11:16:45 PM UTC 24 |
Sep 24 11:25:52 PM UTC 24 |
7699319858 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.1740568618 |
|
|
Sep 24 11:25:00 PM UTC 24 |
Sep 24 11:25:58 PM UTC 24 |
1743912889 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.2166797483 |
|
|
Sep 24 11:16:41 PM UTC 24 |
Sep 24 11:26:01 PM UTC 24 |
4566506120 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2938279812 |
|
|
Sep 24 11:25:19 PM UTC 24 |
Sep 24 11:26:03 PM UTC 24 |
689012154 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.2017713468 |
|
|
Sep 24 11:22:29 PM UTC 24 |
Sep 24 11:26:04 PM UTC 24 |
4046628906 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2213405897 |
|
|
Sep 24 11:15:48 PM UTC 24 |
Sep 24 11:26:20 PM UTC 24 |
39564488080 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.3780472652 |
|
|
Sep 24 11:24:54 PM UTC 24 |
Sep 24 11:26:28 PM UTC 24 |
1674827389 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1093783257 |
|
|
Sep 24 11:26:23 PM UTC 24 |
Sep 24 11:26:32 PM UTC 24 |
165480106 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3079933807 |
|
|
Sep 24 11:26:23 PM UTC 24 |
Sep 24 11:26:33 PM UTC 24 |
40571189 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2099561715 |
|
|
Sep 24 11:22:28 PM UTC 24 |
Sep 24 11:26:46 PM UTC 24 |
785053415 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.84754594 |
|
|
Sep 24 11:15:27 PM UTC 24 |
Sep 24 11:27:12 PM UTC 24 |
71774835949 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.454200412 |
|
|
Sep 24 11:26:50 PM UTC 24 |
Sep 24 11:27:13 PM UTC 24 |
123399526 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.1914729626 |
|
|
Sep 24 11:17:39 PM UTC 24 |
Sep 24 11:27:16 PM UTC 24 |
49140275784 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1790465897 |
|
|
Sep 24 11:26:54 PM UTC 24 |
Sep 24 11:27:19 PM UTC 24 |
143596401 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.996658261 |
|
|
Sep 24 11:14:53 PM UTC 24 |
Sep 24 11:27:30 PM UTC 24 |
14461995806 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1287740973 |
|
|
Sep 24 11:26:41 PM UTC 24 |
Sep 24 11:27:41 PM UTC 24 |
4047962561 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3912846086 |
|
|
Sep 24 11:20:16 PM UTC 24 |
Sep 24 11:27:42 PM UTC 24 |
4799691072 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3945254258 |
|
|
Sep 24 11:25:53 PM UTC 24 |
Sep 24 11:27:56 PM UTC 24 |
309273954 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.747949473 |
|
|
Sep 24 11:13:24 PM UTC 24 |
Sep 24 11:28:00 PM UTC 24 |
52493410387 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.3572016030 |
|
|
Sep 24 11:19:37 PM UTC 24 |
Sep 24 11:28:07 PM UTC 24 |
5942309944 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3038270202 |
|
|
Sep 24 11:21:24 PM UTC 24 |
Sep 24 11:28:21 PM UTC 24 |
25587161242 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2048180010 |
|
|
Sep 24 11:22:15 PM UTC 24 |
Sep 24 11:28:26 PM UTC 24 |
8029639919 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.39243333 |
|
|
Sep 24 11:27:37 PM UTC 24 |
Sep 24 11:28:31 PM UTC 24 |
1320355725 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.2265917489 |
|
|
Sep 24 11:26:26 PM UTC 24 |
Sep 24 11:28:32 PM UTC 24 |
8078602154 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.508415413 |
|
|
Sep 24 11:28:03 PM UTC 24 |
Sep 24 11:28:33 PM UTC 24 |
508383351 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.2836179352 |
|
|
Sep 24 11:26:21 PM UTC 24 |
Sep 24 11:28:39 PM UTC 24 |
2805731252 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3556485000 |
|
|
Sep 24 11:11:54 PM UTC 24 |
Sep 24 11:28:46 PM UTC 24 |
48619240321 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4058676742 |
|
|
Sep 24 11:19:45 PM UTC 24 |
Sep 24 11:29:00 PM UTC 24 |
6725504432 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1881305090 |
|
|
Sep 24 11:27:52 PM UTC 24 |
Sep 24 11:29:07 PM UTC 24 |
1177721448 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3060661479 |
|
|
Sep 24 11:29:00 PM UTC 24 |
Sep 24 11:29:09 PM UTC 24 |
38250217 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.13542568 |
|
|
Sep 24 11:27:28 PM UTC 24 |
Sep 24 11:29:10 PM UTC 24 |
1886954675 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.510909655 |
|
|
Sep 24 11:28:54 PM UTC 24 |
Sep 24 11:29:10 PM UTC 24 |
220859642 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2610727909 |
|
|
Sep 24 11:27:36 PM UTC 24 |
Sep 24 11:29:12 PM UTC 24 |
1903644815 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.58828153 |
|
|
Sep 24 11:25:38 PM UTC 24 |
Sep 24 11:29:16 PM UTC 24 |
306852197 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.1122532920 |
|
|
Sep 24 11:16:49 PM UTC 24 |
Sep 24 11:29:27 PM UTC 24 |
6904737601 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.3502046009 |
|
|
Sep 24 11:29:31 PM UTC 24 |
Sep 24 11:29:42 PM UTC 24 |
45597405 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2663238559 |
|
|
Sep 24 11:19:30 PM UTC 24 |
Sep 24 11:29:45 PM UTC 24 |
6097181585 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1286862508 |
|
|
Sep 24 11:29:29 PM UTC 24 |
Sep 24 11:29:46 PM UTC 24 |
150430221 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.2136946258 |
|
|
Sep 24 11:24:29 PM UTC 24 |
Sep 24 11:30:05 PM UTC 24 |
22479083087 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2753080563 |
|
|
Sep 24 11:23:16 PM UTC 24 |
Sep 24 11:30:17 PM UTC 24 |
3975702800 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.687618359 |
|
|
Sep 24 11:14:14 PM UTC 24 |
Sep 24 11:30:18 PM UTC 24 |
12386313656 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.1079607211 |
|
|
Sep 24 11:29:33 PM UTC 24 |
Sep 24 11:30:27 PM UTC 24 |
479788027 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.1924703311 |
|
|
Sep 24 11:29:07 PM UTC 24 |
Sep 24 11:30:28 PM UTC 24 |
6328544752 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.978947795 |
|
|
Sep 24 11:30:08 PM UTC 24 |
Sep 24 11:30:33 PM UTC 24 |
168030229 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.2671041276 |
|
|
Sep 24 11:29:46 PM UTC 24 |
Sep 24 11:30:33 PM UTC 24 |
485269627 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.172643317 |
|
|
Sep 24 11:11:39 PM UTC 24 |
Sep 24 11:30:33 PM UTC 24 |
7413792740 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1516251482 |
|
|
Sep 24 11:29:22 PM UTC 24 |
Sep 24 11:30:39 PM UTC 24 |
4337681360 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.3204710442 |
|
|
Sep 24 11:30:07 PM UTC 24 |
Sep 24 11:30:56 PM UTC 24 |
817191109 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2809753243 |
|
|
Sep 24 11:30:54 PM UTC 24 |
Sep 24 11:31:04 PM UTC 24 |
126681252 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3553885372 |
|
|
Sep 24 11:31:00 PM UTC 24 |
Sep 24 11:31:11 PM UTC 24 |
53087305 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.1845649794 |
|
|
Sep 24 11:29:33 PM UTC 24 |
Sep 24 11:31:20 PM UTC 24 |
6343300422 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.4236109877 |
|
|
Sep 24 11:30:02 PM UTC 24 |
Sep 24 11:31:23 PM UTC 24 |
1955595181 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3244067881 |
|
|
Sep 24 11:28:21 PM UTC 24 |
Sep 24 11:31:32 PM UTC 24 |
1624895205 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1371143392 |
|
|
Sep 24 11:30:40 PM UTC 24 |
Sep 24 11:31:55 PM UTC 24 |
356211526 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.2081757831 |
|
|
Sep 24 11:31:42 PM UTC 24 |
Sep 24 11:32:07 PM UTC 24 |
166176406 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.296417660 |
|
|
Sep 24 11:28:17 PM UTC 24 |
Sep 24 11:32:16 PM UTC 24 |
521425266 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.4185372178 |
|
|
Sep 24 11:19:42 PM UTC 24 |
Sep 24 11:32:17 PM UTC 24 |
6493370148 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3546853589 |
|
|
Sep 24 11:31:25 PM UTC 24 |
Sep 24 11:32:34 PM UTC 24 |
3857074666 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.888203207 |
|
|
Sep 24 11:31:33 PM UTC 24 |
Sep 24 11:32:41 PM UTC 24 |
532574100 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.492705034 |
|
|
Sep 24 11:26:02 PM UTC 24 |
Sep 24 11:32:45 PM UTC 24 |
4528864023 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.655630687 |
|
|
Sep 24 11:31:16 PM UTC 24 |
Sep 24 11:32:48 PM UTC 24 |
5944270405 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1139908392 |
|
|
Sep 24 11:32:39 PM UTC 24 |
Sep 24 11:32:49 PM UTC 24 |
39775573 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2070265893 |
|
|
Sep 24 11:15:30 PM UTC 24 |
Sep 24 11:32:58 PM UTC 24 |
64869230685 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.4198630524 |
|
|
Sep 24 11:13:25 PM UTC 24 |
Sep 24 11:33:13 PM UTC 24 |
110763134193 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.2316821444 |
|
|
Sep 24 11:28:54 PM UTC 24 |
Sep 24 11:33:23 PM UTC 24 |
3967524728 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1994444291 |
|
|
Sep 24 11:32:37 PM UTC 24 |
Sep 24 11:33:26 PM UTC 24 |
450932955 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.1988067840 |
|
|
Sep 24 11:24:46 PM UTC 24 |
Sep 24 11:33:30 PM UTC 24 |
29519231785 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.673791836 |
|
|
Sep 24 11:31:53 PM UTC 24 |
Sep 24 11:33:32 PM UTC 24 |
4357828881 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3526077397 |
|
|
Sep 24 11:33:02 PM UTC 24 |
Sep 24 11:33:32 PM UTC 24 |
210447714 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.1603128671 |
|
|
Sep 24 11:25:42 PM UTC 24 |
Sep 24 11:33:33 PM UTC 24 |
4841919224 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.2919967168 |
|
|
Sep 24 11:14:13 PM UTC 24 |
Sep 24 11:33:33 PM UTC 24 |
11044048804 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.3847791699 |
|
|
Sep 24 11:32:56 PM UTC 24 |
Sep 24 11:33:39 PM UTC 24 |
673082201 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.1137501373 |
|
|
Sep 24 11:32:16 PM UTC 24 |
Sep 24 11:33:41 PM UTC 24 |
1913136344 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1421691164 |
|
|
Sep 24 11:22:47 PM UTC 24 |
Sep 24 11:33:52 PM UTC 24 |
6919848728 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2243006053 |
|
|
Sep 24 11:33:52 PM UTC 24 |
Sep 24 11:34:03 PM UTC 24 |
45579644 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.257650200 |
|
|
Sep 24 11:33:50 PM UTC 24 |
Sep 24 11:34:03 PM UTC 24 |
205321595 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.249063207 |
|
|
Sep 24 11:22:38 PM UTC 24 |
Sep 24 11:34:11 PM UTC 24 |
5407411636 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3730489943 |
|
|
Sep 24 11:28:28 PM UTC 24 |
Sep 24 11:34:13 PM UTC 24 |
2606810552 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3265465860 |
|
|
Sep 24 11:33:04 PM UTC 24 |
Sep 24 11:34:32 PM UTC 24 |
982212535 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.2797669682 |
|
|
Sep 24 11:33:59 PM UTC 24 |
Sep 24 11:34:32 PM UTC 24 |
352810087 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.561141527 |
|
|
Sep 24 11:34:02 PM UTC 24 |
Sep 24 11:34:38 PM UTC 24 |
335394520 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.3867652057 |
|
|
Sep 24 11:34:34 PM UTC 24 |
Sep 24 11:34:55 PM UTC 24 |
145530289 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2366782897 |
|
|
Sep 24 11:34:24 PM UTC 24 |
Sep 24 11:34:56 PM UTC 24 |
630125024 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3459539309 |
|
|
Sep 24 11:33:51 PM UTC 24 |
Sep 24 11:35:10 PM UTC 24 |
4736071642 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1936202 |
|
|
Sep 24 11:30:26 PM UTC 24 |
Sep 24 11:35:15 PM UTC 24 |
6790256246 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.2826875784 |
|
|
Sep 24 11:21:10 PM UTC 24 |
Sep 24 11:35:15 PM UTC 24 |
53401210423 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.1662366041 |
|
|
Sep 24 11:33:53 PM UTC 24 |
Sep 24 11:35:19 PM UTC 24 |
6519645148 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2087239913 |
|
|
Sep 24 11:33:08 PM UTC 24 |
Sep 24 11:35:36 PM UTC 24 |
3825876116 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.60339317 |
|
|
Sep 24 11:34:51 PM UTC 24 |
Sep 24 11:35:40 PM UTC 24 |
494356632 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2440408400 |
|
|
Sep 24 11:30:37 PM UTC 24 |
Sep 24 11:35:45 PM UTC 24 |
5068299411 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.1348495327 |
|
|
Sep 24 11:34:52 PM UTC 24 |
Sep 24 11:35:46 PM UTC 24 |
931254929 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.824277897 |
|
|
Sep 24 11:34:58 PM UTC 24 |
Sep 24 11:35:57 PM UTC 24 |
1014581005 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1380691455 |
|
|
Sep 24 11:28:04 PM UTC 24 |
Sep 24 11:36:08 PM UTC 24 |
11402829953 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.3342810581 |
|
|
Sep 24 11:36:06 PM UTC 24 |
Sep 24 11:36:16 PM UTC 24 |
41452437 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2958861984 |
|
|
Sep 24 11:36:07 PM UTC 24 |
Sep 24 11:36:17 PM UTC 24 |
39248458 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1106630261 |
|
|
Sep 24 11:33:18 PM UTC 24 |
Sep 24 11:36:36 PM UTC 24 |
430992796 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1055320814 |
|
|
Sep 24 11:35:31 PM UTC 24 |
Sep 24 11:36:40 PM UTC 24 |
1970544676 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3227228778 |
|
|
Sep 24 11:35:36 PM UTC 24 |
Sep 24 11:36:48 PM UTC 24 |
283506443 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.32130062 |
|
|
Sep 24 11:33:49 PM UTC 24 |
Sep 24 11:36:49 PM UTC 24 |
2829715690 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.1311489781 |
|
|
Sep 24 11:36:37 PM UTC 24 |
Sep 24 11:37:07 PM UTC 24 |
194153148 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2966798392 |
|
|
Sep 24 11:35:16 PM UTC 24 |
Sep 24 11:37:11 PM UTC 24 |
2569139188 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3125185281 |
|
|
Sep 24 11:36:38 PM UTC 24 |
Sep 24 11:37:21 PM UTC 24 |
338510016 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1218233952 |
|
|
Sep 24 11:37:28 PM UTC 24 |
Sep 24 11:37:42 PM UTC 24 |
85016744 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2413787667 |
|
|
Sep 24 11:29:29 PM UTC 24 |
Sep 24 11:37:47 PM UTC 24 |
51357063321 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2408502876 |
|
|
Sep 24 11:33:08 PM UTC 24 |
Sep 24 11:37:47 PM UTC 24 |
750223604 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.107034254 |
|
|
Sep 24 11:37:31 PM UTC 24 |
Sep 24 11:37:48 PM UTC 24 |
96624842 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.355356804 |
|
|
Sep 24 11:31:46 PM UTC 24 |
Sep 24 11:37:48 PM UTC 24 |
40712183396 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.74376417 |
|
|
Sep 24 11:37:41 PM UTC 24 |
Sep 24 11:37:52 PM UTC 24 |
74284386 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2207204205 |
|
|
Sep 24 11:36:18 PM UTC 24 |
Sep 24 11:37:53 PM UTC 24 |
6375320144 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1903628452 |
|
|
Sep 24 11:27:08 PM UTC 24 |
Sep 24 11:37:55 PM UTC 24 |
42846855923 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1391411246 |
|
|
Sep 24 11:30:55 PM UTC 24 |
Sep 24 11:38:05 PM UTC 24 |
4349202265 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.985780514 |
|
|
Sep 24 11:36:29 PM UTC 24 |
Sep 24 11:38:08 PM UTC 24 |
4671238693 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.2441721014 |
|
|
Sep 24 11:26:55 PM UTC 24 |
Sep 24 11:38:17 PM UTC 24 |
64446079042 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.943850691 |
|
|
Sep 24 11:37:08 PM UTC 24 |
Sep 24 11:38:39 PM UTC 24 |
1915891673 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.71341431 |
|
|
Sep 24 11:38:29 PM UTC 24 |
Sep 24 11:38:40 PM UTC 24 |
44231103 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1625199929 |
|
|
Sep 24 11:38:38 PM UTC 24 |
Sep 24 11:38:48 PM UTC 24 |
49661975 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.316019515 |
|
|
Sep 24 11:25:28 PM UTC 24 |
Sep 24 11:38:57 PM UTC 24 |
19712783954 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2939727281 |
|
|
Sep 24 11:38:01 PM UTC 24 |
Sep 24 11:39:07 PM UTC 24 |
1396131800 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.4291806555 |
|
|
Sep 24 11:33:34 PM UTC 24 |
Sep 24 11:39:31 PM UTC 24 |
4472502550 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.1926984627 |
|
|
Sep 24 11:30:37 PM UTC 24 |
Sep 24 11:39:32 PM UTC 24 |
12930006722 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.4174938218 |
|
|
Sep 24 11:39:17 PM UTC 24 |
Sep 24 11:39:34 PM UTC 24 |
94806548 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3141494575 |
|
|
Sep 24 11:36:57 PM UTC 24 |
Sep 24 11:39:35 PM UTC 24 |
15218625831 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3526256502 |
|
|
Sep 24 11:13:26 PM UTC 24 |
Sep 24 11:39:47 PM UTC 24 |
100555528516 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3358614452 |
|
|
Sep 24 11:38:07 PM UTC 24 |
Sep 24 11:39:48 PM UTC 24 |
2811225022 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.422076187 |
|
|
Sep 24 11:39:08 PM UTC 24 |
Sep 24 11:40:09 PM UTC 24 |
1296484118 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.416071361 |
|
|
Sep 24 11:39:01 PM UTC 24 |
Sep 24 11:40:29 PM UTC 24 |
4653504297 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.816882041 |
|
|
Sep 24 11:40:11 PM UTC 24 |
Sep 24 11:40:30 PM UTC 24 |
192679518 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.135959894 |
|
|
Sep 24 11:39:53 PM UTC 24 |
Sep 24 11:40:30 PM UTC 24 |
464418762 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.2319645718 |
|
|
Sep 24 11:38:57 PM UTC 24 |
Sep 24 11:40:58 PM UTC 24 |
10413668391 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1319304825 |
|
|
Sep 24 11:30:50 PM UTC 24 |
Sep 24 11:41:09 PM UTC 24 |
6154029861 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.3109484257 |
|
|
Sep 24 11:30:46 PM UTC 24 |
Sep 24 11:41:14 PM UTC 24 |
6615769032 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3437707886 |
|
|
Sep 24 11:12:39 PM UTC 24 |
Sep 24 11:41:16 PM UTC 24 |
16551294058 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.431366669 |
|
|
Sep 24 11:40:30 PM UTC 24 |
Sep 24 11:41:19 PM UTC 24 |
391335926 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.157441844 |
|
|
Sep 24 11:40:26 PM UTC 24 |
Sep 24 11:41:32 PM UTC 24 |
1289682415 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.1611234194 |
|
|
Sep 24 11:39:53 PM UTC 24 |
Sep 24 11:41:35 PM UTC 24 |
2332475220 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.14475540 |
|
|
Sep 24 11:38:25 PM UTC 24 |
Sep 24 11:41:37 PM UTC 24 |
3044017620 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2338758786 |
|
|
Sep 24 11:26:03 PM UTC 24 |
Sep 24 11:41:40 PM UTC 24 |
8332325926 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.2004279547 |
|
|
Sep 24 11:34:23 PM UTC 24 |
Sep 24 11:41:47 PM UTC 24 |
24044490880 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.425760548 |
|
|
Sep 24 11:41:41 PM UTC 24 |
Sep 24 11:41:51 PM UTC 24 |
45004860 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.969872878 |
|
|
Sep 24 11:40:07 PM UTC 24 |
Sep 24 11:41:52 PM UTC 24 |
2424295560 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1357896926 |
|
|
Sep 24 11:41:53 PM UTC 24 |
Sep 24 11:42:03 PM UTC 24 |
45386439 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.807501242 |
|
|
Sep 24 11:38:08 PM UTC 24 |
Sep 24 11:42:11 PM UTC 24 |
6103060052 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.3707860491 |
|
|
Sep 24 11:41:57 PM UTC 24 |
Sep 24 11:42:19 PM UTC 24 |
138708344 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.1216931082 |
|
|
Sep 24 11:42:04 PM UTC 24 |
Sep 24 11:42:19 PM UTC 24 |
70784525 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.634231603 |
|
|
Sep 24 11:36:02 PM UTC 24 |
Sep 24 11:42:40 PM UTC 24 |
4478346472 ps |