| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.758510679 |
|
|
Sep 24 11:56:15 PM UTC 24 |
Sep 25 12:13:21 AM UTC 24 |
99469187192 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.3698075826 |
|
|
Sep 25 12:13:03 AM UTC 24 |
Sep 25 12:13:21 AM UTC 24 |
141540764 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.259995634 |
|
|
Sep 25 12:12:22 AM UTC 24 |
Sep 25 12:13:24 AM UTC 24 |
521913539 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.515490890 |
|
|
Sep 25 12:08:49 AM UTC 24 |
Sep 25 12:13:37 AM UTC 24 |
3294213260 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.4215956789 |
|
|
Sep 25 12:12:42 AM UTC 24 |
Sep 25 12:13:46 AM UTC 24 |
568375384 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1238834697 |
|
|
Sep 24 11:53:11 PM UTC 24 |
Sep 25 12:13:46 AM UTC 24 |
9338344170 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3021697102 |
|
|
Sep 25 12:12:51 AM UTC 24 |
Sep 25 12:13:52 AM UTC 24 |
1832075744 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3142673439 |
|
|
Sep 25 12:13:42 AM UTC 24 |
Sep 25 12:13:53 AM UTC 24 |
47715424 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2621273631 |
|
|
Sep 25 12:13:17 AM UTC 24 |
Sep 25 12:13:57 AM UTC 24 |
331219223 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.550167777 |
|
|
Sep 25 12:13:42 AM UTC 24 |
Sep 25 12:13:59 AM UTC 24 |
232085670 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.439328321 |
|
|
Sep 24 11:39:54 PM UTC 24 |
Sep 25 12:14:08 AM UTC 24 |
114068396917 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.2825009194 |
|
|
Sep 25 12:14:07 AM UTC 24 |
Sep 25 12:14:17 AM UTC 24 |
32021917 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1834264401 |
|
|
Sep 25 12:09:18 AM UTC 24 |
Sep 25 12:14:23 AM UTC 24 |
21595036939 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.1790448154 |
|
|
Sep 25 12:11:34 AM UTC 24 |
Sep 25 12:14:27 AM UTC 24 |
4300610863 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.713232579 |
|
|
Sep 25 12:13:45 AM UTC 24 |
Sep 25 12:14:53 AM UTC 24 |
6246371375 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.3432469544 |
|
|
Sep 25 12:14:35 AM UTC 24 |
Sep 25 12:14:58 AM UTC 24 |
248627702 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3682292983 |
|
|
Sep 25 12:14:05 AM UTC 24 |
Sep 25 12:15:02 AM UTC 24 |
1432863313 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.3190243883 |
|
|
Sep 25 12:13:17 AM UTC 24 |
Sep 25 12:15:05 AM UTC 24 |
3793143712 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.1801189469 |
|
|
Sep 25 12:14:29 AM UTC 24 |
Sep 25 12:15:08 AM UTC 24 |
423874311 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.63286353 |
|
|
Sep 25 12:12:16 AM UTC 24 |
Sep 25 12:15:09 AM UTC 24 |
10374527539 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.2310031473 |
|
|
Sep 25 12:10:26 AM UTC 24 |
Sep 25 12:15:12 AM UTC 24 |
3380995435 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1300953700 |
|
|
Sep 25 12:10:27 AM UTC 24 |
Sep 25 12:15:24 AM UTC 24 |
1948984018 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.798520912 |
|
|
Sep 25 12:13:58 AM UTC 24 |
Sep 25 12:15:27 AM UTC 24 |
4737338532 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2788447389 |
|
|
Sep 25 12:14:47 AM UTC 24 |
Sep 25 12:15:35 AM UTC 24 |
1025076031 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2377313615 |
|
|
Sep 25 12:15:33 AM UTC 24 |
Sep 25 12:15:44 AM UTC 24 |
47254840 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3073516284 |
|
|
Sep 25 12:15:31 AM UTC 24 |
Sep 25 12:15:46 AM UTC 24 |
181970112 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.3783055000 |
|
|
Sep 25 12:14:18 AM UTC 24 |
Sep 25 12:15:53 AM UTC 24 |
2040216089 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1630435512 |
|
|
Sep 25 12:15:57 AM UTC 24 |
Sep 25 12:16:07 AM UTC 24 |
33003881 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2425083868 |
|
|
Sep 25 12:14:45 AM UTC 24 |
Sep 25 12:16:10 AM UTC 24 |
1312740391 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1506588787 |
|
|
Sep 25 12:13:29 AM UTC 24 |
Sep 25 12:16:35 AM UTC 24 |
5564041110 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.171741100 |
|
|
Sep 25 12:11:08 AM UTC 24 |
Sep 25 12:16:35 AM UTC 24 |
20184549621 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.1512745044 |
|
|
Sep 25 12:16:06 AM UTC 24 |
Sep 25 12:16:53 AM UTC 24 |
352905596 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.522826337 |
|
|
Sep 25 12:10:23 AM UTC 24 |
Sep 25 12:17:06 AM UTC 24 |
4169885526 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.2362888414 |
|
|
Sep 25 12:12:33 AM UTC 24 |
Sep 25 12:17:23 AM UTC 24 |
15857371818 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3823952252 |
|
|
Sep 25 12:16:56 AM UTC 24 |
Sep 25 12:17:23 AM UTC 24 |
556990850 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1946545394 |
|
|
Sep 25 12:15:49 AM UTC 24 |
Sep 25 12:17:29 AM UTC 24 |
4434125692 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.500611787 |
|
|
Sep 25 12:11:47 AM UTC 24 |
Sep 25 12:17:33 AM UTC 24 |
3335274324 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2245789763 |
|
|
Sep 24 11:12:25 PM UTC 24 |
Sep 25 12:17:36 AM UTC 24 |
43497438092 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.673914579 |
|
|
Sep 25 12:15:46 AM UTC 24 |
Sep 25 12:17:46 AM UTC 24 |
8949289849 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.1188478048 |
|
|
Sep 25 12:17:14 AM UTC 24 |
Sep 25 12:17:52 AM UTC 24 |
241713567 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.4270274226 |
|
|
Sep 25 12:13:33 AM UTC 24 |
Sep 25 12:17:58 AM UTC 24 |
650005309 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3647110271 |
|
|
Sep 25 12:16:29 AM UTC 24 |
Sep 25 12:17:59 AM UTC 24 |
1544533423 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2169108606 |
|
|
Sep 25 12:13:28 AM UTC 24 |
Sep 25 12:18:00 AM UTC 24 |
2443612869 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.70256099 |
|
|
Sep 25 12:04:51 AM UTC 24 |
Sep 25 12:18:03 AM UTC 24 |
46195169043 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1678808649 |
|
|
Sep 25 12:17:29 AM UTC 24 |
Sep 25 12:18:05 AM UTC 24 |
1008039492 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.3202640506 |
|
|
Sep 25 12:16:56 AM UTC 24 |
Sep 25 12:18:06 AM UTC 24 |
1911903232 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.1223374655 |
|
|
Sep 25 12:18:06 AM UTC 24 |
Sep 25 12:18:20 AM UTC 24 |
191174365 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3816868060 |
|
|
Sep 25 12:18:13 AM UTC 24 |
Sep 25 12:18:23 AM UTC 24 |
35555031 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1751303443 |
|
|
Sep 24 11:14:21 PM UTC 24 |
Sep 25 12:18:25 AM UTC 24 |
28417577710 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.4286300213 |
|
|
Sep 25 12:18:22 AM UTC 24 |
Sep 25 12:18:36 AM UTC 24 |
87011954 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1309816213 |
|
|
Sep 25 12:00:46 AM UTC 24 |
Sep 25 12:18:39 AM UTC 24 |
19730819729 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.325058228 |
|
|
Sep 25 12:18:19 AM UTC 24 |
Sep 25 12:18:51 AM UTC 24 |
380512048 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2444829823 |
|
|
Sep 25 12:18:47 AM UTC 24 |
Sep 25 12:18:58 AM UTC 24 |
281519219 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2878509631 |
|
|
Sep 25 12:18:57 AM UTC 24 |
Sep 25 12:19:05 AM UTC 24 |
30752632 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.4210506610 |
|
|
Sep 25 12:11:34 AM UTC 24 |
Sep 25 12:19:08 AM UTC 24 |
881058987 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.3242184553 |
|
|
Sep 25 12:19:01 AM UTC 24 |
Sep 25 12:19:37 AM UTC 24 |
561691834 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1309128565 |
|
|
Sep 25 12:19:13 AM UTC 24 |
Sep 25 12:19:48 AM UTC 24 |
212175101 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.20971214 |
|
|
Sep 25 12:18:18 AM UTC 24 |
Sep 25 12:19:51 AM UTC 24 |
9009827382 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.547290218 |
|
|
Sep 25 12:13:36 AM UTC 24 |
Sep 25 12:19:55 AM UTC 24 |
4161886875 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.3984437622 |
|
|
Sep 25 12:18:39 AM UTC 24 |
Sep 25 12:20:00 AM UTC 24 |
2074548885 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2386342292 |
|
|
Sep 24 11:46:13 PM UTC 24 |
Sep 25 12:20:12 AM UTC 24 |
127469864679 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3573998788 |
|
|
Sep 25 12:18:20 AM UTC 24 |
Sep 25 12:20:15 AM UTC 24 |
5290250980 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.4191072228 |
|
|
Sep 25 12:08:28 AM UTC 24 |
Sep 25 12:20:19 AM UTC 24 |
10199646033 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1006203514 |
|
|
Sep 25 12:20:14 AM UTC 24 |
Sep 25 12:20:21 AM UTC 24 |
37345110 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.2433992431 |
|
|
Sep 25 12:20:11 AM UTC 24 |
Sep 25 12:20:21 AM UTC 24 |
47865267 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3260183960 |
|
|
Sep 25 12:15:20 AM UTC 24 |
Sep 25 12:20:22 AM UTC 24 |
583962697 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.849884052 |
|
|
Sep 25 12:15:14 AM UTC 24 |
Sep 25 12:20:45 AM UTC 24 |
7543074041 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.1496782074 |
|
|
Sep 25 12:43:24 AM UTC 24 |
Sep 25 12:43:39 AM UTC 24 |
172803832 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.591356941 |
|
|
Sep 24 11:54:17 PM UTC 24 |
Sep 25 12:20:51 AM UTC 24 |
96900344735 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3343125921 |
|
|
Sep 25 12:15:27 AM UTC 24 |
Sep 25 12:20:59 AM UTC 24 |
3851894424 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1094479701 |
|
|
Sep 25 12:11:44 AM UTC 24 |
Sep 25 12:21:00 AM UTC 24 |
5576744069 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.2548884272 |
|
|
Sep 25 12:20:43 AM UTC 24 |
Sep 25 12:21:14 AM UTC 24 |
446978314 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3373224671 |
|
|
Sep 25 12:11:45 AM UTC 24 |
Sep 25 12:21:26 AM UTC 24 |
12026524740 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.959486825 |
|
|
Sep 25 12:11:14 AM UTC 24 |
Sep 25 12:21:28 AM UTC 24 |
46421131452 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.2837488634 |
|
|
Sep 25 12:20:19 AM UTC 24 |
Sep 25 12:21:35 AM UTC 24 |
6237268583 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.43745538 |
|
|
Sep 25 12:19:30 AM UTC 24 |
Sep 25 12:21:36 AM UTC 24 |
2748301848 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.130020953 |
|
|
Sep 25 12:15:30 AM UTC 24 |
Sep 25 12:21:36 AM UTC 24 |
3464374838 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.996643594 |
|
|
Sep 25 12:20:39 AM UTC 24 |
Sep 25 12:21:39 AM UTC 24 |
537829504 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.209176970 |
|
|
Sep 25 12:18:45 AM UTC 24 |
Sep 25 12:21:39 AM UTC 24 |
9883508787 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.3537735551 |
|
|
Sep 25 12:17:58 AM UTC 24 |
Sep 25 12:21:41 AM UTC 24 |
3124227296 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.3206092384 |
|
|
Sep 25 12:21:09 AM UTC 24 |
Sep 25 12:21:41 AM UTC 24 |
283951291 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.1171163405 |
|
|
Sep 25 12:21:21 AM UTC 24 |
Sep 25 12:21:50 AM UTC 24 |
564730042 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3861841867 |
|
|
Sep 25 12:21:22 AM UTC 24 |
Sep 25 12:21:51 AM UTC 24 |
545703147 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.4133150330 |
|
|
Sep 25 12:17:51 AM UTC 24 |
Sep 25 12:21:52 AM UTC 24 |
4869980273 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.4000174834 |
|
|
Sep 25 12:17:55 AM UTC 24 |
Sep 25 12:21:55 AM UTC 24 |
2845669511 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.2458120362 |
|
|
Sep 25 12:21:13 AM UTC 24 |
Sep 25 12:22:01 AM UTC 24 |
552899989 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.633559721 |
|
|
Sep 25 12:22:00 AM UTC 24 |
Sep 25 12:22:11 AM UTC 24 |
48423086 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1300811352 |
|
|
Sep 25 12:21:58 AM UTC 24 |
Sep 25 12:22:11 AM UTC 24 |
202666996 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1708367478 |
|
|
Sep 25 12:21:47 AM UTC 24 |
Sep 25 12:22:14 AM UTC 24 |
20029889 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3770409549 |
|
|
Sep 25 12:20:33 AM UTC 24 |
Sep 25 12:22:27 AM UTC 24 |
4823077633 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.134721680 |
|
|
Sep 25 12:22:33 AM UTC 24 |
Sep 25 12:22:59 AM UTC 24 |
805102300 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3174016532 |
|
|
Sep 25 12:22:32 AM UTC 24 |
Sep 25 12:23:01 AM UTC 24 |
627468237 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.4266414380 |
|
|
Sep 25 12:17:44 AM UTC 24 |
Sep 25 12:23:01 AM UTC 24 |
7506001530 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2096183939 |
|
|
Sep 25 12:22:11 AM UTC 24 |
Sep 25 12:23:02 AM UTC 24 |
571873234 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.4030845619 |
|
|
Sep 25 12:21:36 AM UTC 24 |
Sep 25 12:23:03 AM UTC 24 |
686563656 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.1560656470 |
|
|
Sep 25 12:22:16 AM UTC 24 |
Sep 25 12:23:14 AM UTC 24 |
482363736 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.2329305031 |
|
|
Sep 25 12:22:35 AM UTC 24 |
Sep 25 12:23:17 AM UTC 24 |
675127286 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2481616505 |
|
|
Sep 25 12:22:49 AM UTC 24 |
Sep 25 12:23:23 AM UTC 24 |
182070286 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.823987463 |
|
|
Sep 25 12:04:02 AM UTC 24 |
Sep 25 12:23:32 AM UTC 24 |
11219402488 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.2561121556 |
|
|
Sep 25 12:23:26 AM UTC 24 |
Sep 25 12:23:37 AM UTC 24 |
45591341 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2994666908 |
|
|
Sep 25 12:22:02 AM UTC 24 |
Sep 25 12:23:43 AM UTC 24 |
2344737516 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4079030145 |
|
|
Sep 25 12:23:37 AM UTC 24 |
Sep 25 12:23:47 AM UTC 24 |
44079906 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.4240007405 |
|
|
Sep 25 12:19:19 AM UTC 24 |
Sep 25 12:23:48 AM UTC 24 |
5838609848 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.993438174 |
|
|
Sep 24 11:41:35 PM UTC 24 |
Sep 25 12:23:53 AM UTC 24 |
16656994285 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.3629781529 |
|
|
Sep 25 12:15:25 AM UTC 24 |
Sep 25 12:23:55 AM UTC 24 |
13252236317 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1207708481 |
|
|
Sep 25 12:21:57 AM UTC 24 |
Sep 25 12:24:00 AM UTC 24 |
325977309 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.121262808 |
|
|
Sep 25 12:22:03 AM UTC 24 |
Sep 25 12:24:05 AM UTC 24 |
6294390963 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.4198465855 |
|
|
Sep 25 12:22:00 AM UTC 24 |
Sep 25 12:24:06 AM UTC 24 |
7700758407 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.224045813 |
|
|
Sep 25 12:07:31 AM UTC 24 |
Sep 25 12:24:09 AM UTC 24 |
63793979753 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2152438083 |
|
|
Sep 25 12:21:49 AM UTC 24 |
Sep 25 12:24:29 AM UTC 24 |
3470466681 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2467233407 |
|
|
Sep 25 12:20:08 AM UTC 24 |
Sep 25 12:24:43 AM UTC 24 |
4097808085 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.92506743 |
|
|
Sep 25 12:24:24 AM UTC 24 |
Sep 25 12:24:45 AM UTC 24 |
268652698 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2167544146 |
|
|
Sep 25 12:23:58 AM UTC 24 |
Sep 25 12:24:49 AM UTC 24 |
477542299 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.868920455 |
|
|
Sep 25 12:24:24 AM UTC 24 |
Sep 25 12:24:54 AM UTC 24 |
465761505 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.1335391247 |
|
|
Sep 25 12:22:13 AM UTC 24 |
Sep 25 12:24:54 AM UTC 24 |
10601043194 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1135877556 |
|
|
Sep 25 12:23:38 AM UTC 24 |
Sep 25 12:24:59 AM UTC 24 |
7547702764 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.198184713 |
|
|
Sep 25 12:24:10 AM UTC 24 |
Sep 25 12:24:59 AM UTC 24 |
413240050 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.4006607797 |
|
|
Sep 25 12:16:08 AM UTC 24 |
Sep 25 12:25:05 AM UTC 24 |
49018683642 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2296605237 |
|
|
Sep 25 12:24:17 AM UTC 24 |
Sep 25 12:25:14 AM UTC 24 |
1633128501 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.1992686944 |
|
|
Sep 25 12:25:10 AM UTC 24 |
Sep 25 12:25:20 AM UTC 24 |
37948546 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.3010105100 |
|
|
Sep 25 12:21:58 AM UTC 24 |
Sep 25 12:25:21 AM UTC 24 |
3453890850 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.1989057523 |
|
|
Sep 24 11:50:27 PM UTC 24 |
Sep 25 12:25:22 AM UTC 24 |
16919459718 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3461371449 |
|
|
Sep 25 12:25:15 AM UTC 24 |
Sep 25 12:25:22 AM UTC 24 |
37571421 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.3266674109 |
|
|
Sep 25 12:24:22 AM UTC 24 |
Sep 25 12:25:32 AM UTC 24 |
1865187511 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.2047564870 |
|
|
Sep 25 12:23:54 AM UTC 24 |
Sep 25 12:25:39 AM UTC 24 |
2438505608 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.3192252950 |
|
|
Sep 25 12:25:26 AM UTC 24 |
Sep 25 12:25:45 AM UTC 24 |
114295729 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1599133402 |
|
|
Sep 25 12:23:44 AM UTC 24 |
Sep 25 12:25:48 AM UTC 24 |
4742384848 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.2707121804 |
|
|
Sep 25 12:25:41 AM UTC 24 |
Sep 25 12:26:11 AM UTC 24 |
924368317 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3549509586 |
|
|
Sep 25 12:17:45 AM UTC 24 |
Sep 25 12:26:14 AM UTC 24 |
3822117364 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.3413956068 |
|
|
Sep 25 12:25:21 AM UTC 24 |
Sep 25 12:26:17 AM UTC 24 |
1145037754 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.360123434 |
|
|
Sep 25 12:25:59 AM UTC 24 |
Sep 25 12:26:19 AM UTC 24 |
97469429 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3972898303 |
|
|
Sep 25 12:25:43 AM UTC 24 |
Sep 25 12:26:23 AM UTC 24 |
588302140 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2448581695 |
|
|
Sep 25 12:26:07 AM UTC 24 |
Sep 25 12:26:29 AM UTC 24 |
127384422 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.816861424 |
|
|
Sep 25 12:19:58 AM UTC 24 |
Sep 25 12:26:42 AM UTC 24 |
3463440549 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.869498427 |
|
|
Sep 25 12:25:17 AM UTC 24 |
Sep 25 12:26:47 AM UTC 24 |
5600789505 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.1717519051 |
|
|
Sep 25 12:26:40 AM UTC 24 |
Sep 25 12:26:49 AM UTC 24 |
41676890 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1021992129 |
|
|
Sep 25 12:25:21 AM UTC 24 |
Sep 25 12:26:53 AM UTC 24 |
5819615846 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3316879391 |
|
|
Sep 25 12:26:46 AM UTC 24 |
Sep 25 12:26:57 AM UTC 24 |
54066910 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3665604607 |
|
|
Sep 25 12:14:14 AM UTC 24 |
Sep 25 12:27:02 AM UTC 24 |
40437337621 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.591198484 |
|
|
Sep 25 12:23:24 AM UTC 24 |
Sep 25 12:27:06 AM UTC 24 |
2149406412 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.974938971 |
|
|
Sep 25 12:25:41 AM UTC 24 |
Sep 25 12:27:27 AM UTC 24 |
6127175218 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.2237223732 |
|
|
Sep 25 12:26:09 AM UTC 24 |
Sep 25 12:27:27 AM UTC 24 |
660723253 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.361603500 |
|
|
Sep 25 12:11:08 AM UTC 24 |
Sep 25 12:27:29 AM UTC 24 |
100251859641 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1352438986 |
|
|
Sep 25 12:25:52 AM UTC 24 |
Sep 25 12:27:30 AM UTC 24 |
2353163246 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.3409147565 |
|
|
Sep 25 12:27:11 AM UTC 24 |
Sep 25 12:27:38 AM UTC 24 |
192942165 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.3201433531 |
|
|
Sep 25 12:39:51 AM UTC 24 |
Sep 25 12:43:35 AM UTC 24 |
12174992649 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.609459476 |
|
|
Sep 24 11:26:13 PM UTC 24 |
Sep 25 12:27:42 AM UTC 24 |
30472783883 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.926045930 |
|
|
Sep 25 12:23:20 AM UTC 24 |
Sep 25 12:27:47 AM UTC 24 |
7049703267 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3910325483 |
|
|
Sep 25 12:23:23 AM UTC 24 |
Sep 25 12:27:49 AM UTC 24 |
7518728182 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.243058968 |
|
|
Sep 25 12:20:42 AM UTC 24 |
Sep 25 12:27:53 AM UTC 24 |
24400899925 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.3859317019 |
|
|
Sep 25 12:27:09 AM UTC 24 |
Sep 25 12:27:58 AM UTC 24 |
1126388157 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1927401844 |
|
|
Sep 24 11:58:37 PM UTC 24 |
Sep 25 12:27:58 AM UTC 24 |
14628711671 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.4022162900 |
|
|
Sep 25 12:25:01 AM UTC 24 |
Sep 25 12:27:58 AM UTC 24 |
2334042463 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1824520473 |
|
|
Sep 25 12:27:48 AM UTC 24 |
Sep 25 12:27:58 AM UTC 24 |
39317418 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2307306708 |
|
|
Sep 25 12:25:07 AM UTC 24 |
Sep 25 12:28:15 AM UTC 24 |
751675115 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3236605020 |
|
|
Sep 24 11:56:42 PM UTC 24 |
Sep 25 12:28:24 AM UTC 24 |
117770584231 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.3153469605 |
|
|
Sep 25 12:28:15 AM UTC 24 |
Sep 25 12:28:26 AM UTC 24 |
52858731 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.403693385 |
|
|
Sep 25 12:28:20 AM UTC 24 |
Sep 25 12:28:29 AM UTC 24 |
39657888 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.3731701187 |
|
|
Sep 25 12:27:50 AM UTC 24 |
Sep 25 12:28:29 AM UTC 24 |
255423100 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.467471693 |
|
|
Sep 25 12:27:49 AM UTC 24 |
Sep 25 12:28:33 AM UTC 24 |
1426594039 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.803224604 |
|
|
Sep 25 12:28:19 AM UTC 24 |
Sep 25 12:28:43 AM UTC 24 |
422264009 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.2431261052 |
|
|
Sep 25 12:26:51 AM UTC 24 |
Sep 25 12:28:52 AM UTC 24 |
8541223018 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2071940877 |
|
|
Sep 24 11:46:54 PM UTC 24 |
Sep 25 12:28:52 AM UTC 24 |
15529502936 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2645593295 |
|
|
Sep 25 12:27:53 AM UTC 24 |
Sep 25 12:29:03 AM UTC 24 |
1242410541 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.2501550219 |
|
|
Sep 25 12:27:24 AM UTC 24 |
Sep 25 12:29:03 AM UTC 24 |
1165918523 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2375951861 |
|
|
Sep 25 12:28:56 AM UTC 24 |
Sep 25 12:29:32 AM UTC 24 |
289615072 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.624162414 |
|
|
Sep 25 12:29:15 AM UTC 24 |
Sep 25 12:29:37 AM UTC 24 |
312059955 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.4017152477 |
|
|
Sep 25 12:28:36 AM UTC 24 |
Sep 25 12:29:38 AM UTC 24 |
594471785 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.674389820 |
|
|
Sep 25 12:28:19 AM UTC 24 |
Sep 25 12:29:38 AM UTC 24 |
5001453653 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3275798181 |
|
|
Sep 25 12:27:05 AM UTC 24 |
Sep 25 12:29:45 AM UTC 24 |
6242795233 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3270063382 |
|
|
Sep 25 12:28:50 AM UTC 24 |
Sep 25 12:29:51 AM UTC 24 |
314222652 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.125680014 |
|
|
Sep 25 12:16:15 AM UTC 24 |
Sep 25 12:29:57 AM UTC 24 |
48866460588 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1826108727 |
|
|
Sep 25 12:24:27 AM UTC 24 |
Sep 25 12:30:04 AM UTC 24 |
7889124664 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2767090073 |
|
|
Sep 25 12:14:19 AM UTC 24 |
Sep 25 12:30:07 AM UTC 24 |
55267529417 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3404027321 |
|
|
Sep 25 12:29:26 AM UTC 24 |
Sep 25 12:30:08 AM UTC 24 |
52253666 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.332220976 |
|
|
Sep 25 12:29:58 AM UTC 24 |
Sep 25 12:30:09 AM UTC 24 |
49934372 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.1083539513 |
|
|
Sep 25 12:30:00 AM UTC 24 |
Sep 25 12:30:11 AM UTC 24 |
60019731 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.4115704103 |
|
|
Sep 25 12:26:38 AM UTC 24 |
Sep 25 12:30:14 AM UTC 24 |
2223640331 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.1298507846 |
|
|
Sep 25 12:14:13 AM UTC 24 |
Sep 25 12:30:19 AM UTC 24 |
89411461851 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.3001429501 |
|
|
Sep 25 12:09:19 AM UTC 24 |
Sep 25 12:30:22 AM UTC 24 |
114263677842 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.743550074 |
|
|
Sep 25 12:29:13 AM UTC 24 |
Sep 25 12:30:33 AM UTC 24 |
1303069960 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1795494293 |
|
|
Sep 25 12:23:23 AM UTC 24 |
Sep 25 12:30:42 AM UTC 24 |
1849176842 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2728182970 |
|
|
Sep 25 12:28:19 AM UTC 24 |
Sep 25 12:30:43 AM UTC 24 |
10561019886 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.3003086984 |
|
|
Sep 25 12:25:36 AM UTC 24 |
Sep 25 12:30:44 AM UTC 24 |
19894125752 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.2328907965 |
|
|
Sep 25 12:29:05 AM UTC 24 |
Sep 25 12:30:52 AM UTC 24 |
2164507844 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2539464853 |
|
|
Sep 25 12:12:30 AM UTC 24 |
Sep 25 12:31:02 AM UTC 24 |
103567487809 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.458211694 |
|
|
Sep 25 12:28:08 AM UTC 24 |
Sep 25 12:31:04 AM UTC 24 |
1971831054 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.623176577 |
|
|
Sep 25 12:30:42 AM UTC 24 |
Sep 25 12:31:20 AM UTC 24 |
304855859 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.2357730476 |
|
|
Sep 25 12:18:27 AM UTC 24 |
Sep 25 12:31:22 AM UTC 24 |
71514903588 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.2905109795 |
|
|
Sep 25 12:30:25 AM UTC 24 |
Sep 25 12:31:24 AM UTC 24 |
450110795 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.901196121 |
|
|
Sep 25 12:30:17 AM UTC 24 |
Sep 25 12:31:25 AM UTC 24 |
1986212801 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1928260841 |
|
|
Sep 25 12:30:36 AM UTC 24 |
Sep 25 12:31:27 AM UTC 24 |
442346015 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2127041532 |
|
|
Sep 25 12:30:14 AM UTC 24 |
Sep 25 12:31:31 AM UTC 24 |
5277329879 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.3822231190 |
|
|
Sep 25 12:31:24 AM UTC 24 |
Sep 25 12:31:37 AM UTC 24 |
229109339 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3270602757 |
|
|
Sep 25 12:31:28 AM UTC 24 |
Sep 25 12:31:38 AM UTC 24 |
40375140 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.881642627 |
|
|
Sep 25 12:19:26 AM UTC 24 |
Sep 25 12:31:41 AM UTC 24 |
5494876287 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1778402841 |
|
|
Sep 25 12:30:53 AM UTC 24 |
Sep 25 12:31:50 AM UTC 24 |
1269457796 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1718983159 |
|
|
Sep 24 11:52:03 PM UTC 24 |
Sep 25 12:31:56 AM UTC 24 |
135716083451 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.1739405467 |
|
|
Sep 25 12:26:36 AM UTC 24 |
Sep 25 12:31:57 AM UTC 24 |
3723300533 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.227194989 |
|
|
Sep 24 11:33:45 PM UTC 24 |
Sep 25 12:31:58 AM UTC 24 |
27173072629 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.3372806200 |
|
|
Sep 25 12:30:45 AM UTC 24 |
Sep 25 12:31:59 AM UTC 24 |
1470269613 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3288275549 |
|
|
Sep 25 12:30:06 AM UTC 24 |
Sep 25 12:32:18 AM UTC 24 |
9083508250 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2441465134 |
|
|
Sep 25 12:28:49 AM UTC 24 |
Sep 25 12:32:19 AM UTC 24 |
11492600009 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.453381488 |
|
|
Sep 25 12:31:05 AM UTC 24 |
Sep 25 12:32:19 AM UTC 24 |
726643224 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.1539898035 |
|
|
Sep 25 12:32:09 AM UTC 24 |
Sep 25 12:32:25 AM UTC 24 |
83767469 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3972063011 |
|
|
Sep 25 12:31:59 AM UTC 24 |
Sep 25 12:32:30 AM UTC 24 |
267070885 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.990592773 |
|
|
Sep 25 12:25:42 AM UTC 24 |
Sep 25 12:32:35 AM UTC 24 |
18640334693 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.3258066267 |
|
|
Sep 25 12:22:14 AM UTC 24 |
Sep 25 12:32:36 AM UTC 24 |
36314014234 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.4045773272 |
|
|
Sep 25 12:22:23 AM UTC 24 |
Sep 25 12:32:40 AM UTC 24 |
34081420808 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.1228640318 |
|
|
Sep 25 12:31:47 AM UTC 24 |
Sep 25 12:32:45 AM UTC 24 |
449548555 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1644166436 |
|
|
Sep 25 12:31:47 AM UTC 24 |
Sep 25 12:32:47 AM UTC 24 |
1236063820 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.2265642283 |
|
|
Sep 25 12:32:41 AM UTC 24 |
Sep 25 12:32:50 AM UTC 24 |
178209675 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1827786177 |
|
|
Sep 25 12:32:16 AM UTC 24 |
Sep 25 12:32:51 AM UTC 24 |
651286955 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.849099303 |
|
|
Sep 25 12:32:48 AM UTC 24 |
Sep 25 12:32:57 AM UTC 24 |
47715790 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3493316331 |
|
|
Sep 25 12:31:45 AM UTC 24 |
Sep 25 12:33:03 AM UTC 24 |
4462247121 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.4083725082 |
|
|
Sep 25 12:32:18 AM UTC 24 |
Sep 25 12:33:12 AM UTC 24 |
1101279147 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.554604896 |
|
|
Sep 25 12:31:43 AM UTC 24 |
Sep 25 12:33:14 AM UTC 24 |
6744511895 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3608206059 |
|
|
Sep 25 12:30:33 AM UTC 24 |
Sep 25 12:33:18 AM UTC 24 |
8767525011 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.3772470285 |
|
|
Sep 25 12:29:26 AM UTC 24 |
Sep 25 12:33:27 AM UTC 24 |
5648054907 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2226305234 |
|
|
Sep 25 12:32:02 AM UTC 24 |
Sep 25 12:33:30 AM UTC 24 |
2528700878 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.901934029 |
|
|
Sep 25 12:33:01 AM UTC 24 |
Sep 25 12:33:35 AM UTC 24 |
247701984 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2330432434 |
|
|
Sep 25 12:33:24 AM UTC 24 |
Sep 25 12:33:36 AM UTC 24 |
63451795 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4283236049 |
|
|
Sep 25 12:33:36 AM UTC 24 |
Sep 25 12:33:44 AM UTC 24 |
68663369 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.3632466396 |
|
|
Sep 25 12:28:47 AM UTC 24 |
Sep 25 12:33:47 AM UTC 24 |
25878960948 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.3880960356 |
|
|
Sep 25 12:33:33 AM UTC 24 |
Sep 25 12:33:49 AM UTC 24 |
70323879 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.4117985318 |
|
|
Sep 25 12:30:32 AM UTC 24 |
Sep 25 12:33:52 AM UTC 24 |
3593322771 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.2663063176 |
|
|
Sep 25 12:31:52 AM UTC 24 |
Sep 25 12:33:56 AM UTC 24 |
6016733736 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.560974216 |
|
|
Sep 25 12:33:17 AM UTC 24 |
Sep 25 12:33:58 AM UTC 24 |
1257916325 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1834113144 |
|
|
Sep 25 12:21:06 AM UTC 24 |
Sep 25 12:34:04 AM UTC 24 |
44819160207 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2759880312 |
|
|
Sep 25 12:33:57 AM UTC 24 |
Sep 25 12:34:07 AM UTC 24 |
199794271 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1607863136 |
|
|
Sep 25 12:31:03 AM UTC 24 |
Sep 25 12:34:12 AM UTC 24 |
465858406 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.407659031 |
|
|
Sep 25 12:32:55 AM UTC 24 |
Sep 25 12:34:13 AM UTC 24 |
1909658772 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3455704230 |
|
|
Sep 25 12:32:51 AM UTC 24 |
Sep 25 12:34:16 AM UTC 24 |
7153515098 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3133893075 |
|
|
Sep 25 12:34:07 AM UTC 24 |
Sep 25 12:34:18 AM UTC 24 |
55773698 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2221301459 |
|
|
Sep 25 12:29:54 AM UTC 24 |
Sep 25 12:34:23 AM UTC 24 |
6812581114 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.680183049 |
|
|
Sep 25 12:32:56 AM UTC 24 |
Sep 25 12:34:32 AM UTC 24 |
6249440246 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.4078706128 |
|
|
Sep 25 12:33:38 AM UTC 24 |
Sep 25 12:34:48 AM UTC 24 |
622768677 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2315697579 |
|
|
Sep 25 12:05:11 AM UTC 24 |
Sep 25 12:34:51 AM UTC 24 |
116665707314 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.271784240 |
|
|
Sep 25 12:26:34 AM UTC 24 |
Sep 25 12:34:58 AM UTC 24 |
10204798819 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.1518325615 |
|
|
Sep 25 12:34:13 AM UTC 24 |
Sep 25 12:34:59 AM UTC 24 |
427640383 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.1947183790 |
|
|
Sep 25 12:34:17 AM UTC 24 |
Sep 25 12:35:01 AM UTC 24 |
321254690 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.811137278 |
|
|
Sep 25 12:29:58 AM UTC 24 |
Sep 25 12:35:16 AM UTC 24 |
3410814127 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1589396092 |
|
|
Sep 25 12:34:41 AM UTC 24 |
Sep 25 12:35:16 AM UTC 24 |
247165297 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.4133499465 |
|
|
Sep 25 12:33:12 AM UTC 24 |
Sep 25 12:35:16 AM UTC 24 |
2043219820 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.4254140386 |
|
|
Sep 25 12:16:33 AM UTC 24 |
Sep 25 12:35:18 AM UTC 24 |
79436046282 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.4001918637 |
|
|
Sep 25 12:34:35 AM UTC 24 |
Sep 25 12:35:23 AM UTC 24 |
1025405992 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2598175532 |
|
|
Sep 25 12:34:38 AM UTC 24 |
Sep 25 12:35:26 AM UTC 24 |
381960542 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1715974565 |
|
|
Sep 25 12:33:57 AM UTC 24 |
Sep 25 12:35:26 AM UTC 24 |
259888076 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.3771955932 |
|
|
Sep 25 12:34:30 AM UTC 24 |
Sep 25 12:35:26 AM UTC 24 |
374761355 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1183751481 |
|
|
Sep 25 12:34:46 AM UTC 24 |
Sep 25 12:35:26 AM UTC 24 |
303528447 ps |