| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.1846400502 |
|
|
Oct 03 04:07:11 PM UTC 24 |
Oct 03 06:33:49 PM UTC 24 |
31371796250 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.2973084944 |
|
|
Oct 03 06:30:57 PM UTC 24 |
Oct 03 06:34:34 PM UTC 24 |
2795009040 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3803010805 |
|
|
Oct 03 06:29:15 PM UTC 24 |
Oct 03 06:35:17 PM UTC 24 |
3343405150 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.3721647293 |
|
|
Oct 03 06:30:41 PM UTC 24 |
Oct 03 06:35:33 PM UTC 24 |
3786075500 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4009486045 |
|
|
Oct 03 05:22:51 PM UTC 24 |
Oct 03 06:36:07 PM UTC 24 |
14425954436 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1303317139 |
|
|
Oct 03 04:12:27 PM UTC 24 |
Oct 03 06:37:17 PM UTC 24 |
44779794100 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3107696862 |
|
|
Oct 03 05:23:58 PM UTC 24 |
Oct 03 06:37:26 PM UTC 24 |
12019834140 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.1516696908 |
|
|
Oct 03 05:25:45 PM UTC 24 |
Oct 03 06:38:33 PM UTC 24 |
15120690114 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.887775615 |
|
|
Oct 03 06:27:44 PM UTC 24 |
Oct 03 06:39:00 PM UTC 24 |
6424698696 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1324967022 |
|
|
Oct 03 05:09:08 PM UTC 24 |
Oct 03 06:39:26 PM UTC 24 |
15276039194 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.2727454809 |
|
|
Oct 03 05:09:26 PM UTC 24 |
Oct 03 06:40:26 PM UTC 24 |
14498240550 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.901910523 |
|
|
Oct 03 06:34:13 PM UTC 24 |
Oct 03 06:40:59 PM UTC 24 |
4637265202 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2909084151 |
|
|
Oct 03 06:30:58 PM UTC 24 |
Oct 03 06:41:14 PM UTC 24 |
3727261782 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.827844941 |
|
|
Oct 03 06:28:41 PM UTC 24 |
Oct 03 06:41:18 PM UTC 24 |
6251816256 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1516727778 |
|
|
Oct 03 05:33:50 PM UTC 24 |
Oct 03 06:41:49 PM UTC 24 |
19104721370 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.161736277 |
|
|
Oct 03 06:30:36 PM UTC 24 |
Oct 03 06:42:23 PM UTC 24 |
5581405964 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1438662104 |
|
|
Oct 03 06:36:43 PM UTC 24 |
Oct 03 06:42:53 PM UTC 24 |
2743735886 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4287671479 |
|
|
Oct 03 05:11:38 PM UTC 24 |
Oct 03 06:43:04 PM UTC 24 |
15083854342 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.1486435175 |
|
|
Oct 03 05:36:15 PM UTC 24 |
Oct 03 06:43:15 PM UTC 24 |
19191144230 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.496890755 |
|
|
Oct 03 06:27:40 PM UTC 24 |
Oct 03 06:43:18 PM UTC 24 |
4810678286 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.1711137050 |
|
|
Oct 03 06:31:22 PM UTC 24 |
Oct 03 06:43:31 PM UTC 24 |
4811589994 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2128832180 |
|
|
Oct 03 05:01:45 PM UTC 24 |
Oct 03 06:43:38 PM UTC 24 |
25106798611 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.4203147923 |
|
|
Oct 03 05:34:10 PM UTC 24 |
Oct 03 06:44:12 PM UTC 24 |
20050689356 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.1162446013 |
|
|
Oct 03 06:36:12 PM UTC 24 |
Oct 03 06:44:31 PM UTC 24 |
3718888105 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.2919215715 |
|
|
Oct 03 05:32:08 PM UTC 24 |
Oct 03 06:45:55 PM UTC 24 |
14850592547 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.760245606 |
|
|
Oct 03 06:38:11 PM UTC 24 |
Oct 03 06:45:57 PM UTC 24 |
4004024144 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.4095675533 |
|
|
Oct 03 06:30:54 PM UTC 24 |
Oct 03 06:46:16 PM UTC 24 |
4908417776 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.3135582066 |
|
|
Oct 03 06:35:55 PM UTC 24 |
Oct 03 06:46:08 PM UTC 24 |
4341399366 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.318762035 |
|
|
Oct 03 05:24:40 PM UTC 24 |
Oct 03 06:46:17 PM UTC 24 |
16215450317 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.3153727383 |
|
|
Oct 03 06:32:04 PM UTC 24 |
Oct 03 06:46:45 PM UTC 24 |
4479247144 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.487160342 |
|
|
Oct 03 06:20:02 PM UTC 24 |
Oct 03 06:46:48 PM UTC 24 |
7123235090 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4063593437 |
|
|
Oct 03 05:10:47 PM UTC 24 |
Oct 03 06:47:32 PM UTC 24 |
14822843640 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.1459564590 |
|
|
Oct 03 06:39:15 PM UTC 24 |
Oct 03 06:48:04 PM UTC 24 |
4252487085 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1335742479 |
|
|
Oct 03 05:23:57 PM UTC 24 |
Oct 03 06:48:35 PM UTC 24 |
14816006403 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.3844308834 |
|
|
Oct 03 06:34:14 PM UTC 24 |
Oct 03 06:48:41 PM UTC 24 |
4596709090 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3138381700 |
|
|
Oct 03 06:34:28 PM UTC 24 |
Oct 03 06:48:43 PM UTC 24 |
5317922288 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3547277826 |
|
|
Oct 03 06:44:25 PM UTC 24 |
Oct 03 06:49:04 PM UTC 24 |
3106904340 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1653193029 |
|
|
Oct 03 06:42:30 PM UTC 24 |
Oct 03 06:49:11 PM UTC 24 |
3424939360 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.550776653 |
|
|
Oct 03 06:38:11 PM UTC 24 |
Oct 03 06:49:31 PM UTC 24 |
6994806268 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3250032670 |
|
|
Oct 03 06:44:28 PM UTC 24 |
Oct 03 06:49:46 PM UTC 24 |
2730669720 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2272961438 |
|
|
Oct 03 06:41:39 PM UTC 24 |
Oct 03 06:49:54 PM UTC 24 |
5593734023 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.294007336 |
|
|
Oct 03 06:35:12 PM UTC 24 |
Oct 03 06:49:55 PM UTC 24 |
5297801008 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.232456438 |
|
|
Oct 03 06:39:42 PM UTC 24 |
Oct 03 06:49:58 PM UTC 24 |
4332728700 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3528132923 |
|
|
Oct 03 06:48:43 PM UTC 24 |
Oct 03 06:50:38 PM UTC 24 |
2102627975 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.4288440375 |
|
|
Oct 03 06:40:06 PM UTC 24 |
Oct 03 06:50:48 PM UTC 24 |
4032480616 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.371904636 |
|
|
Oct 03 06:47:30 PM UTC 24 |
Oct 03 06:51:08 PM UTC 24 |
2981618336 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1950356331 |
|
|
Oct 03 06:49:40 PM UTC 24 |
Oct 03 06:52:30 PM UTC 24 |
2778370136 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4010658719 |
|
|
Oct 03 06:47:49 PM UTC 24 |
Oct 03 06:52:33 PM UTC 24 |
2466405769 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.848926485 |
|
|
Oct 03 06:41:07 PM UTC 24 |
Oct 03 06:52:33 PM UTC 24 |
4905910496 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4167565458 |
|
|
Oct 03 06:47:43 PM UTC 24 |
Oct 03 06:53:02 PM UTC 24 |
3112961765 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3162650652 |
|
|
Oct 03 05:09:59 PM UTC 24 |
Oct 03 06:54:15 PM UTC 24 |
15664511800 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1539653290 |
|
|
Oct 03 05:12:09 PM UTC 24 |
Oct 03 06:55:14 PM UTC 24 |
16322635200 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.76129852 |
|
|
Oct 03 06:50:11 PM UTC 24 |
Oct 03 06:56:10 PM UTC 24 |
3567432244 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1905257725 |
|
|
Oct 03 05:46:39 PM UTC 24 |
Oct 03 06:57:31 PM UTC 24 |
14909420520 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3157403271 |
|
|
Oct 03 06:30:36 PM UTC 24 |
Oct 03 06:57:32 PM UTC 24 |
8831693480 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.2718951171 |
|
|
Oct 03 06:47:54 PM UTC 24 |
Oct 03 06:57:35 PM UTC 24 |
3680038764 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1787486801 |
|
|
Oct 03 06:51:05 PM UTC 24 |
Oct 03 06:57:59 PM UTC 24 |
3500101760 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.573774904 |
|
|
Oct 03 06:47:46 PM UTC 24 |
Oct 03 06:58:13 PM UTC 24 |
7031556374 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3318235490 |
|
|
Oct 03 05:05:25 PM UTC 24 |
Oct 03 06:58:13 PM UTC 24 |
30234088448 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2041802236 |
|
|
Oct 03 06:50:00 PM UTC 24 |
Oct 03 06:58:46 PM UTC 24 |
5137003362 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2279213066 |
|
|
Oct 03 06:42:06 PM UTC 24 |
Oct 03 06:59:00 PM UTC 24 |
5690423632 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3065622623 |
|
|
Oct 03 06:44:29 PM UTC 24 |
Oct 03 06:59:24 PM UTC 24 |
4338569820 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3371544894 |
|
|
Oct 03 05:19:33 PM UTC 24 |
Oct 03 06:59:33 PM UTC 24 |
15350102808 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2113564008 |
|
|
Oct 03 06:53:43 PM UTC 24 |
Oct 03 07:00:31 PM UTC 24 |
5584391050 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.385919709 |
|
|
Oct 03 06:51:18 PM UTC 24 |
Oct 03 07:00:59 PM UTC 24 |
8981480810 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3450740446 |
|
|
Oct 03 06:56:48 PM UTC 24 |
Oct 03 07:01:20 PM UTC 24 |
2851108750 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2134830721 |
|
|
Oct 03 06:54:56 PM UTC 24 |
Oct 03 07:02:58 PM UTC 24 |
5903541180 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.2065908088 |
|
|
Oct 03 06:51:06 PM UTC 24 |
Oct 03 07:02:58 PM UTC 24 |
6523697040 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.2366610767 |
|
|
Oct 03 06:59:02 PM UTC 24 |
Oct 03 07:04:38 PM UTC 24 |
2513648748 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2538289425 |
|
|
Oct 03 06:58:37 PM UTC 24 |
Oct 03 07:04:54 PM UTC 24 |
4505717848 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.537505123 |
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|
Oct 03 06:59:17 PM UTC 24 |
Oct 03 07:05:05 PM UTC 24 |
5791473564 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3710993841 |
|
|
Oct 03 06:44:32 PM UTC 24 |
Oct 03 07:05:09 PM UTC 24 |
7813504654 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3877050551 |
|
|
Oct 03 06:43:40 PM UTC 24 |
Oct 03 07:05:28 PM UTC 24 |
5794688083 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.485150908 |
|
|
Oct 03 06:42:06 PM UTC 24 |
Oct 03 07:05:36 PM UTC 24 |
5910454878 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.893023235 |
|
|
Oct 03 07:00:15 PM UTC 24 |
Oct 03 07:07:01 PM UTC 24 |
7259576392 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.3298502447 |
|
|
Oct 03 06:33:36 PM UTC 24 |
Oct 03 07:07:03 PM UTC 24 |
8592807432 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2843318402 |
|
|
Oct 03 05:31:05 PM UTC 24 |
Oct 03 07:07:50 PM UTC 24 |
15858580144 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1658895260 |
|
|
Oct 03 06:45:07 PM UTC 24 |
Oct 03 07:07:52 PM UTC 24 |
8895560592 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.6018066 |
|
|
Oct 03 06:59:19 PM UTC 24 |
Oct 03 07:07:56 PM UTC 24 |
3062919951 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1311847228 |
|
|
Oct 03 06:48:10 PM UTC 24 |
Oct 03 07:08:08 PM UTC 24 |
8653245298 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.795266844 |
|
|
Oct 03 07:00:14 PM UTC 24 |
Oct 03 07:08:52 PM UTC 24 |
3877831048 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2197329529 |
|
|
Oct 03 06:59:47 PM UTC 24 |
Oct 03 07:09:15 PM UTC 24 |
4113920816 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1669406116 |
|
|
Oct 03 06:33:42 PM UTC 24 |
Oct 03 07:09:34 PM UTC 24 |
8334148837 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.790427263 |
|
|
Oct 03 05:51:50 PM UTC 24 |
Oct 03 07:09:35 PM UTC 24 |
15557382096 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4088159384 |
|
|
Oct 03 06:59:09 PM UTC 24 |
Oct 03 07:09:38 PM UTC 24 |
4034364182 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.318712484 |
|
|
Oct 03 07:01:59 PM UTC 24 |
Oct 03 07:10:24 PM UTC 24 |
4189617244 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.2196089486 |
|
|
Oct 03 07:06:21 PM UTC 24 |
Oct 03 07:10:25 PM UTC 24 |
3200143905 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3801530610 |
|
|
Oct 03 06:53:45 PM UTC 24 |
Oct 03 07:11:43 PM UTC 24 |
10537909052 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.2740264651 |
|
|
Oct 03 07:06:20 PM UTC 24 |
Oct 03 07:12:02 PM UTC 24 |
2983958360 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2135437299 |
|
|
Oct 03 07:01:37 PM UTC 24 |
Oct 03 07:12:15 PM UTC 24 |
5400368510 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.269506543 |
|
|
Oct 03 05:43:39 PM UTC 24 |
Oct 03 07:12:22 PM UTC 24 |
17871953216 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1167414896 |
|
|
Oct 03 06:44:51 PM UTC 24 |
Oct 03 07:12:50 PM UTC 24 |
8014834138 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1931944114 |
|
|
Oct 03 07:07:50 PM UTC 24 |
Oct 03 07:13:00 PM UTC 24 |
2673820248 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2929800830 |
|
|
Oct 03 05:13:18 PM UTC 24 |
Oct 03 07:13:34 PM UTC 24 |
18059817186 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.2245618953 |
|
|
Oct 03 07:07:50 PM UTC 24 |
Oct 03 07:14:21 PM UTC 24 |
3772288633 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.2358923107 |
|
|
Oct 03 07:09:02 PM UTC 24 |
Oct 03 07:14:34 PM UTC 24 |
3253216240 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.3865369559 |
|
|
Oct 03 07:05:29 PM UTC 24 |
Oct 03 07:15:23 PM UTC 24 |
3611737064 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.932717403 |
|
|
Oct 03 07:09:49 PM UTC 24 |
Oct 03 07:15:43 PM UTC 24 |
3509884000 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.2458680421 |
|
|
Oct 03 07:11:14 PM UTC 24 |
Oct 03 07:16:05 PM UTC 24 |
3132168898 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3643052879 |
|
|
Oct 03 05:13:52 PM UTC 24 |
Oct 03 07:16:09 PM UTC 24 |
23380587731 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1555320334 |
|
|
Oct 03 07:01:10 PM UTC 24 |
Oct 03 07:16:30 PM UTC 24 |
9778367044 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.1852547979 |
|
|
Oct 03 07:11:13 PM UTC 24 |
Oct 03 07:16:42 PM UTC 24 |
3360219815 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1169036249 |
|
|
Oct 03 07:09:07 PM UTC 24 |
Oct 03 07:17:27 PM UTC 24 |
3925600776 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1690139789 |
|
|
Oct 03 06:53:38 PM UTC 24 |
Oct 03 07:17:43 PM UTC 24 |
9391419318 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.2757747381 |
|
|
Oct 03 07:12:24 PM UTC 24 |
Oct 03 07:17:49 PM UTC 24 |
3002171720 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.3714301031 |
|
|
Oct 03 07:08:59 PM UTC 24 |
Oct 03 07:18:51 PM UTC 24 |
4518323980 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.2367419964 |
|
|
Oct 03 06:42:56 PM UTC 24 |
Oct 03 07:19:07 PM UTC 24 |
16221845130 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.153523112 |
|
|
Oct 03 06:51:18 PM UTC 24 |
Oct 03 07:19:37 PM UTC 24 |
7758758187 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.959438208 |
|
|
Oct 03 07:05:57 PM UTC 24 |
Oct 03 07:19:39 PM UTC 24 |
4863135580 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.891460565 |
|
|
Oct 03 05:14:13 PM UTC 24 |
Oct 03 07:20:04 PM UTC 24 |
21954121506 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.2903820419 |
|
|
Oct 03 07:03:49 PM UTC 24 |
Oct 03 07:20:24 PM UTC 24 |
5936110806 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.510565481 |
|
|
Oct 03 07:15:59 PM UTC 24 |
Oct 03 07:20:29 PM UTC 24 |
3573225608 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1906564923 |
|
|
Oct 03 07:15:09 PM UTC 24 |
Oct 03 07:20:31 PM UTC 24 |
3482997032 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2284984277 |
|
|
Oct 03 07:02:44 PM UTC 24 |
Oct 03 07:21:08 PM UTC 24 |
19814024264 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.409872449 |
|
|
Oct 03 06:51:51 PM UTC 24 |
Oct 03 07:21:10 PM UTC 24 |
12755813703 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1344258875 |
|
|
Oct 03 07:17:23 PM UTC 24 |
Oct 03 07:21:32 PM UTC 24 |
2562501344 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.3699957026 |
|
|
Oct 03 07:18:13 PM UTC 24 |
Oct 03 07:21:56 PM UTC 24 |
2850009992 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.2670354992 |
|
|
Oct 03 07:17:24 PM UTC 24 |
Oct 03 07:22:58 PM UTC 24 |
3075918599 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.758166551 |
|
|
Oct 03 05:11:25 PM UTC 24 |
Oct 03 07:23:10 PM UTC 24 |
24590556744 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.344999164 |
|
|
Oct 03 07:15:14 PM UTC 24 |
Oct 03 07:23:49 PM UTC 24 |
4287131290 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3058983022 |
|
|
Oct 03 07:18:29 PM UTC 24 |
Oct 03 07:24:00 PM UTC 24 |
2538411560 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.833013673 |
|
|
Oct 03 07:13:07 PM UTC 24 |
Oct 03 07:24:22 PM UTC 24 |
3132613744 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.800053389 |
|
|
Oct 03 05:12:56 PM UTC 24 |
Oct 03 07:24:36 PM UTC 24 |
19140182688 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.4051574694 |
|
|
Oct 03 07:13:06 PM UTC 24 |
Oct 03 07:25:06 PM UTC 24 |
3340816040 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2351567315 |
|
|
Oct 03 06:51:36 PM UTC 24 |
Oct 03 07:25:18 PM UTC 24 |
11347484719 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2033809132 |
|
|
Oct 03 05:41:21 PM UTC 24 |
Oct 03 07:25:29 PM UTC 24 |
63759083041 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.2685922908 |
|
|
Oct 03 07:21:56 PM UTC 24 |
Oct 03 07:25:38 PM UTC 24 |
2769111306 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2584717752 |
|
|
Oct 03 07:22:10 PM UTC 24 |
Oct 03 07:26:21 PM UTC 24 |
2861645090 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.140131986 |
|
|
Oct 03 07:21:25 PM UTC 24 |
Oct 03 07:26:27 PM UTC 24 |
2771964888 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1734844869 |
|
|
Oct 03 06:50:35 PM UTC 24 |
Oct 03 07:26:51 PM UTC 24 |
11717995436 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.721596572 |
|
|
Oct 03 07:12:41 PM UTC 24 |
Oct 03 07:27:02 PM UTC 24 |
3530030356 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.2882114807 |
|
|
Oct 03 07:21:22 PM UTC 24 |
Oct 03 07:27:06 PM UTC 24 |
2823304866 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2914186972 |
|
|
Oct 03 06:59:22 PM UTC 24 |
Oct 03 07:27:11 PM UTC 24 |
21868602422 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1421339848 |
|
|
Oct 03 07:21:56 PM UTC 24 |
Oct 03 07:27:23 PM UTC 24 |
3211754362 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3584924532 |
|
|
Oct 03 07:05:56 PM UTC 24 |
Oct 03 07:29:01 PM UTC 24 |
5878057152 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3119107442 |
|
|
Oct 03 06:01:27 PM UTC 24 |
Oct 03 07:29:58 PM UTC 24 |
15437732564 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.2808408954 |
|
|
Oct 03 05:41:39 PM UTC 24 |
Oct 03 07:30:33 PM UTC 24 |
57162903537 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3040894374 |
|
|
Oct 03 07:22:28 PM UTC 24 |
Oct 03 07:30:48 PM UTC 24 |
9760812921 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.1827962399 |
|
|
Oct 03 07:26:15 PM UTC 24 |
Oct 03 07:31:00 PM UTC 24 |
2779630845 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3745475974 |
|
|
Oct 03 07:13:43 PM UTC 24 |
Oct 03 07:31:30 PM UTC 24 |
5956129120 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.83360273 |
|
|
Oct 03 07:09:03 PM UTC 24 |
Oct 03 07:32:02 PM UTC 24 |
7527526004 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.1381811825 |
|
|
Oct 03 07:27:29 PM UTC 24 |
Oct 03 07:32:20 PM UTC 24 |
2795961880 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.3953633669 |
|
|
Oct 03 07:24:38 PM UTC 24 |
Oct 03 07:33:48 PM UTC 24 |
6065713497 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1670453526 |
|
|
Oct 03 07:28:19 PM UTC 24 |
Oct 03 07:34:18 PM UTC 24 |
4632035496 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1145578879 |
|
|
Oct 03 07:13:41 PM UTC 24 |
Oct 03 07:34:28 PM UTC 24 |
6185925622 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.352173736 |
|
|
Oct 03 07:26:19 PM UTC 24 |
Oct 03 07:35:00 PM UTC 24 |
5133406610 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2952026986 |
|
|
Oct 03 07:23:51 PM UTC 24 |
Oct 03 07:35:08 PM UTC 24 |
5661742088 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2172544639 |
|
|
Oct 03 07:28:20 PM UTC 24 |
Oct 03 07:35:12 PM UTC 24 |
5035244920 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.4129969320 |
|
|
Oct 03 07:17:07 PM UTC 24 |
Oct 03 07:35:14 PM UTC 24 |
7142177126 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.293266210 |
|
|
Oct 03 07:23:51 PM UTC 24 |
Oct 03 07:36:27 PM UTC 24 |
4955950008 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.432410993 |
|
|
Oct 03 07:10:40 PM UTC 24 |
Oct 03 07:37:15 PM UTC 24 |
13189091032 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.4167713745 |
|
|
Oct 03 07:27:12 PM UTC 24 |
Oct 03 07:37:37 PM UTC 24 |
3685733864 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.638775693 |
|
|
Oct 03 07:25:12 PM UTC 24 |
Oct 03 07:38:07 PM UTC 24 |
8092380776 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4245757512 |
|
|
Oct 03 07:17:08 PM UTC 24 |
Oct 03 07:38:18 PM UTC 24 |
7418884840 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1660922722 |
|
|
Oct 03 07:25:15 PM UTC 24 |
Oct 03 07:38:19 PM UTC 24 |
5271856512 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2752769141 |
|
|
Oct 03 07:29:41 PM UTC 24 |
Oct 03 07:39:05 PM UTC 24 |
5392407712 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.1977733868 |
|
|
Oct 03 07:35:08 PM UTC 24 |
Oct 03 07:39:20 PM UTC 24 |
3364970302 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.528711919 |
|
|
Oct 03 07:28:19 PM UTC 24 |
Oct 03 07:40:34 PM UTC 24 |
5332267412 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1914038899 |
|
|
Oct 03 07:27:13 PM UTC 24 |
Oct 03 07:40:43 PM UTC 24 |
4797513300 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3727696286 |
|
|
Oct 03 07:24:39 PM UTC 24 |
Oct 03 07:42:09 PM UTC 24 |
8692841592 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.132961126 |
|
|
Oct 03 07:31:38 PM UTC 24 |
Oct 03 07:42:09 PM UTC 24 |
5023318198 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1970496031 |
|
|
Oct 03 07:30:37 PM UTC 24 |
Oct 03 07:42:27 PM UTC 24 |
10249212600 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3962786448 |
|
|
Oct 03 07:34:28 PM UTC 24 |
Oct 03 07:42:55 PM UTC 24 |
4004461376 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2570864494 |
|
|
Oct 03 05:13:03 PM UTC 24 |
Oct 03 07:43:17 PM UTC 24 |
23630079247 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.2538845394 |
|
|
Oct 03 07:42:58 PM UTC 24 |
Oct 03 07:46:56 PM UTC 24 |
3194636167 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2829055935 |
|
|
Oct 03 05:12:16 PM UTC 24 |
Oct 03 07:43:17 PM UTC 24 |
24278593440 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.72719795 |
|
|
Oct 03 07:35:04 PM UTC 24 |
Oct 03 07:43:49 PM UTC 24 |
2909514864 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4166182181 |
|
|
Oct 03 07:10:38 PM UTC 24 |
Oct 03 07:44:05 PM UTC 24 |
6650797532 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3206575383 |
|
|
Oct 03 07:32:12 PM UTC 24 |
Oct 03 07:44:16 PM UTC 24 |
5159246840 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2650776040 |
|
|
Oct 03 07:31:24 PM UTC 24 |
Oct 03 07:44:43 PM UTC 24 |
4340732320 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1521905884 |
|
|
Oct 03 07:33:00 PM UTC 24 |
Oct 03 07:45:11 PM UTC 24 |
4489196170 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2262390785 |
|
|
Oct 03 07:35:36 PM UTC 24 |
Oct 03 07:45:50 PM UTC 24 |
4365785606 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2125222248 |
|
|
Oct 03 07:39:58 PM UTC 24 |
Oct 03 07:46:01 PM UTC 24 |
3372632960 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.1728571096 |
|
|
Oct 03 07:26:24 PM UTC 24 |
Oct 03 07:46:58 PM UTC 24 |
6695275032 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3183995174 |
|
|
Oct 03 07:31:42 PM UTC 24 |
Oct 03 07:47:00 PM UTC 24 |
4872937732 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.2472093186 |
|
|
Oct 03 08:06:14 PM UTC 24 |
Oct 03 08:08:49 PM UTC 24 |
2207287688 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.340025235 |
|
|
Oct 03 07:42:47 PM UTC 24 |
Oct 03 07:47:20 PM UTC 24 |
3444479106 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1717180026 |
|
|
Oct 03 05:13:44 PM UTC 24 |
Oct 03 07:47:26 PM UTC 24 |
23781119904 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2868821671 |
|
|
Oct 03 07:37:08 PM UTC 24 |
Oct 03 07:47:31 PM UTC 24 |
4882641744 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2468505748 |
|
|
Oct 03 06:49:57 PM UTC 24 |
Oct 03 07:47:35 PM UTC 24 |
26186029572 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.329613592 |
|
|
Oct 03 07:32:43 PM UTC 24 |
Oct 03 07:47:51 PM UTC 24 |
4193161608 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4166105484 |
|
|
Oct 03 06:51:37 PM UTC 24 |
Oct 03 07:47:54 PM UTC 24 |
21069624814 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4019363743 |
|
|
Oct 03 05:12:24 PM UTC 24 |
Oct 03 07:48:08 PM UTC 24 |
23619375528 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1586913603 |
|
|
Oct 03 07:37:55 PM UTC 24 |
Oct 03 07:48:46 PM UTC 24 |
7234408648 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1606197334 |
|
|
Oct 03 07:39:43 PM UTC 24 |
Oct 03 07:49:13 PM UTC 24 |
6396966230 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3040807013 |
|
|
Oct 03 07:41:27 PM UTC 24 |
Oct 03 07:49:20 PM UTC 24 |
5670594460 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2647543539 |
|
|
Oct 03 07:39:07 PM UTC 24 |
Oct 03 07:49:22 PM UTC 24 |
6547786936 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3439244836 |
|
|
Oct 03 07:45:22 PM UTC 24 |
Oct 03 07:49:34 PM UTC 24 |
2455029665 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3950394891 |
|
|
Oct 03 07:44:29 PM UTC 24 |
Oct 03 07:49:36 PM UTC 24 |
3008568830 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.1813050177 |
|
|
Oct 03 07:44:59 PM UTC 24 |
Oct 03 07:50:14 PM UTC 24 |
2879134436 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.918071557 |
|
|
Oct 03 07:18:30 PM UTC 24 |
Oct 03 07:50:30 PM UTC 24 |
8177180044 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2189327308 |
|
|
Oct 03 07:46:55 PM UTC 24 |
Oct 03 07:50:39 PM UTC 24 |
2747280323 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2565346654 |
|
|
Oct 03 07:41:24 PM UTC 24 |
Oct 03 07:50:47 PM UTC 24 |
5368415640 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3238946849 |
|
|
Oct 03 07:44:08 PM UTC 24 |
Oct 03 07:51:05 PM UTC 24 |
3280422520 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3155000204 |
|
|
Oct 03 07:16:22 PM UTC 24 |
Oct 03 07:52:46 PM UTC 24 |
8072064696 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.4255232657 |
|
|
Oct 03 07:35:51 PM UTC 24 |
Oct 03 07:53:13 PM UTC 24 |
8687825872 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.417438228 |
|
|
Oct 03 07:42:50 PM UTC 24 |
Oct 03 07:54:00 PM UTC 24 |
6365003638 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2860470510 |
|
|
Oct 03 07:10:39 PM UTC 24 |
Oct 03 07:54:03 PM UTC 24 |
8957540442 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3844725427 |
|
|
Oct 03 07:49:03 PM UTC 24 |
Oct 03 07:54:03 PM UTC 24 |
3346015994 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3983181084 |
|
|
Oct 03 07:49:35 PM UTC 24 |
Oct 03 07:54:17 PM UTC 24 |
2241800906 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2766037515 |
|
|
Oct 03 07:51:08 PM UTC 24 |
Oct 03 07:55:33 PM UTC 24 |
2513764816 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.780260955 |
|
|
Oct 03 05:13:01 PM UTC 24 |
Oct 03 07:56:40 PM UTC 24 |
24321857632 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.935573493 |
|
|
Oct 03 07:55:08 PM UTC 24 |
Oct 03 07:57:37 PM UTC 24 |
2263679466 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.3907137362 |
|
|
Oct 03 07:44:58 PM UTC 24 |
Oct 03 07:58:04 PM UTC 24 |
5349254032 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1600511607 |
|
|
Oct 03 07:19:43 PM UTC 24 |
Oct 03 07:58:24 PM UTC 24 |
9365885034 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.1014783324 |
|
|
Oct 03 07:28:21 PM UTC 24 |
Oct 03 07:58:57 PM UTC 24 |
9723163624 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3503697469 |
|
|
Oct 03 07:45:53 PM UTC 24 |
Oct 03 07:59:39 PM UTC 24 |
5231463163 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3191643912 |
|
|
Oct 03 07:49:09 PM UTC 24 |
Oct 03 07:59:53 PM UTC 24 |
4729885601 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2100875264 |
|
|
Oct 03 07:55:23 PM UTC 24 |
Oct 03 08:00:29 PM UTC 24 |
5582866562 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2758366275 |
|
|
Oct 03 07:56:10 PM UTC 24 |
Oct 03 08:00:48 PM UTC 24 |
2795164962 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2864174640 |
|
|
Oct 03 07:20:44 PM UTC 24 |
Oct 03 08:01:07 PM UTC 24 |
11654155256 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2004581262 |
|
|
Oct 03 07:20:29 PM UTC 24 |
Oct 03 08:01:16 PM UTC 24 |
11272862323 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.394416300 |
|
|
Oct 03 07:57:22 PM UTC 24 |
Oct 03 08:02:33 PM UTC 24 |
2957499788 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.1317027529 |
|
|
Oct 03 07:58:15 PM UTC 24 |
Oct 03 08:02:48 PM UTC 24 |
2538516568 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.3462047061 |
|
|
Oct 03 07:58:41 PM UTC 24 |
Oct 03 08:02:54 PM UTC 24 |
2714896112 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.36055782 |
|
|
Oct 03 07:49:33 PM UTC 24 |
Oct 03 08:03:11 PM UTC 24 |
10821110170 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.3533767259 |
|
|
Oct 03 07:51:39 PM UTC 24 |
Oct 03 08:03:13 PM UTC 24 |
4725988448 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.934801863 |
|
|
Oct 03 07:59:37 PM UTC 24 |
Oct 03 08:04:10 PM UTC 24 |
2811892124 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.2486423348 |
|
|
Oct 03 08:01:26 PM UTC 24 |
Oct 03 08:05:42 PM UTC 24 |
2903962500 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2957942615 |
|
|
Oct 03 08:00:28 PM UTC 24 |
Oct 03 08:06:12 PM UTC 24 |
3679205780 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1316544426 |
|
|
Oct 03 08:00:33 PM UTC 24 |
Oct 03 08:06:59 PM UTC 24 |
3116038784 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.845997844 |
|
|
Oct 03 07:39:10 PM UTC 24 |
Oct 03 08:07:01 PM UTC 24 |
24869869182 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.181621442 |
|
|
Oct 03 08:01:54 PM UTC 24 |
Oct 03 08:07:18 PM UTC 24 |
6096803716 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3399802809 |
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|
Oct 03 08:03:38 PM UTC 24 |
Oct 03 08:07:21 PM UTC 24 |
2828031176 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.2116463688 |
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|
Oct 03 07:55:17 PM UTC 24 |
Oct 03 08:07:23 PM UTC 24 |
4008079244 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.662639172 |
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|
Oct 03 07:59:02 PM UTC 24 |
Oct 03 08:07:46 PM UTC 24 |
3160006408 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.46777489 |
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|
Oct 03 08:04:02 PM UTC 24 |
Oct 03 08:07:49 PM UTC 24 |
2665724424 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.2227136470 |
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Oct 03 08:03:31 PM UTC 24 |
Oct 03 08:08:29 PM UTC 24 |
2813248966 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.2603641836 |
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|
Oct 03 08:03:38 PM UTC 24 |
Oct 03 08:08:34 PM UTC 24 |
3239963540 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4265260016 |
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Oct 03 07:46:51 PM UTC 24 |
Oct 03 08:08:38 PM UTC 24 |
7442413760 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1552578176 |
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|
Oct 03 07:26:24 PM UTC 24 |
Oct 03 08:08:41 PM UTC 24 |
26341162037 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3206132854 |
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|
Oct 03 08:04:50 PM UTC 24 |
Oct 03 08:09:37 PM UTC 24 |
2560651000 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.1829576741 |
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|
Oct 03 07:19:31 PM UTC 24 |
Oct 03 08:09:59 PM UTC 24 |
11429554546 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4187431210 |
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Oct 03 08:01:57 PM UTC 24 |
Oct 03 08:10:05 PM UTC 24 |
5024350618 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.3357522603 |
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|
Oct 03 08:04:02 PM UTC 24 |
Oct 03 08:10:11 PM UTC 24 |
2793208174 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3523277593 |
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|
Oct 03 08:06:52 PM UTC 24 |
Oct 03 08:12:13 PM UTC 24 |
2974295282 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.236939549 |
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|
Oct 03 06:59:48 PM UTC 24 |
Oct 03 08:12:23 PM UTC 24 |
20866505925 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1616790247 |
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|
Oct 03 07:39:07 PM UTC 24 |
Oct 03 08:12:35 PM UTC 24 |
27661937290 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3961005002 |
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|
Oct 03 06:05:38 PM UTC 24 |
Oct 03 08:12:37 PM UTC 24 |
25796144932 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.75508744 |
|
|
Oct 03 08:09:02 PM UTC 24 |
Oct 03 08:12:55 PM UTC 24 |
3501331680 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.1553311505 |
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|
Oct 03 07:35:36 PM UTC 24 |
Oct 03 08:12:56 PM UTC 24 |
22328259912 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4261381404 |
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|
Oct 03 07:49:47 PM UTC 24 |
Oct 03 08:12:59 PM UTC 24 |
8071109687 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.525049448 |
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|
Oct 03 08:08:09 PM UTC 24 |
Oct 03 08:13:07 PM UTC 24 |
2851072946 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1746453741 |
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|
Oct 03 07:50:03 PM UTC 24 |
Oct 03 08:13:33 PM UTC 24 |
5819525752 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.3975735924 |
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|
Oct 03 08:09:59 PM UTC 24 |
Oct 03 08:13:34 PM UTC 24 |
2589267000 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.671913911 |
|
|
Oct 03 08:08:53 PM UTC 24 |
Oct 03 08:13:42 PM UTC 24 |
2894146556 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2055403041 |
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|
Oct 03 08:09:39 PM UTC 24 |
Oct 03 08:14:28 PM UTC 24 |
3067532458 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.869847560 |
|
|
Oct 03 08:09:40 PM UTC 24 |
Oct 03 08:15:21 PM UTC 24 |
3894219456 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.994562315 |
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|
Oct 03 07:20:29 PM UTC 24 |
Oct 03 08:16:44 PM UTC 24 |
12729795902 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.57842664 |
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Oct 03 07:50:52 PM UTC 24 |
Oct 03 08:17:13 PM UTC 24 |
5849649932 ps |