| T2515 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.3725284491 |
|
|
Oct 03 03:16:08 PM UTC 24 |
Oct 03 03:38:00 PM UTC 24 |
68217093249 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.1023264969 |
|
|
Oct 03 03:35:57 PM UTC 24 |
Oct 03 03:38:01 PM UTC 24 |
2423922541 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.670686912 |
|
|
Oct 03 03:32:16 PM UTC 24 |
Oct 03 03:38:05 PM UTC 24 |
5723919540 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.2405262249 |
|
|
Oct 03 03:37:25 PM UTC 24 |
Oct 03 03:38:06 PM UTC 24 |
249587098 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.4265440285 |
|
|
Oct 03 03:37:12 PM UTC 24 |
Oct 03 03:38:09 PM UTC 24 |
964292597 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3934472936 |
|
|
Oct 03 03:37:59 PM UTC 24 |
Oct 03 03:38:09 PM UTC 24 |
48676598 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.2520528293 |
|
|
Oct 03 03:37:13 PM UTC 24 |
Oct 03 03:38:10 PM UTC 24 |
522738545 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3560351577 |
|
|
Oct 03 03:27:19 PM UTC 24 |
Oct 03 03:38:11 PM UTC 24 |
5374161822 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2644240835 |
|
|
Oct 03 03:31:42 PM UTC 24 |
Oct 03 03:38:18 PM UTC 24 |
21748218433 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2573002682 |
|
|
Oct 03 03:32:15 PM UTC 24 |
Oct 03 03:38:19 PM UTC 24 |
10213060201 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.1926784881 |
|
|
Oct 03 03:37:06 PM UTC 24 |
Oct 03 03:38:19 PM UTC 24 |
832674356 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.409446266 |
|
|
Oct 03 03:36:13 PM UTC 24 |
Oct 03 03:38:22 PM UTC 24 |
1389304488 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.28817993 |
|
|
Oct 03 03:38:12 PM UTC 24 |
Oct 03 03:38:29 PM UTC 24 |
114397672 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3553258587 |
|
|
Oct 03 03:36:45 PM UTC 24 |
Oct 03 03:38:34 PM UTC 24 |
4682138238 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.4278315723 |
|
|
Oct 03 03:31:07 PM UTC 24 |
Oct 03 03:38:40 PM UTC 24 |
14398331024 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1552256102 |
|
|
Oct 03 03:38:31 PM UTC 24 |
Oct 03 03:38:49 PM UTC 24 |
287447520 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.1342061963 |
|
|
Oct 03 03:35:05 PM UTC 24 |
Oct 03 03:38:49 PM UTC 24 |
2578053419 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.829253624 |
|
|
Oct 03 03:33:30 PM UTC 24 |
Oct 03 03:38:50 PM UTC 24 |
637366181 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3423357026 |
|
|
Oct 03 03:38:44 PM UTC 24 |
Oct 03 03:38:54 PM UTC 24 |
54940303 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.1515870986 |
|
|
Oct 03 03:38:26 PM UTC 24 |
Oct 03 03:38:55 PM UTC 24 |
247936644 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2418623260 |
|
|
Oct 03 03:36:43 PM UTC 24 |
Oct 03 03:38:57 PM UTC 24 |
9701350210 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2936764065 |
|
|
Oct 03 03:38:35 PM UTC 24 |
Oct 03 03:39:01 PM UTC 24 |
328020919 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.2487441074 |
|
|
Oct 03 03:38:46 PM UTC 24 |
Oct 03 03:39:02 PM UTC 24 |
175985052 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.3701056297 |
|
|
Oct 03 03:37:12 PM UTC 24 |
Oct 03 03:39:03 PM UTC 24 |
2494285370 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2723215346 |
|
|
Oct 03 03:38:37 PM UTC 24 |
Oct 03 03:39:04 PM UTC 24 |
197601294 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.2396080139 |
|
|
Oct 03 03:38:32 PM UTC 24 |
Oct 03 03:39:05 PM UTC 24 |
340291748 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.2249808475 |
|
|
Oct 03 03:38:18 PM UTC 24 |
Oct 03 03:39:05 PM UTC 24 |
374227629 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1419792262 |
|
|
Oct 03 03:28:00 PM UTC 24 |
Oct 03 03:39:35 PM UTC 24 |
38316552261 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.678226300 |
|
|
Oct 03 03:38:37 PM UTC 24 |
Oct 03 03:39:37 PM UTC 24 |
123103412 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3541716678 |
|
|
Oct 03 03:39:30 PM UTC 24 |
Oct 03 03:39:43 PM UTC 24 |
35330605 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.668762216 |
|
|
Oct 03 03:38:06 PM UTC 24 |
Oct 03 03:39:44 PM UTC 24 |
9839755516 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.2763577789 |
|
|
Oct 03 03:39:17 PM UTC 24 |
Oct 03 03:39:46 PM UTC 24 |
222897842 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3650310325 |
|
|
Oct 03 03:33:50 PM UTC 24 |
Oct 03 03:39:47 PM UTC 24 |
2416520136 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1432904447 |
|
|
Oct 03 03:38:11 PM UTC 24 |
Oct 03 03:39:48 PM UTC 24 |
4997583284 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.1889021384 |
|
|
Oct 03 03:39:29 PM UTC 24 |
Oct 03 03:39:53 PM UTC 24 |
446493459 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1814139436 |
|
|
Oct 03 03:28:21 PM UTC 24 |
Oct 03 03:40:03 PM UTC 24 |
10720598774 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.102457821 |
|
|
Oct 03 03:39:23 PM UTC 24 |
Oct 03 03:40:03 PM UTC 24 |
707245592 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1436330180 |
|
|
Oct 03 03:21:46 PM UTC 24 |
Oct 03 03:40:05 PM UTC 24 |
61804909271 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.3906367229 |
|
|
Oct 03 03:39:12 PM UTC 24 |
Oct 03 03:40:07 PM UTC 24 |
432962881 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.2348076587 |
|
|
Oct 03 03:38:54 PM UTC 24 |
Oct 03 03:40:14 PM UTC 24 |
8622802607 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.1659971109 |
|
|
Oct 03 03:40:04 PM UTC 24 |
Oct 03 03:40:17 PM UTC 24 |
184475860 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.438876998 |
|
|
Oct 03 03:38:24 PM UTC 24 |
Oct 03 03:40:19 PM UTC 24 |
6076401845 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4215120718 |
|
|
Oct 03 03:40:10 PM UTC 24 |
Oct 03 03:40:22 PM UTC 24 |
49478898 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.1926948325 |
|
|
Oct 03 03:24:07 PM UTC 24 |
Oct 03 03:40:23 PM UTC 24 |
60203649115 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2622412879 |
|
|
Oct 03 03:39:29 PM UTC 24 |
Oct 03 03:40:24 PM UTC 24 |
1185979025 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.1482552404 |
|
|
Oct 03 03:38:43 PM UTC 24 |
Oct 03 03:40:28 PM UTC 24 |
1114811231 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3607900601 |
|
|
Oct 03 03:39:01 PM UTC 24 |
Oct 03 03:40:35 PM UTC 24 |
6301532352 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2840803928 |
|
|
Oct 03 03:39:02 PM UTC 24 |
Oct 03 03:40:35 PM UTC 24 |
1952257662 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.3449411082 |
|
|
Oct 03 03:28:26 PM UTC 24 |
Oct 03 03:40:43 PM UTC 24 |
20310667593 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1475041426 |
|
|
Oct 03 03:37:25 PM UTC 24 |
Oct 03 03:40:54 PM UTC 24 |
3552360590 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2552047270 |
|
|
Oct 03 03:40:45 PM UTC 24 |
Oct 03 03:40:55 PM UTC 24 |
91505854 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.2007984585 |
|
|
Oct 03 03:40:40 PM UTC 24 |
Oct 03 03:40:56 PM UTC 24 |
124181550 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.4072367305 |
|
|
Oct 03 03:40:45 PM UTC 24 |
Oct 03 03:41:07 PM UTC 24 |
220090919 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3563882580 |
|
|
Oct 03 03:41:00 PM UTC 24 |
Oct 03 03:41:10 PM UTC 24 |
47167064 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.1567293810 |
|
|
Oct 03 03:40:31 PM UTC 24 |
Oct 03 03:41:14 PM UTC 24 |
469693761 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1110313322 |
|
|
Oct 03 03:41:01 PM UTC 24 |
Oct 03 03:41:16 PM UTC 24 |
188533929 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1025982480 |
|
|
Oct 03 03:40:17 PM UTC 24 |
Oct 03 03:41:22 PM UTC 24 |
1650602718 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.2146734371 |
|
|
Oct 03 03:40:15 PM UTC 24 |
Oct 03 03:41:25 PM UTC 24 |
559668602 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3268008307 |
|
|
Oct 03 03:40:36 PM UTC 24 |
Oct 03 03:41:32 PM UTC 24 |
1294515050 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.1148341855 |
|
|
Oct 03 03:41:20 PM UTC 24 |
Oct 03 03:41:34 PM UTC 24 |
68471178 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1628579861 |
|
|
Oct 03 03:39:31 PM UTC 24 |
Oct 03 03:41:45 PM UTC 24 |
1435534729 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.4046161818 |
|
|
Oct 03 03:36:21 PM UTC 24 |
Oct 03 03:41:47 PM UTC 24 |
10100007255 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.4233983832 |
|
|
Oct 03 03:40:11 PM UTC 24 |
Oct 03 03:41:50 PM UTC 24 |
6708320924 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3943709970 |
|
|
Oct 03 03:35:05 PM UTC 24 |
Oct 03 03:41:51 PM UTC 24 |
2840653603 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1878739238 |
|
|
Oct 03 03:39:27 PM UTC 24 |
Oct 03 03:42:11 PM UTC 24 |
3701221822 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2143908580 |
|
|
Oct 03 03:40:10 PM UTC 24 |
Oct 03 03:42:11 PM UTC 24 |
7956902170 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.4079219116 |
|
|
Oct 03 03:38:22 PM UTC 24 |
Oct 03 03:42:14 PM UTC 24 |
20890856900 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2884273499 |
|
|
Oct 03 03:26:33 PM UTC 24 |
Oct 03 03:42:20 PM UTC 24 |
67457562818 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2791424914 |
|
|
Oct 03 03:38:44 PM UTC 24 |
Oct 03 03:42:22 PM UTC 24 |
611486075 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.723312296 |
|
|
Oct 03 03:41:41 PM UTC 24 |
Oct 03 03:42:22 PM UTC 24 |
1018963669 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1902243035 |
|
|
Oct 03 03:34:30 PM UTC 24 |
Oct 03 03:42:23 PM UTC 24 |
26220892535 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1161592850 |
|
|
Oct 03 03:46:54 PM UTC 24 |
Oct 03 03:47:53 PM UTC 24 |
1140822599 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.526753315 |
|
|
Oct 03 03:40:04 PM UTC 24 |
Oct 03 03:42:28 PM UTC 24 |
551749834 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.2640413762 |
|
|
Oct 03 03:41:59 PM UTC 24 |
Oct 03 03:42:28 PM UTC 24 |
153034767 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3637921585 |
|
|
Oct 03 03:41:51 PM UTC 24 |
Oct 03 03:42:30 PM UTC 24 |
849073403 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1881343991 |
|
|
Oct 03 03:41:09 PM UTC 24 |
Oct 03 03:42:33 PM UTC 24 |
6393546346 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2737999352 |
|
|
Oct 03 03:31:24 PM UTC 24 |
Oct 03 03:42:39 PM UTC 24 |
64490755989 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1022161113 |
|
|
Oct 03 03:41:18 PM UTC 24 |
Oct 03 03:42:40 PM UTC 24 |
5101516103 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.706787332 |
|
|
Oct 03 03:42:33 PM UTC 24 |
Oct 03 03:42:45 PM UTC 24 |
197841842 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1504228235 |
|
|
Oct 03 03:41:22 PM UTC 24 |
Oct 03 03:42:46 PM UTC 24 |
1549929149 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3179520990 |
|
|
Oct 03 03:42:37 PM UTC 24 |
Oct 03 03:42:46 PM UTC 24 |
43298376 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.1102961152 |
|
|
Oct 03 03:40:49 PM UTC 24 |
Oct 03 03:42:48 PM UTC 24 |
2677677032 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1026936068 |
|
|
Oct 03 03:42:01 PM UTC 24 |
Oct 03 03:42:52 PM UTC 24 |
309113797 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.3677468302 |
|
|
Oct 03 03:41:50 PM UTC 24 |
Oct 03 03:43:07 PM UTC 24 |
2193626352 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.866761477 |
|
|
Oct 03 03:42:46 PM UTC 24 |
Oct 03 03:43:09 PM UTC 24 |
301723263 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.343131674 |
|
|
Oct 03 03:42:56 PM UTC 24 |
Oct 03 03:43:21 PM UTC 24 |
338426674 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1380954630 |
|
|
Oct 03 03:42:44 PM UTC 24 |
Oct 03 03:43:21 PM UTC 24 |
325473779 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1070539151 |
|
|
Oct 03 03:34:50 PM UTC 24 |
Oct 03 03:43:21 PM UTC 24 |
14578940929 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.46764160 |
|
|
Oct 03 03:43:04 PM UTC 24 |
Oct 03 03:43:39 PM UTC 24 |
390318058 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.798674025 |
|
|
Oct 03 03:43:31 PM UTC 24 |
Oct 03 03:43:43 PM UTC 24 |
227423669 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2622603611 |
|
|
Oct 03 03:43:36 PM UTC 24 |
Oct 03 03:43:46 PM UTC 24 |
37039255 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.460055854 |
|
|
Oct 03 03:38:25 PM UTC 24 |
Oct 03 03:43:47 PM UTC 24 |
20856471863 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.758468287 |
|
|
Oct 03 03:43:12 PM UTC 24 |
Oct 03 03:43:55 PM UTC 24 |
753744567 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.4041248672 |
|
|
Oct 03 03:43:05 PM UTC 24 |
Oct 03 03:43:57 PM UTC 24 |
1333692641 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1617142027 |
|
|
Oct 03 03:42:39 PM UTC 24 |
Oct 03 03:43:57 PM UTC 24 |
8403182097 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.4135514889 |
|
|
Oct 03 03:43:45 PM UTC 24 |
Oct 03 03:43:59 PM UTC 24 |
61058871 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1335400165 |
|
|
Oct 03 03:42:43 PM UTC 24 |
Oct 03 03:44:06 PM UTC 24 |
5325291684 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3088633026 |
|
|
Oct 03 03:37:26 PM UTC 24 |
Oct 03 03:44:07 PM UTC 24 |
3701971482 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.516295941 |
|
|
Oct 03 03:27:59 PM UTC 24 |
Oct 03 03:44:09 PM UTC 24 |
52371998197 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1862234482 |
|
|
Oct 03 03:03:11 PM UTC 24 |
Oct 03 03:44:13 PM UTC 24 |
163523183933 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.264759483 |
|
|
Oct 03 03:44:04 PM UTC 24 |
Oct 03 03:44:18 PM UTC 24 |
111883784 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.8710440 |
|
|
Oct 03 03:38:34 PM UTC 24 |
Oct 03 03:44:23 PM UTC 24 |
9363641410 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3999735128 |
|
|
Oct 03 03:42:50 PM UTC 24 |
Oct 03 03:44:30 PM UTC 24 |
2500943692 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.33756024 |
|
|
Oct 03 03:32:57 PM UTC 24 |
Oct 03 03:44:32 PM UTC 24 |
64367191932 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.988627875 |
|
|
Oct 03 03:37:36 PM UTC 24 |
Oct 03 03:44:33 PM UTC 24 |
5872337547 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2834052192 |
|
|
Oct 03 03:44:23 PM UTC 24 |
Oct 03 03:44:35 PM UTC 24 |
78760503 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1345914042 |
|
|
Oct 03 03:41:42 PM UTC 24 |
Oct 03 03:44:45 PM UTC 24 |
10279076988 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.4007482829 |
|
|
Oct 03 03:42:18 PM UTC 24 |
Oct 03 03:44:46 PM UTC 24 |
438764225 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2469203583 |
|
|
Oct 03 03:33:26 PM UTC 24 |
Oct 03 03:44:48 PM UTC 24 |
15488243369 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2478076776 |
|
|
Oct 03 03:44:35 PM UTC 24 |
Oct 03 03:44:55 PM UTC 24 |
45372789 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2623032914 |
|
|
Oct 03 03:43:50 PM UTC 24 |
Oct 03 03:44:57 PM UTC 24 |
4397735394 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.1893129418 |
|
|
Oct 03 03:44:51 PM UTC 24 |
Oct 03 03:45:04 PM UTC 24 |
54065885 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.1109999093 |
|
|
Oct 03 03:44:25 PM UTC 24 |
Oct 03 03:45:08 PM UTC 24 |
693555638 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.162564864 |
|
|
Oct 03 03:44:58 PM UTC 24 |
Oct 03 03:45:09 PM UTC 24 |
47223807 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.337662105 |
|
|
Oct 03 03:44:19 PM UTC 24 |
Oct 03 03:45:09 PM UTC 24 |
2962359659 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.2246701049 |
|
|
Oct 03 03:44:12 PM UTC 24 |
Oct 03 03:45:21 PM UTC 24 |
642477095 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4154254864 |
|
|
Oct 03 03:44:33 PM UTC 24 |
Oct 03 03:45:22 PM UTC 24 |
1110766081 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.2268095538 |
|
|
Oct 03 03:45:08 PM UTC 24 |
Oct 03 03:45:31 PM UTC 24 |
213324849 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3726159717 |
|
|
Oct 03 03:45:35 PM UTC 24 |
Oct 03 03:45:46 PM UTC 24 |
70689052 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.578246173 |
|
|
Oct 03 03:40:47 PM UTC 24 |
Oct 03 03:45:46 PM UTC 24 |
8475030106 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.2943021346 |
|
|
Oct 03 03:36:57 PM UTC 24 |
Oct 03 03:46:02 PM UTC 24 |
46124890435 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.2139839780 |
|
|
Oct 03 03:45:00 PM UTC 24 |
Oct 03 03:46:03 PM UTC 24 |
542218849 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2349486903 |
|
|
Oct 03 03:40:49 PM UTC 24 |
Oct 03 03:46:05 PM UTC 24 |
653578209 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.2065948156 |
|
|
Oct 03 03:44:24 PM UTC 24 |
Oct 03 03:46:06 PM UTC 24 |
2279824300 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2905233350 |
|
|
Oct 03 03:45:01 PM UTC 24 |
Oct 03 03:46:08 PM UTC 24 |
3754954357 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.1028012768 |
|
|
Oct 03 03:45:01 PM UTC 24 |
Oct 03 03:46:15 PM UTC 24 |
7691050041 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3182708456 |
|
|
Oct 03 03:45:39 PM UTC 24 |
Oct 03 03:46:15 PM UTC 24 |
239808986 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.3471145602 |
|
|
Oct 03 03:43:50 PM UTC 24 |
Oct 03 03:46:17 PM UTC 24 |
8482677162 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.2315416295 |
|
|
Oct 03 03:45:24 PM UTC 24 |
Oct 03 03:46:18 PM UTC 24 |
507746642 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2309611109 |
|
|
Oct 03 03:46:14 PM UTC 24 |
Oct 03 03:46:23 PM UTC 24 |
35681359 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1057570265 |
|
|
Oct 03 03:43:19 PM UTC 24 |
Oct 03 03:46:28 PM UTC 24 |
837567283 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3529333835 |
|
|
Oct 03 03:45:34 PM UTC 24 |
Oct 03 03:46:29 PM UTC 24 |
409228412 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2858864506 |
|
|
Oct 03 03:46:13 PM UTC 24 |
Oct 03 03:46:36 PM UTC 24 |
107608100 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1199887738 |
|
|
Oct 03 03:46:28 PM UTC 24 |
Oct 03 03:46:38 PM UTC 24 |
42362799 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.4171668398 |
|
|
Oct 03 03:46:30 PM UTC 24 |
Oct 03 03:46:57 PM UTC 24 |
719660794 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.2870545418 |
|
|
Oct 03 03:44:32 PM UTC 24 |
Oct 03 03:46:59 PM UTC 24 |
3099700066 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.2463248925 |
|
|
Oct 03 03:46:46 PM UTC 24 |
Oct 03 03:47:02 PM UTC 24 |
84801751 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.2754132852 |
|
|
Oct 03 03:45:33 PM UTC 24 |
Oct 03 03:47:03 PM UTC 24 |
2472130796 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2538660405 |
|
|
Oct 03 03:46:37 PM UTC 24 |
Oct 03 03:47:10 PM UTC 24 |
217787427 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.2529967452 |
|
|
Oct 03 03:35:50 PM UTC 24 |
Oct 03 03:47:11 PM UTC 24 |
41480315872 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.4111520746 |
|
|
Oct 03 03:42:16 PM UTC 24 |
Oct 03 03:47:12 PM UTC 24 |
6354660908 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2183555433 |
|
|
Oct 03 03:14:48 PM UTC 24 |
Oct 03 03:47:18 PM UTC 24 |
106604132506 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.207203745 |
|
|
Oct 03 03:46:41 PM UTC 24 |
Oct 03 03:47:19 PM UTC 24 |
584474300 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3950977491 |
|
|
Oct 03 03:47:00 PM UTC 24 |
Oct 03 03:47:26 PM UTC 24 |
177886116 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.2087281290 |
|
|
Oct 03 03:47:29 PM UTC 24 |
Oct 03 03:47:36 PM UTC 24 |
50199033 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3645601162 |
|
|
Oct 03 03:16:13 PM UTC 24 |
Oct 03 03:47:42 PM UTC 24 |
111285252674 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.4065982876 |
|
|
Oct 03 03:46:44 PM UTC 24 |
Oct 03 03:47:43 PM UTC 24 |
2874026765 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.667501844 |
|
|
Oct 03 03:47:36 PM UTC 24 |
Oct 03 03:47:46 PM UTC 24 |
53616480 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.2110862137 |
|
|
Oct 03 03:46:29 PM UTC 24 |
Oct 03 03:47:49 PM UTC 24 |
6827424150 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.1218246301 |
|
|
Oct 03 03:47:05 PM UTC 24 |
Oct 03 03:47:52 PM UTC 24 |
1292758628 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1255727669 |
|
|
Oct 03 03:40:53 PM UTC 24 |
Oct 03 03:48:07 PM UTC 24 |
3773996077 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.1198236976 |
|
|
Oct 03 03:43:14 PM UTC 24 |
Oct 03 03:48:11 PM UTC 24 |
3191510636 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.158555722 |
|
|
Oct 03 03:46:31 PM UTC 24 |
Oct 03 03:48:20 PM UTC 24 |
4912855165 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.300712854 |
|
|
Oct 03 03:35:03 PM UTC 24 |
Oct 03 03:48:23 PM UTC 24 |
5176153655 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.4056665924 |
|
|
Oct 03 03:48:14 PM UTC 24 |
Oct 03 03:48:35 PM UTC 24 |
156809020 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.307936824 |
|
|
Oct 03 03:46:56 PM UTC 24 |
Oct 03 03:48:36 PM UTC 24 |
2487172562 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.1879500950 |
|
|
Oct 03 03:48:21 PM UTC 24 |
Oct 03 03:48:48 PM UTC 24 |
339562287 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2111303085 |
|
|
Oct 03 03:43:13 PM UTC 24 |
Oct 03 03:48:50 PM UTC 24 |
3137639343 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.3474204066 |
|
|
Oct 03 03:47:43 PM UTC 24 |
Oct 03 03:48:52 PM UTC 24 |
2026569709 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.303645156 |
|
|
Oct 03 03:47:45 PM UTC 24 |
Oct 03 03:48:58 PM UTC 24 |
611895936 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.4238746758 |
|
|
Oct 03 03:48:20 PM UTC 24 |
Oct 03 03:49:08 PM UTC 24 |
705448495 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.4183930940 |
|
|
Oct 03 03:49:04 PM UTC 24 |
Oct 03 03:49:14 PM UTC 24 |
110023533 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.3502807565 |
|
|
Oct 03 03:33:03 PM UTC 24 |
Oct 03 03:49:16 PM UTC 24 |
65679621685 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.234860551 |
|
|
Oct 03 03:49:04 PM UTC 24 |
Oct 03 03:49:16 PM UTC 24 |
57960216 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.1099693634 |
|
|
Oct 03 03:39:17 PM UTC 24 |
Oct 03 03:49:17 PM UTC 24 |
30027355727 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3334182015 |
|
|
Oct 03 03:48:12 PM UTC 24 |
Oct 03 03:49:21 PM UTC 24 |
563134205 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2860707429 |
|
|
Oct 03 03:45:48 PM UTC 24 |
Oct 03 03:49:22 PM UTC 24 |
1543511136 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.1777624755 |
|
|
Oct 03 03:44:14 PM UTC 24 |
Oct 03 03:49:24 PM UTC 24 |
22285472030 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3138819306 |
|
|
Oct 03 03:42:13 PM UTC 24 |
Oct 03 03:49:27 PM UTC 24 |
2128566130 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.2271980517 |
|
|
Oct 03 03:29:03 PM UTC 24 |
Oct 03 03:49:28 PM UTC 24 |
113660527203 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1928840101 |
|
|
Oct 03 03:42:13 PM UTC 24 |
Oct 03 03:49:28 PM UTC 24 |
11289164069 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3895228669 |
|
|
Oct 03 03:37:04 PM UTC 24 |
Oct 03 03:49:28 PM UTC 24 |
39484045574 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2143904223 |
|
|
Oct 03 03:47:39 PM UTC 24 |
Oct 03 03:49:31 PM UTC 24 |
7701273603 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3467517706 |
|
|
Oct 03 03:48:15 PM UTC 24 |
Oct 03 03:49:38 PM UTC 24 |
2702150255 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.553931534 |
|
|
Oct 03 03:49:17 PM UTC 24 |
Oct 03 03:49:43 PM UTC 24 |
192172396 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.900255680 |
|
|
Oct 03 03:39:30 PM UTC 24 |
Oct 03 03:49:44 PM UTC 24 |
2173095032 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.414221551 |
|
|
Oct 03 03:47:22 PM UTC 24 |
Oct 03 03:49:44 PM UTC 24 |
169132069 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1576635380 |
|
|
Oct 03 03:47:40 PM UTC 24 |
Oct 03 03:49:54 PM UTC 24 |
5319800216 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.3390615195 |
|
|
Oct 03 03:49:46 PM UTC 24 |
Oct 03 03:49:56 PM UTC 24 |
131561259 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1418093161 |
|
|
Oct 03 03:49:24 PM UTC 24 |
Oct 03 03:49:57 PM UTC 24 |
300103840 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.1796067328 |
|
|
Oct 03 03:49:42 PM UTC 24 |
Oct 03 03:50:01 PM UTC 24 |
318325144 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.326680738 |
|
|
Oct 03 03:45:10 PM UTC 24 |
Oct 03 03:50:07 PM UTC 24 |
28617666986 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.2434555782 |
|
|
Oct 03 03:49:56 PM UTC 24 |
Oct 03 03:50:09 PM UTC 24 |
242270190 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.905275863 |
|
|
Oct 03 03:49:59 PM UTC 24 |
Oct 03 03:50:09 PM UTC 24 |
39007730 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2796985069 |
|
|
Oct 03 03:49:43 PM UTC 24 |
Oct 03 03:50:13 PM UTC 24 |
342832689 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.3920238869 |
|
|
Oct 03 03:47:26 PM UTC 24 |
Oct 03 03:50:16 PM UTC 24 |
2169735950 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.947222163 |
|
|
Oct 03 03:50:10 PM UTC 24 |
Oct 03 03:50:24 PM UTC 24 |
169253427 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.507042960 |
|
|
Oct 03 03:49:49 PM UTC 24 |
Oct 03 03:50:25 PM UTC 24 |
892414089 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.4127700944 |
|
|
Oct 03 03:49:48 PM UTC 24 |
Oct 03 03:50:31 PM UTC 24 |
1156373825 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.548932838 |
|
|
Oct 03 03:49:17 PM UTC 24 |
Oct 03 03:50:42 PM UTC 24 |
4130739836 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.94005470 |
|
|
Oct 03 03:44:38 PM UTC 24 |
Oct 03 03:50:48 PM UTC 24 |
10290181124 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.2302364459 |
|
|
Oct 03 03:50:33 PM UTC 24 |
Oct 03 03:50:50 PM UTC 24 |
170183836 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1288006219 |
|
|
Oct 03 03:45:50 PM UTC 24 |
Oct 03 03:50:57 PM UTC 24 |
2529815093 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.1587557432 |
|
|
Oct 03 03:49:16 PM UTC 24 |
Oct 03 03:50:57 PM UTC 24 |
8137708556 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3469679653 |
|
|
Oct 03 03:44:48 PM UTC 24 |
Oct 03 03:50:57 PM UTC 24 |
5626556290 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.3059912355 |
|
|
Oct 03 03:50:39 PM UTC 24 |
Oct 03 03:51:05 PM UTC 24 |
223270728 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2280417544 |
|
|
Oct 03 03:50:44 PM UTC 24 |
Oct 03 03:51:05 PM UTC 24 |
234585611 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1137576827 |
|
|
Oct 03 03:49:52 PM UTC 24 |
Oct 03 03:51:19 PM UTC 24 |
887591621 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.1764238739 |
|
|
Oct 03 03:45:59 PM UTC 24 |
Oct 03 03:51:20 PM UTC 24 |
3410154833 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.2841598303 |
|
|
Oct 03 03:50:18 PM UTC 24 |
Oct 03 03:51:21 PM UTC 24 |
502350401 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2102694313 |
|
|
Oct 03 03:51:15 PM UTC 24 |
Oct 03 03:51:27 PM UTC 24 |
208551183 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3576171635 |
|
|
Oct 03 03:51:17 PM UTC 24 |
Oct 03 03:51:27 PM UTC 24 |
49290815 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.4229237534 |
|
|
Oct 03 03:50:07 PM UTC 24 |
Oct 03 03:51:30 PM UTC 24 |
4242557283 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.2672817686 |
|
|
Oct 03 03:44:10 PM UTC 24 |
Oct 03 03:51:33 PM UTC 24 |
47580275721 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.3228577909 |
|
|
Oct 03 03:50:30 PM UTC 24 |
Oct 03 03:51:42 PM UTC 24 |
930511270 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1505256651 |
|
|
Oct 03 03:51:33 PM UTC 24 |
Oct 03 03:51:44 PM UTC 24 |
65500757 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2229606186 |
|
|
Oct 03 03:51:08 PM UTC 24 |
Oct 03 03:52:03 PM UTC 24 |
214790506 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.967309491 |
|
|
Oct 03 03:50:09 PM UTC 24 |
Oct 03 03:52:04 PM UTC 24 |
7273916914 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3085064703 |
|
|
Oct 03 03:50:35 PM UTC 24 |
Oct 03 03:52:09 PM UTC 24 |
2589567067 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3565655876 |
|
|
Oct 03 03:51:24 PM UTC 24 |
Oct 03 03:52:14 PM UTC 24 |
1235281223 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.414375642 |
|
|
Oct 03 03:48:49 PM UTC 24 |
Oct 03 03:52:17 PM UTC 24 |
2141157090 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.2518233585 |
|
|
Oct 03 03:51:56 PM UTC 24 |
Oct 03 03:52:39 PM UTC 24 |
354015997 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.2693855072 |
|
|
Oct 03 03:51:53 PM UTC 24 |
Oct 03 03:52:41 PM UTC 24 |
1055206194 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2029179253 |
|
|
Oct 03 03:52:03 PM UTC 24 |
Oct 03 03:52:45 PM UTC 24 |
283814749 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1925434539 |
|
|
Oct 03 03:51:24 PM UTC 24 |
Oct 03 03:52:51 PM UTC 24 |
4672686341 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.1872531769 |
|
|
Oct 03 03:52:40 PM UTC 24 |
Oct 03 03:52:56 PM UTC 24 |
193858127 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3056604827 |
|
|
Oct 03 03:52:44 PM UTC 24 |
Oct 03 03:52:57 PM UTC 24 |
54030021 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3931466346 |
|
|
Oct 03 03:51:45 PM UTC 24 |
Oct 03 03:52:57 PM UTC 24 |
1724910400 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.1929157509 |
|
|
Oct 03 03:49:33 PM UTC 24 |
Oct 03 03:52:58 PM UTC 24 |
19191704901 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3846235956 |
|
|
Oct 03 03:51:55 PM UTC 24 |
Oct 03 03:53:02 PM UTC 24 |
977270289 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.1897320820 |
|
|
Oct 03 03:49:40 PM UTC 24 |
Oct 03 03:53:14 PM UTC 24 |
9759517439 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.647005149 |
|
|
Oct 03 03:36:16 PM UTC 24 |
Oct 03 03:53:19 PM UTC 24 |
7358832092 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.4054707009 |
|
|
Oct 03 03:48:38 PM UTC 24 |
Oct 03 03:53:21 PM UTC 24 |
485415252 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.2551278661 |
|
|
Oct 03 03:51:18 PM UTC 24 |
Oct 03 03:53:30 PM UTC 24 |
11017491087 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.1480450638 |
|
|
Oct 03 03:34:26 PM UTC 24 |
Oct 03 03:53:36 PM UTC 24 |
92366611663 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.143759556 |
|
|
Oct 03 03:53:10 PM UTC 24 |
Oct 03 03:53:39 PM UTC 24 |
347640230 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.571876512 |
|
|
Oct 03 03:46:38 PM UTC 24 |
Oct 03 03:53:49 PM UTC 24 |
25026251656 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.1623073959 |
|
|
Oct 03 03:53:13 PM UTC 24 |
Oct 03 03:53:53 PM UTC 24 |
385245496 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.3695357949 |
|
|
Oct 03 03:52:45 PM UTC 24 |
Oct 03 03:54:03 PM UTC 24 |
7507062954 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1703040620 |
|
|
Oct 03 03:53:40 PM UTC 24 |
Oct 03 03:54:03 PM UTC 24 |
506747505 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1674306046 |
|
|
Oct 03 03:49:53 PM UTC 24 |
Oct 03 03:54:04 PM UTC 24 |
6783326212 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1383397542 |
|
|
Oct 03 03:50:54 PM UTC 24 |
Oct 03 03:54:16 PM UTC 24 |
525408085 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.73135835 |
|
|
Oct 03 03:54:13 PM UTC 24 |
Oct 03 03:54:23 PM UTC 24 |
36801556 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3145824356 |
|
|
Oct 03 03:35:53 PM UTC 24 |
Oct 03 03:54:24 PM UTC 24 |
69789883486 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1362122161 |
|
|
Oct 03 03:54:17 PM UTC 24 |
Oct 03 03:54:26 PM UTC 24 |
36424136 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.4076350749 |
|
|
Oct 03 03:53:26 PM UTC 24 |
Oct 03 03:54:29 PM UTC 24 |
1266183189 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.690109670 |
|
|
Oct 03 03:53:44 PM UTC 24 |
Oct 03 03:54:31 PM UTC 24 |
843750254 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.2095585055 |
|
|
Oct 03 03:52:32 PM UTC 24 |
Oct 03 03:54:32 PM UTC 24 |
3055770102 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3020347976 |
|
|
Oct 03 03:41:35 PM UTC 24 |
Oct 03 03:54:33 PM UTC 24 |
79990763154 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.350519986 |
|
|
Oct 03 03:54:28 PM UTC 24 |
Oct 03 03:54:43 PM UTC 24 |
125721464 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.588947267 |
|
|
Oct 03 03:53:30 PM UTC 24 |
Oct 03 03:54:46 PM UTC 24 |
1415547696 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.941338604 |
|
|
Oct 03 03:51:47 PM UTC 24 |
Oct 03 03:54:50 PM UTC 24 |
10243271494 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1035144430 |
|
|
Oct 03 03:49:54 PM UTC 24 |
Oct 03 03:54:52 PM UTC 24 |
905877830 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.799632411 |
|
|
Oct 03 03:52:06 PM UTC 24 |
Oct 03 03:54:56 PM UTC 24 |
1990035834 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.354206130 |
|
|
Oct 03 03:54:43 PM UTC 24 |
Oct 03 03:54:57 PM UTC 24 |
84321335 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1765909491 |
|
|
Oct 03 03:48:48 PM UTC 24 |
Oct 03 03:55:02 PM UTC 24 |
4369811985 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3272427779 |
|
|
Oct 03 03:47:30 PM UTC 24 |
Oct 03 03:55:04 PM UTC 24 |
6100542270 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.349511884 |
|
|
Oct 03 03:51:01 PM UTC 24 |
Oct 03 03:55:08 PM UTC 24 |
3167861085 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.3129742489 |
|
|
Oct 03 03:50:22 PM UTC 24 |
Oct 03 03:55:10 PM UTC 24 |
23214175474 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.2760242434 |
|
|
Oct 03 03:39:13 PM UTC 24 |
Oct 03 03:55:13 PM UTC 24 |
93413725442 ps |