| T1362 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2570153579 |
|
|
Oct 03 10:13:34 PM UTC 24 |
Oct 03 11:57:09 PM UTC 24 |
26891735798 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.1579446671 |
|
|
Oct 03 08:10:57 PM UTC 24 |
Oct 04 12:06:00 AM UTC 24 |
67289613726 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3263363436 |
|
|
Oct 03 07:52:19 PM UTC 24 |
Oct 04 12:14:40 AM UTC 24 |
85709844569 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2248761770 |
|
|
Oct 03 08:53:28 PM UTC 24 |
Oct 04 12:27:34 AM UTC 24 |
255736511744 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3685767232 |
|
|
Oct 03 08:10:56 PM UTC 24 |
Oct 04 12:34:21 AM UTC 24 |
81850787600 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2102255538 |
|
|
Oct 03 01:10:44 PM UTC 24 |
Oct 03 01:10:55 PM UTC 24 |
44916099 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2626323814 |
|
|
Oct 03 01:10:44 PM UTC 24 |
Oct 03 01:10:55 PM UTC 24 |
46423412 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.4264217654 |
|
|
Oct 03 01:11:21 PM UTC 24 |
Oct 03 01:11:33 PM UTC 24 |
66705018 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.382495979 |
|
|
Oct 03 01:11:07 PM UTC 24 |
Oct 03 01:11:39 PM UTC 24 |
430463878 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1511102515 |
|
|
Oct 03 01:11:15 PM UTC 24 |
Oct 03 01:11:45 PM UTC 24 |
197256484 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.126729371 |
|
|
Oct 03 01:11:58 PM UTC 24 |
Oct 03 01:12:09 PM UTC 24 |
31009340 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3995463036 |
|
|
Oct 03 01:12:00 PM UTC 24 |
Oct 03 01:12:16 PM UTC 24 |
103985976 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.595604705 |
|
|
Oct 03 01:12:02 PM UTC 24 |
Oct 03 01:12:19 PM UTC 24 |
73332367 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3576587564 |
|
|
Oct 03 01:10:47 PM UTC 24 |
Oct 03 01:12:29 PM UTC 24 |
8019102349 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.84004255 |
|
|
Oct 03 01:10:45 PM UTC 24 |
Oct 03 01:12:38 PM UTC 24 |
3401113600 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2189887450 |
|
|
Oct 03 01:10:46 PM UTC 24 |
Oct 03 01:12:38 PM UTC 24 |
4568914249 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2037084943 |
|
|
Oct 03 01:12:08 PM UTC 24 |
Oct 03 01:12:41 PM UTC 24 |
736802044 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.4182618071 |
|
|
Oct 03 01:15:19 PM UTC 24 |
Oct 03 01:15:33 PM UTC 24 |
189960913 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1939247171 |
|
|
Oct 03 01:12:37 PM UTC 24 |
Oct 03 01:15:58 PM UTC 24 |
6248283777 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2087069806 |
|
|
Oct 03 01:15:58 PM UTC 24 |
Oct 03 01:16:09 PM UTC 24 |
49736878 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2004179875 |
|
|
Oct 03 01:16:23 PM UTC 24 |
Oct 03 01:16:59 PM UTC 24 |
582602096 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3025447167 |
|
|
Oct 03 01:13:12 PM UTC 24 |
Oct 03 01:17:15 PM UTC 24 |
3217982454 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2639863372 |
|
|
Oct 03 01:16:34 PM UTC 24 |
Oct 03 01:17:31 PM UTC 24 |
467024764 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2160338104 |
|
|
Oct 03 01:10:46 PM UTC 24 |
Oct 03 01:17:39 PM UTC 24 |
8335525236 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1580066015 |
|
|
Oct 03 01:17:23 PM UTC 24 |
Oct 03 01:17:52 PM UTC 24 |
659135205 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.4038183154 |
|
|
Oct 03 01:12:18 PM UTC 24 |
Oct 03 01:17:52 PM UTC 24 |
5583444733 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.494128460 |
|
|
Oct 03 01:16:03 PM UTC 24 |
Oct 03 01:17:55 PM UTC 24 |
10695069434 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3655622958 |
|
|
Oct 03 01:17:56 PM UTC 24 |
Oct 03 01:18:07 PM UTC 24 |
70705232 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1277996316 |
|
|
Oct 03 01:16:23 PM UTC 24 |
Oct 03 01:18:21 PM UTC 24 |
6054934997 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.661772141 |
|
|
Oct 03 01:16:55 PM UTC 24 |
Oct 03 01:18:43 PM UTC 24 |
1642197353 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3951712292 |
|
|
Oct 03 01:12:34 PM UTC 24 |
Oct 03 01:18:45 PM UTC 24 |
447469903 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3501564221 |
|
|
Oct 03 01:18:02 PM UTC 24 |
Oct 03 01:18:50 PM UTC 24 |
998104805 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.4028513091 |
|
|
Oct 03 01:17:19 PM UTC 24 |
Oct 03 01:18:53 PM UTC 24 |
2332941827 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1831763087 |
|
|
Oct 03 01:17:39 PM UTC 24 |
Oct 03 01:18:54 PM UTC 24 |
1419367245 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.1919740142 |
|
|
Oct 03 01:19:14 PM UTC 24 |
Oct 03 01:19:27 PM UTC 24 |
203136246 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.141569662 |
|
|
Oct 03 01:19:17 PM UTC 24 |
Oct 03 01:19:27 PM UTC 24 |
39843466 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.2109145883 |
|
|
Oct 03 01:18:12 PM UTC 24 |
Oct 03 01:19:29 PM UTC 24 |
588092156 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.772511088 |
|
|
Oct 03 01:12:43 PM UTC 24 |
Oct 03 01:19:31 PM UTC 24 |
7372657494 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2669835524 |
|
|
Oct 03 01:19:56 PM UTC 24 |
Oct 03 01:20:18 PM UTC 24 |
240633958 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.1034925316 |
|
|
Oct 03 01:19:21 PM UTC 24 |
Oct 03 01:20:28 PM UTC 24 |
7068008112 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1944315568 |
|
|
Oct 03 01:19:28 PM UTC 24 |
Oct 03 01:20:47 PM UTC 24 |
4367153354 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2255973114 |
|
|
Oct 03 01:19:52 PM UTC 24 |
Oct 03 01:20:51 PM UTC 24 |
463804598 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.775016656 |
|
|
Oct 03 01:17:17 PM UTC 24 |
Oct 03 01:20:52 PM UTC 24 |
13770348418 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.964331521 |
|
|
Oct 03 01:20:45 PM UTC 24 |
Oct 03 01:21:01 PM UTC 24 |
152583440 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1544458945 |
|
|
Oct 03 01:11:20 PM UTC 24 |
Oct 03 01:21:03 PM UTC 24 |
39341569338 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.2580974529 |
|
|
Oct 03 01:19:54 PM UTC 24 |
Oct 03 01:21:11 PM UTC 24 |
537573205 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1715215190 |
|
|
Oct 03 01:21:11 PM UTC 24 |
Oct 03 01:21:27 PM UTC 24 |
70114547 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.1177474950 |
|
|
Oct 03 01:20:53 PM UTC 24 |
Oct 03 01:21:39 PM UTC 24 |
939281120 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.1442030635 |
|
|
Oct 03 01:21:10 PM UTC 24 |
Oct 03 01:21:47 PM UTC 24 |
264696542 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.62642930 |
|
|
Oct 03 01:18:15 PM UTC 24 |
Oct 03 01:22:10 PM UTC 24 |
372914539 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3798250943 |
|
|
Oct 03 01:21:25 PM UTC 24 |
Oct 03 01:22:30 PM UTC 24 |
589489497 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1459340928 |
|
|
Oct 03 01:19:02 PM UTC 24 |
Oct 03 01:22:31 PM UTC 24 |
3264239752 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1287625192 |
|
|
Oct 03 01:21:24 PM UTC 24 |
Oct 03 01:22:38 PM UTC 24 |
181737725 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.831709782 |
|
|
Oct 03 01:22:34 PM UTC 24 |
Oct 03 01:22:51 PM UTC 24 |
200518332 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.2926140004 |
|
|
Oct 03 01:18:16 PM UTC 24 |
Oct 03 01:22:54 PM UTC 24 |
4346762316 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1680957467 |
|
|
Oct 03 01:22:55 PM UTC 24 |
Oct 03 01:23:07 PM UTC 24 |
51181010 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3930160103 |
|
|
Oct 03 01:23:14 PM UTC 24 |
Oct 03 01:23:26 PM UTC 24 |
65971202 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.283565714 |
|
|
Oct 03 01:11:18 PM UTC 24 |
Oct 03 01:24:00 PM UTC 24 |
65727235000 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.872136753 |
|
|
Oct 03 01:23:04 PM UTC 24 |
Oct 03 01:24:24 PM UTC 24 |
1654729654 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3695567838 |
|
|
Oct 03 01:22:56 PM UTC 24 |
Oct 03 01:24:37 PM UTC 24 |
9974105552 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3963363720 |
|
|
Oct 03 01:19:10 PM UTC 24 |
Oct 03 01:24:43 PM UTC 24 |
6365853982 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.488495805 |
|
|
Oct 03 01:14:09 PM UTC 24 |
Oct 03 01:24:46 PM UTC 24 |
12415025128 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.1476693841 |
|
|
Oct 03 01:24:31 PM UTC 24 |
Oct 03 01:24:47 PM UTC 24 |
94125138 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2265999631 |
|
|
Oct 03 01:22:58 PM UTC 24 |
Oct 03 01:24:47 PM UTC 24 |
5514240992 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.498969975 |
|
|
Oct 03 01:21:18 PM UTC 24 |
Oct 03 01:24:51 PM UTC 24 |
554831692 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3005643287 |
|
|
Oct 03 01:10:43 PM UTC 24 |
Oct 03 01:24:51 PM UTC 24 |
16136544931 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.217425852 |
|
|
Oct 03 01:24:26 PM UTC 24 |
Oct 03 01:25:13 PM UTC 24 |
378742395 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1999295363 |
|
|
Oct 03 01:25:02 PM UTC 24 |
Oct 03 01:25:14 PM UTC 24 |
220397388 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3081850137 |
|
|
Oct 03 01:12:52 PM UTC 24 |
Oct 03 01:25:20 PM UTC 24 |
5708506696 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3624209352 |
|
|
Oct 03 01:24:48 PM UTC 24 |
Oct 03 01:25:25 PM UTC 24 |
221881013 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2279730483 |
|
|
Oct 03 01:13:14 PM UTC 24 |
Oct 03 01:25:50 PM UTC 24 |
8853028640 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3918454960 |
|
|
Oct 03 01:25:45 PM UTC 24 |
Oct 03 01:25:54 PM UTC 24 |
45104166 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2866368380 |
|
|
Oct 03 01:25:39 PM UTC 24 |
Oct 03 01:25:55 PM UTC 24 |
247875574 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.3473970674 |
|
|
Oct 03 01:21:16 PM UTC 24 |
Oct 03 01:25:59 PM UTC 24 |
3152598978 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.1346535843 |
|
|
Oct 03 01:23:52 PM UTC 24 |
Oct 03 01:26:23 PM UTC 24 |
2422600394 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2656743511 |
|
|
Oct 03 01:10:43 PM UTC 24 |
Oct 03 01:26:53 PM UTC 24 |
7700926319 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.789762489 |
|
|
Oct 03 01:12:39 PM UTC 24 |
Oct 03 01:26:53 PM UTC 24 |
16852327572 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.4294597923 |
|
|
Oct 03 01:26:44 PM UTC 24 |
Oct 03 01:27:05 PM UTC 24 |
85671920 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.2244207712 |
|
|
Oct 03 01:26:19 PM UTC 24 |
Oct 03 01:27:09 PM UTC 24 |
417845508 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.170874681 |
|
|
Oct 03 01:22:33 PM UTC 24 |
Oct 03 01:27:17 PM UTC 24 |
2970753764 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1385321251 |
|
|
Oct 03 01:25:08 PM UTC 24 |
Oct 03 01:27:26 PM UTC 24 |
1640559519 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.3067777714 |
|
|
Oct 03 01:16:55 PM UTC 24 |
Oct 03 01:27:30 PM UTC 24 |
34640099768 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3569279650 |
|
|
Oct 03 01:27:20 PM UTC 24 |
Oct 03 01:27:43 PM UTC 24 |
294317931 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.2051541155 |
|
|
Oct 03 01:26:19 PM UTC 24 |
Oct 03 01:27:51 PM UTC 24 |
2459609327 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2469025499 |
|
|
Oct 03 01:27:27 PM UTC 24 |
Oct 03 01:27:52 PM UTC 24 |
205974855 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.160008438 |
|
|
Oct 03 01:18:09 PM UTC 24 |
Oct 03 01:27:55 PM UTC 24 |
10377383346 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1614155745 |
|
|
Oct 03 01:26:15 PM UTC 24 |
Oct 03 01:27:57 PM UTC 24 |
5380944481 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.4255641842 |
|
|
Oct 03 01:25:39 PM UTC 24 |
Oct 03 01:28:00 PM UTC 24 |
2601511620 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.709438089 |
|
|
Oct 03 01:25:51 PM UTC 24 |
Oct 03 01:28:13 PM UTC 24 |
8921429931 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2260613122 |
|
|
Oct 03 01:22:04 PM UTC 24 |
Oct 03 01:28:16 PM UTC 24 |
4089711304 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.2392500362 |
|
|
Oct 03 01:19:09 PM UTC 24 |
Oct 03 01:28:34 PM UTC 24 |
9292721696 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2320949474 |
|
|
Oct 03 01:28:21 PM UTC 24 |
Oct 03 01:28:34 PM UTC 24 |
206801728 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.486507996 |
|
|
Oct 03 01:28:23 PM UTC 24 |
Oct 03 01:28:35 PM UTC 24 |
46181086 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.2127220180 |
|
|
Oct 03 01:27:16 PM UTC 24 |
Oct 03 01:28:40 PM UTC 24 |
1647679057 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1154933511 |
|
|
Oct 03 01:27:06 PM UTC 24 |
Oct 03 01:28:44 PM UTC 24 |
2239137210 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1879058808 |
|
|
Oct 03 01:13:03 PM UTC 24 |
Oct 03 01:29:12 PM UTC 24 |
11532186795 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.2350624432 |
|
|
Oct 03 01:28:41 PM UTC 24 |
Oct 03 01:29:16 PM UTC 24 |
219824529 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3138382048 |
|
|
Oct 03 01:28:29 PM UTC 24 |
Oct 03 01:29:26 PM UTC 24 |
3219475049 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.2669534963 |
|
|
Oct 03 01:29:11 PM UTC 24 |
Oct 03 01:29:33 PM UTC 24 |
331135361 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3355152971 |
|
|
Oct 03 01:29:26 PM UTC 24 |
Oct 03 01:29:40 PM UTC 24 |
69237642 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3211175102 |
|
|
Oct 03 01:21:32 PM UTC 24 |
Oct 03 01:29:43 PM UTC 24 |
5995761102 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.2381083720 |
|
|
Oct 03 01:29:02 PM UTC 24 |
Oct 03 01:29:49 PM UTC 24 |
950655753 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2478141966 |
|
|
Oct 03 01:18:17 PM UTC 24 |
Oct 03 01:30:02 PM UTC 24 |
6180334494 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.3500917778 |
|
|
Oct 03 01:28:57 PM UTC 24 |
Oct 03 01:30:12 PM UTC 24 |
6190496205 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.1180667799 |
|
|
Oct 03 01:28:37 PM UTC 24 |
Oct 03 01:30:23 PM UTC 24 |
2231645145 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2324447757 |
|
|
Oct 03 01:29:41 PM UTC 24 |
Oct 03 01:30:26 PM UTC 24 |
840624301 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.695671836 |
|
|
Oct 03 01:28:26 PM UTC 24 |
Oct 03 01:30:35 PM UTC 24 |
7638523911 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3049700096 |
|
|
Oct 03 01:11:48 PM UTC 24 |
Oct 03 01:30:35 PM UTC 24 |
80144075527 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.3324874403 |
|
|
Oct 03 01:29:39 PM UTC 24 |
Oct 03 01:30:43 PM UTC 24 |
1183518384 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1944943443 |
|
|
Oct 03 01:30:50 PM UTC 24 |
Oct 03 01:31:01 PM UTC 24 |
51464839 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.131889989 |
|
|
Oct 03 01:25:07 PM UTC 24 |
Oct 03 01:31:02 PM UTC 24 |
5210716700 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2599522534 |
|
|
Oct 03 01:27:52 PM UTC 24 |
Oct 03 01:31:08 PM UTC 24 |
529390897 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1636283292 |
|
|
Oct 03 01:30:59 PM UTC 24 |
Oct 03 01:31:08 PM UTC 24 |
42516414 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.820689827 |
|
|
Oct 03 01:29:57 PM UTC 24 |
Oct 03 01:31:16 PM UTC 24 |
203413246 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2457094404 |
|
|
Oct 03 01:25:13 PM UTC 24 |
Oct 03 01:31:38 PM UTC 24 |
4887560300 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2016592025 |
|
|
Oct 03 01:24:03 PM UTC 24 |
Oct 03 01:31:45 PM UTC 24 |
28259424363 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.4019161961 |
|
|
Oct 03 01:31:36 PM UTC 24 |
Oct 03 01:31:59 PM UTC 24 |
264968863 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.438718914 |
|
|
Oct 03 01:28:17 PM UTC 24 |
Oct 03 01:32:01 PM UTC 24 |
3303436836 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2351334023 |
|
|
Oct 03 01:27:33 PM UTC 24 |
Oct 03 01:32:06 PM UTC 24 |
2576365207 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.1567119524 |
|
|
Oct 03 01:31:28 PM UTC 24 |
Oct 03 01:32:07 PM UTC 24 |
286422192 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.788926254 |
|
|
Oct 03 01:25:05 PM UTC 24 |
Oct 03 01:32:13 PM UTC 24 |
4178787854 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.999041834 |
|
|
Oct 03 01:30:02 PM UTC 24 |
Oct 03 01:32:13 PM UTC 24 |
1058033927 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3747591724 |
|
|
Oct 03 01:31:26 PM UTC 24 |
Oct 03 01:32:13 PM UTC 24 |
597859597 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1561057203 |
|
|
Oct 03 01:18:23 PM UTC 24 |
Oct 03 01:32:17 PM UTC 24 |
11425427936 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1962177514 |
|
|
Oct 03 01:31:09 PM UTC 24 |
Oct 03 01:32:19 PM UTC 24 |
4547084341 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.586028682 |
|
|
Oct 03 01:32:10 PM UTC 24 |
Oct 03 01:32:20 PM UTC 24 |
41470650 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.530493722 |
|
|
Oct 03 01:27:49 PM UTC 24 |
Oct 03 01:32:31 PM UTC 24 |
2736285176 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2926197769 |
|
|
Oct 03 01:32:25 PM UTC 24 |
Oct 03 01:32:49 PM UTC 24 |
427244131 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.1793038649 |
|
|
Oct 03 01:32:03 PM UTC 24 |
Oct 03 01:33:04 PM UTC 24 |
1385256189 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.271559316 |
|
|
Oct 03 01:21:51 PM UTC 24 |
Oct 03 01:33:08 PM UTC 24 |
5821306119 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.673664484 |
|
|
Oct 03 01:32:57 PM UTC 24 |
Oct 03 01:33:08 PM UTC 24 |
190647467 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.1134514370 |
|
|
Oct 03 01:31:02 PM UTC 24 |
Oct 03 01:33:14 PM UTC 24 |
9510495104 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3903440573 |
|
|
Oct 03 01:32:26 PM UTC 24 |
Oct 03 01:33:15 PM UTC 24 |
341554385 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3353482423 |
|
|
Oct 03 01:33:14 PM UTC 24 |
Oct 03 01:33:26 PM UTC 24 |
52063589 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.1825749183 |
|
|
Oct 03 01:30:49 PM UTC 24 |
Oct 03 01:33:27 PM UTC 24 |
2703116784 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.2286543277 |
|
|
Oct 03 01:29:51 PM UTC 24 |
Oct 03 01:33:33 PM UTC 24 |
4424581412 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.905596429 |
|
|
Oct 03 01:33:32 PM UTC 24 |
Oct 03 01:34:18 PM UTC 24 |
467789760 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.701906966 |
|
|
Oct 03 01:33:38 PM UTC 24 |
Oct 03 01:34:19 PM UTC 24 |
426246587 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2931139498 |
|
|
Oct 03 01:33:33 PM UTC 24 |
Oct 03 01:34:27 PM UTC 24 |
3340890005 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1970582742 |
|
|
Oct 03 01:16:32 PM UTC 24 |
Oct 03 01:34:36 PM UTC 24 |
93644368313 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.167844551 |
|
|
Oct 03 01:33:28 PM UTC 24 |
Oct 03 01:34:41 PM UTC 24 |
8037389392 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.693529258 |
|
|
Oct 03 01:33:52 PM UTC 24 |
Oct 03 01:34:42 PM UTC 24 |
450500588 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.574426241 |
|
|
Oct 03 01:27:49 PM UTC 24 |
Oct 03 01:34:55 PM UTC 24 |
6198732135 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.3642271575 |
|
|
Oct 03 01:34:44 PM UTC 24 |
Oct 03 01:35:24 PM UTC 24 |
471602759 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.271416690 |
|
|
Oct 03 01:34:58 PM UTC 24 |
Oct 03 01:35:25 PM UTC 24 |
170590917 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3213812565 |
|
|
Oct 03 01:21:55 PM UTC 24 |
Oct 03 01:35:37 PM UTC 24 |
11095277900 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1357297445 |
|
|
Oct 03 01:34:45 PM UTC 24 |
Oct 03 01:35:38 PM UTC 24 |
1197498829 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2297847864 |
|
|
Oct 03 01:25:10 PM UTC 24 |
Oct 03 01:35:38 PM UTC 24 |
8729273379 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3841042952 |
|
|
Oct 03 01:35:04 PM UTC 24 |
Oct 03 01:35:54 PM UTC 24 |
43041428 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3132200102 |
|
|
Oct 03 01:25:09 PM UTC 24 |
Oct 03 01:36:04 PM UTC 24 |
7315313300 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.552159743 |
|
|
Oct 03 01:30:07 PM UTC 24 |
Oct 03 01:36:08 PM UTC 24 |
766898311 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.2159088898 |
|
|
Oct 03 01:35:07 PM UTC 24 |
Oct 03 01:36:11 PM UTC 24 |
1720650291 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.1542834182 |
|
|
Oct 03 01:34:53 PM UTC 24 |
Oct 03 01:36:13 PM UTC 24 |
1267474381 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.3725567426 |
|
|
Oct 03 01:36:02 PM UTC 24 |
Oct 03 01:36:18 PM UTC 24 |
229821822 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3070132796 |
|
|
Oct 03 01:32:39 PM UTC 24 |
Oct 03 01:36:22 PM UTC 24 |
2393715634 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2376013455 |
|
|
Oct 03 01:36:18 PM UTC 24 |
Oct 03 01:36:29 PM UTC 24 |
42058977 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1102507554 |
|
|
Oct 03 01:18:21 PM UTC 24 |
Oct 03 01:36:43 PM UTC 24 |
9039902449 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.4180400676 |
|
|
Oct 03 01:26:19 PM UTC 24 |
Oct 03 01:36:52 PM UTC 24 |
59331710203 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3763372823 |
|
|
Oct 03 01:23:31 PM UTC 24 |
Oct 03 01:36:53 PM UTC 24 |
47603808817 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3635352727 |
|
|
Oct 03 01:23:19 PM UTC 24 |
Oct 03 01:37:04 PM UTC 24 |
80018083108 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.1320216856 |
|
|
Oct 03 01:36:37 PM UTC 24 |
Oct 03 01:37:07 PM UTC 24 |
166744727 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1761212832 |
|
|
Oct 03 01:32:44 PM UTC 24 |
Oct 03 01:37:08 PM UTC 24 |
3529580928 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.4119923070 |
|
|
Oct 03 01:36:54 PM UTC 24 |
Oct 03 01:37:25 PM UTC 24 |
240621959 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.2291199566 |
|
|
Oct 03 01:36:41 PM UTC 24 |
Oct 03 01:37:27 PM UTC 24 |
416799844 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.2750533051 |
|
|
Oct 03 01:36:26 PM UTC 24 |
Oct 03 01:37:31 PM UTC 24 |
5402006563 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1142396978 |
|
|
Oct 03 01:37:10 PM UTC 24 |
Oct 03 01:37:32 PM UTC 24 |
488875856 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1013041811 |
|
|
Oct 03 01:37:19 PM UTC 24 |
Oct 03 01:37:33 PM UTC 24 |
159764197 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.2650104461 |
|
|
Oct 03 01:32:37 PM UTC 24 |
Oct 03 01:37:41 PM UTC 24 |
4043404538 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.524460309 |
|
|
Oct 03 01:32:37 PM UTC 24 |
Oct 03 01:37:42 PM UTC 24 |
7991386405 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.4190719106 |
|
|
Oct 03 01:36:51 PM UTC 24 |
Oct 03 01:37:53 PM UTC 24 |
3805891211 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.3865056456 |
|
|
Oct 03 01:37:17 PM UTC 24 |
Oct 03 01:37:54 PM UTC 24 |
204698217 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.1052055256 |
|
|
Oct 03 01:19:56 PM UTC 24 |
Oct 03 01:37:54 PM UTC 24 |
60495891722 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1704447190 |
|
|
Oct 03 01:37:31 PM UTC 24 |
Oct 03 01:37:57 PM UTC 24 |
129676077 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.2133181673 |
|
|
Oct 03 01:33:37 PM UTC 24 |
Oct 03 01:37:58 PM UTC 24 |
19688429035 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.3292881899 |
|
|
Oct 03 01:38:02 PM UTC 24 |
Oct 03 01:38:11 PM UTC 24 |
47512076 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1485483030 |
|
|
Oct 03 01:38:12 PM UTC 24 |
Oct 03 01:38:24 PM UTC 24 |
45119560 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.62804348 |
|
|
Oct 03 01:27:41 PM UTC 24 |
Oct 03 01:38:33 PM UTC 24 |
3321199781 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2448766090 |
|
|
Oct 03 01:36:33 PM UTC 24 |
Oct 03 01:38:38 PM UTC 24 |
6316895799 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2631106618 |
|
|
Oct 03 01:20:42 PM UTC 24 |
Oct 03 01:38:43 PM UTC 24 |
57289471922 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.2322218649 |
|
|
Oct 03 01:32:29 PM UTC 24 |
Oct 03 01:38:51 PM UTC 24 |
8088534413 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2925474078 |
|
|
Oct 03 01:35:19 PM UTC 24 |
Oct 03 01:38:52 PM UTC 24 |
921559243 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.897296549 |
|
|
Oct 03 01:38:20 PM UTC 24 |
Oct 03 01:38:56 PM UTC 24 |
226917649 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1679173251 |
|
|
Oct 03 01:38:51 PM UTC 24 |
Oct 03 01:39:06 PM UTC 24 |
251433497 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.1917790798 |
|
|
Oct 03 01:37:33 PM UTC 24 |
Oct 03 01:39:11 PM UTC 24 |
866810083 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.3814854870 |
|
|
Oct 03 01:38:20 PM UTC 24 |
Oct 03 01:39:13 PM UTC 24 |
1175597207 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2046503336 |
|
|
Oct 03 01:39:11 PM UTC 24 |
Oct 03 01:39:23 PM UTC 24 |
62232646 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2633861160 |
|
|
Oct 03 01:29:01 PM UTC 24 |
Oct 03 01:39:24 PM UTC 24 |
30220880325 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3636587253 |
|
|
Oct 03 01:25:07 PM UTC 24 |
Oct 03 01:39:26 PM UTC 24 |
7464136757 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.2125326768 |
|
|
Oct 03 01:36:02 PM UTC 24 |
Oct 03 01:39:34 PM UTC 24 |
3854259409 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.2993015008 |
|
|
Oct 03 01:39:17 PM UTC 24 |
Oct 03 01:39:40 PM UTC 24 |
322307668 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.1511406657 |
|
|
Oct 03 01:35:01 PM UTC 24 |
Oct 03 01:39:53 PM UTC 24 |
2983945709 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.923989442 |
|
|
Oct 03 01:38:17 PM UTC 24 |
Oct 03 01:39:57 PM UTC 24 |
5185044002 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.256730194 |
|
|
Oct 03 01:26:23 PM UTC 24 |
Oct 03 01:39:58 PM UTC 24 |
43284066577 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2981583809 |
|
|
Oct 03 01:39:21 PM UTC 24 |
Oct 03 01:40:11 PM UTC 24 |
323597714 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.547101953 |
|
|
Oct 03 01:28:00 PM UTC 24 |
Oct 03 01:40:11 PM UTC 24 |
5680270802 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.652241624 |
|
|
Oct 03 01:30:14 PM UTC 24 |
Oct 03 01:40:18 PM UTC 24 |
6116147863 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.269612100 |
|
|
Oct 03 01:40:07 PM UTC 24 |
Oct 03 01:40:19 PM UTC 24 |
44664086 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.3485964184 |
|
|
Oct 03 01:38:20 PM UTC 24 |
Oct 03 01:40:24 PM UTC 24 |
7451729322 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1943282247 |
|
|
Oct 03 01:40:18 PM UTC 24 |
Oct 03 01:40:30 PM UTC 24 |
40540116 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.1821433668 |
|
|
Oct 03 01:38:06 PM UTC 24 |
Oct 03 01:40:38 PM UTC 24 |
2712970719 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.4016186268 |
|
|
Oct 03 01:39:06 PM UTC 24 |
Oct 03 01:40:57 PM UTC 24 |
2479084089 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.1102420217 |
|
|
Oct 03 01:19:55 PM UTC 24 |
Oct 03 01:40:57 PM UTC 24 |
106436544638 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.53167184 |
|
|
Oct 03 01:40:37 PM UTC 24 |
Oct 03 01:41:25 PM UTC 24 |
1042442112 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3579296099 |
|
|
Oct 03 01:40:40 PM UTC 24 |
Oct 03 01:41:40 PM UTC 24 |
573138285 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3618227390 |
|
|
Oct 03 01:41:06 PM UTC 24 |
Oct 03 01:41:47 PM UTC 24 |
502241283 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2804566467 |
|
|
Oct 03 01:32:42 PM UTC 24 |
Oct 03 01:41:53 PM UTC 24 |
6170812840 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1291821313 |
|
|
Oct 03 01:40:49 PM UTC 24 |
Oct 03 01:41:55 PM UTC 24 |
789916791 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.2963814735 |
|
|
Oct 03 01:40:25 PM UTC 24 |
Oct 03 01:41:56 PM UTC 24 |
8932807147 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1707113992 |
|
|
Oct 03 01:40:27 PM UTC 24 |
Oct 03 01:42:00 PM UTC 24 |
5627861175 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.484039151 |
|
|
Oct 03 01:35:48 PM UTC 24 |
Oct 03 01:42:05 PM UTC 24 |
4311774601 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2175428483 |
|
|
Oct 03 01:39:33 PM UTC 24 |
Oct 03 01:42:10 PM UTC 24 |
376198095 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4032583422 |
|
|
Oct 03 01:41:25 PM UTC 24 |
Oct 03 01:42:17 PM UTC 24 |
1131090501 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2955024996 |
|
|
Oct 03 01:37:50 PM UTC 24 |
Oct 03 01:42:27 PM UTC 24 |
3171367601 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2054036916 |
|
|
Oct 03 01:41:52 PM UTC 24 |
Oct 03 01:42:42 PM UTC 24 |
1018668151 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2899369860 |
|
|
Oct 03 01:41:25 PM UTC 24 |
Oct 03 01:42:47 PM UTC 24 |
1937016668 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.1061843942 |
|
|
Oct 03 01:42:44 PM UTC 24 |
Oct 03 01:42:59 PM UTC 24 |
137918713 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.951891014 |
|
|
Oct 03 01:42:54 PM UTC 24 |
Oct 03 01:43:02 PM UTC 24 |
41015844 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.60852488 |
|
|
Oct 03 01:42:21 PM UTC 24 |
Oct 03 01:43:13 PM UTC 24 |
96851911 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1408136083 |
|
|
Oct 03 01:43:26 PM UTC 24 |
Oct 03 01:43:57 PM UTC 24 |
416735894 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.1020722999 |
|
|
Oct 03 01:31:34 PM UTC 24 |
Oct 03 01:43:59 PM UTC 24 |
42288339729 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1041360213 |
|
|
Oct 03 01:37:55 PM UTC 24 |
Oct 03 01:44:05 PM UTC 24 |
4705754800 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3496763125 |
|
|
Oct 03 01:32:32 PM UTC 24 |
Oct 03 01:44:17 PM UTC 24 |
10047969840 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.612830038 |
|
|
Oct 03 01:40:01 PM UTC 24 |
Oct 03 01:44:23 PM UTC 24 |
3744734731 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.2928464347 |
|
|
Oct 03 01:28:09 PM UTC 24 |
Oct 03 01:44:23 PM UTC 24 |
11181329400 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.2556973721 |
|
|
Oct 03 01:43:31 PM UTC 24 |
Oct 03 01:44:36 PM UTC 24 |
543789278 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.4271625319 |
|
|
Oct 03 01:42:17 PM UTC 24 |
Oct 03 01:44:44 PM UTC 24 |
1670689637 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3701484249 |
|
|
Oct 03 01:43:14 PM UTC 24 |
Oct 03 01:44:53 PM UTC 24 |
5949356603 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2675255108 |
|
|
Oct 03 01:44:24 PM UTC 24 |
Oct 03 01:44:53 PM UTC 24 |
380849984 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4089375424 |
|
|
Oct 03 01:44:51 PM UTC 24 |
Oct 03 01:45:03 PM UTC 24 |
44893059 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.926427400 |
|
|
Oct 03 01:44:43 PM UTC 24 |
Oct 03 01:45:07 PM UTC 24 |
368191190 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3287356190 |
|
|
Oct 03 01:43:08 PM UTC 24 |
Oct 03 01:45:14 PM UTC 24 |
7730012615 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.3334935344 |
|
|
Oct 03 01:39:21 PM UTC 24 |
Oct 03 01:45:17 PM UTC 24 |
3260170990 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2548049844 |
|
|
Oct 03 01:36:58 PM UTC 24 |
Oct 03 01:45:24 PM UTC 24 |
28682619610 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1453203967 |
|
|
Oct 03 01:37:52 PM UTC 24 |
Oct 03 01:45:25 PM UTC 24 |
8586197198 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.225341266 |
|
|
Oct 03 01:26:50 PM UTC 24 |
Oct 03 01:45:25 PM UTC 24 |
79040795793 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.2761141651 |
|
|
Oct 03 01:44:32 PM UTC 24 |
Oct 03 01:45:46 PM UTC 24 |
2198673442 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.489459802 |
|
|
Oct 03 01:33:48 PM UTC 24 |
Oct 03 01:45:54 PM UTC 24 |
40817305183 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4204258396 |
|
|
Oct 03 01:45:49 PM UTC 24 |
Oct 03 01:45:59 PM UTC 24 |
42866485 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.408697412 |
|
|
Oct 03 01:44:50 PM UTC 24 |
Oct 03 01:46:01 PM UTC 24 |
1127233471 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1636007798 |
|
|
Oct 03 01:45:51 PM UTC 24 |
Oct 03 01:46:05 PM UTC 24 |
188773492 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.553406237 |
|
|
Oct 03 01:39:51 PM UTC 24 |
Oct 03 01:46:11 PM UTC 24 |
4705365196 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.2957188750 |
|
|
Oct 03 01:46:24 PM UTC 24 |
Oct 03 01:46:43 PM UTC 24 |
84690226 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.257800613 |
|
|
Oct 03 01:42:05 PM UTC 24 |
Oct 03 01:46:58 PM UTC 24 |
3376696009 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1657416825 |
|
|
Oct 03 01:43:34 PM UTC 24 |
Oct 03 01:46:59 PM UTC 24 |
12175285277 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3295882888 |
|
|
Oct 03 01:38:00 PM UTC 24 |
Oct 03 01:47:10 PM UTC 24 |
5679829152 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3595073292 |
|
|
Oct 03 01:39:41 PM UTC 24 |
Oct 03 01:47:17 PM UTC 24 |
2758478520 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.3738447229 |
|
|
Oct 03 01:42:36 PM UTC 24 |
Oct 03 01:47:32 PM UTC 24 |
3633192680 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.4230615239 |
|
|
Oct 03 01:40:48 PM UTC 24 |
Oct 03 01:47:34 PM UTC 24 |
22548957084 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.4161725808 |
|
|
Oct 03 01:46:36 PM UTC 24 |
Oct 03 01:47:37 PM UTC 24 |
477994974 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1243788675 |
|
|
Oct 03 01:39:37 PM UTC 24 |
Oct 03 01:47:48 PM UTC 24 |
10756358177 ps |