| T2020 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2618575833 |
|
|
Oct 03 03:00:54 PM UTC 24 |
Oct 03 03:01:49 PM UTC 24 |
1081245607 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2830125486 |
|
|
Oct 03 03:01:41 PM UTC 24 |
Oct 03 03:01:53 PM UTC 24 |
125138407 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.1990474539 |
|
|
Oct 03 03:00:03 PM UTC 24 |
Oct 03 03:01:56 PM UTC 24 |
8695163648 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.284929431 |
|
|
Oct 03 03:00:50 PM UTC 24 |
Oct 03 03:02:02 PM UTC 24 |
1630732471 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.931802396 |
|
|
Oct 03 01:45:40 PM UTC 24 |
Oct 03 03:02:05 PM UTC 24 |
29526506530 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2014947397 |
|
|
Oct 03 02:57:48 PM UTC 24 |
Oct 03 03:02:15 PM UTC 24 |
26800451374 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.4167147302 |
|
|
Oct 03 03:00:16 PM UTC 24 |
Oct 03 03:02:15 PM UTC 24 |
7262605850 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.3755704494 |
|
|
Oct 03 03:01:18 PM UTC 24 |
Oct 03 03:02:17 PM UTC 24 |
477611906 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1744235848 |
|
|
Oct 03 03:01:03 PM UTC 24 |
Oct 03 03:02:19 PM UTC 24 |
1566787809 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2405665762 |
|
|
Oct 03 03:02:24 PM UTC 24 |
Oct 03 03:02:34 PM UTC 24 |
60435126 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3333013735 |
|
|
Oct 03 03:02:16 PM UTC 24 |
Oct 03 03:02:35 PM UTC 24 |
334728289 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.4171920950 |
|
|
Oct 03 03:00:09 PM UTC 24 |
Oct 03 03:02:38 PM UTC 24 |
6036833066 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2299225665 |
|
|
Oct 03 03:02:20 PM UTC 24 |
Oct 03 03:02:39 PM UTC 24 |
228061684 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.4054731751 |
|
|
Oct 03 02:52:15 PM UTC 24 |
Oct 03 03:02:44 PM UTC 24 |
35593813681 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3328131716 |
|
|
Oct 03 02:28:07 PM UTC 24 |
Oct 03 03:02:46 PM UTC 24 |
121994555837 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.3142542147 |
|
|
Oct 03 02:51:09 PM UTC 24 |
Oct 03 03:02:49 PM UTC 24 |
18258466894 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.4292660918 |
|
|
Oct 03 03:02:17 PM UTC 24 |
Oct 03 03:02:49 PM UTC 24 |
328550800 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2110535287 |
|
|
Oct 03 03:02:42 PM UTC 24 |
Oct 03 03:02:49 PM UTC 24 |
6506471 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.1042408378 |
|
|
Oct 03 03:02:43 PM UTC 24 |
Oct 03 03:02:52 PM UTC 24 |
48540347 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3306541468 |
|
|
Oct 03 03:02:45 PM UTC 24 |
Oct 03 03:02:56 PM UTC 24 |
52830557 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4025280222 |
|
|
Oct 03 02:55:34 PM UTC 24 |
Oct 03 03:03:01 PM UTC 24 |
2853381480 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.3390603323 |
|
|
Oct 03 02:56:10 PM UTC 24 |
Oct 03 03:03:01 PM UTC 24 |
33700909187 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.480452884 |
|
|
Oct 03 03:02:01 PM UTC 24 |
Oct 03 03:03:03 PM UTC 24 |
568552467 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.4171280327 |
|
|
Oct 03 02:56:39 PM UTC 24 |
Oct 03 03:03:04 PM UTC 24 |
9927631187 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.836436542 |
|
|
Oct 03 02:58:08 PM UTC 24 |
Oct 03 03:03:17 PM UTC 24 |
8118562872 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.4125703280 |
|
|
Oct 03 03:01:35 PM UTC 24 |
Oct 03 03:03:19 PM UTC 24 |
8735423962 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.2736822935 |
|
|
Oct 03 03:01:36 PM UTC 24 |
Oct 03 03:03:21 PM UTC 24 |
5507060006 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2432083107 |
|
|
Oct 03 03:01:20 PM UTC 24 |
Oct 03 03:03:29 PM UTC 24 |
270980083 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.69848232 |
|
|
Oct 03 03:02:06 PM UTC 24 |
Oct 03 03:03:44 PM UTC 24 |
931670207 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.2227984641 |
|
|
Oct 03 03:03:23 PM UTC 24 |
Oct 03 03:03:45 PM UTC 24 |
498320501 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2550504082 |
|
|
Oct 03 02:41:12 PM UTC 24 |
Oct 03 03:03:49 PM UTC 24 |
77573284138 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.934273721 |
|
|
Oct 03 02:50:13 PM UTC 24 |
Oct 03 03:03:51 PM UTC 24 |
46569145684 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3068717269 |
|
|
Oct 03 03:03:25 PM UTC 24 |
Oct 03 03:03:54 PM UTC 24 |
206014604 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.4022705166 |
|
|
Oct 03 03:03:47 PM UTC 24 |
Oct 03 03:03:57 PM UTC 24 |
45541893 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.215744737 |
|
|
Oct 03 03:03:48 PM UTC 24 |
Oct 03 03:03:57 PM UTC 24 |
38505532 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.3375253393 |
|
|
Oct 03 03:03:14 PM UTC 24 |
Oct 03 03:03:59 PM UTC 24 |
464462673 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2358604121 |
|
|
Oct 03 02:53:47 PM UTC 24 |
Oct 03 03:04:09 PM UTC 24 |
4196648609 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.2422141669 |
|
|
Oct 03 02:56:17 PM UTC 24 |
Oct 03 03:04:13 PM UTC 24 |
30838985602 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.1503314207 |
|
|
Oct 03 03:03:06 PM UTC 24 |
Oct 03 03:04:18 PM UTC 24 |
587542618 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.3155072340 |
|
|
Oct 03 03:03:16 PM UTC 24 |
Oct 03 03:04:22 PM UTC 24 |
581618090 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4147664540 |
|
|
Oct 03 02:31:29 PM UTC 24 |
Oct 03 03:04:22 PM UTC 24 |
138623634133 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1997493271 |
|
|
Oct 03 02:46:20 PM UTC 24 |
Oct 03 03:04:25 PM UTC 24 |
100602501299 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3917946677 |
|
|
Oct 03 03:03:24 PM UTC 24 |
Oct 03 03:04:30 PM UTC 24 |
123795313 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1628304738 |
|
|
Oct 03 02:53:59 PM UTC 24 |
Oct 03 03:04:32 PM UTC 24 |
4585911545 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.566562480 |
|
|
Oct 03 03:02:28 PM UTC 24 |
Oct 03 03:04:33 PM UTC 24 |
1600358472 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2149097465 |
|
|
Oct 03 02:56:56 PM UTC 24 |
Oct 03 03:04:44 PM UTC 24 |
3399155860 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1295248773 |
|
|
Oct 03 03:03:01 PM UTC 24 |
Oct 03 03:04:53 PM UTC 24 |
6110060593 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.2621896586 |
|
|
Oct 03 03:04:13 PM UTC 24 |
Oct 03 03:04:56 PM UTC 24 |
253190781 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3773016427 |
|
|
Oct 03 02:58:23 PM UTC 24 |
Oct 03 03:04:58 PM UTC 24 |
630745372 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.1327353283 |
|
|
Oct 03 03:03:04 PM UTC 24 |
Oct 03 03:04:58 PM UTC 24 |
2386806239 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.1705027636 |
|
|
Oct 03 03:04:11 PM UTC 24 |
Oct 03 03:04:59 PM UTC 24 |
552307708 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3381259570 |
|
|
Oct 03 03:04:55 PM UTC 24 |
Oct 03 03:05:06 PM UTC 24 |
56147516 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.1764502624 |
|
|
Oct 03 03:04:36 PM UTC 24 |
Oct 03 03:05:07 PM UTC 24 |
193656445 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3568951031 |
|
|
Oct 03 03:04:42 PM UTC 24 |
Oct 03 03:05:07 PM UTC 24 |
161772343 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.3170878543 |
|
|
Oct 03 03:04:58 PM UTC 24 |
Oct 03 03:05:15 PM UTC 24 |
213100046 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.2144812118 |
|
|
Oct 03 03:03:01 PM UTC 24 |
Oct 03 03:05:19 PM UTC 24 |
9823300536 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3759585614 |
|
|
Oct 03 03:04:23 PM UTC 24 |
Oct 03 03:05:23 PM UTC 24 |
1584310126 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.3671360816 |
|
|
Oct 03 03:03:30 PM UTC 24 |
Oct 03 03:05:25 PM UTC 24 |
3063001415 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3219120120 |
|
|
Oct 03 03:03:13 PM UTC 24 |
Oct 03 03:05:26 PM UTC 24 |
2901224209 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.4009087707 |
|
|
Oct 03 02:59:37 PM UTC 24 |
Oct 03 03:05:33 PM UTC 24 |
7415506902 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.866953803 |
|
|
Oct 03 02:59:01 PM UTC 24 |
Oct 03 03:05:33 PM UTC 24 |
20791336304 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.980343983 |
|
|
Oct 03 03:02:40 PM UTC 24 |
Oct 03 03:05:41 PM UTC 24 |
625123187 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.111400824 |
|
|
Oct 03 03:04:13 PM UTC 24 |
Oct 03 03:05:45 PM UTC 24 |
5705511984 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.2514977046 |
|
|
Oct 03 03:05:52 PM UTC 24 |
Oct 03 03:06:02 PM UTC 24 |
61345375 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2582703669 |
|
|
Oct 03 03:03:55 PM UTC 24 |
Oct 03 03:06:04 PM UTC 24 |
8959141846 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.2531576741 |
|
|
Oct 03 03:05:27 PM UTC 24 |
Oct 03 03:06:05 PM UTC 24 |
345342300 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1552559259 |
|
|
Oct 03 03:04:23 PM UTC 24 |
Oct 03 03:06:08 PM UTC 24 |
1104104861 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.3878146841 |
|
|
Oct 03 03:04:31 PM UTC 24 |
Oct 03 03:06:09 PM UTC 24 |
2392890247 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.2454197875 |
|
|
Oct 03 03:05:42 PM UTC 24 |
Oct 03 03:06:17 PM UTC 24 |
664610477 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3339165855 |
|
|
Oct 03 03:05:19 PM UTC 24 |
Oct 03 03:06:19 PM UTC 24 |
4122641820 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2626539100 |
|
|
Oct 03 03:06:09 PM UTC 24 |
Oct 03 03:06:20 PM UTC 24 |
52382332 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2173134771 |
|
|
Oct 03 02:59:11 PM UTC 24 |
Oct 03 03:06:23 PM UTC 24 |
29057170174 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2322493155 |
|
|
Oct 03 03:06:14 PM UTC 24 |
Oct 03 03:06:24 PM UTC 24 |
54202860 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.1619849383 |
|
|
Oct 03 03:05:22 PM UTC 24 |
Oct 03 03:06:35 PM UTC 24 |
1556972029 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.4090991317 |
|
|
Oct 03 03:05:48 PM UTC 24 |
Oct 03 03:06:36 PM UTC 24 |
624015844 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.3034016148 |
|
|
Oct 03 02:53:31 PM UTC 24 |
Oct 03 03:06:46 PM UTC 24 |
49680049681 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.1949217121 |
|
|
Oct 03 03:05:34 PM UTC 24 |
Oct 03 03:06:58 PM UTC 24 |
2413145063 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.2295330432 |
|
|
Oct 03 03:06:47 PM UTC 24 |
Oct 03 03:06:59 PM UTC 24 |
35263514 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3404209561 |
|
|
Oct 03 03:05:48 PM UTC 24 |
Oct 03 03:06:59 PM UTC 24 |
1040249029 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.380358374 |
|
|
Oct 03 03:05:10 PM UTC 24 |
Oct 03 03:07:02 PM UTC 24 |
9503659141 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3626759094 |
|
|
Oct 03 03:06:32 PM UTC 24 |
Oct 03 03:07:05 PM UTC 24 |
329282608 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.468893970 |
|
|
Oct 03 03:06:02 PM UTC 24 |
Oct 03 03:07:09 PM UTC 24 |
176861642 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.2549067273 |
|
|
Oct 03 03:06:34 PM UTC 24 |
Oct 03 03:07:10 PM UTC 24 |
269378842 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.589675175 |
|
|
Oct 03 03:05:29 PM UTC 24 |
Oct 03 03:07:12 PM UTC 24 |
2070946065 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.3496211045 |
|
|
Oct 03 03:06:52 PM UTC 24 |
Oct 03 03:07:15 PM UTC 24 |
262063178 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3090059192 |
|
|
Oct 03 02:58:10 PM UTC 24 |
Oct 03 03:07:35 PM UTC 24 |
4494293492 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3474086964 |
|
|
Oct 03 03:07:30 PM UTC 24 |
Oct 03 03:07:43 PM UTC 24 |
47049628 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2999412265 |
|
|
Oct 03 02:53:34 PM UTC 24 |
Oct 03 03:07:43 PM UTC 24 |
42764545496 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3510193047 |
|
|
Oct 03 02:46:35 PM UTC 24 |
Oct 03 03:07:45 PM UTC 24 |
73939543252 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2967627247 |
|
|
Oct 03 03:07:35 PM UTC 24 |
Oct 03 03:07:46 PM UTC 24 |
43449176 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.3178045800 |
|
|
Oct 03 03:07:03 PM UTC 24 |
Oct 03 03:07:53 PM UTC 24 |
268045968 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3921019225 |
|
|
Oct 03 03:07:02 PM UTC 24 |
Oct 03 03:07:55 PM UTC 24 |
1175840665 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1526971530 |
|
|
Oct 03 02:01:38 PM UTC 24 |
Oct 03 03:07:57 PM UTC 24 |
26547998935 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2554114012 |
|
|
Oct 03 02:59:31 PM UTC 24 |
Oct 03 03:08:03 PM UTC 24 |
12293615525 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.1530118189 |
|
|
Oct 03 03:07:39 PM UTC 24 |
Oct 03 03:08:16 PM UTC 24 |
997763990 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2265260058 |
|
|
Oct 03 02:48:40 PM UTC 24 |
Oct 03 03:08:17 PM UTC 24 |
62192522017 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3617815035 |
|
|
Oct 03 03:06:29 PM UTC 24 |
Oct 03 03:08:25 PM UTC 24 |
9358455232 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.120617181 |
|
|
Oct 03 03:06:30 PM UTC 24 |
Oct 03 03:08:26 PM UTC 24 |
7337342410 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.2791700677 |
|
|
Oct 03 03:07:42 PM UTC 24 |
Oct 03 03:08:27 PM UTC 24 |
334710771 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.57934045 |
|
|
Oct 03 03:07:12 PM UTC 24 |
Oct 03 03:08:28 PM UTC 24 |
692128080 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2679144506 |
|
|
Oct 03 03:04:57 PM UTC 24 |
Oct 03 03:08:29 PM UTC 24 |
713273367 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.258952328 |
|
|
Oct 03 02:39:42 PM UTC 24 |
Oct 03 03:08:34 PM UTC 24 |
104873932471 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.3525339979 |
|
|
Oct 03 03:06:45 PM UTC 24 |
Oct 03 03:08:38 PM UTC 24 |
2028947020 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.1660755158 |
|
|
Oct 03 03:07:35 PM UTC 24 |
Oct 03 03:08:44 PM UTC 24 |
6343646079 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.218884810 |
|
|
Oct 03 03:01:10 PM UTC 24 |
Oct 03 03:08:52 PM UTC 24 |
2015637186 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2142707114 |
|
|
Oct 03 03:07:26 PM UTC 24 |
Oct 03 03:08:53 PM UTC 24 |
121608930 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4100782539 |
|
|
Oct 03 03:07:36 PM UTC 24 |
Oct 03 03:08:55 PM UTC 24 |
4863767384 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3654186520 |
|
|
Oct 03 03:08:23 PM UTC 24 |
Oct 03 03:09:00 PM UTC 24 |
331220514 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1077307594 |
|
|
Oct 03 03:08:53 PM UTC 24 |
Oct 03 03:09:01 PM UTC 24 |
43697267 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2893403830 |
|
|
Oct 03 02:59:33 PM UTC 24 |
Oct 03 03:09:09 PM UTC 24 |
5104055947 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.4258894472 |
|
|
Oct 03 03:08:18 PM UTC 24 |
Oct 03 03:09:09 PM UTC 24 |
1222637736 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.312389172 |
|
|
Oct 03 02:57:09 PM UTC 24 |
Oct 03 03:09:19 PM UTC 24 |
6842694858 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2465689346 |
|
|
Oct 03 03:08:13 PM UTC 24 |
Oct 03 03:09:25 PM UTC 24 |
2235430347 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.2140800032 |
|
|
Oct 03 03:08:22 PM UTC 24 |
Oct 03 03:09:33 PM UTC 24 |
1450994219 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.3867340546 |
|
|
Oct 03 03:08:59 PM UTC 24 |
Oct 03 03:09:36 PM UTC 24 |
281605356 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.1814481449 |
|
|
Oct 03 03:09:27 PM UTC 24 |
Oct 03 03:09:41 PM UTC 24 |
92225693 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2102889285 |
|
|
Oct 03 03:09:36 PM UTC 24 |
Oct 03 03:09:50 PM UTC 24 |
150054652 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.1094519281 |
|
|
Oct 03 03:08:08 PM UTC 24 |
Oct 03 03:09:52 PM UTC 24 |
2458633145 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.3278495637 |
|
|
Oct 03 03:09:06 PM UTC 24 |
Oct 03 03:09:56 PM UTC 24 |
317972964 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.940430421 |
|
|
Oct 03 03:04:45 PM UTC 24 |
Oct 03 03:09:59 PM UTC 24 |
6135808434 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1319256330 |
|
|
Oct 03 03:09:19 PM UTC 24 |
Oct 03 03:10:03 PM UTC 24 |
336833668 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2518133275 |
|
|
Oct 03 03:05:58 PM UTC 24 |
Oct 03 03:10:10 PM UTC 24 |
5866229955 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.897027516 |
|
|
Oct 03 03:10:05 PM UTC 24 |
Oct 03 03:10:13 PM UTC 24 |
44707702 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.4283308152 |
|
|
Oct 03 03:10:08 PM UTC 24 |
Oct 03 03:10:16 PM UTC 24 |
45695797 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2459210943 |
|
|
Oct 03 03:08:50 PM UTC 24 |
Oct 03 03:10:33 PM UTC 24 |
6024093032 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.807876349 |
|
|
Oct 03 03:02:05 PM UTC 24 |
Oct 03 03:10:39 PM UTC 24 |
26182557316 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3912714479 |
|
|
Oct 03 03:10:25 PM UTC 24 |
Oct 03 03:10:42 PM UTC 24 |
91766845 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.3990532066 |
|
|
Oct 03 03:08:55 PM UTC 24 |
Oct 03 03:10:43 PM UTC 24 |
8508482048 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.673471991 |
|
|
Oct 03 03:02:09 PM UTC 24 |
Oct 03 03:10:43 PM UTC 24 |
31370128342 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.1266860331 |
|
|
Oct 03 03:03:28 PM UTC 24 |
Oct 03 03:10:47 PM UTC 24 |
13185747148 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.306149860 |
|
|
Oct 03 03:09:30 PM UTC 24 |
Oct 03 03:11:04 PM UTC 24 |
1402957962 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.19886175 |
|
|
Oct 03 03:09:28 PM UTC 24 |
Oct 03 03:11:05 PM UTC 24 |
2402965951 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2840742993 |
|
|
Oct 03 03:02:33 PM UTC 24 |
Oct 03 03:11:10 PM UTC 24 |
4331593208 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3305481932 |
|
|
Oct 03 02:04:35 PM UTC 24 |
Oct 03 03:11:12 PM UTC 24 |
33061741232 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.1829204218 |
|
|
Oct 03 03:10:39 PM UTC 24 |
Oct 03 03:11:15 PM UTC 24 |
494722491 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2843345389 |
|
|
Oct 03 03:04:48 PM UTC 24 |
Oct 03 03:11:15 PM UTC 24 |
9501561273 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.905767548 |
|
|
Oct 03 03:10:02 PM UTC 24 |
Oct 03 03:11:17 PM UTC 24 |
313266132 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.4107061050 |
|
|
Oct 03 03:06:44 PM UTC 24 |
Oct 03 03:11:25 PM UTC 24 |
14283003576 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.3249018387 |
|
|
Oct 03 03:11:05 PM UTC 24 |
Oct 03 03:11:25 PM UTC 24 |
187927392 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1516697527 |
|
|
Oct 03 03:11:11 PM UTC 24 |
Oct 03 03:11:34 PM UTC 24 |
136985569 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3722327965 |
|
|
Oct 03 03:11:08 PM UTC 24 |
Oct 03 03:11:36 PM UTC 24 |
477679276 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.3865607263 |
|
|
Oct 03 03:08:40 PM UTC 24 |
Oct 03 03:11:46 PM UTC 24 |
4890491022 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1785705945 |
|
|
Oct 03 03:11:30 PM UTC 24 |
Oct 03 03:11:48 PM UTC 24 |
18475620 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3572391459 |
|
|
Oct 03 03:11:38 PM UTC 24 |
Oct 03 03:11:48 PM UTC 24 |
53613434 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.3963717885 |
|
|
Oct 03 03:11:01 PM UTC 24 |
Oct 03 03:11:52 PM UTC 24 |
1017947607 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4099862178 |
|
|
Oct 03 03:11:39 PM UTC 24 |
Oct 03 03:11:55 PM UTC 24 |
192284882 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.1494770742 |
|
|
Oct 03 03:10:13 PM UTC 24 |
Oct 03 03:11:55 PM UTC 24 |
9149594531 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.637414785 |
|
|
Oct 03 03:04:45 PM UTC 24 |
Oct 03 03:12:02 PM UTC 24 |
855911842 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2973366008 |
|
|
Oct 03 03:05:53 PM UTC 24 |
Oct 03 03:12:12 PM UTC 24 |
4397596936 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3065861655 |
|
|
Oct 03 03:10:23 PM UTC 24 |
Oct 03 03:12:14 PM UTC 24 |
2224852659 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.4175720806 |
|
|
Oct 03 03:11:55 PM UTC 24 |
Oct 03 03:12:15 PM UTC 24 |
193710207 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.413983884 |
|
|
Oct 03 03:10:20 PM UTC 24 |
Oct 03 03:12:18 PM UTC 24 |
5749182578 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.4221005665 |
|
|
Oct 03 03:07:26 PM UTC 24 |
Oct 03 03:12:21 PM UTC 24 |
8800789492 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.1795348957 |
|
|
Oct 03 03:11:43 PM UTC 24 |
Oct 03 03:12:26 PM UTC 24 |
834717005 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3044698044 |
|
|
Oct 03 03:08:09 PM UTC 24 |
Oct 03 03:12:31 PM UTC 24 |
13615789183 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1808923318 |
|
|
Oct 03 03:12:17 PM UTC 24 |
Oct 03 03:12:47 PM UTC 24 |
900631190 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.1495637352 |
|
|
Oct 03 03:12:45 PM UTC 24 |
Oct 03 03:12:57 PM UTC 24 |
40911502 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3454609664 |
|
|
Oct 03 03:12:46 PM UTC 24 |
Oct 03 03:12:57 PM UTC 24 |
51572063 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2348921764 |
|
|
Oct 03 03:12:14 PM UTC 24 |
Oct 03 03:13:02 PM UTC 24 |
382560962 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.201276145 |
|
|
Oct 03 03:12:20 PM UTC 24 |
Oct 03 03:13:05 PM UTC 24 |
889842667 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.4114886589 |
|
|
Oct 03 03:05:28 PM UTC 24 |
Oct 03 03:13:11 PM UTC 24 |
34224362214 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1511605389 |
|
|
Oct 03 03:11:42 PM UTC 24 |
Oct 03 03:13:16 PM UTC 24 |
4788604698 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1539043891 |
|
|
Oct 03 03:12:22 PM UTC 24 |
Oct 03 03:13:24 PM UTC 24 |
1139050927 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.808849736 |
|
|
Oct 03 03:07:27 PM UTC 24 |
Oct 03 03:13:29 PM UTC 24 |
2563505139 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1258462744 |
|
|
Oct 03 03:03:43 PM UTC 24 |
Oct 03 03:13:31 PM UTC 24 |
8041035238 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.1622530456 |
|
|
Oct 03 03:04:16 PM UTC 24 |
Oct 03 03:13:40 PM UTC 24 |
48537265625 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.3232595840 |
|
|
Oct 03 03:11:11 PM UTC 24 |
Oct 03 03:13:44 PM UTC 24 |
1509667535 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.2591478060 |
|
|
Oct 03 03:13:14 PM UTC 24 |
Oct 03 03:13:47 PM UTC 24 |
332143213 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3525532818 |
|
|
Oct 03 03:11:40 PM UTC 24 |
Oct 03 03:13:48 PM UTC 24 |
8369241014 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1135619269 |
|
|
Oct 03 03:08:28 PM UTC 24 |
Oct 03 03:13:48 PM UTC 24 |
4084724152 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3468829678 |
|
|
Oct 03 03:12:00 PM UTC 24 |
Oct 03 03:13:59 PM UTC 24 |
3114483095 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1932056522 |
|
|
Oct 03 02:33:02 PM UTC 24 |
Oct 03 03:14:02 PM UTC 24 |
139789643291 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.4207683116 |
|
|
Oct 03 03:13:44 PM UTC 24 |
Oct 03 03:14:04 PM UTC 24 |
203416929 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2045214756 |
|
|
Oct 03 03:13:56 PM UTC 24 |
Oct 03 03:14:20 PM UTC 24 |
153614270 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2432292614 |
|
|
Oct 03 03:14:13 PM UTC 24 |
Oct 03 03:14:21 PM UTC 24 |
48536087 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.3664363834 |
|
|
Oct 03 03:13:24 PM UTC 24 |
Oct 03 03:14:21 PM UTC 24 |
4919597576 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.283673921 |
|
|
Oct 03 03:13:37 PM UTC 24 |
Oct 03 03:14:24 PM UTC 24 |
593238858 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.2330660282 |
|
|
Oct 03 03:13:52 PM UTC 24 |
Oct 03 03:14:24 PM UTC 24 |
587740040 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.988038367 |
|
|
Oct 03 03:14:14 PM UTC 24 |
Oct 03 03:14:25 PM UTC 24 |
225930781 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1090821508 |
|
|
Oct 03 03:12:56 PM UTC 24 |
Oct 03 03:14:29 PM UTC 24 |
2291336704 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3910971229 |
|
|
Oct 03 03:12:53 PM UTC 24 |
Oct 03 03:14:31 PM UTC 24 |
5249958862 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.987577470 |
|
|
Oct 03 03:08:45 PM UTC 24 |
Oct 03 03:14:31 PM UTC 24 |
919627812 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2312905645 |
|
|
Oct 03 03:13:27 PM UTC 24 |
Oct 03 03:14:38 PM UTC 24 |
1420401183 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1444947057 |
|
|
Oct 03 03:06:36 PM UTC 24 |
Oct 03 03:14:57 PM UTC 24 |
53160918344 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.473815415 |
|
|
Oct 03 03:09:54 PM UTC 24 |
Oct 03 03:14:58 PM UTC 24 |
7246865595 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2842168811 |
|
|
Oct 03 03:25:57 PM UTC 24 |
Oct 03 03:26:09 PM UTC 24 |
164260499 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.2757070248 |
|
|
Oct 03 03:14:43 PM UTC 24 |
Oct 03 03:14:59 PM UTC 24 |
114290500 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.3979566304 |
|
|
Oct 03 03:12:49 PM UTC 24 |
Oct 03 03:14:59 PM UTC 24 |
8406396199 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.11547457 |
|
|
Oct 03 03:09:35 PM UTC 24 |
Oct 03 03:15:03 PM UTC 24 |
6624588513 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.1305895335 |
|
|
Oct 03 03:14:55 PM UTC 24 |
Oct 03 03:15:07 PM UTC 24 |
75269665 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.4201181087 |
|
|
Oct 03 03:08:42 PM UTC 24 |
Oct 03 03:15:08 PM UTC 24 |
699339587 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.2605457630 |
|
|
Oct 03 03:14:31 PM UTC 24 |
Oct 03 03:15:15 PM UTC 24 |
383178589 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.4070611784 |
|
|
Oct 03 03:15:24 PM UTC 24 |
Oct 03 03:15:34 PM UTC 24 |
40106485 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.459407857 |
|
|
Oct 03 03:15:28 PM UTC 24 |
Oct 03 03:15:38 PM UTC 24 |
45635611 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1264935856 |
|
|
Oct 03 03:09:10 PM UTC 24 |
Oct 03 03:15:41 PM UTC 24 |
36951454860 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.2967426097 |
|
|
Oct 03 03:11:32 PM UTC 24 |
Oct 03 03:15:47 PM UTC 24 |
2596325190 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.365579901 |
|
|
Oct 03 03:15:23 PM UTC 24 |
Oct 03 03:15:47 PM UTC 24 |
7680288 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2777043183 |
|
|
Oct 03 03:14:51 PM UTC 24 |
Oct 03 03:15:48 PM UTC 24 |
570277696 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.4253842177 |
|
|
Oct 03 03:14:57 PM UTC 24 |
Oct 03 03:15:52 PM UTC 24 |
1332154012 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1690779776 |
|
|
Oct 03 03:14:27 PM UTC 24 |
Oct 03 03:15:55 PM UTC 24 |
5435966693 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.2789505851 |
|
|
Oct 03 03:14:54 PM UTC 24 |
Oct 03 03:16:01 PM UTC 24 |
1647331381 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.3051646690 |
|
|
Oct 03 03:14:25 PM UTC 24 |
Oct 03 03:16:07 PM UTC 24 |
8714322781 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1061696878 |
|
|
Oct 03 03:04:16 PM UTC 24 |
Oct 03 03:16:08 PM UTC 24 |
51732071793 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.2460149627 |
|
|
Oct 03 03:14:48 PM UTC 24 |
Oct 03 03:16:20 PM UTC 24 |
1685615404 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.1856500538 |
|
|
Oct 03 03:15:42 PM UTC 24 |
Oct 03 03:16:31 PM UTC 24 |
790932414 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.1573362337 |
|
|
Oct 03 03:16:21 PM UTC 24 |
Oct 03 03:16:35 PM UTC 24 |
153506195 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3247320595 |
|
|
Oct 03 03:16:15 PM UTC 24 |
Oct 03 03:16:36 PM UTC 24 |
197757496 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.4029097309 |
|
|
Oct 03 03:06:41 PM UTC 24 |
Oct 03 03:16:45 PM UTC 24 |
29736155267 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2656484816 |
|
|
Oct 03 03:15:36 PM UTC 24 |
Oct 03 03:16:47 PM UTC 24 |
4529292389 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1883501592 |
|
|
Oct 03 03:16:28 PM UTC 24 |
Oct 03 03:16:51 PM UTC 24 |
150780167 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.2709953385 |
|
|
Oct 03 02:58:55 PM UTC 24 |
Oct 03 03:16:52 PM UTC 24 |
75242400195 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.2709118012 |
|
|
Oct 03 03:16:02 PM UTC 24 |
Oct 03 03:16:54 PM UTC 24 |
331686604 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.464880825 |
|
|
Oct 03 03:12:00 PM UTC 24 |
Oct 03 03:16:55 PM UTC 24 |
14845344688 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.445022749 |
|
|
Oct 03 03:16:23 PM UTC 24 |
Oct 03 03:16:56 PM UTC 24 |
155852542 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1876798285 |
|
|
Oct 03 03:17:02 PM UTC 24 |
Oct 03 03:17:13 PM UTC 24 |
49085054 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.289948069 |
|
|
Oct 03 03:17:02 PM UTC 24 |
Oct 03 03:17:17 PM UTC 24 |
243289508 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.1617180142 |
|
|
Oct 03 03:03:14 PM UTC 24 |
Oct 03 03:17:23 PM UTC 24 |
84928991295 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3312367597 |
|
|
Oct 03 02:29:46 PM UTC 24 |
Oct 03 03:17:25 PM UTC 24 |
162023370592 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.3375691536 |
|
|
Oct 03 03:08:02 PM UTC 24 |
Oct 03 03:17:29 PM UTC 24 |
44783746609 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3197682312 |
|
|
Oct 03 03:17:18 PM UTC 24 |
Oct 03 03:17:38 PM UTC 24 |
196442022 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.1225923220 |
|
|
Oct 03 03:00:17 PM UTC 24 |
Oct 03 03:17:51 PM UTC 24 |
95243496190 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.1871558198 |
|
|
Oct 03 03:15:33 PM UTC 24 |
Oct 03 03:17:54 PM UTC 24 |
10429810665 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.3300140891 |
|
|
Oct 03 03:15:02 PM UTC 24 |
Oct 03 03:18:02 PM UTC 24 |
3569666369 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.65817272 |
|
|
Oct 03 03:16:11 PM UTC 24 |
Oct 03 03:18:13 PM UTC 24 |
2533389051 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.75772973 |
|
|
Oct 03 03:16:48 PM UTC 24 |
Oct 03 03:18:27 PM UTC 24 |
930217896 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3764328997 |
|
|
Oct 03 03:09:21 PM UTC 24 |
Oct 03 03:18:33 PM UTC 24 |
35815243300 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.55408782 |
|
|
Oct 03 03:17:19 PM UTC 24 |
Oct 03 03:18:33 PM UTC 24 |
1697925044 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2834087738 |
|
|
Oct 03 03:17:56 PM UTC 24 |
Oct 03 03:18:37 PM UTC 24 |
241158261 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.2157646555 |
|
|
Oct 03 03:12:38 PM UTC 24 |
Oct 03 03:18:40 PM UTC 24 |
9643621531 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.357727696 |
|
|
Oct 03 03:17:43 PM UTC 24 |
Oct 03 03:18:51 PM UTC 24 |
2105214973 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.3412499735 |
|
|
Oct 03 03:18:38 PM UTC 24 |
Oct 03 03:18:54 PM UTC 24 |
242413820 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3894181824 |
|
|
Oct 03 03:17:53 PM UTC 24 |
Oct 03 03:18:55 PM UTC 24 |
1055183162 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.188413846 |
|
|
Oct 03 03:17:52 PM UTC 24 |
Oct 03 03:18:56 PM UTC 24 |
1646027605 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.601031649 |
|
|
Oct 03 03:18:54 PM UTC 24 |
Oct 03 03:19:02 PM UTC 24 |
50262555 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.2678534000 |
|
|
Oct 03 03:05:27 PM UTC 24 |
Oct 03 03:19:06 PM UTC 24 |
91983817048 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.3444854567 |
|
|
Oct 03 03:02:05 PM UTC 24 |
Oct 03 03:19:09 PM UTC 24 |
96028276155 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3219621067 |
|
|
Oct 03 03:13:31 PM UTC 24 |
Oct 03 03:19:09 PM UTC 24 |
18206431867 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1986020163 |
|
|
Oct 03 03:17:17 PM UTC 24 |
Oct 03 03:19:25 PM UTC 24 |
5847886185 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.994307449 |
|
|
Oct 03 03:18:31 PM UTC 24 |
Oct 03 03:19:25 PM UTC 24 |
255656979 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.2416673371 |
|
|
Oct 03 03:17:12 PM UTC 24 |
Oct 03 03:19:33 PM UTC 24 |
7610480251 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.377174845 |
|
|
Oct 03 03:19:07 PM UTC 24 |
Oct 03 03:19:49 PM UTC 24 |
394675105 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.3101545906 |
|
|
Oct 03 03:18:57 PM UTC 24 |
Oct 03 03:19:56 PM UTC 24 |
5461342541 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2580564893 |
|
|
Oct 03 03:12:43 PM UTC 24 |
Oct 03 03:19:58 PM UTC 24 |
3242017909 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.1823007824 |
|
|
Oct 03 03:19:20 PM UTC 24 |
Oct 03 03:20:03 PM UTC 24 |
960836342 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3250315489 |
|
|
Oct 03 03:15:23 PM UTC 24 |
Oct 03 03:20:04 PM UTC 24 |
2402954662 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.2659896239 |
|
|
Oct 03 03:08:08 PM UTC 24 |
Oct 03 03:20:08 PM UTC 24 |
36158753483 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.200680745 |
|
|
Oct 03 03:19:38 PM UTC 24 |
Oct 03 03:20:10 PM UTC 24 |
610340853 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.2356181352 |
|
|
Oct 03 03:17:23 PM UTC 24 |
Oct 03 03:20:13 PM UTC 24 |
2767155531 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.2676659759 |
|
|
Oct 03 03:19:15 PM UTC 24 |
Oct 03 03:20:18 PM UTC 24 |
6473416038 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.4266885908 |
|
|
Oct 03 03:09:47 PM UTC 24 |
Oct 03 03:20:18 PM UTC 24 |
5461436650 ps |