| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657081101 |
|
|
Oct 03 09:57:19 PM UTC 24 |
Oct 03 10:05:18 PM UTC 24 |
4231221960 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2821993176 |
|
|
Oct 03 09:04:12 PM UTC 24 |
Oct 03 10:05:33 PM UTC 24 |
12455112232 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.2659260321 |
|
|
Oct 03 09:55:08 PM UTC 24 |
Oct 03 10:05:42 PM UTC 24 |
4628782568 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.62186905 |
|
|
Oct 03 09:46:58 PM UTC 24 |
Oct 03 10:05:46 PM UTC 24 |
8471560308 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.2252171432 |
|
|
Oct 03 09:55:07 PM UTC 24 |
Oct 03 10:06:11 PM UTC 24 |
4427954392 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.940325391 |
|
|
Oct 03 09:51:14 PM UTC 24 |
Oct 03 10:06:14 PM UTC 24 |
6189344968 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.2537225965 |
|
|
Oct 03 09:57:17 PM UTC 24 |
Oct 03 10:06:17 PM UTC 24 |
5234291495 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.499717563 |
|
|
Oct 03 09:59:03 PM UTC 24 |
Oct 03 10:06:31 PM UTC 24 |
5048699088 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.287557384 |
|
|
Oct 03 09:56:12 PM UTC 24 |
Oct 03 10:07:30 PM UTC 24 |
8290987465 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.1845790667 |
|
|
Oct 03 09:55:07 PM UTC 24 |
Oct 03 10:07:37 PM UTC 24 |
4266010080 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2359920680 |
|
|
Oct 03 08:47:31 PM UTC 24 |
Oct 03 10:07:50 PM UTC 24 |
17430319606 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.2393010459 |
|
|
Oct 03 09:48:41 PM UTC 24 |
Oct 03 10:09:43 PM UTC 24 |
10095249520 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.2314870826 |
|
|
Oct 03 09:31:18 PM UTC 24 |
Oct 03 10:10:03 PM UTC 24 |
18627083765 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.1794116272 |
|
|
Oct 03 09:58:10 PM UTC 24 |
Oct 03 10:10:46 PM UTC 24 |
7882262305 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.978424922 |
|
|
Oct 03 09:57:18 PM UTC 24 |
Oct 03 10:10:51 PM UTC 24 |
6306448306 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1963211039 |
|
|
Oct 03 10:04:23 PM UTC 24 |
Oct 03 10:11:26 PM UTC 24 |
4190205080 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.837048742 |
|
|
Oct 03 10:01:27 PM UTC 24 |
Oct 03 10:12:43 PM UTC 24 |
4744728632 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3117890739 |
|
|
Oct 03 09:55:25 PM UTC 24 |
Oct 03 10:12:52 PM UTC 24 |
8095361565 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.424582218 |
|
|
Oct 03 10:02:51 PM UTC 24 |
Oct 03 10:13:42 PM UTC 24 |
6340353768 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654194427 |
|
|
Oct 03 10:06:59 PM UTC 24 |
Oct 03 10:14:11 PM UTC 24 |
3729641722 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.4276555870 |
|
|
Oct 03 10:04:24 PM UTC 24 |
Oct 03 10:14:17 PM UTC 24 |
4447219652 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.619793033 |
|
|
Oct 03 10:07:34 PM UTC 24 |
Oct 03 10:14:24 PM UTC 24 |
3483847916 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.714478531 |
|
|
Oct 03 08:29:13 PM UTC 24 |
Oct 03 10:16:21 PM UTC 24 |
48034000740 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.1079131439 |
|
|
Oct 03 09:25:17 PM UTC 24 |
Oct 03 10:16:23 PM UTC 24 |
30957031469 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.1001624221 |
|
|
Oct 03 10:08:33 PM UTC 24 |
Oct 03 10:17:12 PM UTC 24 |
4712203320 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4007982584 |
|
|
Oct 03 10:10:23 PM UTC 24 |
Oct 03 10:17:22 PM UTC 24 |
4108207958 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.2408456813 |
|
|
Oct 03 10:06:36 PM UTC 24 |
Oct 03 10:17:32 PM UTC 24 |
4254103976 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.3746425698 |
|
|
Oct 03 10:06:58 PM UTC 24 |
Oct 03 10:18:14 PM UTC 24 |
4946811580 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3908824306 |
|
|
Oct 03 10:07:26 PM UTC 24 |
Oct 03 10:18:35 PM UTC 24 |
4166252762 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2770311808 |
|
|
Oct 03 10:08:32 PM UTC 24 |
Oct 03 10:20:40 PM UTC 24 |
7280582822 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1269512553 |
|
|
Oct 03 10:04:22 PM UTC 24 |
Oct 03 10:20:55 PM UTC 24 |
11875671416 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1409899876 |
|
|
Oct 03 10:12:03 PM UTC 24 |
Oct 03 10:21:18 PM UTC 24 |
6737641715 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.168977445 |
|
|
Oct 03 10:13:00 PM UTC 24 |
Oct 03 10:22:00 PM UTC 24 |
3990543288 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049446837 |
|
|
Oct 03 10:15:13 PM UTC 24 |
Oct 03 10:22:06 PM UTC 24 |
4069179424 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.1757269891 |
|
|
Oct 03 09:38:56 PM UTC 24 |
Oct 03 10:22:41 PM UTC 24 |
11218307970 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.502399896 |
|
|
Oct 03 10:07:29 PM UTC 24 |
Oct 03 10:23:12 PM UTC 24 |
9475700986 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2559883955 |
|
|
Oct 03 10:11:35 PM UTC 24 |
Oct 03 10:23:26 PM UTC 24 |
5429554776 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.878810013 |
|
|
Oct 03 08:29:50 PM UTC 24 |
Oct 03 10:24:01 PM UTC 24 |
48888602470 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.2879500668 |
|
|
Oct 03 10:13:35 PM UTC 24 |
Oct 03 10:25:08 PM UTC 24 |
4900200120 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1300428013 |
|
|
Oct 03 09:55:22 PM UTC 24 |
Oct 03 10:25:21 PM UTC 24 |
8351598175 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.3307442290 |
|
|
Oct 03 10:15:15 PM UTC 24 |
Oct 03 10:25:36 PM UTC 24 |
7806200127 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750606588 |
|
|
Oct 03 10:18:18 PM UTC 24 |
Oct 03 10:25:55 PM UTC 24 |
4260001904 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.2218142320 |
|
|
Oct 03 10:15:14 PM UTC 24 |
Oct 03 10:26:31 PM UTC 24 |
4551875280 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4121960563 |
|
|
Oct 03 10:19:13 PM UTC 24 |
Oct 03 10:27:55 PM UTC 24 |
3409181016 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2576618669 |
|
|
Oct 03 08:29:13 PM UTC 24 |
Oct 03 10:27:57 PM UTC 24 |
49174109495 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.1401229923 |
|
|
Oct 03 10:07:01 PM UTC 24 |
Oct 03 10:28:27 PM UTC 24 |
13848141066 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1379370542 |
|
|
Oct 03 09:33:52 PM UTC 24 |
Oct 03 10:28:58 PM UTC 24 |
11870346974 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2301776334 |
|
|
Oct 03 10:18:17 PM UTC 24 |
Oct 03 10:29:37 PM UTC 24 |
5792785612 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076099938 |
|
|
Oct 03 10:22:50 PM UTC 24 |
Oct 03 10:30:05 PM UTC 24 |
3609001250 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.2283054131 |
|
|
Oct 03 10:21:55 PM UTC 24 |
Oct 03 10:30:56 PM UTC 24 |
5400566689 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3530833637 |
|
|
Oct 03 10:24:06 PM UTC 24 |
Oct 03 10:31:26 PM UTC 24 |
3471348546 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.1453395038 |
|
|
Oct 03 09:59:24 PM UTC 24 |
Oct 03 10:31:39 PM UTC 24 |
21922999192 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.2288120092 |
|
|
Oct 03 10:21:32 PM UTC 24 |
Oct 03 10:32:07 PM UTC 24 |
5780797800 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.4290144277 |
|
|
Oct 03 10:23:50 PM UTC 24 |
Oct 03 10:32:46 PM UTC 24 |
5722941126 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.3930950359 |
|
|
Oct 03 10:23:18 PM UTC 24 |
Oct 03 10:32:54 PM UTC 24 |
4279511400 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1842469662 |
|
|
Oct 03 10:26:01 PM UTC 24 |
Oct 03 10:33:04 PM UTC 24 |
3088028830 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.18651031 |
|
|
Oct 03 10:27:07 PM UTC 24 |
Oct 03 10:33:59 PM UTC 24 |
3696097270 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.98937668 |
|
|
Oct 03 10:22:51 PM UTC 24 |
Oct 03 10:34:48 PM UTC 24 |
5548186266 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017694820 |
|
|
Oct 03 10:29:16 PM UTC 24 |
Oct 03 10:35:53 PM UTC 24 |
3396198718 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.1080533420 |
|
|
Oct 03 10:18:50 PM UTC 24 |
Oct 03 10:36:00 PM UTC 24 |
13621953333 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3565443649 |
|
|
Oct 03 10:17:11 PM UTC 24 |
Oct 03 10:36:31 PM UTC 24 |
13288494542 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2202302541 |
|
|
Oct 03 04:08:08 PM UTC 24 |
Oct 03 10:36:35 PM UTC 24 |
81776377450 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.4180481220 |
|
|
Oct 03 10:26:17 PM UTC 24 |
Oct 03 10:36:52 PM UTC 24 |
6355355362 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.1073206706 |
|
|
Oct 03 10:07:27 PM UTC 24 |
Oct 03 10:37:13 PM UTC 24 |
8387956360 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1939115095 |
|
|
Oct 03 09:46:59 PM UTC 24 |
Oct 03 10:37:18 PM UTC 24 |
13645218537 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.49903262 |
|
|
Oct 03 10:11:36 PM UTC 24 |
Oct 03 10:37:20 PM UTC 24 |
8296343626 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1855143079 |
|
|
Oct 03 10:29:16 PM UTC 24 |
Oct 03 10:38:31 PM UTC 24 |
6296696668 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.94890341 |
|
|
Oct 03 10:30:15 PM UTC 24 |
Oct 03 10:38:44 PM UTC 24 |
4606043592 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.404335645 |
|
|
Oct 03 10:30:45 PM UTC 24 |
Oct 03 10:39:33 PM UTC 24 |
3895859288 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626174679 |
|
|
Oct 03 10:32:47 PM UTC 24 |
Oct 03 10:40:02 PM UTC 24 |
4251659092 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3434648215 |
|
|
Oct 03 10:31:35 PM UTC 24 |
Oct 03 10:40:23 PM UTC 24 |
4092966080 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3979033865 |
|
|
Oct 03 10:32:16 PM UTC 24 |
Oct 03 10:40:27 PM UTC 24 |
3698108504 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295760176 |
|
|
Oct 03 10:33:51 PM UTC 24 |
Oct 03 10:40:43 PM UTC 24 |
3543228706 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.203180503 |
|
|
Oct 03 09:55:21 PM UTC 24 |
Oct 03 10:41:17 PM UTC 24 |
12627220944 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.454719196 |
|
|
Oct 03 09:35:14 PM UTC 24 |
Oct 03 10:41:28 PM UTC 24 |
24737097325 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2409093636 |
|
|
Oct 03 10:34:40 PM UTC 24 |
Oct 03 10:41:48 PM UTC 24 |
3545468974 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.3112104991 |
|
|
Oct 03 10:32:20 PM UTC 24 |
Oct 03 10:42:02 PM UTC 24 |
4751956380 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1746353281 |
|
|
Oct 03 10:28:46 PM UTC 24 |
Oct 03 10:42:35 PM UTC 24 |
5278728250 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2751919236 |
|
|
Oct 03 09:30:52 PM UTC 24 |
Oct 03 10:43:12 PM UTC 24 |
19353634866 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.17085540 |
|
|
Oct 03 10:14:22 PM UTC 24 |
Oct 03 10:43:16 PM UTC 24 |
8600036152 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4036494709 |
|
|
Oct 03 10:37:35 PM UTC 24 |
Oct 03 10:44:19 PM UTC 24 |
3440936348 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.2414822808 |
|
|
Oct 03 09:34:53 PM UTC 24 |
Oct 03 10:44:19 PM UTC 24 |
25966023524 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.361311536 |
|
|
Oct 03 10:37:36 PM UTC 24 |
Oct 03 10:44:31 PM UTC 24 |
3771273350 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.300092263 |
|
|
Oct 03 09:33:48 PM UTC 24 |
Oct 03 10:44:43 PM UTC 24 |
15407142405 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.4101825950 |
|
|
Oct 03 10:33:48 PM UTC 24 |
Oct 03 10:45:00 PM UTC 24 |
5026993462 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.429954118 |
|
|
Oct 03 09:33:06 PM UTC 24 |
Oct 03 10:45:05 PM UTC 24 |
14106440529 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3537397137 |
|
|
Oct 03 09:35:03 PM UTC 24 |
Oct 03 10:45:20 PM UTC 24 |
14795578760 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1708870598 |
|
|
Oct 03 10:35:29 PM UTC 24 |
Oct 03 10:45:54 PM UTC 24 |
5384256510 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.3450344321 |
|
|
Oct 03 10:33:48 PM UTC 24 |
Oct 03 10:46:28 PM UTC 24 |
6435571652 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2735272647 |
|
|
Oct 03 10:39:22 PM UTC 24 |
Oct 03 10:46:37 PM UTC 24 |
4047511242 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.1342088018 |
|
|
Oct 03 10:21:37 PM UTC 24 |
Oct 03 10:46:58 PM UTC 24 |
7915131748 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3026763405 |
|
|
Oct 03 09:35:24 PM UTC 24 |
Oct 03 10:47:56 PM UTC 24 |
15658868116 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2650925951 |
|
|
Oct 03 10:42:10 PM UTC 24 |
Oct 03 10:48:04 PM UTC 24 |
3970745800 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126024605 |
|
|
Oct 03 10:40:42 PM UTC 24 |
Oct 03 10:48:22 PM UTC 24 |
3782657016 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4247551631 |
|
|
Oct 03 10:40:16 PM UTC 24 |
Oct 03 10:48:33 PM UTC 24 |
3269630600 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.3750653851 |
|
|
Oct 03 10:37:33 PM UTC 24 |
Oct 03 10:48:39 PM UTC 24 |
5067204040 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2150604953 |
|
|
Oct 03 10:41:27 PM UTC 24 |
Oct 03 10:49:07 PM UTC 24 |
3570359150 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3679204469 |
|
|
Oct 03 09:28:47 PM UTC 24 |
Oct 03 10:49:19 PM UTC 24 |
25086281681 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3338209363 |
|
|
Oct 03 09:33:17 PM UTC 24 |
Oct 03 10:49:24 PM UTC 24 |
15138711630 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.3315622208 |
|
|
Oct 03 09:35:05 PM UTC 24 |
Oct 03 10:49:35 PM UTC 24 |
14998945370 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3885786682 |
|
|
Oct 03 09:35:27 PM UTC 24 |
Oct 03 10:49:37 PM UTC 24 |
15477558500 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.159256094 |
|
|
Oct 03 10:43:16 PM UTC 24 |
Oct 03 10:49:52 PM UTC 24 |
4037935652 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.3738282242 |
|
|
Oct 03 09:48:55 PM UTC 24 |
Oct 03 10:50:02 PM UTC 24 |
34394246809 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2413397856 |
|
|
Oct 03 10:42:39 PM UTC 24 |
Oct 03 10:50:10 PM UTC 24 |
4002237716 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.148072713 |
|
|
Oct 03 10:36:45 PM UTC 24 |
Oct 03 10:50:12 PM UTC 24 |
4931396360 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.3436967008 |
|
|
Oct 03 10:38:20 PM UTC 24 |
Oct 03 10:50:17 PM UTC 24 |
5031013044 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.106821764 |
|
|
Oct 03 10:41:30 PM UTC 24 |
Oct 03 10:50:19 PM UTC 24 |
4623126400 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.691356390 |
|
|
Oct 03 10:39:26 PM UTC 24 |
Oct 03 10:50:39 PM UTC 24 |
6434581880 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.466680816 |
|
|
Oct 03 10:38:19 PM UTC 24 |
Oct 03 10:50:56 PM UTC 24 |
5891402416 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618977366 |
|
|
Oct 03 10:44:01 PM UTC 24 |
Oct 03 10:51:21 PM UTC 24 |
4062224428 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.650800819 |
|
|
Oct 03 10:42:43 PM UTC 24 |
Oct 03 10:51:21 PM UTC 24 |
5373804872 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.519304599 |
|
|
Oct 03 10:42:12 PM UTC 24 |
Oct 03 10:51:22 PM UTC 24 |
5797171644 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1277032077 |
|
|
Oct 03 10:40:17 PM UTC 24 |
Oct 03 10:51:52 PM UTC 24 |
5319516920 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.1620182223 |
|
|
Oct 03 10:26:35 PM UTC 24 |
Oct 03 10:52:12 PM UTC 24 |
7532604936 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.2371752526 |
|
|
Oct 03 10:41:31 PM UTC 24 |
Oct 03 10:52:50 PM UTC 24 |
5348555176 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607087165 |
|
|
Oct 03 10:45:53 PM UTC 24 |
Oct 03 10:52:57 PM UTC 24 |
3693890000 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2200058308 |
|
|
Oct 03 10:46:45 PM UTC 24 |
Oct 03 10:52:58 PM UTC 24 |
3943128624 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.4039758816 |
|
|
Oct 03 09:34:29 PM UTC 24 |
Oct 03 10:53:10 PM UTC 24 |
16057212188 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386670936 |
|
|
Oct 03 10:46:33 PM UTC 24 |
Oct 03 10:53:31 PM UTC 24 |
4019498280 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.4063471398 |
|
|
Oct 03 10:28:47 PM UTC 24 |
Oct 03 10:53:37 PM UTC 24 |
7758384278 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.352718133 |
|
|
Oct 03 10:46:31 PM UTC 24 |
Oct 03 10:53:41 PM UTC 24 |
5361813218 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770845959 |
|
|
Oct 03 10:47:37 PM UTC 24 |
Oct 03 10:53:45 PM UTC 24 |
3149612032 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.4208261674 |
|
|
Oct 03 10:29:35 PM UTC 24 |
Oct 03 10:53:49 PM UTC 24 |
8171129098 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2851660525 |
|
|
Oct 03 10:46:49 PM UTC 24 |
Oct 03 10:54:03 PM UTC 24 |
4726979024 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2859823965 |
|
|
Oct 03 10:25:58 PM UTC 24 |
Oct 03 10:54:12 PM UTC 24 |
8177601090 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1730902907 |
|
|
Oct 03 10:49:31 PM UTC 24 |
Oct 03 10:55:03 PM UTC 24 |
3761273864 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.3127380906 |
|
|
Oct 03 10:46:45 PM UTC 24 |
Oct 03 10:55:11 PM UTC 24 |
5223980584 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.804591150 |
|
|
Oct 03 10:48:59 PM UTC 24 |
Oct 03 10:55:13 PM UTC 24 |
3587856424 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762446626 |
|
|
Oct 03 10:49:27 PM UTC 24 |
Oct 03 10:55:44 PM UTC 24 |
3223368680 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.89205957 |
|
|
Oct 03 10:10:42 PM UTC 24 |
Oct 03 10:55:50 PM UTC 24 |
9419112008 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3335890446 |
|
|
Oct 03 10:44:01 PM UTC 24 |
Oct 03 10:55:55 PM UTC 24 |
5248887316 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.626734175 |
|
|
Oct 03 09:34:54 PM UTC 24 |
Oct 03 10:55:56 PM UTC 24 |
16173705838 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.3087568753 |
|
|
Oct 03 10:47:18 PM UTC 24 |
Oct 03 10:56:15 PM UTC 24 |
5838369400 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.752628962 |
|
|
Oct 03 10:08:34 PM UTC 24 |
Oct 03 10:56:20 PM UTC 24 |
12684367656 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.62328201 |
|
|
Oct 03 10:47:35 PM UTC 24 |
Oct 03 10:56:25 PM UTC 24 |
5062377312 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1710143232 |
|
|
Oct 03 10:47:19 PM UTC 24 |
Oct 03 10:56:31 PM UTC 24 |
5737536924 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.1031357199 |
|
|
Oct 03 10:49:28 PM UTC 24 |
Oct 03 10:56:35 PM UTC 24 |
4700850292 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.2701121031 |
|
|
Oct 03 09:48:42 PM UTC 24 |
Oct 03 10:56:48 PM UTC 24 |
14823368584 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.552262403 |
|
|
Oct 03 09:35:02 PM UTC 24 |
Oct 03 10:57:13 PM UTC 24 |
17574859700 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852033809 |
|
|
Oct 03 10:51:26 PM UTC 24 |
Oct 03 10:57:14 PM UTC 24 |
3807882948 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1358757398 |
|
|
Oct 03 10:47:05 PM UTC 24 |
Oct 03 10:57:59 PM UTC 24 |
6264844728 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2099097003 |
|
|
Oct 03 10:50:45 PM UTC 24 |
Oct 03 10:58:00 PM UTC 24 |
3915805256 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2672609103 |
|
|
Oct 03 10:53:03 PM UTC 24 |
Oct 03 10:58:40 PM UTC 24 |
3240780924 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.238151361 |
|
|
Oct 03 10:49:11 PM UTC 24 |
Oct 03 10:58:50 PM UTC 24 |
5543119504 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.317486852 |
|
|
Oct 03 10:51:42 PM UTC 24 |
Oct 03 10:58:52 PM UTC 24 |
5148344374 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1666524591 |
|
|
Oct 03 10:53:44 PM UTC 24 |
Oct 03 10:59:00 PM UTC 24 |
3135633112 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.3593952496 |
|
|
Oct 03 10:47:39 PM UTC 24 |
Oct 03 10:59:18 PM UTC 24 |
5993030204 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.139671458 |
|
|
Oct 03 10:53:05 PM UTC 24 |
Oct 03 10:59:20 PM UTC 24 |
3615154900 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878026457 |
|
|
Oct 03 10:53:06 PM UTC 24 |
Oct 03 10:59:38 PM UTC 24 |
4442713940 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477991764 |
|
|
Oct 03 10:53:04 PM UTC 24 |
Oct 03 10:59:38 PM UTC 24 |
4031385544 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3117812067 |
|
|
Oct 03 10:53:11 PM UTC 24 |
Oct 03 10:59:41 PM UTC 24 |
4105142400 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.241442690 |
|
|
Oct 03 10:51:06 PM UTC 24 |
Oct 03 10:59:46 PM UTC 24 |
4345940950 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.297573101 |
|
|
Oct 03 09:57:14 PM UTC 24 |
Oct 03 11:00:08 PM UTC 24 |
14001788850 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543167770 |
|
|
Oct 03 10:53:00 PM UTC 24 |
Oct 03 11:00:10 PM UTC 24 |
3251693080 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2540225190 |
|
|
Oct 03 10:50:13 PM UTC 24 |
Oct 03 11:00:45 PM UTC 24 |
5138646424 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.148731435 |
|
|
Oct 03 10:54:58 PM UTC 24 |
Oct 03 11:00:58 PM UTC 24 |
4160441944 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.622783393 |
|
|
Oct 03 10:17:11 PM UTC 24 |
Oct 03 11:01:00 PM UTC 24 |
13595725832 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2471880631 |
|
|
Oct 03 10:55:25 PM UTC 24 |
Oct 03 11:01:15 PM UTC 24 |
3535760396 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.1612669500 |
|
|
Oct 03 10:53:01 PM UTC 24 |
Oct 03 11:01:24 PM UTC 24 |
5014556568 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3769396652 |
|
|
Oct 03 10:55:27 PM UTC 24 |
Oct 03 11:01:44 PM UTC 24 |
3386398450 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1581043203 |
|
|
Oct 03 10:53:12 PM UTC 24 |
Oct 03 11:01:54 PM UTC 24 |
4272719416 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3369013479 |
|
|
Oct 03 10:55:28 PM UTC 24 |
Oct 03 11:02:10 PM UTC 24 |
4333324100 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.3459585668 |
|
|
Oct 03 10:53:10 PM UTC 24 |
Oct 03 11:02:24 PM UTC 24 |
5188267204 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1567019005 |
|
|
Oct 03 10:55:16 PM UTC 24 |
Oct 03 11:02:49 PM UTC 24 |
3664600776 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.3897115190 |
|
|
Oct 03 10:51:56 PM UTC 24 |
Oct 03 11:03:01 PM UTC 24 |
6073422212 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.2185010010 |
|
|
Oct 03 10:53:54 PM UTC 24 |
Oct 03 11:03:46 PM UTC 24 |
4477754474 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437510081 |
|
|
Oct 03 10:58:24 PM UTC 24 |
Oct 03 11:03:58 PM UTC 24 |
3560380326 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.1604075166 |
|
|
Oct 03 10:55:27 PM UTC 24 |
Oct 03 11:04:08 PM UTC 24 |
4416183496 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.761218478 |
|
|
Oct 03 10:53:07 PM UTC 24 |
Oct 03 11:04:10 PM UTC 24 |
5240392956 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.875864434 |
|
|
Oct 03 10:58:20 PM UTC 24 |
Oct 03 11:04:24 PM UTC 24 |
3591564912 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.402992957 |
|
|
Oct 03 10:55:23 PM UTC 24 |
Oct 03 11:04:33 PM UTC 24 |
5581574420 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.3510874415 |
|
|
Oct 03 10:56:02 PM UTC 24 |
Oct 03 11:04:37 PM UTC 24 |
4680520000 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.2289283996 |
|
|
Oct 03 10:56:52 PM UTC 24 |
Oct 03 11:05:05 PM UTC 24 |
4164802298 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.956190191 |
|
|
Oct 03 10:58:46 PM UTC 24 |
Oct 03 11:05:06 PM UTC 24 |
3945632760 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.1569119379 |
|
|
Oct 03 10:56:12 PM UTC 24 |
Oct 03 11:05:20 PM UTC 24 |
5947974184 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.378137705 |
|
|
Oct 03 10:55:26 PM UTC 24 |
Oct 03 11:05:21 PM UTC 24 |
5451874782 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105876795 |
|
|
Oct 03 10:58:49 PM UTC 24 |
Oct 03 11:05:33 PM UTC 24 |
4436804584 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2916070018 |
|
|
Oct 03 10:58:24 PM UTC 24 |
Oct 03 11:05:48 PM UTC 24 |
3671392648 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2770714948 |
|
|
Oct 03 10:54:49 PM UTC 24 |
Oct 03 11:05:49 PM UTC 24 |
5186683288 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.596809014 |
|
|
Oct 03 10:59:00 PM UTC 24 |
Oct 03 11:05:52 PM UTC 24 |
3418603544 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.627964967 |
|
|
Oct 03 11:00:31 PM UTC 24 |
Oct 03 11:05:59 PM UTC 24 |
3378205630 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081536591 |
|
|
Oct 03 10:59:04 PM UTC 24 |
Oct 03 11:06:10 PM UTC 24 |
3994905750 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363206843 |
|
|
Oct 03 10:59:59 PM UTC 24 |
Oct 03 11:06:17 PM UTC 24 |
3944772944 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756950355 |
|
|
Oct 03 10:59:46 PM UTC 24 |
Oct 03 11:06:21 PM UTC 24 |
3858640654 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.3086773535 |
|
|
Oct 03 10:18:18 PM UTC 24 |
Oct 03 11:06:33 PM UTC 24 |
13348648208 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1243703166 |
|
|
Oct 03 10:58:23 PM UTC 24 |
Oct 03 11:06:54 PM UTC 24 |
5539695820 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.2027324343 |
|
|
Oct 03 10:58:19 PM UTC 24 |
Oct 03 11:06:58 PM UTC 24 |
4263485840 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911848264 |
|
|
Oct 03 11:01:26 PM UTC 24 |
Oct 03 11:07:07 PM UTC 24 |
3791602042 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.833993446 |
|
|
Oct 03 10:59:00 PM UTC 24 |
Oct 03 11:07:12 PM UTC 24 |
4456518200 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3907193697 |
|
|
Oct 03 11:01:21 PM UTC 24 |
Oct 03 11:07:20 PM UTC 24 |
4111618310 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1075667308 |
|
|
Oct 03 11:02:30 PM UTC 24 |
Oct 03 11:07:59 PM UTC 24 |
3748821336 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.1207141330 |
|
|
Oct 03 10:58:20 PM UTC 24 |
Oct 03 11:08:00 PM UTC 24 |
4649165600 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.959095133 |
|
|
Oct 03 10:58:59 PM UTC 24 |
Oct 03 11:08:06 PM UTC 24 |
5503237152 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604044984 |
|
|
Oct 03 11:01:38 PM UTC 24 |
Oct 03 11:08:21 PM UTC 24 |
3366126256 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2123823254 |
|
|
Oct 03 10:58:33 PM UTC 24 |
Oct 03 11:08:39 PM UTC 24 |
5554095018 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1370847770 |
|
|
Oct 03 11:03:11 PM UTC 24 |
Oct 03 11:09:18 PM UTC 24 |
3597196220 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108483904 |
|
|
Oct 03 11:03:21 PM UTC 24 |
Oct 03 11:09:21 PM UTC 24 |
3972171180 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.49517526 |
|
|
Oct 03 11:03:51 PM UTC 24 |
Oct 03 11:09:22 PM UTC 24 |
4147147932 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.994109449 |
|
|
Oct 03 11:02:47 PM UTC 24 |
Oct 03 11:09:25 PM UTC 24 |
3947059748 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2930001811 |
|
|
Oct 03 11:03:22 PM UTC 24 |
Oct 03 11:09:27 PM UTC 24 |
3860338050 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.471152993 |
|
|
Oct 03 11:03:01 PM UTC 24 |
Oct 03 11:09:52 PM UTC 24 |
4410678036 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.514192852 |
|
|
Oct 03 10:58:53 PM UTC 24 |
Oct 03 11:10:18 PM UTC 24 |
5387800492 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.701683494 |
|
|
Oct 03 11:01:38 PM UTC 24 |
Oct 03 11:10:26 PM UTC 24 |
5617999688 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993631338 |
|
|
Oct 03 11:03:45 PM UTC 24 |
Oct 03 11:10:46 PM UTC 24 |
4041068090 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1385039057 |
|
|
Oct 03 11:01:37 PM UTC 24 |
Oct 03 11:10:48 PM UTC 24 |
6450762360 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.411401877 |
|
|
Oct 03 11:01:10 PM UTC 24 |
Oct 03 11:11:01 PM UTC 24 |
5081408152 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851372435 |
|
|
Oct 03 11:04:48 PM UTC 24 |
Oct 03 11:11:11 PM UTC 24 |
3737547576 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.1358572119 |
|
|
Oct 03 11:04:24 PM UTC 24 |
Oct 03 11:12:11 PM UTC 24 |
5269233444 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.2621861774 |
|
|
Oct 03 11:01:07 PM UTC 24 |
Oct 03 11:12:26 PM UTC 24 |
6281574984 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.2867931100 |
|
|
Oct 03 11:01:57 PM UTC 24 |
Oct 03 11:12:43 PM UTC 24 |
5899539622 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.105304559 |
|
|
Oct 03 11:02:58 PM UTC 24 |
Oct 03 11:12:46 PM UTC 24 |
4632359660 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.51432826 |
|
|
Oct 03 11:03:49 PM UTC 24 |
Oct 03 11:13:00 PM UTC 24 |
5275392878 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1172791980 |
|
|
Oct 03 11:07:00 PM UTC 24 |
Oct 03 11:13:02 PM UTC 24 |
3853678140 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.169025760 |
|
|
Oct 03 11:03:51 PM UTC 24 |
Oct 03 11:13:03 PM UTC 24 |
4881995102 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.1999272861 |
|
|
Oct 03 11:03:12 PM UTC 24 |
Oct 03 11:13:04 PM UTC 24 |
5727650930 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.2196861702 |
|
|
Oct 03 11:03:20 PM UTC 24 |
Oct 03 11:13:07 PM UTC 24 |
4697004200 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2516875613 |
|
|
Oct 03 10:04:55 PM UTC 24 |
Oct 03 11:13:09 PM UTC 24 |
15599307416 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.853142166 |
|
|
Oct 03 11:03:43 PM UTC 24 |
Oct 03 11:13:59 PM UTC 24 |
5633370950 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.3721078074 |
|
|
Oct 03 11:05:34 PM UTC 24 |
Oct 03 11:14:07 PM UTC 24 |
4699222350 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192933036 |
|
|
Oct 03 11:09:06 PM UTC 24 |
Oct 03 11:14:07 PM UTC 24 |
3924642840 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.897608336 |
|
|
Oct 03 11:08:05 PM UTC 24 |
Oct 03 11:14:36 PM UTC 24 |
4040494168 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3804942145 |
|
|
Oct 03 11:09:05 PM UTC 24 |
Oct 03 11:14:55 PM UTC 24 |
4483780120 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.947445423 |
|
|
Oct 03 11:07:22 PM UTC 24 |
Oct 03 11:15:16 PM UTC 24 |
3781605834 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1289385455 |
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Oct 03 11:09:53 PM UTC 24 |
Oct 03 11:15:27 PM UTC 24 |
3688512328 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558077922 |
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|
Oct 03 11:09:21 PM UTC 24 |
Oct 03 11:15:29 PM UTC 24 |
4106424970 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.1345325452 |
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|
Oct 03 06:33:41 PM UTC 24 |
Oct 03 11:15:41 PM UTC 24 |
67583745493 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963542435 |
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|
Oct 03 11:09:24 PM UTC 24 |
Oct 03 11:15:44 PM UTC 24 |
3929997310 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.4200930076 |
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|
Oct 03 11:06:14 PM UTC 24 |
Oct 03 11:16:10 PM UTC 24 |
5821458080 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1923480856 |
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|
Oct 03 11:08:49 PM UTC 24 |
Oct 03 11:16:26 PM UTC 24 |
5746491870 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.1717012176 |
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|
Oct 03 11:09:26 PM UTC 24 |
Oct 03 11:16:55 PM UTC 24 |
5112516784 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.884613115 |
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|
Oct 03 11:08:45 PM UTC 24 |
Oct 03 11:17:11 PM UTC 24 |
5488725860 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.1381441046 |
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|
Oct 03 11:09:25 PM UTC 24 |
Oct 03 11:17:31 PM UTC 24 |
4443846216 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2875735018 |
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|
Oct 03 11:09:58 PM UTC 24 |
Oct 03 11:17:32 PM UTC 24 |
5911516556 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.2996114809 |
|
|
Oct 03 11:09:47 PM UTC 24 |
Oct 03 11:17:37 PM UTC 24 |
4725925000 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3079003115 |
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|
Oct 03 11:09:57 PM UTC 24 |
Oct 03 11:17:43 PM UTC 24 |
5367142400 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.920141639 |
|
|
Oct 03 11:09:12 PM UTC 24 |
Oct 03 11:18:01 PM UTC 24 |
5811948550 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.733746044 |
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|
Oct 03 11:08:47 PM UTC 24 |
Oct 03 11:18:12 PM UTC 24 |
6402308824 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.2431827106 |
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|
Oct 03 11:09:12 PM UTC 24 |
Oct 03 11:18:19 PM UTC 24 |
5554873448 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.1636077574 |
|
|
Oct 03 11:08:45 PM UTC 24 |
Oct 03 11:18:30 PM UTC 24 |
5125756760 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.598519329 |
|
|
Oct 03 11:09:13 PM UTC 24 |
Oct 03 11:18:40 PM UTC 24 |
5485942160 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.1914247550 |
|
|
Oct 03 11:09:31 PM UTC 24 |
Oct 03 11:18:54 PM UTC 24 |
4901138108 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1986103543 |
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|
Oct 03 11:09:57 PM UTC 24 |
Oct 03 11:18:56 PM UTC 24 |
4875309358 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.3210000632 |
|
|
Oct 03 11:09:46 PM UTC 24 |
Oct 03 11:18:59 PM UTC 24 |
5640774020 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2518713947 |
|
|
Oct 03 11:09:34 PM UTC 24 |
Oct 03 11:19:03 PM UTC 24 |
4750681204 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.742010214 |
|
|
Oct 03 11:09:58 PM UTC 24 |
Oct 03 11:20:03 PM UTC 24 |
5688999448 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1454635538 |
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|
Oct 03 08:57:37 PM UTC 24 |
Oct 03 11:20:55 PM UTC 24 |
28805616408 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.104733623 |
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|
Oct 03 09:35:02 PM UTC 24 |
Oct 03 11:32:17 PM UTC 24 |
25556165874 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.2449120984 |
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|
Oct 03 10:07:34 PM UTC 24 |
Oct 03 11:48:51 PM UTC 24 |
24967267320 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.3625159659 |
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|
Oct 03 10:07:26 PM UTC 24 |
Oct 03 11:50:11 PM UTC 24 |
26392004130 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.992740223 |
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Oct 03 06:33:19 PM UTC 24 |
Oct 03 11:54:15 PM UTC 24 |
81679214001 ps |