| T1783 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.404722408 |
|
|
Oct 03 02:37:39 PM UTC 24 |
Oct 03 02:39:41 PM UTC 24 |
6207076297 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.3503679176 |
|
|
Oct 03 02:39:20 PM UTC 24 |
Oct 03 02:39:59 PM UTC 24 |
350892456 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.434657802 |
|
|
Oct 03 02:39:21 PM UTC 24 |
Oct 03 02:40:03 PM UTC 24 |
688061344 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.341478606 |
|
|
Oct 03 02:39:53 PM UTC 24 |
Oct 03 02:40:07 PM UTC 24 |
64747382 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.3419526631 |
|
|
Oct 03 02:39:57 PM UTC 24 |
Oct 03 02:40:09 PM UTC 24 |
36496438 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.833117216 |
|
|
Oct 03 02:37:04 PM UTC 24 |
Oct 03 02:40:09 PM UTC 24 |
1995992471 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.313835400 |
|
|
Oct 03 02:39:42 PM UTC 24 |
Oct 03 02:40:12 PM UTC 24 |
221521320 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.2982272127 |
|
|
Oct 03 02:39:39 PM UTC 24 |
Oct 03 02:40:12 PM UTC 24 |
276011057 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.561349356 |
|
|
Oct 03 02:31:11 PM UTC 24 |
Oct 03 02:40:12 PM UTC 24 |
29724076706 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2831336695 |
|
|
Oct 03 02:37:01 PM UTC 24 |
Oct 03 02:40:22 PM UTC 24 |
483248116 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1242414966 |
|
|
Oct 03 02:27:56 PM UTC 24 |
Oct 03 02:40:35 PM UTC 24 |
80554174637 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2084106239 |
|
|
Oct 03 02:40:36 PM UTC 24 |
Oct 03 02:40:45 PM UTC 24 |
54821610 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.859687910 |
|
|
Oct 03 02:35:22 PM UTC 24 |
Oct 03 02:40:47 PM UTC 24 |
6834652028 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3997884028 |
|
|
Oct 03 02:40:37 PM UTC 24 |
Oct 03 02:40:47 PM UTC 24 |
49906090 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.2128021690 |
|
|
Oct 03 02:35:48 PM UTC 24 |
Oct 03 02:40:50 PM UTC 24 |
3195578838 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.4204012544 |
|
|
Oct 03 02:39:16 PM UTC 24 |
Oct 03 02:40:50 PM UTC 24 |
4690425715 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.81918170 |
|
|
Oct 03 02:39:11 PM UTC 24 |
Oct 03 02:40:58 PM UTC 24 |
7599825384 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.774576601 |
|
|
Oct 03 02:40:08 PM UTC 24 |
Oct 03 02:41:03 PM UTC 24 |
992491541 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2527792584 |
|
|
Oct 03 02:38:49 PM UTC 24 |
Oct 03 02:41:09 PM UTC 24 |
435391728 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3104498557 |
|
|
Oct 03 02:40:48 PM UTC 24 |
Oct 03 02:41:13 PM UTC 24 |
157783850 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.218260926 |
|
|
Oct 03 02:35:36 PM UTC 24 |
Oct 03 02:41:15 PM UTC 24 |
6593082037 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2559304093 |
|
|
Oct 03 02:40:35 PM UTC 24 |
Oct 03 02:41:34 PM UTC 24 |
84689131 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.898410936 |
|
|
Oct 03 02:40:40 PM UTC 24 |
Oct 03 02:41:36 PM UTC 24 |
602110377 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3825777489 |
|
|
Oct 03 02:40:40 PM UTC 24 |
Oct 03 02:41:53 PM UTC 24 |
3740850843 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1325222637 |
|
|
Oct 03 02:41:27 PM UTC 24 |
Oct 03 02:41:58 PM UTC 24 |
719076957 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.4058442644 |
|
|
Oct 03 02:41:13 PM UTC 24 |
Oct 03 02:42:00 PM UTC 24 |
442036325 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2560924970 |
|
|
Oct 03 02:41:16 PM UTC 24 |
Oct 03 02:42:03 PM UTC 24 |
402267798 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1162560028 |
|
|
Oct 03 02:31:09 PM UTC 24 |
Oct 03 02:42:03 PM UTC 24 |
56834008259 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.1301287196 |
|
|
Oct 03 02:42:06 PM UTC 24 |
Oct 03 02:42:17 PM UTC 24 |
49397583 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.3243177890 |
|
|
Oct 03 02:41:21 PM UTC 24 |
Oct 03 02:42:19 PM UTC 24 |
1012065209 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.4218468436 |
|
|
Oct 03 02:41:11 PM UTC 24 |
Oct 03 02:42:28 PM UTC 24 |
893643815 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.27743583 |
|
|
Oct 03 02:42:33 PM UTC 24 |
Oct 03 02:44:17 PM UTC 24 |
2302898664 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1106186961 |
|
|
Oct 03 02:42:20 PM UTC 24 |
Oct 03 02:42:30 PM UTC 24 |
44573629 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3006573575 |
|
|
Oct 03 02:06:06 PM UTC 24 |
Oct 03 02:42:36 PM UTC 24 |
110581404331 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.2773224599 |
|
|
Oct 03 02:39:29 PM UTC 24 |
Oct 03 02:42:49 PM UTC 24 |
9490816769 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3722478432 |
|
|
Oct 03 02:35:50 PM UTC 24 |
Oct 03 02:42:49 PM UTC 24 |
4542213879 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3524398186 |
|
|
Oct 03 02:40:39 PM UTC 24 |
Oct 03 02:43:06 PM UTC 24 |
10502996879 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.3102019718 |
|
|
Oct 03 02:42:32 PM UTC 24 |
Oct 03 02:43:08 PM UTC 24 |
261262658 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.217140746 |
|
|
Oct 03 02:36:29 PM UTC 24 |
Oct 03 02:43:18 PM UTC 24 |
24047992427 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2151064327 |
|
|
Oct 03 02:29:35 PM UTC 24 |
Oct 03 02:43:20 PM UTC 24 |
73514172556 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1739527926 |
|
|
Oct 03 02:22:19 PM UTC 24 |
Oct 03 02:43:30 PM UTC 24 |
77391112671 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3336417956 |
|
|
Oct 03 02:42:25 PM UTC 24 |
Oct 03 02:43:42 PM UTC 24 |
6587289018 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.747532471 |
|
|
Oct 03 02:43:16 PM UTC 24 |
Oct 03 02:43:44 PM UTC 24 |
150497213 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.3987536324 |
|
|
Oct 03 02:43:17 PM UTC 24 |
Oct 03 02:43:57 PM UTC 24 |
315047353 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.792098544 |
|
|
Oct 03 02:43:03 PM UTC 24 |
Oct 03 02:44:03 PM UTC 24 |
463130876 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.4043036001 |
|
|
Oct 03 02:42:29 PM UTC 24 |
Oct 03 02:44:08 PM UTC 24 |
5613014404 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1633489580 |
|
|
Oct 03 02:40:26 PM UTC 24 |
Oct 03 02:44:13 PM UTC 24 |
851431061 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3495791828 |
|
|
Oct 03 02:44:05 PM UTC 24 |
Oct 03 02:44:16 PM UTC 24 |
39278183 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3564337210 |
|
|
Oct 03 02:44:10 PM UTC 24 |
Oct 03 02:44:18 PM UTC 24 |
47382211 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.3551249374 |
|
|
Oct 03 02:27:56 PM UTC 24 |
Oct 03 02:44:24 PM UTC 24 |
49080068284 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.634316727 |
|
|
Oct 03 02:38:41 PM UTC 24 |
Oct 03 02:44:25 PM UTC 24 |
3233060080 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3149365060 |
|
|
Oct 03 02:43:32 PM UTC 24 |
Oct 03 02:44:26 PM UTC 24 |
955159247 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.1833462839 |
|
|
Oct 03 01:18:31 PM UTC 24 |
Oct 03 02:44:28 PM UTC 24 |
27814004072 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.4072670510 |
|
|
Oct 03 02:42:55 PM UTC 24 |
Oct 03 02:44:38 PM UTC 24 |
1621948327 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1204244338 |
|
|
Oct 03 02:41:40 PM UTC 24 |
Oct 03 02:44:49 PM UTC 24 |
4391191637 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.395471535 |
|
|
Oct 03 02:26:59 PM UTC 24 |
Oct 03 02:45:00 PM UTC 24 |
97867414156 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.2461291509 |
|
|
Oct 03 02:44:35 PM UTC 24 |
Oct 03 02:45:09 PM UTC 24 |
298657476 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.1977939968 |
|
|
Oct 03 02:44:52 PM UTC 24 |
Oct 03 02:45:18 PM UTC 24 |
200813095 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.1476859020 |
|
|
Oct 03 02:38:47 PM UTC 24 |
Oct 03 02:45:19 PM UTC 24 |
9962939770 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.2435948670 |
|
|
Oct 03 02:39:28 PM UTC 24 |
Oct 03 02:45:20 PM UTC 24 |
28576219823 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.3985939672 |
|
|
Oct 03 02:40:28 PM UTC 24 |
Oct 03 02:45:23 PM UTC 24 |
2916325137 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.4027632849 |
|
|
Oct 03 02:44:40 PM UTC 24 |
Oct 03 02:45:30 PM UTC 24 |
332075558 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.414681732 |
|
|
Oct 03 02:44:55 PM UTC 24 |
Oct 03 02:45:39 PM UTC 24 |
283724455 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.1760598372 |
|
|
Oct 03 02:41:32 PM UTC 24 |
Oct 03 02:45:42 PM UTC 24 |
2519947829 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.2274024984 |
|
|
Oct 03 02:43:49 PM UTC 24 |
Oct 03 02:45:52 PM UTC 24 |
3274655954 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.3019473900 |
|
|
Oct 03 02:45:49 PM UTC 24 |
Oct 03 02:46:01 PM UTC 24 |
245807258 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1974669494 |
|
|
Oct 03 02:45:49 PM UTC 24 |
Oct 03 02:46:01 PM UTC 24 |
50076127 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4127044563 |
|
|
Oct 03 02:45:05 PM UTC 24 |
Oct 03 02:46:06 PM UTC 24 |
843956247 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.3077080756 |
|
|
Oct 03 02:44:25 PM UTC 24 |
Oct 03 02:46:19 PM UTC 24 |
8104949301 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.3653575873 |
|
|
Oct 03 02:44:53 PM UTC 24 |
Oct 03 02:46:41 PM UTC 24 |
2537726668 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.779519671 |
|
|
Oct 03 02:44:29 PM UTC 24 |
Oct 03 02:46:51 PM UTC 24 |
6667316423 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2292747405 |
|
|
Oct 03 02:17:07 PM UTC 24 |
Oct 03 02:46:52 PM UTC 24 |
100106459214 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.4114329994 |
|
|
Oct 03 02:46:12 PM UTC 24 |
Oct 03 02:47:01 PM UTC 24 |
445513825 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3867637483 |
|
|
Oct 03 02:44:45 PM UTC 24 |
Oct 03 02:47:16 PM UTC 24 |
3514194476 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.3065592184 |
|
|
Oct 03 02:45:52 PM UTC 24 |
Oct 03 02:47:22 PM UTC 24 |
8583197267 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.4193400410 |
|
|
Oct 03 02:46:49 PM UTC 24 |
Oct 03 02:47:37 PM UTC 24 |
1630398993 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1635153085 |
|
|
Oct 03 02:47:18 PM UTC 24 |
Oct 03 02:47:40 PM UTC 24 |
316323540 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.41309370 |
|
|
Oct 03 02:47:18 PM UTC 24 |
Oct 03 02:47:44 PM UTC 24 |
404113800 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3894269166 |
|
|
Oct 03 02:25:36 PM UTC 24 |
Oct 03 02:47:47 PM UTC 24 |
68984567216 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1846594637 |
|
|
Oct 03 02:46:08 PM UTC 24 |
Oct 03 02:47:52 PM UTC 24 |
2307186007 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.635215489 |
|
|
Oct 03 02:36:57 PM UTC 24 |
Oct 03 02:47:58 PM UTC 24 |
18150158114 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2527273564 |
|
|
Oct 03 02:45:55 PM UTC 24 |
Oct 03 02:48:04 PM UTC 24 |
4997491661 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1509014096 |
|
|
Oct 03 02:43:57 PM UTC 24 |
Oct 03 02:48:09 PM UTC 24 |
679029978 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1359697617 |
|
|
Oct 03 02:48:06 PM UTC 24 |
Oct 03 02:48:15 PM UTC 24 |
44036933 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3547492494 |
|
|
Oct 03 02:48:08 PM UTC 24 |
Oct 03 02:48:18 PM UTC 24 |
49545577 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.3036660911 |
|
|
Oct 03 02:46:28 PM UTC 24 |
Oct 03 02:48:29 PM UTC 24 |
4702076463 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.700646645 |
|
|
Oct 03 02:38:43 PM UTC 24 |
Oct 03 02:48:30 PM UTC 24 |
3772102812 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1185079359 |
|
|
Oct 03 02:46:29 PM UTC 24 |
Oct 03 02:48:32 PM UTC 24 |
1773303656 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1576199823 |
|
|
Oct 03 02:48:22 PM UTC 24 |
Oct 03 02:48:41 PM UTC 24 |
109440457 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3372849386 |
|
|
Oct 03 02:47:08 PM UTC 24 |
Oct 03 02:48:42 PM UTC 24 |
1905962366 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.783283550 |
|
|
Oct 03 02:32:54 PM UTC 24 |
Oct 03 02:48:45 PM UTC 24 |
97421800588 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.685467862 |
|
|
Oct 03 02:47:47 PM UTC 24 |
Oct 03 02:49:01 PM UTC 24 |
1733197876 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1197022500 |
|
|
Oct 03 02:49:00 PM UTC 24 |
Oct 03 02:49:15 PM UTC 24 |
206174023 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.3351811581 |
|
|
Oct 03 02:32:58 PM UTC 24 |
Oct 03 02:49:16 PM UTC 24 |
57033989141 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.3682306362 |
|
|
Oct 03 02:48:46 PM UTC 24 |
Oct 03 02:49:20 PM UTC 24 |
485273730 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.1018548144 |
|
|
Oct 03 02:45:16 PM UTC 24 |
Oct 03 02:49:23 PM UTC 24 |
2696689821 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3463032650 |
|
|
Oct 03 02:48:58 PM UTC 24 |
Oct 03 02:49:25 PM UTC 24 |
237177262 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2081429921 |
|
|
Oct 03 02:15:04 PM UTC 24 |
Oct 03 02:49:26 PM UTC 24 |
120084264640 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.2126515053 |
|
|
Oct 03 02:49:10 PM UTC 24 |
Oct 03 02:49:28 PM UTC 24 |
60724372 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.943925112 |
|
|
Oct 03 02:49:08 PM UTC 24 |
Oct 03 02:49:31 PM UTC 24 |
261205591 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.1468305785 |
|
|
Oct 03 02:40:09 PM UTC 24 |
Oct 03 02:49:39 PM UTC 24 |
10709771454 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.2459580103 |
|
|
Oct 03 02:48:32 PM UTC 24 |
Oct 03 02:49:44 PM UTC 24 |
577798642 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2701949324 |
|
|
Oct 03 02:37:44 PM UTC 24 |
Oct 03 02:49:49 PM UTC 24 |
57051825744 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.540373317 |
|
|
Oct 03 02:49:42 PM UTC 24 |
Oct 03 02:49:50 PM UTC 24 |
50407757 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3815577673 |
|
|
Oct 03 02:49:46 PM UTC 24 |
Oct 03 02:49:55 PM UTC 24 |
44489678 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2076199478 |
|
|
Oct 03 02:48:19 PM UTC 24 |
Oct 03 02:50:09 PM UTC 24 |
5063078003 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2967432144 |
|
|
Oct 03 02:45:37 PM UTC 24 |
Oct 03 02:50:14 PM UTC 24 |
6191312935 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.1551494146 |
|
|
Oct 03 02:37:48 PM UTC 24 |
Oct 03 02:50:22 PM UTC 24 |
46300249064 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3474557093 |
|
|
Oct 03 02:49:58 PM UTC 24 |
Oct 03 02:50:24 PM UTC 24 |
175802882 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3796114698 |
|
|
Oct 03 02:41:39 PM UTC 24 |
Oct 03 02:50:38 PM UTC 24 |
5421765073 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.1052586874 |
|
|
Oct 03 02:49:57 PM UTC 24 |
Oct 03 02:50:43 PM UTC 24 |
846112201 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.798896700 |
|
|
Oct 03 02:43:35 PM UTC 24 |
Oct 03 02:50:55 PM UTC 24 |
9860503943 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.699793687 |
|
|
Oct 03 01:42:33 PM UTC 24 |
Oct 03 02:50:57 PM UTC 24 |
30981814385 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.902394370 |
|
|
Oct 03 02:48:11 PM UTC 24 |
Oct 03 02:51:09 PM UTC 24 |
11315248045 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1272639138 |
|
|
Oct 03 02:50:51 PM UTC 24 |
Oct 03 02:51:18 PM UTC 24 |
643728017 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2885087924 |
|
|
Oct 03 02:42:03 PM UTC 24 |
Oct 03 02:51:30 PM UTC 24 |
7894785118 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.410933821 |
|
|
Oct 03 02:51:23 PM UTC 24 |
Oct 03 02:51:31 PM UTC 24 |
49629153 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.2626736694 |
|
|
Oct 03 02:49:51 PM UTC 24 |
Oct 03 02:51:31 PM UTC 24 |
7449299809 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.548928297 |
|
|
Oct 03 02:50:43 PM UTC 24 |
Oct 03 02:51:38 PM UTC 24 |
818618875 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.965774289 |
|
|
Oct 03 02:48:55 PM UTC 24 |
Oct 03 02:51:47 PM UTC 24 |
9556189928 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2118501158 |
|
|
Oct 03 02:51:37 PM UTC 24 |
Oct 03 02:51:47 PM UTC 24 |
47395406 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.507063755 |
|
|
Oct 03 02:49:53 PM UTC 24 |
Oct 03 02:51:52 PM UTC 24 |
4760256315 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.5267048 |
|
|
Oct 03 02:50:39 PM UTC 24 |
Oct 03 02:51:56 PM UTC 24 |
1699517792 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1959414571 |
|
|
Oct 03 02:50:24 PM UTC 24 |
Oct 03 02:51:56 PM UTC 24 |
2693168937 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2807501429 |
|
|
Oct 03 02:51:57 PM UTC 24 |
Oct 03 02:52:07 PM UTC 24 |
28351694 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.2837083699 |
|
|
Oct 03 02:51:58 PM UTC 24 |
Oct 03 02:52:07 PM UTC 24 |
56040403 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3097735123 |
|
|
Oct 03 03:08:49 PM UTC 24 |
Oct 03 03:09:05 PM UTC 24 |
182176949 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2208804566 |
|
|
Oct 03 02:36:26 PM UTC 24 |
Oct 03 02:52:09 PM UTC 24 |
93793149854 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.1467031809 |
|
|
Oct 03 02:42:43 PM UTC 24 |
Oct 03 02:52:11 PM UTC 24 |
62898432221 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2308131950 |
|
|
Oct 03 02:49:42 PM UTC 24 |
Oct 03 02:52:14 PM UTC 24 |
3704129904 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.2662412379 |
|
|
Oct 03 02:41:11 PM UTC 24 |
Oct 03 02:52:18 PM UTC 24 |
40016308303 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.2446434866 |
|
|
Oct 03 02:50:18 PM UTC 24 |
Oct 03 02:52:24 PM UTC 24 |
1939521513 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.4073354515 |
|
|
Oct 03 02:34:36 PM UTC 24 |
Oct 03 02:52:37 PM UTC 24 |
87161888587 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2247186147 |
|
|
Oct 03 02:43:47 PM UTC 24 |
Oct 03 02:52:42 PM UTC 24 |
3592902919 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2897290842 |
|
|
Oct 03 02:51:25 PM UTC 24 |
Oct 03 02:52:42 PM UTC 24 |
208320142 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1763722688 |
|
|
Oct 03 02:52:24 PM UTC 24 |
Oct 03 02:52:59 PM UTC 24 |
232865005 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.980698527 |
|
|
Oct 03 02:52:16 PM UTC 24 |
Oct 03 02:53:03 PM UTC 24 |
561143574 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.413916408 |
|
|
Oct 03 02:47:41 PM UTC 24 |
Oct 03 02:53:03 PM UTC 24 |
2720678947 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4130299368 |
|
|
Oct 03 02:45:47 PM UTC 24 |
Oct 03 02:53:03 PM UTC 24 |
3446391756 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.589991976 |
|
|
Oct 03 02:52:23 PM UTC 24 |
Oct 03 02:53:04 PM UTC 24 |
1021796380 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3523940925 |
|
|
Oct 03 02:52:50 PM UTC 24 |
Oct 03 02:53:08 PM UTC 24 |
233609741 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2131066960 |
|
|
Oct 03 02:48:03 PM UTC 24 |
Oct 03 02:53:13 PM UTC 24 |
3267231386 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3718832450 |
|
|
Oct 03 02:53:02 PM UTC 24 |
Oct 03 02:53:14 PM UTC 24 |
56102852 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1334647979 |
|
|
Oct 03 02:52:38 PM UTC 24 |
Oct 03 02:53:14 PM UTC 24 |
725557844 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2828769993 |
|
|
Oct 03 01:58:45 PM UTC 24 |
Oct 03 02:53:15 PM UTC 24 |
17192675177 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.1682924640 |
|
|
Oct 03 02:49:13 PM UTC 24 |
Oct 03 02:53:16 PM UTC 24 |
2840449231 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.604756768 |
|
|
Oct 03 02:52:34 PM UTC 24 |
Oct 03 02:53:23 PM UTC 24 |
906200731 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.4194973256 |
|
|
Oct 03 02:20:39 PM UTC 24 |
Oct 03 02:53:34 PM UTC 24 |
107767721309 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.885215981 |
|
|
Oct 03 02:51:42 PM UTC 24 |
Oct 03 02:53:36 PM UTC 24 |
9723500619 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.701026626 |
|
|
Oct 03 02:45:29 PM UTC 24 |
Oct 03 02:53:50 PM UTC 24 |
6373025529 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.2159526823 |
|
|
Oct 03 02:53:30 PM UTC 24 |
Oct 03 02:53:52 PM UTC 24 |
128640227 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1855660485 |
|
|
Oct 03 02:51:53 PM UTC 24 |
Oct 03 02:53:52 PM UTC 24 |
5764180902 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.3504395155 |
|
|
Oct 03 02:53:37 PM UTC 24 |
Oct 03 02:54:00 PM UTC 24 |
160490234 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.4015655273 |
|
|
Oct 03 02:53:26 PM UTC 24 |
Oct 03 02:54:10 PM UTC 24 |
455853078 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2421225398 |
|
|
Oct 03 02:49:32 PM UTC 24 |
Oct 03 02:54:16 PM UTC 24 |
4813679595 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2543298987 |
|
|
Oct 03 02:53:43 PM UTC 24 |
Oct 03 02:54:17 PM UTC 24 |
623253136 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2056460245 |
|
|
Oct 03 02:44:43 PM UTC 24 |
Oct 03 02:54:18 PM UTC 24 |
38873816472 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.231169227 |
|
|
Oct 03 02:53:10 PM UTC 24 |
Oct 03 02:54:24 PM UTC 24 |
5153661223 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2568814086 |
|
|
Oct 03 02:53:32 PM UTC 24 |
Oct 03 02:54:27 PM UTC 24 |
410927150 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.2043713483 |
|
|
Oct 03 02:54:17 PM UTC 24 |
Oct 03 02:54:27 PM UTC 24 |
39505930 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.1326810342 |
|
|
Oct 03 02:53:42 PM UTC 24 |
Oct 03 02:54:28 PM UTC 24 |
641062101 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.1451302025 |
|
|
Oct 03 01:36:01 PM UTC 24 |
Oct 03 02:54:28 PM UTC 24 |
31234394774 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4064116356 |
|
|
Oct 03 02:54:18 PM UTC 24 |
Oct 03 02:54:30 PM UTC 24 |
53741676 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.402992216 |
|
|
Oct 03 02:57:43 PM UTC 24 |
Oct 03 02:57:57 PM UTC 24 |
75019715 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.1555340947 |
|
|
Oct 03 02:53:40 PM UTC 24 |
Oct 03 02:54:49 PM UTC 24 |
1826887714 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2170906257 |
|
|
Oct 03 02:52:18 PM UTC 24 |
Oct 03 02:55:01 PM UTC 24 |
10205921591 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3448695056 |
|
|
Oct 03 02:52:41 PM UTC 24 |
Oct 03 02:55:07 PM UTC 24 |
480254027 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.375015509 |
|
|
Oct 03 02:54:42 PM UTC 24 |
Oct 03 02:55:08 PM UTC 24 |
189334943 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.2323040397 |
|
|
Oct 03 02:44:42 PM UTC 24 |
Oct 03 02:55:12 PM UTC 24 |
57248802419 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.424104139 |
|
|
Oct 03 02:54:53 PM UTC 24 |
Oct 03 02:55:17 PM UTC 24 |
166141678 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2231436562 |
|
|
Oct 03 02:41:01 PM UTC 24 |
Oct 03 02:55:21 PM UTC 24 |
70741676015 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3370347016 |
|
|
Oct 03 02:53:11 PM UTC 24 |
Oct 03 02:55:22 PM UTC 24 |
9143935814 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.2349615714 |
|
|
Oct 03 02:50:51 PM UTC 24 |
Oct 03 02:55:23 PM UTC 24 |
2664853396 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2213175519 |
|
|
Oct 03 02:54:53 PM UTC 24 |
Oct 03 02:55:36 PM UTC 24 |
228098749 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.927621233 |
|
|
Oct 03 02:54:17 PM UTC 24 |
Oct 03 02:55:43 PM UTC 24 |
8315887562 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.967621395 |
|
|
Oct 03 02:55:37 PM UTC 24 |
Oct 03 02:55:49 PM UTC 24 |
204456300 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.2224168027 |
|
|
Oct 03 02:52:35 PM UTC 24 |
Oct 03 02:55:54 PM UTC 24 |
4068066866 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1464893359 |
|
|
Oct 03 02:55:44 PM UTC 24 |
Oct 03 02:55:54 PM UTC 24 |
44857361 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.1133935971 |
|
|
Oct 03 02:54:55 PM UTC 24 |
Oct 03 02:56:06 PM UTC 24 |
1674961133 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.889354419 |
|
|
Oct 03 02:55:50 PM UTC 24 |
Oct 03 02:56:09 PM UTC 24 |
116053016 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.31388664 |
|
|
Oct 03 02:54:51 PM UTC 24 |
Oct 03 02:56:09 PM UTC 24 |
655686250 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.587182757 |
|
|
Oct 03 02:54:54 PM UTC 24 |
Oct 03 02:56:10 PM UTC 24 |
1732677680 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.3267486668 |
|
|
Oct 03 02:54:38 PM UTC 24 |
Oct 03 02:56:14 PM UTC 24 |
2412990829 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.1832426942 |
|
|
Oct 03 02:56:03 PM UTC 24 |
Oct 03 02:56:32 PM UTC 24 |
202619483 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3334311206 |
|
|
Oct 03 02:55:35 PM UTC 24 |
Oct 03 02:56:40 PM UTC 24 |
609290697 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1377358088 |
|
|
Oct 03 02:54:25 PM UTC 24 |
Oct 03 02:56:41 PM UTC 24 |
7220951288 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.241113004 |
|
|
Oct 03 02:56:21 PM UTC 24 |
Oct 03 02:56:52 PM UTC 24 |
250218051 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1214429826 |
|
|
Oct 03 02:47:25 PM UTC 24 |
Oct 03 02:57:06 PM UTC 24 |
16222232701 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.29010958 |
|
|
Oct 03 02:51:07 PM UTC 24 |
Oct 03 02:57:09 PM UTC 24 |
880348751 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.207216283 |
|
|
Oct 03 02:56:32 PM UTC 24 |
Oct 03 02:57:19 PM UTC 24 |
441136183 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.803126988 |
|
|
Oct 03 02:42:48 PM UTC 24 |
Oct 03 02:57:20 PM UTC 24 |
45721451291 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1712507089 |
|
|
Oct 03 02:36:32 PM UTC 24 |
Oct 03 02:57:20 PM UTC 24 |
66174962829 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2512419054 |
|
|
Oct 03 02:34:45 PM UTC 24 |
Oct 03 02:57:25 PM UTC 24 |
88580659922 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.3808776395 |
|
|
Oct 03 02:56:35 PM UTC 24 |
Oct 03 02:57:26 PM UTC 24 |
872792813 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.791409910 |
|
|
Oct 03 02:53:30 PM UTC 24 |
Oct 03 02:57:26 PM UTC 24 |
19256157429 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3395603814 |
|
|
Oct 03 02:56:35 PM UTC 24 |
Oct 03 02:57:30 PM UTC 24 |
1710097049 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2270820286 |
|
|
Oct 03 02:55:30 PM UTC 24 |
Oct 03 02:57:31 PM UTC 24 |
449913738 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3775748061 |
|
|
Oct 03 02:57:21 PM UTC 24 |
Oct 03 02:57:32 PM UTC 24 |
178907993 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.866372818 |
|
|
Oct 03 02:55:49 PM UTC 24 |
Oct 03 02:57:37 PM UTC 24 |
6405004465 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.1005606621 |
|
|
Oct 03 02:54:43 PM UTC 24 |
Oct 03 02:57:42 PM UTC 24 |
12876297700 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3441696550 |
|
|
Oct 03 02:57:34 PM UTC 24 |
Oct 03 02:57:44 PM UTC 24 |
46906826 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1588038805 |
|
|
Oct 03 02:56:38 PM UTC 24 |
Oct 03 02:57:44 PM UTC 24 |
1204391873 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3441907907 |
|
|
Oct 03 02:50:03 PM UTC 24 |
Oct 03 02:57:48 PM UTC 24 |
32815002998 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.925778386 |
|
|
Oct 03 02:55:16 PM UTC 24 |
Oct 03 02:57:56 PM UTC 24 |
3311111477 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.3049070247 |
|
|
Oct 03 01:55:34 PM UTC 24 |
Oct 03 02:58:09 PM UTC 24 |
28529636818 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.115679136 |
|
|
Oct 03 02:55:45 PM UTC 24 |
Oct 03 02:58:13 PM UTC 24 |
8695263334 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.4230646784 |
|
|
Oct 03 02:57:44 PM UTC 24 |
Oct 03 02:58:13 PM UTC 24 |
280700130 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3844179290 |
|
|
Oct 03 02:53:41 PM UTC 24 |
Oct 03 02:58:23 PM UTC 24 |
6914806693 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2632320671 |
|
|
Oct 03 02:49:45 PM UTC 24 |
Oct 03 02:58:25 PM UTC 24 |
6440972910 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.397528237 |
|
|
Oct 03 02:58:03 PM UTC 24 |
Oct 03 02:58:30 PM UTC 24 |
157436427 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.2369848896 |
|
|
Oct 03 02:58:23 PM UTC 24 |
Oct 03 02:58:35 PM UTC 24 |
123857945 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.2387831640 |
|
|
Oct 03 02:52:05 PM UTC 24 |
Oct 03 02:58:44 PM UTC 24 |
37134564865 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3305398311 |
|
|
Oct 03 02:58:34 PM UTC 24 |
Oct 03 02:58:46 PM UTC 24 |
54818306 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3346433193 |
|
|
Oct 03 02:57:59 PM UTC 24 |
Oct 03 02:58:51 PM UTC 24 |
1006743310 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.3036335915 |
|
|
Oct 03 02:58:09 PM UTC 24 |
Oct 03 02:58:55 PM UTC 24 |
494415200 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1185233050 |
|
|
Oct 03 02:57:45 PM UTC 24 |
Oct 03 02:58:59 PM UTC 24 |
4323248471 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.285923045 |
|
|
Oct 03 01:52:52 PM UTC 24 |
Oct 03 02:59:05 PM UTC 24 |
27937724460 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.1052636953 |
|
|
Oct 03 02:54:44 PM UTC 24 |
Oct 03 02:59:06 PM UTC 24 |
17476819962 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.2687286632 |
|
|
Oct 03 02:57:35 PM UTC 24 |
Oct 03 02:59:07 PM UTC 24 |
7443408472 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.2137680244 |
|
|
Oct 03 02:57:53 PM UTC 24 |
Oct 03 02:59:12 PM UTC 24 |
2501028068 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.3445739997 |
|
|
Oct 03 02:59:08 PM UTC 24 |
Oct 03 02:59:27 PM UTC 24 |
323035882 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.1347087298 |
|
|
Oct 03 02:59:16 PM UTC 24 |
Oct 03 02:59:29 PM UTC 24 |
119153054 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.48806794 |
|
|
Oct 03 02:53:57 PM UTC 24 |
Oct 03 02:59:33 PM UTC 24 |
9081083255 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.2737764091 |
|
|
Oct 03 02:57:55 PM UTC 24 |
Oct 03 02:59:39 PM UTC 24 |
2043633741 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.529217040 |
|
|
Oct 03 02:59:22 PM UTC 24 |
Oct 03 02:59:42 PM UTC 24 |
239581565 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.586604788 |
|
|
Oct 03 02:59:29 PM UTC 24 |
Oct 03 02:59:48 PM UTC 24 |
66105488 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.319342872 |
|
|
Oct 03 02:58:54 PM UTC 24 |
Oct 03 02:59:49 PM UTC 24 |
612818193 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3429435857 |
|
|
Oct 03 02:58:41 PM UTC 24 |
Oct 03 02:59:51 PM UTC 24 |
3797514289 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.2152667330 |
|
|
Oct 03 02:58:52 PM UTC 24 |
Oct 03 02:59:51 PM UTC 24 |
552233155 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.673932595 |
|
|
Oct 03 02:27:08 PM UTC 24 |
Oct 03 03:00:01 PM UTC 24 |
121492749075 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3955882860 |
|
|
Oct 03 02:59:57 PM UTC 24 |
Oct 03 03:00:07 PM UTC 24 |
40345078 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.3943382022 |
|
|
Oct 03 02:59:56 PM UTC 24 |
Oct 03 03:00:09 PM UTC 24 |
45009747 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.1048424252 |
|
|
Oct 03 02:48:35 PM UTC 24 |
Oct 03 03:00:22 PM UTC 24 |
74059526941 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3889841021 |
|
|
Oct 03 02:52:45 PM UTC 24 |
Oct 03 03:00:25 PM UTC 24 |
1501072535 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.980569430 |
|
|
Oct 03 02:57:50 PM UTC 24 |
Oct 03 03:00:29 PM UTC 24 |
2918543112 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.98493466 |
|
|
Oct 03 03:00:13 PM UTC 24 |
Oct 03 03:00:38 PM UTC 24 |
633392341 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3985862276 |
|
|
Oct 03 02:52:40 PM UTC 24 |
Oct 03 03:00:44 PM UTC 24 |
13228563237 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.726066190 |
|
|
Oct 03 02:59:50 PM UTC 24 |
Oct 03 03:00:52 PM UTC 24 |
101228894 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.2028021473 |
|
|
Oct 03 02:58:39 PM UTC 24 |
Oct 03 03:00:58 PM UTC 24 |
9836907859 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.136295147 |
|
|
Oct 03 03:00:52 PM UTC 24 |
Oct 03 03:01:04 PM UTC 24 |
201132784 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.1928945237 |
|
|
Oct 03 02:59:20 PM UTC 24 |
Oct 03 03:01:07 PM UTC 24 |
2437026855 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.2577619878 |
|
|
Oct 03 03:00:36 PM UTC 24 |
Oct 03 03:01:08 PM UTC 24 |
305332446 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.990637204 |
|
|
Oct 03 02:37:57 PM UTC 24 |
Oct 03 03:01:12 PM UTC 24 |
80152501826 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1812365781 |
|
|
Oct 03 01:50:39 PM UTC 24 |
Oct 03 03:01:13 PM UTC 24 |
28427147971 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.1884535161 |
|
|
Oct 03 03:00:16 PM UTC 24 |
Oct 03 03:01:32 PM UTC 24 |
581296173 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.3444688507 |
|
|
Oct 03 03:00:25 PM UTC 24 |
Oct 03 03:01:38 PM UTC 24 |
1627694487 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.252464802 |
|
|
Oct 03 03:01:29 PM UTC 24 |
Oct 03 03:01:39 PM UTC 24 |
47266376 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.3545465834 |
|
|
Oct 03 02:57:47 PM UTC 24 |
Oct 03 03:01:40 PM UTC 24 |
12737532412 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.543849970 |
|
|
Oct 03 03:01:28 PM UTC 24 |
Oct 03 03:01:41 PM UTC 24 |
215189479 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.1379899732 |
|
|
Oct 03 02:57:08 PM UTC 24 |
Oct 03 03:01:48 PM UTC 24 |
5753109419 ps |