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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.44 93.98 95.48 94.84 97.57 99.55


Total test records in report: 2923
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T2268 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.833510654 Oct 03 03:17:21 PM UTC 24 Oct 03 03:20:19 PM UTC 24 9775569355 ps
T2269 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.131489104 Oct 03 03:18:58 PM UTC 24 Oct 03 03:20:21 PM UTC 24 5560330130 ps
T2270 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3427318860 Oct 03 03:19:37 PM UTC 24 Oct 03 03:20:21 PM UTC 24 313717397 ps
T2271 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.4294315729 Oct 03 03:20:19 PM UTC 24 Oct 03 03:20:28 PM UTC 24 111699949 ps
T2272 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.1877106053 Oct 03 03:19:04 PM UTC 24 Oct 03 03:20:29 PM UTC 24 1968152000 ps
T2273 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4044628031 Oct 03 03:20:24 PM UTC 24 Oct 03 03:20:34 PM UTC 24 42833542 ps
T2274 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.3713869709 Oct 03 03:19:24 PM UTC 24 Oct 03 03:20:34 PM UTC 24 1638090063 ps
T2275 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.244517225 Oct 03 03:14:11 PM UTC 24 Oct 03 03:20:42 PM UTC 24 4471394513 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3967431960 Oct 03 03:14:13 PM UTC 24 Oct 03 03:20:42 PM UTC 24 3799069762 ps
T2276 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.4240857998 Oct 03 03:19:53 PM UTC 24 Oct 03 03:20:45 PM UTC 24 1097900958 ps
T2277 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1531541815 Oct 03 03:20:14 PM UTC 24 Oct 03 03:20:49 PM UTC 24 143897327 ps
T2278 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.4106201369 Oct 03 03:20:34 PM UTC 24 Oct 03 03:20:50 PM UTC 24 119331030 ps
T2279 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.3540880154 Oct 03 03:16:04 PM UTC 24 Oct 03 03:20:51 PM UTC 24 21899954656 ps
T2280 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.661719068 Oct 03 03:19:54 PM UTC 24 Oct 03 03:20:51 PM UTC 24 152879762 ps
T2281 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2854083963 Oct 03 03:20:33 PM UTC 24 Oct 03 03:20:58 PM UTC 24 199808382 ps
T2282 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3414455093 Oct 03 03:19:34 PM UTC 24 Oct 03 03:21:01 PM UTC 24 2065721249 ps
T2283 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.459685358 Oct 03 03:12:13 PM UTC 24 Oct 03 03:21:04 PM UTC 24 34355215552 ps
T2284 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1209166937 Oct 03 03:20:43 PM UTC 24 Oct 03 03:21:13 PM UTC 24 590432943 ps
T2285 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1308084643 Oct 03 03:21:09 PM UTC 24 Oct 03 03:21:20 PM UTC 24 50219625 ps
T2286 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2358591222 Oct 03 03:21:15 PM UTC 24 Oct 03 03:21:24 PM UTC 24 53086434 ps
T2287 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.3483201186 Oct 03 03:20:42 PM UTC 24 Oct 03 03:21:29 PM UTC 24 1117996369 ps
T2288 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4285895947 Oct 03 03:14:07 PM UTC 24 Oct 03 03:21:29 PM UTC 24 3702764107 ps
T2289 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2137691657 Oct 03 03:20:29 PM UTC 24 Oct 03 03:21:45 PM UTC 24 4036145138 ps
T2290 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.3964842539 Oct 03 03:21:26 PM UTC 24 Oct 03 03:21:46 PM UTC 24 128231543 ps
T2291 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2479486595 Oct 03 03:20:45 PM UTC 24 Oct 03 03:21:49 PM UTC 24 1925231463 ps
T2292 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2100995625 Oct 03 03:16:34 PM UTC 24 Oct 03 03:21:50 PM UTC 24 7732234501 ps
T2293 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3400339076 Oct 03 03:20:58 PM UTC 24 Oct 03 03:21:55 PM UTC 24 1189038308 ps
T2294 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.1282600719 Oct 03 03:20:28 PM UTC 24 Oct 03 03:22:03 PM UTC 24 7207480783 ps
T2295 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.907833965 Oct 03 03:20:51 PM UTC 24 Oct 03 03:22:09 PM UTC 24 1498919646 ps
T2296 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.420018550 Oct 03 03:21:12 PM UTC 24 Oct 03 03:22:11 PM UTC 24 1197648381 ps
T2297 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1441675205 Oct 03 03:17:00 PM UTC 24 Oct 03 03:22:11 PM UTC 24 4102234443 ps
T2298 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.77148611 Oct 03 03:21:40 PM UTC 24 Oct 03 03:22:12 PM UTC 24 429317323 ps
T547 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.964016872 Oct 03 03:12:31 PM UTC 24 Oct 03 03:22:26 PM UTC 24 8380018452 ps
T2299 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1614056612 Oct 03 03:21:16 PM UTC 24 Oct 03 03:22:27 PM UTC 24 4276462687 ps
T2300 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2420554742 Oct 03 02:44:50 PM UTC 24 Oct 03 03:22:32 PM UTC 24 125731524249 ps
T2301 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1638405471 Oct 03 02:50:19 PM UTC 24 Oct 03 03:22:32 PM UTC 24 106372050059 ps
T2302 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.574714340 Oct 03 03:16:36 PM UTC 24 Oct 03 03:22:32 PM UTC 24 4612671404 ps
T2303 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.2973071209 Oct 03 03:22:29 PM UTC 24 Oct 03 03:22:46 PM UTC 24 268949006 ps
T2304 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1840190094 Oct 03 03:22:35 PM UTC 24 Oct 03 03:22:46 PM UTC 24 53992087 ps
T2305 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.861289408 Oct 03 03:22:09 PM UTC 24 Oct 03 03:22:47 PM UTC 24 814655204 ps
T2306 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2263556548 Oct 03 03:21:55 PM UTC 24 Oct 03 03:22:49 PM UTC 24 1019335152 ps
T2307 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3098073460 Oct 03 03:22:39 PM UTC 24 Oct 03 03:22:55 PM UTC 24 103413355 ps
T548 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.1416110434 Oct 03 03:12:21 PM UTC 24 Oct 03 03:23:01 PM UTC 24 17723170672 ps
T2308 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.3569421460 Oct 03 03:21:55 PM UTC 24 Oct 03 03:23:12 PM UTC 24 1513956953 ps
T2309 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.744814734 Oct 03 03:21:15 PM UTC 24 Oct 03 03:23:14 PM UTC 24 9286792156 ps
T2310 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1238884835 Oct 03 03:22:16 PM UTC 24 Oct 03 03:23:19 PM UTC 24 72231645 ps
T2311 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1434037944 Oct 03 03:09:23 PM UTC 24 Oct 03 03:23:22 PM UTC 24 46393326210 ps
T2312 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.257248485 Oct 03 03:21:50 PM UTC 24 Oct 03 03:23:22 PM UTC 24 2218622261 ps
T2313 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2562702499 Oct 03 03:23:11 PM UTC 24 Oct 03 03:23:23 PM UTC 24 69901942 ps
T2314 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1391360960 Oct 03 03:22:56 PM UTC 24 Oct 03 03:23:34 PM UTC 24 380801091 ps
T2315 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.3955551839 Oct 03 03:13:25 PM UTC 24 Oct 03 03:23:37 PM UTC 24 36856107820 ps
T2316 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.74773660 Oct 03 03:13:58 PM UTC 24 Oct 03 03:23:39 PM UTC 24 12913293075 ps
T2317 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.295613241 Oct 03 03:23:12 PM UTC 24 Oct 03 03:23:39 PM UTC 24 139119995 ps
T2318 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3841811041 Oct 03 03:23:16 PM UTC 24 Oct 03 03:23:40 PM UTC 24 272763022 ps
T2319 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.4207393239 Oct 03 03:21:01 PM UTC 24 Oct 03 03:23:52 PM UTC 24 178016450 ps
T2320 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.1999298315 Oct 03 03:22:55 PM UTC 24 Oct 03 03:23:56 PM UTC 24 527141772 ps
T2321 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.171022043 Oct 03 03:23:45 PM UTC 24 Oct 03 03:23:56 PM UTC 24 38114601 ps
T2322 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2537356555 Oct 03 03:18:06 PM UTC 24 Oct 03 03:24:00 PM UTC 24 3785139347 ps
T2323 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3183901345 Oct 03 03:23:47 PM UTC 24 Oct 03 03:24:01 PM UTC 24 195760491 ps
T2324 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2542785636 Oct 03 03:23:15 PM UTC 24 Oct 03 03:24:03 PM UTC 24 1112360624 ps
T2325 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.2891787001 Oct 03 03:21:09 PM UTC 24 Oct 03 03:24:04 PM UTC 24 4128448284 ps
T2326 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.3431663706 Oct 03 03:03:11 PM UTC 24 Oct 03 03:24:20 PM UTC 24 65528044068 ps
T2327 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.658031372 Oct 03 03:22:39 PM UTC 24 Oct 03 03:24:22 PM UTC 24 7838741840 ps
T2328 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.1044098569 Oct 03 03:18:22 PM UTC 24 Oct 03 03:24:23 PM UTC 24 10085067489 ps
T2329 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.3849540970 Oct 03 03:24:03 PM UTC 24 Oct 03 03:24:32 PM UTC 24 252849219 ps
T2330 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.4191138187 Oct 03 03:24:21 PM UTC 24 Oct 03 03:24:32 PM UTC 24 41981190 ps
T2331 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.46260719 Oct 03 03:22:17 PM UTC 24 Oct 03 03:24:34 PM UTC 24 2885702670 ps
T2332 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.3331542532 Oct 03 03:24:00 PM UTC 24 Oct 03 03:24:39 PM UTC 24 906421099 ps
T2333 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.1991714985 Oct 03 03:24:28 PM UTC 24 Oct 03 03:24:43 PM UTC 24 40699281 ps
T2334 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3125446926 Oct 03 03:24:23 PM UTC 24 Oct 03 03:24:44 PM UTC 24 311520501 ps
T2335 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2196007893 Oct 03 03:22:40 PM UTC 24 Oct 03 03:24:45 PM UTC 24 4665449179 ps
T2336 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.3225493507 Oct 03 03:23:00 PM UTC 24 Oct 03 03:24:48 PM UTC 24 6079199384 ps
T2337 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.486908744 Oct 03 03:25:09 PM UTC 24 Oct 03 03:26:06 PM UTC 24 449272460 ps
T2338 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.83331369 Oct 03 03:15:22 PM UTC 24 Oct 03 03:24:48 PM UTC 24 13924758406 ps
T2339 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.4131523226 Oct 03 03:24:50 PM UTC 24 Oct 03 03:25:03 PM UTC 24 207611337 ps
T2340 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.123941088 Oct 03 03:23:30 PM UTC 24 Oct 03 03:25:06 PM UTC 24 240994177 ps
T2341 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.608953108 Oct 03 03:24:07 PM UTC 24 Oct 03 03:25:07 PM UTC 24 945410081 ps
T2342 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3287268200 Oct 03 03:24:57 PM UTC 24 Oct 03 03:25:08 PM UTC 24 43904411 ps
T2343 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.823079186 Oct 03 03:23:53 PM UTC 24 Oct 03 03:25:18 PM UTC 24 4748961247 ps
T2344 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.3017861806 Oct 03 03:23:52 PM UTC 24 Oct 03 03:25:23 PM UTC 24 8136419470 ps
T2345 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.2703840993 Oct 03 03:21:28 PM UTC 24 Oct 03 03:25:31 PM UTC 24 22841833224 ps
T2346 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.2723895682 Oct 03 03:20:01 PM UTC 24 Oct 03 03:25:33 PM UTC 24 3969771934 ps
T2347 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.382427605 Oct 03 03:11:15 PM UTC 24 Oct 03 03:25:38 PM UTC 24 5678018541 ps
T2348 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.2735986134 Oct 03 03:25:34 PM UTC 24 Oct 03 03:25:41 PM UTC 24 41993460 ps
T2349 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.2166704899 Oct 03 03:10:30 PM UTC 24 Oct 03 03:25:43 PM UTC 24 86565028858 ps
T2350 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.4181495564 Oct 03 03:25:09 PM UTC 24 Oct 03 03:25:44 PM UTC 24 705652846 ps
T2351 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2986557657 Oct 03 03:21:06 PM UTC 24 Oct 03 03:25:44 PM UTC 24 4655718083 ps
T2352 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.587478740 Oct 03 03:10:42 PM UTC 24 Oct 03 03:25:45 PM UTC 24 47733699541 ps
T2353 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3309748393 Oct 03 03:24:29 PM UTC 24 Oct 03 03:25:57 PM UTC 24 165562689 ps
T2354 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.102990602 Oct 03 03:24:24 PM UTC 24 Oct 03 03:26:01 PM UTC 24 1982159646 ps
T2355 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3316735120 Oct 03 03:26:02 PM UTC 24 Oct 03 03:26:09 PM UTC 24 44862932 ps
T2356 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.261813088 Oct 03 03:25:34 PM UTC 24 Oct 03 03:26:19 PM UTC 24 974693018 ps
T2357 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.571298663 Oct 03 03:20:59 PM UTC 24 Oct 03 03:26:22 PM UTC 24 9248147067 ps
T2358 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2544637805 Oct 03 03:24:57 PM UTC 24 Oct 03 03:26:25 PM UTC 24 5539333520 ps
T2359 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.1306764629 Oct 03 03:25:29 PM UTC 24 Oct 03 03:26:29 PM UTC 24 1727475782 ps
T2360 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.4062751054 Oct 03 03:26:10 PM UTC 24 Oct 03 03:26:35 PM UTC 24 198892224 ps
T2361 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2395535942 Oct 03 03:25:33 PM UTC 24 Oct 03 03:26:39 PM UTC 24 1190939828 ps
T2362 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3535050871 Oct 03 03:24:57 PM UTC 24 Oct 03 03:26:51 PM UTC 24 8863386174 ps
T2363 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.690158532 Oct 03 03:26:12 PM UTC 24 Oct 03 03:26:55 PM UTC 24 455127255 ps
T2364 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.500508999 Oct 03 03:04:20 PM UTC 24 Oct 03 03:26:59 PM UTC 24 75504840794 ps
T2365 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.1885704990 Oct 03 03:25:43 PM UTC 24 Oct 03 03:27:04 PM UTC 24 738365243 ps
T2366 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1956691481 Oct 03 03:26:37 PM UTC 24 Oct 03 03:27:14 PM UTC 24 300131134 ps
T2367 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2624861611 Oct 03 03:19:22 PM UTC 24 Oct 03 03:27:22 PM UTC 24 33171100770 ps
T2368 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.897816187 Oct 03 03:25:13 PM UTC 24 Oct 03 03:27:27 PM UTC 24 3427939504 ps
T2369 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.4162876718 Oct 03 03:18:21 PM UTC 24 Oct 03 03:27:31 PM UTC 24 3983501306 ps
T2370 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1898367627 Oct 03 03:26:31 PM UTC 24 Oct 03 03:27:32 PM UTC 24 557762767 ps
T2371 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2328570009 Oct 03 03:27:24 PM UTC 24 Oct 03 03:27:36 PM UTC 24 47115827 ps
T2372 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2855847282 Oct 03 03:27:22 PM UTC 24 Oct 03 03:27:35 PM UTC 24 183509511 ps
T2373 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.2809110330 Oct 03 03:24:02 PM UTC 24 Oct 03 03:27:38 PM UTC 24 21126412398 ps
T2374 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.750959010 Oct 03 03:26:48 PM UTC 24 Oct 03 03:27:41 PM UTC 24 319796323 ps
T2375 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.3955360725 Oct 03 03:10:37 PM UTC 24 Oct 03 03:27:41 PM UTC 24 61189402315 ps
T2376 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1575283103 Oct 03 03:26:53 PM UTC 24 Oct 03 03:27:42 PM UTC 24 1119880993 ps
T2377 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3309760841 Oct 03 03:26:08 PM UTC 24 Oct 03 03:27:49 PM UTC 24 7283309648 ps
T2378 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.2942266837 Oct 03 03:25:54 PM UTC 24 Oct 03 03:27:55 PM UTC 24 3345944897 ps
T2379 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.931058205 Oct 03 03:25:56 PM UTC 24 Oct 03 03:27:59 PM UTC 24 487059051 ps
T2380 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2745112325 Oct 03 03:27:56 PM UTC 24 Oct 03 03:28:15 PM UTC 24 149868502 ps
T2381 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.859531962 Oct 03 03:26:08 PM UTC 24 Oct 03 03:28:18 PM UTC 24 5768281609 ps
T2382 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.1604024693 Oct 03 03:26:42 PM UTC 24 Oct 03 03:28:18 PM UTC 24 2471683576 ps
T2383 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.918541767 Oct 03 03:28:06 PM UTC 24 Oct 03 03:28:22 PM UTC 24 164633747 ps
T2384 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3291553755 Oct 03 03:23:41 PM UTC 24 Oct 03 03:28:29 PM UTC 24 7739470225 ps
T2385 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.366390525 Oct 03 03:27:46 PM UTC 24 Oct 03 03:28:29 PM UTC 24 1170561341 ps
T2386 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.2719023759 Oct 03 03:28:05 PM UTC 24 Oct 03 03:28:38 PM UTC 24 801637785 ps
T2387 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.3554241369 Oct 03 03:28:02 PM UTC 24 Oct 03 03:28:43 PM UTC 24 317952003 ps
T2388 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.1489596041 Oct 03 03:24:32 PM UTC 24 Oct 03 03:28:44 PM UTC 24 2828293714 ps
T2389 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.2869718321 Oct 03 03:28:08 PM UTC 24 Oct 03 03:28:47 PM UTC 24 262216564 ps
T2390 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.1873773752 Oct 03 03:22:10 PM UTC 24 Oct 03 03:28:52 PM UTC 24 10876784501 ps
T2391 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.214504520 Oct 03 03:25:49 PM UTC 24 Oct 03 03:28:52 PM UTC 24 286575611 ps
T2392 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2310835272 Oct 03 03:28:45 PM UTC 24 Oct 03 03:28:55 PM UTC 24 39965453 ps
T2393 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.2281360541 Oct 03 03:28:45 PM UTC 24 Oct 03 03:28:56 PM UTC 24 49678666 ps
T2394 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.2264477498 Oct 03 03:27:33 PM UTC 24 Oct 03 03:28:57 PM UTC 24 7263349312 ps
T2395 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.1009689421 Oct 03 03:17:23 PM UTC 24 Oct 03 03:28:59 PM UTC 24 50401647222 ps
T2396 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.111517422 Oct 03 03:28:53 PM UTC 24 Oct 03 03:29:04 PM UTC 24 59055560 ps
T2397 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.321786973 Oct 03 03:23:20 PM UTC 24 Oct 03 03:29:05 PM UTC 24 8083408600 ps
T2398 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.101780683 Oct 03 03:23:43 PM UTC 24 Oct 03 03:29:06 PM UTC 24 5310002862 ps
T2399 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.730361613 Oct 03 03:27:42 PM UTC 24 Oct 03 03:29:08 PM UTC 24 4090014211 ps
T2400 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3275873597 Oct 03 03:27:56 PM UTC 24 Oct 03 03:29:10 PM UTC 24 644740783 ps
T2401 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3398171441 Oct 03 03:29:02 PM UTC 24 Oct 03 03:29:14 PM UTC 24 74572233 ps
T2402 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.939601739 Oct 03 03:29:18 PM UTC 24 Oct 03 03:29:28 PM UTC 24 68742693 ps
T2403 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2721296488 Oct 03 02:56:23 PM UTC 24 Oct 03 03:29:32 PM UTC 24 119043231789 ps
T2404 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1045308701 Oct 03 03:29:10 PM UTC 24 Oct 03 03:29:34 PM UTC 24 175393464 ps
T2405 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.142631112 Oct 03 03:27:01 PM UTC 24 Oct 03 03:29:35 PM UTC 24 308320951 ps
T2406 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3437748396 Oct 03 03:29:32 PM UTC 24 Oct 03 03:29:40 PM UTC 24 47406823 ps
T2407 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1536263350 Oct 03 03:29:31 PM UTC 24 Oct 03 03:29:42 PM UTC 24 50302131 ps
T2408 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2788413763 Oct 03 03:22:54 PM UTC 24 Oct 03 03:31:47 PM UTC 24 42503814397 ps
T2409 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.1468508568 Oct 03 03:29:15 PM UTC 24 Oct 03 03:29:42 PM UTC 24 341056425 ps
T2410 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3216550824 Oct 03 03:29:19 PM UTC 24 Oct 03 03:29:43 PM UTC 24 144406874 ps
T2411 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3980714138 Oct 03 02:42:55 PM UTC 24 Oct 03 03:29:45 PM UTC 24 157589751376 ps
T2412 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.2614418515 Oct 03 03:29:16 PM UTC 24 Oct 03 03:29:47 PM UTC 24 666553678 ps
T2413 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.154716234 Oct 03 03:25:05 PM UTC 24 Oct 03 03:29:50 PM UTC 24 17077552185 ps
T2414 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.3660536017 Oct 03 03:30:14 PM UTC 24 Oct 03 03:30:34 PM UTC 24 235692040 ps
T2415 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.465391410 Oct 03 03:29:57 PM UTC 24 Oct 03 03:30:38 PM UTC 24 359212170 ps
T2416 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.235722532 Oct 03 03:28:41 PM UTC 24 Oct 03 03:30:41 PM UTC 24 389258411 ps
T2417 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3983177389 Oct 03 03:24:43 PM UTC 24 Oct 03 03:30:42 PM UTC 24 9959331291 ps
T2418 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2779514013 Oct 03 03:30:16 PM UTC 24 Oct 03 03:30:42 PM UTC 24 155854528 ps
T2419 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.1768492907 Oct 03 03:30:13 PM UTC 24 Oct 03 03:30:44 PM UTC 24 237120680 ps
T2420 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2049256798 Oct 03 03:29:39 PM UTC 24 Oct 03 03:30:44 PM UTC 24 5352865015 ps
T2421 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.2979268264 Oct 03 03:14:45 PM UTC 24 Oct 03 03:30:50 PM UTC 24 97207740569 ps
T2422 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.2044298092 Oct 03 03:28:47 PM UTC 24 Oct 03 03:30:50 PM UTC 24 10248757451 ps
T2423 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1937259201 Oct 03 03:29:54 PM UTC 24 Oct 03 03:30:51 PM UTC 24 3329185120 ps
T2424 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.2112224489 Oct 03 03:29:23 PM UTC 24 Oct 03 03:30:58 PM UTC 24 2632288417 ps
T2425 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.433686472 Oct 03 03:27:58 PM UTC 24 Oct 03 03:31:08 PM UTC 24 17512716288 ps
T2426 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1297721861 Oct 03 03:28:56 PM UTC 24 Oct 03 03:31:12 PM UTC 24 5994476387 ps
T2427 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.3555226558 Oct 03 03:30:03 PM UTC 24 Oct 03 03:31:12 PM UTC 24 4041172838 ps
T2428 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1897337950 Oct 03 03:31:07 PM UTC 24 Oct 03 03:31:17 PM UTC 24 166666028 ps
T2429 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1922064868 Oct 03 03:31:10 PM UTC 24 Oct 03 03:31:21 PM UTC 24 49306781 ps
T2430 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2657914136 Oct 03 03:30:04 PM UTC 24 Oct 03 03:31:29 PM UTC 24 2055604004 ps
T2431 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3472775532 Oct 03 03:29:57 PM UTC 24 Oct 03 03:31:30 PM UTC 24 2357502474 ps
T2432 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.1650714244 Oct 03 03:31:18 PM UTC 24 Oct 03 03:31:33 PM UTC 24 97311967 ps
T2433 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.2660972475 Oct 03 03:27:06 PM UTC 24 Oct 03 03:31:36 PM UTC 24 7997773917 ps
T2434 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.5465272 Oct 03 03:29:15 PM UTC 24 Oct 03 03:31:47 PM UTC 24 10426210202 ps
T2435 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.4294430036 Oct 03 03:31:18 PM UTC 24 Oct 03 03:32:09 PM UTC 24 453696867 ps
T2436 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.77971018 Oct 03 03:31:55 PM UTC 24 Oct 03 03:32:17 PM UTC 24 145034850 ps
T2437 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2139013830 Oct 03 03:31:37 PM UTC 24 Oct 03 03:32:20 PM UTC 24 576818051 ps
T2438 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3192819737 Oct 03 03:31:11 PM UTC 24 Oct 03 03:32:28 PM UTC 24 5279820871 ps
T2439 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.22249345 Oct 03 03:31:53 PM UTC 24 Oct 03 03:32:31 PM UTC 24 275352785 ps
T2440 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.1382758502 Oct 03 03:31:43 PM UTC 24 Oct 03 03:32:31 PM UTC 24 513536608 ps
T2441 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.750973602 Oct 03 03:22:17 PM UTC 24 Oct 03 03:32:32 PM UTC 24 4455229672 ps
T2442 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2204493822 Oct 03 03:31:10 PM UTC 24 Oct 03 03:32:36 PM UTC 24 7110199953 ps
T2443 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2333985685 Oct 03 03:31:49 PM UTC 24 Oct 03 03:32:38 PM UTC 24 445294090 ps
T2444 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1918245912 Oct 03 03:32:30 PM UTC 24 Oct 03 03:32:39 PM UTC 24 144916365 ps
T2445 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2870952983 Oct 03 03:24:49 PM UTC 24 Oct 03 03:32:40 PM UTC 24 8367763694 ps
T2446 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2960892866 Oct 03 02:57:49 PM UTC 24 Oct 03 03:32:53 PM UTC 24 112206469567 ps
T2447 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.369579181 Oct 03 03:32:44 PM UTC 24 Oct 03 03:32:55 PM UTC 24 54852881 ps
T2448 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.144270820 Oct 03 03:26:58 PM UTC 24 Oct 03 03:32:55 PM UTC 24 3807393210 ps
T2449 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.218182655 Oct 03 03:11:55 PM UTC 24 Oct 03 03:33:01 PM UTC 24 107410396758 ps
T2450 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.3238201243 Oct 03 03:32:53 PM UTC 24 Oct 03 03:33:03 PM UTC 24 31122399 ps
T2451 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.1970384811 Oct 03 03:19:17 PM UTC 24 Oct 03 03:33:21 PM UTC 24 50770072221 ps
T2452 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3517492385 Oct 03 03:31:08 PM UTC 24 Oct 03 03:33:23 PM UTC 24 438888610 ps
T2453 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.19381764 Oct 03 03:30:08 PM UTC 24 Oct 03 03:33:25 PM UTC 24 3153480969 ps
T2454 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.1397253965 Oct 03 03:33:19 PM UTC 24 Oct 03 03:33:39 PM UTC 24 89599205 ps
T2455 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.2439637976 Oct 03 03:32:54 PM UTC 24 Oct 03 03:33:42 PM UTC 24 473633894 ps
T2456 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3371641877 Oct 03 03:33:22 PM UTC 24 Oct 03 03:33:50 PM UTC 24 189105379 ps
T2457 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2465148426 Oct 03 03:33:07 PM UTC 24 Oct 03 03:33:53 PM UTC 24 981061944 ps
T2458 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.4071001589 Oct 03 03:20:44 PM UTC 24 Oct 03 03:33:58 PM UTC 24 45042781046 ps
T2459 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1756272689 Oct 03 03:30:08 PM UTC 24 Oct 03 03:33:59 PM UTC 24 10471809129 ps
T2460 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3944181911 Oct 03 03:31:34 PM UTC 24 Oct 03 03:34:02 PM UTC 24 7872541428 ps
T2461 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2747177400 Oct 03 03:33:53 PM UTC 24 Oct 03 03:34:03 PM UTC 24 53284082 ps
T2462 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.459736844 Oct 03 03:33:08 PM UTC 24 Oct 03 03:34:03 PM UTC 24 613044915 ps
T2463 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2409889154 Oct 03 03:29:32 PM UTC 24 Oct 03 03:34:09 PM UTC 24 1767687618 ps
T2464 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.1668911401 Oct 03 03:25:15 PM UTC 24 Oct 03 03:34:11 PM UTC 24 31298192723 ps
T2465 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2137545609 Oct 03 03:34:07 PM UTC 24 Oct 03 03:34:16 PM UTC 24 54951584 ps
T2466 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1838247671 Oct 03 03:32:44 PM UTC 24 Oct 03 03:34:20 PM UTC 24 9034870442 ps
T2467 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2172812952 Oct 03 03:32:55 PM UTC 24 Oct 03 03:34:24 PM UTC 24 4718267279 ps
T2468 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3661543117 Oct 03 03:29:29 PM UTC 24 Oct 03 03:34:36 PM UTC 24 2949777272 ps
T2469 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1161384707 Oct 03 03:26:24 PM UTC 24 Oct 03 03:34:36 PM UTC 24 42911081277 ps
T2470 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.1386912072 Oct 03 03:33:22 PM UTC 24 Oct 03 03:34:37 PM UTC 24 1776063708 ps
T2471 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.187078122 Oct 03 03:29:29 PM UTC 24 Oct 03 03:34:43 PM UTC 24 3708356256 ps
T2472 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.1004887582 Oct 03 03:20:42 PM UTC 24 Oct 03 03:34:45 PM UTC 24 50843587893 ps
T2473 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3145745165 Oct 03 03:34:21 PM UTC 24 Oct 03 03:34:51 PM UTC 24 646841957 ps
T2474 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.1116909090 Oct 03 03:34:23 PM UTC 24 Oct 03 03:34:52 PM UTC 24 281220423 ps
T2475 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1399226869 Oct 03 03:34:37 PM UTC 24 Oct 03 03:35:00 PM UTC 24 729654953 ps
T2476 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.2392110907 Oct 03 03:34:27 PM UTC 24 Oct 03 03:35:10 PM UTC 24 343279694 ps
T2477 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2715436163 Oct 03 03:32:00 PM UTC 24 Oct 03 03:35:17 PM UTC 24 394307059 ps
T2478 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3496906449 Oct 03 03:35:07 PM UTC 24 Oct 03 03:35:19 PM UTC 24 146880500 ps
T2479 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.2313723621 Oct 03 03:34:44 PM UTC 24 Oct 03 03:35:24 PM UTC 24 244643048 ps
T2480 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.271030359 Oct 03 03:35:14 PM UTC 24 Oct 03 03:35:24 PM UTC 24 45686079 ps
T2481 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2924602498 Oct 03 03:05:33 PM UTC 24 Oct 03 03:35:25 PM UTC 24 108118105938 ps
T2482 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1431329993 Oct 03 03:32:00 PM UTC 24 Oct 03 03:35:29 PM UTC 24 1905015314 ps
T2483 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1563052424 Oct 03 03:34:17 PM UTC 24 Oct 03 03:35:39 PM UTC 24 4409130800 ps
T2484 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.450280368 Oct 03 03:34:04 PM UTC 24 Oct 03 03:35:42 PM UTC 24 8260630463 ps
T2485 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1275848393 Oct 03 03:30:59 PM UTC 24 Oct 03 03:35:45 PM UTC 24 2865876571 ps
T2486 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.827743838 Oct 03 03:34:46 PM UTC 24 Oct 03 03:35:48 PM UTC 24 1195204641 ps
T2487 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.703589259 Oct 03 03:34:36 PM UTC 24 Oct 03 03:35:49 PM UTC 24 2007766886 ps
T2488 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.4197835708 Oct 03 03:35:29 PM UTC 24 Oct 03 03:35:52 PM UTC 24 497576367 ps
T2489 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.1042589956 Oct 03 03:33:49 PM UTC 24 Oct 03 03:36:06 PM UTC 24 3615900574 ps
T2490 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3252804207 Oct 03 03:31:04 PM UTC 24 Oct 03 03:36:12 PM UTC 24 505311843 ps
T2491 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.2138524389 Oct 03 03:35:54 PM UTC 24 Oct 03 03:36:13 PM UTC 24 145516839 ps
T2492 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.164188810 Oct 03 03:14:49 PM UTC 24 Oct 03 03:36:18 PM UTC 24 66303199411 ps
T2493 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4047484777 Oct 03 03:36:11 PM UTC 24 Oct 03 03:36:21 PM UTC 24 63072236 ps
T2494 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.3840389020 Oct 03 03:28:14 PM UTC 24 Oct 03 03:36:21 PM UTC 24 9264817440 ps
T2495 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2935196361 Oct 03 03:35:38 PM UTC 24 Oct 03 03:36:28 PM UTC 24 487039527 ps
T2496 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.3165678388 Oct 03 03:29:09 PM UTC 24 Oct 03 03:36:36 PM UTC 24 22767133293 ps
T2497 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.1932880814 Oct 03 03:35:18 PM UTC 24 Oct 03 03:36:37 PM UTC 24 7926150357 ps
T2498 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.3644379689 Oct 03 03:35:53 PM UTC 24 Oct 03 03:36:43 PM UTC 24 389088615 ps
T2499 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3576797687 Oct 03 03:36:36 PM UTC 24 Oct 03 03:36:45 PM UTC 24 40104566 ps
T2500 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.1403912625 Oct 03 03:36:36 PM UTC 24 Oct 03 03:36:46 PM UTC 24 44996987 ps
T2501 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3277055690 Oct 03 03:00:36 PM UTC 24 Oct 03 03:36:48 PM UTC 24 138210780960 ps
T2502 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.686017621 Oct 03 03:36:07 PM UTC 24 Oct 03 03:36:52 PM UTC 24 781384669 ps
T2503 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3906048354 Oct 03 03:35:21 PM UTC 24 Oct 03 03:36:58 PM UTC 24 5413293668 ps
T2504 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1293603446 Oct 03 03:22:57 PM UTC 24 Oct 03 03:36:59 PM UTC 24 47620287843 ps
T2505 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2245109160 Oct 03 03:20:41 PM UTC 24 Oct 03 03:37:00 PM UTC 24 91648016598 ps
T2506 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3534426026 Oct 03 03:21:30 PM UTC 24 Oct 03 03:37:10 PM UTC 24 52316525862 ps
T2507 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1241827761 Oct 03 03:30:06 PM UTC 24 Oct 03 03:37:14 PM UTC 24 27453260392 ps
T2508 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.543079810 Oct 03 02:54:54 PM UTC 24 Oct 03 03:37:32 PM UTC 24 139365773807 ps
T2509 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.551950546 Oct 03 03:37:17 PM UTC 24 Oct 03 03:37:40 PM UTC 24 125002010 ps
T2510 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2810697303 Oct 03 03:36:51 PM UTC 24 Oct 03 03:37:43 PM UTC 24 574631807 ps
T2511 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3342983327 Oct 03 03:26:26 PM UTC 24 Oct 03 03:37:47 PM UTC 24 40454676508 ps
T2512 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.2422238389 Oct 03 03:37:41 PM UTC 24 Oct 03 03:37:52 PM UTC 24 50447962 ps
T2513 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2547334833 Oct 03 03:36:21 PM UTC 24 Oct 03 03:37:56 PM UTC 24 243027188 ps
T2514 /workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.1207021165 Oct 03 03:36:50 PM UTC 24 Oct 03 03:37:59 PM UTC 24 1635078289 ps
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