| T1434 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1231075696 |
|
|
Oct 03 01:46:13 PM UTC 24 |
Oct 03 01:47:48 PM UTC 24 |
5267237494 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2389211152 |
|
|
Oct 03 01:47:38 PM UTC 24 |
Oct 03 01:48:05 PM UTC 24 |
124845701 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.3928198971 |
|
|
Oct 03 01:45:02 PM UTC 24 |
Oct 03 01:48:07 PM UTC 24 |
2166543490 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3458979482 |
|
|
Oct 03 01:45:10 PM UTC 24 |
Oct 03 01:48:07 PM UTC 24 |
333518665 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.2217924810 |
|
|
Oct 03 01:46:18 PM UTC 24 |
Oct 03 01:48:17 PM UTC 24 |
2288709780 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.470708661 |
|
|
Oct 03 01:47:42 PM UTC 24 |
Oct 03 01:48:20 PM UTC 24 |
857564836 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1139514856 |
|
|
Oct 03 01:47:25 PM UTC 24 |
Oct 03 01:48:25 PM UTC 24 |
1536899371 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.4123414364 |
|
|
Oct 03 01:47:25 PM UTC 24 |
Oct 03 01:48:26 PM UTC 24 |
603751444 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2967844393 |
|
|
Oct 03 01:30:28 PM UTC 24 |
Oct 03 01:48:26 PM UTC 24 |
9908776680 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.3702032575 |
|
|
Oct 03 01:45:51 PM UTC 24 |
Oct 03 01:48:28 PM UTC 24 |
9521499701 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1041343717 |
|
|
Oct 03 01:35:49 PM UTC 24 |
Oct 03 01:48:42 PM UTC 24 |
11173983987 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2070117116 |
|
|
Oct 03 01:48:42 PM UTC 24 |
Oct 03 01:48:52 PM UTC 24 |
41094764 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.760496660 |
|
|
Oct 03 01:18:49 PM UTC 24 |
Oct 03 01:48:52 PM UTC 24 |
15597943188 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2775307333 |
|
|
Oct 03 01:48:42 PM UTC 24 |
Oct 03 01:48:55 PM UTC 24 |
50045842 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3678640422 |
|
|
Oct 03 01:45:19 PM UTC 24 |
Oct 03 01:48:56 PM UTC 24 |
5340707623 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.1556889744 |
|
|
Oct 03 01:31:34 PM UTC 24 |
Oct 03 01:49:08 PM UTC 24 |
81894381677 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.3405282304 |
|
|
Oct 03 01:48:53 PM UTC 24 |
Oct 03 01:49:23 PM UTC 24 |
578770433 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.1299812507 |
|
|
Oct 03 01:47:58 PM UTC 24 |
Oct 03 01:49:39 PM UTC 24 |
2080435832 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3697006091 |
|
|
Oct 03 01:48:01 PM UTC 24 |
Oct 03 01:49:44 PM UTC 24 |
191812649 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.2555018038 |
|
|
Oct 03 01:49:21 PM UTC 24 |
Oct 03 01:49:48 PM UTC 24 |
211987902 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2000634337 |
|
|
Oct 03 01:13:01 PM UTC 24 |
Oct 03 01:49:49 PM UTC 24 |
15060219858 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.246951240 |
|
|
Oct 03 01:45:42 PM UTC 24 |
Oct 03 01:49:51 PM UTC 24 |
3325681751 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1410234818 |
|
|
Oct 03 01:45:21 PM UTC 24 |
Oct 03 01:49:55 PM UTC 24 |
967663758 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.1724066504 |
|
|
Oct 03 01:49:49 PM UTC 24 |
Oct 03 01:50:10 PM UTC 24 |
70581767 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3064948468 |
|
|
Oct 03 01:48:55 PM UTC 24 |
Oct 03 01:50:12 PM UTC 24 |
612048611 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3581879498 |
|
|
Oct 03 01:13:08 PM UTC 24 |
Oct 03 01:50:22 PM UTC 24 |
16380855016 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4049462903 |
|
|
Oct 03 01:50:04 PM UTC 24 |
Oct 03 01:50:26 PM UTC 24 |
321212534 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1065583779 |
|
|
Oct 03 01:49:35 PM UTC 24 |
Oct 03 01:50:27 PM UTC 24 |
829356432 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.4216660487 |
|
|
Oct 03 01:48:51 PM UTC 24 |
Oct 03 01:50:33 PM UTC 24 |
7186310851 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.4068479925 |
|
|
Oct 03 01:46:26 PM UTC 24 |
Oct 03 01:50:39 PM UTC 24 |
21178914978 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.644355513 |
|
|
Oct 03 01:40:46 PM UTC 24 |
Oct 03 01:50:50 PM UTC 24 |
47681887319 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1245285058 |
|
|
Oct 03 01:42:25 PM UTC 24 |
Oct 03 01:50:51 PM UTC 24 |
7347260228 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.238628877 |
|
|
Oct 03 01:25:13 PM UTC 24 |
Oct 03 01:50:53 PM UTC 24 |
11783224501 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1827266733 |
|
|
Oct 03 01:48:52 PM UTC 24 |
Oct 03 01:50:58 PM UTC 24 |
6032293023 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2122477752 |
|
|
Oct 03 01:45:29 PM UTC 24 |
Oct 03 01:50:58 PM UTC 24 |
3825738280 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.2206277054 |
|
|
Oct 03 01:50:53 PM UTC 24 |
Oct 03 01:51:01 PM UTC 24 |
40404147 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2646667849 |
|
|
Oct 03 01:50:52 PM UTC 24 |
Oct 03 01:51:01 PM UTC 24 |
43830846 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1742485520 |
|
|
Oct 03 01:42:10 PM UTC 24 |
Oct 03 01:51:27 PM UTC 24 |
3871139789 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1448985199 |
|
|
Oct 03 01:46:31 PM UTC 24 |
Oct 03 01:51:28 PM UTC 24 |
16968731986 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.28873855 |
|
|
Oct 03 01:49:16 PM UTC 24 |
Oct 03 01:51:32 PM UTC 24 |
3326251827 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3618838138 |
|
|
Oct 03 01:51:26 PM UTC 24 |
Oct 03 01:51:45 PM UTC 24 |
329097792 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.793508289 |
|
|
Oct 03 01:51:03 PM UTC 24 |
Oct 03 01:51:55 PM UTC 24 |
440304280 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.3989163015 |
|
|
Oct 03 01:51:15 PM UTC 24 |
Oct 03 01:52:09 PM UTC 24 |
297845098 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3531065951 |
|
|
Oct 03 01:51:54 PM UTC 24 |
Oct 03 01:52:12 PM UTC 24 |
87559505 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3471603283 |
|
|
Oct 03 01:51:27 PM UTC 24 |
Oct 03 01:52:19 PM UTC 24 |
890773052 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2124114704 |
|
|
Oct 03 01:37:35 PM UTC 24 |
Oct 03 01:52:26 PM UTC 24 |
12823796847 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1742043965 |
|
|
Oct 03 01:51:05 PM UTC 24 |
Oct 03 01:52:29 PM UTC 24 |
4541943663 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.3932593478 |
|
|
Oct 03 01:51:53 PM UTC 24 |
Oct 03 01:52:43 PM UTC 24 |
744323683 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.288282593 |
|
|
Oct 03 01:51:01 PM UTC 24 |
Oct 03 01:52:49 PM UTC 24 |
8664792315 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3614006548 |
|
|
Oct 03 01:52:11 PM UTC 24 |
Oct 03 01:52:54 PM UTC 24 |
100506459 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.333058382 |
|
|
Oct 03 01:43:41 PM UTC 24 |
Oct 03 01:53:02 PM UTC 24 |
28348546368 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1312603842 |
|
|
Oct 03 01:39:00 PM UTC 24 |
Oct 03 01:53:02 PM UTC 24 |
48814423284 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3869079887 |
|
|
Oct 03 01:51:22 PM UTC 24 |
Oct 03 01:53:10 PM UTC 24 |
2279437538 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.896056108 |
|
|
Oct 03 01:53:09 PM UTC 24 |
Oct 03 01:53:20 PM UTC 24 |
51012929 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2981620786 |
|
|
Oct 03 01:53:14 PM UTC 24 |
Oct 03 01:53:26 PM UTC 24 |
57646253 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.1854522457 |
|
|
Oct 03 01:38:36 PM UTC 24 |
Oct 03 01:53:35 PM UTC 24 |
41527761039 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.4036519233 |
|
|
Oct 03 01:38:21 PM UTC 24 |
Oct 03 01:53:38 PM UTC 24 |
91329035129 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2596856221 |
|
|
Oct 03 01:42:21 PM UTC 24 |
Oct 03 01:53:49 PM UTC 24 |
6117801080 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.1185462694 |
|
|
Oct 03 01:53:28 PM UTC 24 |
Oct 03 01:53:50 PM UTC 24 |
186650235 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.624143090 |
|
|
Oct 03 01:50:16 PM UTC 24 |
Oct 03 01:54:01 PM UTC 24 |
522087572 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.1831162256 |
|
|
Oct 03 01:51:58 PM UTC 24 |
Oct 03 01:54:02 PM UTC 24 |
1123376779 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.28702641 |
|
|
Oct 03 01:33:55 PM UTC 24 |
Oct 03 01:54:10 PM UTC 24 |
67108075979 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1869250734 |
|
|
Oct 03 01:53:36 PM UTC 24 |
Oct 03 01:54:28 PM UTC 24 |
385104922 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3502552777 |
|
|
Oct 03 01:48:33 PM UTC 24 |
Oct 03 01:54:37 PM UTC 24 |
3959423838 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3112649487 |
|
|
Oct 03 01:51:16 PM UTC 24 |
Oct 03 01:54:44 PM UTC 24 |
12295417264 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1517616225 |
|
|
Oct 03 01:54:29 PM UTC 24 |
Oct 03 01:55:00 PM UTC 24 |
519582620 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.1745847750 |
|
|
Oct 03 01:54:27 PM UTC 24 |
Oct 03 01:55:04 PM UTC 24 |
716301243 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.578942335 |
|
|
Oct 03 01:53:21 PM UTC 24 |
Oct 03 01:55:08 PM UTC 24 |
9126190272 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2779546971 |
|
|
Oct 03 01:53:28 PM UTC 24 |
Oct 03 01:55:18 PM UTC 24 |
6693170385 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.4087073149 |
|
|
Oct 03 01:36:43 PM UTC 24 |
Oct 03 01:55:21 PM UTC 24 |
105446859043 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.1863248950 |
|
|
Oct 03 01:48:15 PM UTC 24 |
Oct 03 01:55:30 PM UTC 24 |
4470163700 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.3221130698 |
|
|
Oct 03 01:52:19 PM UTC 24 |
Oct 03 01:55:36 PM UTC 24 |
4495065441 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3895421701 |
|
|
Oct 03 01:55:09 PM UTC 24 |
Oct 03 01:55:38 PM UTC 24 |
91128033 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.3389815211 |
|
|
Oct 03 01:54:11 PM UTC 24 |
Oct 03 01:55:43 PM UTC 24 |
2069407189 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.3546077313 |
|
|
Oct 03 01:55:45 PM UTC 24 |
Oct 03 01:55:57 PM UTC 24 |
141313852 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1198912615 |
|
|
Oct 03 01:54:13 PM UTC 24 |
Oct 03 01:55:59 PM UTC 24 |
2341992940 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.1004990237 |
|
|
Oct 03 01:51:18 PM UTC 24 |
Oct 03 01:56:00 PM UTC 24 |
23467960865 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.612971654 |
|
|
Oct 03 01:55:55 PM UTC 24 |
Oct 03 01:56:05 PM UTC 24 |
43908100 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.122595998 |
|
|
Oct 03 01:48:15 PM UTC 24 |
Oct 03 01:56:10 PM UTC 24 |
3399456189 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.3058119747 |
|
|
Oct 03 01:53:59 PM UTC 24 |
Oct 03 01:56:37 PM UTC 24 |
3320896274 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.184628676 |
|
|
Oct 03 01:56:23 PM UTC 24 |
Oct 03 01:56:52 PM UTC 24 |
212925274 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.1448174733 |
|
|
Oct 03 01:56:07 PM UTC 24 |
Oct 03 01:57:00 PM UTC 24 |
1080253483 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.2070156283 |
|
|
Oct 03 01:57:03 PM UTC 24 |
Oct 03 01:57:15 PM UTC 24 |
50004664 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.2184151044 |
|
|
Oct 03 01:56:01 PM UTC 24 |
Oct 03 01:57:18 PM UTC 24 |
6867409356 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.751658132 |
|
|
Oct 03 01:56:05 PM UTC 24 |
Oct 03 01:57:27 PM UTC 24 |
5039771114 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.3997290433 |
|
|
Oct 03 01:57:17 PM UTC 24 |
Oct 03 01:58:03 PM UTC 24 |
1100513947 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3726496861 |
|
|
Oct 03 01:52:35 PM UTC 24 |
Oct 03 01:58:14 PM UTC 24 |
3254063613 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.4132764725 |
|
|
Oct 03 01:56:28 PM UTC 24 |
Oct 03 01:58:16 PM UTC 24 |
1013945106 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.883951072 |
|
|
Oct 03 01:57:40 PM UTC 24 |
Oct 03 01:58:17 PM UTC 24 |
868763381 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.4023879398 |
|
|
Oct 03 01:52:55 PM UTC 24 |
Oct 03 01:58:20 PM UTC 24 |
3297501504 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.1123620256 |
|
|
Oct 03 01:50:49 PM UTC 24 |
Oct 03 01:58:23 PM UTC 24 |
4031284584 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2030025997 |
|
|
Oct 03 01:39:50 PM UTC 24 |
Oct 03 01:58:29 PM UTC 24 |
12744196231 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3055901139 |
|
|
Oct 03 01:54:53 PM UTC 24 |
Oct 03 01:58:30 PM UTC 24 |
328120472 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3279569416 |
|
|
Oct 03 01:50:17 PM UTC 24 |
Oct 03 01:58:35 PM UTC 24 |
12762248499 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1843128531 |
|
|
Oct 03 01:49:18 PM UTC 24 |
Oct 03 01:58:40 PM UTC 24 |
35183070693 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2695935914 |
|
|
Oct 03 01:57:26 PM UTC 24 |
Oct 03 01:58:46 PM UTC 24 |
1244152179 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.791265248 |
|
|
Oct 03 01:58:53 PM UTC 24 |
Oct 03 01:59:03 PM UTC 24 |
203111198 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2655129772 |
|
|
Oct 03 01:58:56 PM UTC 24 |
Oct 03 01:59:07 PM UTC 24 |
50803203 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.186806009 |
|
|
Oct 03 01:59:10 PM UTC 24 |
Oct 03 01:59:35 PM UTC 24 |
244097290 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1056874654 |
|
|
Oct 03 01:53:53 PM UTC 24 |
Oct 03 01:59:39 PM UTC 24 |
18479392566 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.977340972 |
|
|
Oct 03 01:50:38 PM UTC 24 |
Oct 03 01:59:45 PM UTC 24 |
6032591970 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.1216578060 |
|
|
Oct 03 01:50:21 PM UTC 24 |
Oct 03 02:00:08 PM UTC 24 |
5656073136 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.2730601639 |
|
|
Oct 03 01:59:25 PM UTC 24 |
Oct 03 02:00:09 PM UTC 24 |
304911309 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1675745640 |
|
|
Oct 03 01:55:43 PM UTC 24 |
Oct 03 02:00:20 PM UTC 24 |
3013185840 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.680596213 |
|
|
Oct 03 01:50:14 PM UTC 24 |
Oct 03 02:00:26 PM UTC 24 |
8512993147 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.2757945028 |
|
|
Oct 03 01:50:07 PM UTC 24 |
Oct 03 02:00:35 PM UTC 24 |
15061263071 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3544388954 |
|
|
Oct 03 01:58:56 PM UTC 24 |
Oct 03 02:00:51 PM UTC 24 |
8603097757 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2089203231 |
|
|
Oct 03 01:57:44 PM UTC 24 |
Oct 03 02:00:57 PM UTC 24 |
1437586085 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.174877135 |
|
|
Oct 03 02:00:31 PM UTC 24 |
Oct 03 02:01:05 PM UTC 24 |
644391153 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.3932258381 |
|
|
Oct 03 02:00:33 PM UTC 24 |
Oct 03 02:01:13 PM UTC 24 |
866573623 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2256376754 |
|
|
Oct 03 01:59:04 PM UTC 24 |
Oct 03 02:01:13 PM UTC 24 |
6507936243 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3312746538 |
|
|
Oct 03 01:49:08 PM UTC 24 |
Oct 03 02:01:14 PM UTC 24 |
62641732398 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.317702369 |
|
|
Oct 03 01:49:19 PM UTC 24 |
Oct 03 02:01:24 PM UTC 24 |
45080353951 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1785087660 |
|
|
Oct 03 01:48:02 PM UTC 24 |
Oct 03 02:01:29 PM UTC 24 |
19387770134 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.185447361 |
|
|
Oct 03 02:00:52 PM UTC 24 |
Oct 03 02:01:32 PM UTC 24 |
529034097 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.3772535335 |
|
|
Oct 03 02:00:46 PM UTC 24 |
Oct 03 02:01:35 PM UTC 24 |
307596662 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.492426064 |
|
|
Oct 03 02:01:16 PM UTC 24 |
Oct 03 02:01:41 PM UTC 24 |
100263151 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.859376520 |
|
|
Oct 03 02:01:53 PM UTC 24 |
Oct 03 02:02:02 PM UTC 24 |
45063752 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2394338622 |
|
|
Oct 03 01:28:15 PM UTC 24 |
Oct 03 02:02:02 PM UTC 24 |
14476794570 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.610298764 |
|
|
Oct 03 01:30:38 PM UTC 24 |
Oct 03 02:02:04 PM UTC 24 |
16554534684 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2323818165 |
|
|
Oct 03 02:01:54 PM UTC 24 |
Oct 03 02:02:08 PM UTC 24 |
209375794 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3043845909 |
|
|
Oct 03 02:01:02 PM UTC 24 |
Oct 03 02:02:18 PM UTC 24 |
731782552 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2982880087 |
|
|
Oct 03 01:54:32 PM UTC 24 |
Oct 03 02:02:44 PM UTC 24 |
9374169428 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.2813882672 |
|
|
Oct 03 02:00:02 PM UTC 24 |
Oct 03 02:02:57 PM UTC 24 |
2865619147 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3631314636 |
|
|
Oct 03 02:02:26 PM UTC 24 |
Oct 03 02:03:02 PM UTC 24 |
228803420 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.236616661 |
|
|
Oct 03 02:02:08 PM UTC 24 |
Oct 03 02:03:15 PM UTC 24 |
4443344270 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.764036302 |
|
|
Oct 03 02:02:42 PM UTC 24 |
Oct 03 02:03:15 PM UTC 24 |
620784671 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2429401542 |
|
|
Oct 03 02:02:28 PM UTC 24 |
Oct 03 02:03:17 PM UTC 24 |
450591495 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.213546421 |
|
|
Oct 03 01:57:54 PM UTC 24 |
Oct 03 02:03:18 PM UTC 24 |
900870046 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.1243525944 |
|
|
Oct 03 01:55:04 PM UTC 24 |
Oct 03 02:03:43 PM UTC 24 |
10006832966 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.2120897062 |
|
|
Oct 03 02:02:02 PM UTC 24 |
Oct 03 02:03:45 PM UTC 24 |
10710638950 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3725758996 |
|
|
Oct 03 01:40:58 PM UTC 24 |
Oct 03 02:04:01 PM UTC 24 |
83209055552 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.2295022710 |
|
|
Oct 03 01:58:43 PM UTC 24 |
Oct 03 02:04:10 PM UTC 24 |
4149856560 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2364022365 |
|
|
Oct 03 01:58:29 PM UTC 24 |
Oct 03 02:04:10 PM UTC 24 |
7845407927 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2150705313 |
|
|
Oct 03 02:03:28 PM UTC 24 |
Oct 03 02:04:12 PM UTC 24 |
764930672 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2989028118 |
|
|
Oct 03 02:03:37 PM UTC 24 |
Oct 03 02:04:21 PM UTC 24 |
730081670 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.496725147 |
|
|
Oct 03 02:07:40 PM UTC 24 |
Oct 03 02:09:00 PM UTC 24 |
1480318665 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1676149881 |
|
|
Oct 03 01:52:40 PM UTC 24 |
Oct 03 02:04:30 PM UTC 24 |
5495375672 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.2827104749 |
|
|
Oct 03 02:03:41 PM UTC 24 |
Oct 03 02:04:53 PM UTC 24 |
1231192893 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2080661884 |
|
|
Oct 03 02:04:45 PM UTC 24 |
Oct 03 02:04:53 PM UTC 24 |
44258081 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.501100048 |
|
|
Oct 03 02:03:23 PM UTC 24 |
Oct 03 02:04:59 PM UTC 24 |
2484840747 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.4067123151 |
|
|
Oct 03 02:04:56 PM UTC 24 |
Oct 03 02:05:09 PM UTC 24 |
53048078 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.1355093955 |
|
|
Oct 03 01:58:48 PM UTC 24 |
Oct 03 02:05:09 PM UTC 24 |
3259156693 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.4029556672 |
|
|
Oct 03 02:03:44 PM UTC 24 |
Oct 03 02:05:12 PM UTC 24 |
1673891997 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2756956353 |
|
|
Oct 03 01:52:47 PM UTC 24 |
Oct 03 02:05:33 PM UTC 24 |
8760991806 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1515920321 |
|
|
Oct 03 01:58:40 PM UTC 24 |
Oct 03 02:05:41 PM UTC 24 |
5438075723 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.4205307275 |
|
|
Oct 03 01:29:07 PM UTC 24 |
Oct 03 02:05:49 PM UTC 24 |
149480822675 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.3815679646 |
|
|
Oct 03 02:01:51 PM UTC 24 |
Oct 03 02:06:00 PM UTC 24 |
3406257060 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.814514506 |
|
|
Oct 03 01:58:43 PM UTC 24 |
Oct 03 02:06:03 PM UTC 24 |
7181364506 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3820695272 |
|
|
Oct 03 02:05:25 PM UTC 24 |
Oct 03 02:06:15 PM UTC 24 |
433657639 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2014115371 |
|
|
Oct 03 01:45:34 PM UTC 24 |
Oct 03 02:06:19 PM UTC 24 |
9395684749 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.3201549945 |
|
|
Oct 03 02:02:33 PM UTC 24 |
Oct 03 02:06:27 PM UTC 24 |
12779787134 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3608111439 |
|
|
Oct 03 02:05:36 PM UTC 24 |
Oct 03 02:06:30 PM UTC 24 |
448753360 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1701843592 |
|
|
Oct 03 02:05:17 PM UTC 24 |
Oct 03 02:06:32 PM UTC 24 |
3715697914 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.149857670 |
|
|
Oct 03 02:01:38 PM UTC 24 |
Oct 03 02:06:33 PM UTC 24 |
4870722059 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.1175601338 |
|
|
Oct 03 02:06:26 PM UTC 24 |
Oct 03 02:06:37 PM UTC 24 |
142738917 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.2949700158 |
|
|
Oct 03 02:06:16 PM UTC 24 |
Oct 03 02:06:37 PM UTC 24 |
121839306 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.4185525187 |
|
|
Oct 03 02:04:11 PM UTC 24 |
Oct 03 02:06:37 PM UTC 24 |
2655891562 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.521915911 |
|
|
Oct 03 02:06:00 PM UTC 24 |
Oct 03 02:06:39 PM UTC 24 |
490388683 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2255665725 |
|
|
Oct 03 02:06:59 PM UTC 24 |
Oct 03 02:07:11 PM UTC 24 |
188255758 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3095654560 |
|
|
Oct 03 02:06:41 PM UTC 24 |
Oct 03 02:07:06 PM UTC 24 |
216237987 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3544511965 |
|
|
Oct 03 02:07:04 PM UTC 24 |
Oct 03 02:07:17 PM UTC 24 |
45356340 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2575102538 |
|
|
Oct 03 02:05:20 PM UTC 24 |
Oct 03 02:07:23 PM UTC 24 |
8753610068 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1857145496 |
|
|
Oct 03 02:03:44 PM UTC 24 |
Oct 03 02:07:29 PM UTC 24 |
1545409149 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.1522463558 |
|
|
Oct 03 02:06:30 PM UTC 24 |
Oct 03 02:07:41 PM UTC 24 |
1087870285 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.1658867477 |
|
|
Oct 03 02:01:22 PM UTC 24 |
Oct 03 02:07:56 PM UTC 24 |
10814451385 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2665817755 |
|
|
Oct 03 01:31:41 PM UTC 24 |
Oct 03 02:08:16 PM UTC 24 |
114428739998 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2021291931 |
|
|
Oct 03 02:07:37 PM UTC 24 |
Oct 03 02:08:39 PM UTC 24 |
4370872381 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2984866221 |
|
|
Oct 03 02:07:49 PM UTC 24 |
Oct 03 02:08:46 PM UTC 24 |
432653479 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3372908202 |
|
|
Oct 03 02:04:11 PM UTC 24 |
Oct 03 02:08:50 PM UTC 24 |
5181443661 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2035084874 |
|
|
Oct 03 02:08:07 PM UTC 24 |
Oct 03 02:08:51 PM UTC 24 |
644818765 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.3122518162 |
|
|
Oct 03 02:08:43 PM UTC 24 |
Oct 03 02:08:55 PM UTC 24 |
36775730 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1106881469 |
|
|
Oct 03 02:06:54 PM UTC 24 |
Oct 03 02:09:25 PM UTC 24 |
3535265237 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.4448478 |
|
|
Oct 03 01:55:26 PM UTC 24 |
Oct 03 02:09:33 PM UTC 24 |
5924914688 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.2700898082 |
|
|
Oct 03 02:07:31 PM UTC 24 |
Oct 03 02:09:44 PM UTC 24 |
8436633060 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3296096879 |
|
|
Oct 03 02:09:05 PM UTC 24 |
Oct 03 02:09:45 PM UTC 24 |
269349644 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.3597915041 |
|
|
Oct 03 02:09:12 PM UTC 24 |
Oct 03 02:09:47 PM UTC 24 |
269279657 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2829173392 |
|
|
Oct 03 02:09:16 PM UTC 24 |
Oct 03 02:10:01 PM UTC 24 |
314783874 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.1152003343 |
|
|
Oct 03 02:07:02 PM UTC 24 |
Oct 03 02:10:13 PM UTC 24 |
2521029870 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3695837385 |
|
|
Oct 03 02:10:11 PM UTC 24 |
Oct 03 02:10:19 PM UTC 24 |
49014827 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2808355765 |
|
|
Oct 03 02:06:56 PM UTC 24 |
Oct 03 02:10:23 PM UTC 24 |
504587043 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2552175245 |
|
|
Oct 03 02:10:11 PM UTC 24 |
Oct 03 02:10:26 PM UTC 24 |
231522980 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.4188222145 |
|
|
Oct 03 02:00:00 PM UTC 24 |
Oct 03 02:10:33 PM UTC 24 |
41530338468 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3352639362 |
|
|
Oct 03 02:01:36 PM UTC 24 |
Oct 03 02:10:40 PM UTC 24 |
6139857615 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2838627709 |
|
|
Oct 03 02:09:51 PM UTC 24 |
Oct 03 02:11:04 PM UTC 24 |
294549383 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.1351627270 |
|
|
Oct 03 02:10:46 PM UTC 24 |
Oct 03 02:11:07 PM UTC 24 |
127935086 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.476465809 |
|
|
Oct 03 01:48:29 PM UTC 24 |
Oct 03 02:11:08 PM UTC 24 |
12717171564 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3860455240 |
|
|
Oct 03 02:01:28 PM UTC 24 |
Oct 03 02:11:12 PM UTC 24 |
4861978198 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2385752744 |
|
|
Oct 03 02:05:35 PM UTC 24 |
Oct 03 02:11:22 PM UTC 24 |
29653014011 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.3605316893 |
|
|
Oct 03 02:11:00 PM UTC 24 |
Oct 03 02:11:28 PM UTC 24 |
272784501 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3155026477 |
|
|
Oct 03 02:10:40 PM UTC 24 |
Oct 03 02:11:37 PM UTC 24 |
1584572632 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2654855953 |
|
|
Oct 03 02:10:29 PM UTC 24 |
Oct 03 02:11:39 PM UTC 24 |
5050297527 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1782545766 |
|
|
Oct 03 01:55:29 PM UTC 24 |
Oct 03 02:11:41 PM UTC 24 |
10334178532 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.2900052338 |
|
|
Oct 03 02:02:27 PM UTC 24 |
Oct 03 02:11:43 PM UTC 24 |
38965909679 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1814483576 |
|
|
Oct 03 02:06:50 PM UTC 24 |
Oct 03 02:11:44 PM UTC 24 |
579297901 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1639527520 |
|
|
Oct 03 02:10:15 PM UTC 24 |
Oct 03 02:11:50 PM UTC 24 |
9352399479 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.4117910368 |
|
|
Oct 03 02:11:30 PM UTC 24 |
Oct 03 02:11:52 PM UTC 24 |
442030184 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.1435063889 |
|
|
Oct 03 02:11:33 PM UTC 24 |
Oct 03 02:11:56 PM UTC 24 |
108891999 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1923963163 |
|
|
Oct 03 02:11:10 PM UTC 24 |
Oct 03 02:11:56 PM UTC 24 |
927825942 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.507121713 |
|
|
Oct 03 02:04:39 PM UTC 24 |
Oct 03 02:12:01 PM UTC 24 |
4103211750 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.3037085924 |
|
|
Oct 03 01:59:33 PM UTC 24 |
Oct 03 02:12:02 PM UTC 24 |
62213849693 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2293128824 |
|
|
Oct 03 02:11:35 PM UTC 24 |
Oct 03 02:12:09 PM UTC 24 |
625066565 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.383943860 |
|
|
Oct 03 02:12:08 PM UTC 24 |
Oct 03 02:12:18 PM UTC 24 |
41458951 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.1065936697 |
|
|
Oct 03 02:12:06 PM UTC 24 |
Oct 03 02:12:19 PM UTC 24 |
213001428 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2114949219 |
|
|
Oct 03 02:12:23 PM UTC 24 |
Oct 03 02:12:38 PM UTC 24 |
97594871 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.2737661008 |
|
|
Oct 03 02:12:19 PM UTC 24 |
Oct 03 02:12:44 PM UTC 24 |
532571550 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3530506404 |
|
|
Oct 03 02:04:35 PM UTC 24 |
Oct 03 02:12:52 PM UTC 24 |
6917282140 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.755454234 |
|
|
Oct 03 02:12:47 PM UTC 24 |
Oct 03 02:13:00 PM UTC 24 |
98968017 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.4103231184 |
|
|
Oct 03 02:12:45 PM UTC 24 |
Oct 03 02:13:21 PM UTC 24 |
707541163 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2750461907 |
|
|
Oct 03 02:03:09 PM UTC 24 |
Oct 03 02:13:30 PM UTC 24 |
42603503075 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1428137907 |
|
|
Oct 03 02:09:59 PM UTC 24 |
Oct 03 02:14:05 PM UTC 24 |
3438907545 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.2046754778 |
|
|
Oct 03 02:13:06 PM UTC 24 |
Oct 03 02:14:06 PM UTC 24 |
968397355 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.925983161 |
|
|
Oct 03 02:06:44 PM UTC 24 |
Oct 03 02:14:07 PM UTC 24 |
10687063370 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1911368954 |
|
|
Oct 03 02:09:27 PM UTC 24 |
Oct 03 02:14:17 PM UTC 24 |
6600574271 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.979404822 |
|
|
Oct 03 02:12:10 PM UTC 24 |
Oct 03 02:14:20 PM UTC 24 |
8377518201 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.845645729 |
|
|
Oct 03 02:12:27 PM UTC 24 |
Oct 03 02:14:20 PM UTC 24 |
831030117 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.328870072 |
|
|
Oct 03 02:13:11 PM UTC 24 |
Oct 03 02:14:23 PM UTC 24 |
1168803737 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1604620872 |
|
|
Oct 03 02:12:14 PM UTC 24 |
Oct 03 02:14:25 PM UTC 24 |
5853294801 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.95103612 |
|
|
Oct 03 01:39:55 PM UTC 24 |
Oct 03 02:14:28 PM UTC 24 |
15525285588 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.1438071593 |
|
|
Oct 03 01:53:47 PM UTC 24 |
Oct 03 02:14:29 PM UTC 24 |
106291922866 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.680269601 |
|
|
Oct 03 02:14:29 PM UTC 24 |
Oct 03 02:14:39 PM UTC 24 |
51885892 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3842657197 |
|
|
Oct 03 02:14:29 PM UTC 24 |
Oct 03 02:14:40 PM UTC 24 |
46740977 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.2689058836 |
|
|
Oct 03 02:07:52 PM UTC 24 |
Oct 03 02:14:45 PM UTC 24 |
37147651523 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.116233898 |
|
|
Oct 03 02:04:25 PM UTC 24 |
Oct 03 02:15:15 PM UTC 24 |
5880102776 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.2294522221 |
|
|
Oct 03 02:15:05 PM UTC 24 |
Oct 03 02:15:34 PM UTC 24 |
554499572 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.2449404266 |
|
|
Oct 03 02:14:53 PM UTC 24 |
Oct 03 02:15:39 PM UTC 24 |
545413607 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.259519969 |
|
|
Oct 03 02:14:48 PM UTC 24 |
Oct 03 02:15:45 PM UTC 24 |
581427886 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.2957323362 |
|
|
Oct 03 02:09:16 PM UTC 24 |
Oct 03 02:15:50 PM UTC 24 |
7821180814 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.469248956 |
|
|
Oct 03 02:09:22 PM UTC 24 |
Oct 03 02:15:51 PM UTC 24 |
3258888787 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1986689816 |
|
|
Oct 03 02:15:10 PM UTC 24 |
Oct 03 02:15:55 PM UTC 24 |
738458328 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.1996258550 |
|
|
Oct 03 02:12:20 PM UTC 24 |
Oct 03 02:15:56 PM UTC 24 |
19634130725 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.856653570 |
|
|
Oct 03 02:15:37 PM UTC 24 |
Oct 03 02:15:57 PM UTC 24 |
336392771 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.2779825070 |
|
|
Oct 03 02:14:41 PM UTC 24 |
Oct 03 02:15:57 PM UTC 24 |
7296010466 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1957128090 |
|
|
Oct 03 02:14:47 PM UTC 24 |
Oct 03 02:16:08 PM UTC 24 |
3812457796 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.3735673986 |
|
|
Oct 03 01:56:24 PM UTC 24 |
Oct 03 02:16:13 PM UTC 24 |
82964360027 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4091098841 |
|
|
Oct 03 02:15:59 PM UTC 24 |
Oct 03 02:16:15 PM UTC 24 |
111461574 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3057422132 |
|
|
Oct 03 01:44:19 PM UTC 24 |
Oct 03 02:16:31 PM UTC 24 |
119615001016 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.605003387 |
|
|
Oct 03 02:16:19 PM UTC 24 |
Oct 03 02:16:34 PM UTC 24 |
172392265 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2201365196 |
|
|
Oct 03 02:16:24 PM UTC 24 |
Oct 03 02:16:34 PM UTC 24 |
44369160 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.57437758 |
|
|
Oct 03 02:12:05 PM UTC 24 |
Oct 03 02:16:39 PM UTC 24 |
3628139996 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2940069958 |
|
|
Oct 03 02:00:10 PM UTC 24 |
Oct 03 02:16:39 PM UTC 24 |
50845228216 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3384022262 |
|
|
Oct 03 02:11:53 PM UTC 24 |
Oct 03 02:16:59 PM UTC 24 |
3026130680 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.3293050906 |
|
|
Oct 03 02:16:38 PM UTC 24 |
Oct 03 02:17:00 PM UTC 24 |
538940600 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1235442569 |
|
|
Oct 03 02:14:46 PM UTC 24 |
Oct 03 02:17:04 PM UTC 24 |
2530349236 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.820197875 |
|
|
Oct 03 02:17:04 PM UTC 24 |
Oct 03 02:17:20 PM UTC 24 |
225794316 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.868736713 |
|
|
Oct 03 02:13:56 PM UTC 24 |
Oct 03 02:17:22 PM UTC 24 |
1232756274 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.2477729559 |
|
|
Oct 03 02:16:40 PM UTC 24 |
Oct 03 02:17:25 PM UTC 24 |
501764007 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.3020634482 |
|
|
Oct 03 02:16:20 PM UTC 24 |
Oct 03 02:17:43 PM UTC 24 |
4689602577 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2987556220 |
|
|
Oct 03 02:17:25 PM UTC 24 |
Oct 03 02:17:45 PM UTC 24 |
189498534 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1288947797 |
|
|
Oct 03 02:11:46 PM UTC 24 |
Oct 03 02:17:45 PM UTC 24 |
1011175296 ps |