| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2090170921 |
|
|
Oct 03 02:16:08 PM UTC 24 |
Oct 03 02:17:51 PM UTC 24 |
330418964 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.4196503696 |
|
|
Oct 03 02:14:26 PM UTC 24 |
Oct 03 02:17:51 PM UTC 24 |
3101009272 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2872269587 |
|
|
Oct 03 02:17:01 PM UTC 24 |
Oct 03 02:17:57 PM UTC 24 |
531751789 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3412713145 |
|
|
Oct 03 02:17:31 PM UTC 24 |
Oct 03 02:18:00 PM UTC 24 |
206454207 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3641083081 |
|
|
Oct 03 02:16:33 PM UTC 24 |
Oct 03 02:18:02 PM UTC 24 |
6136896104 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2430447556 |
|
|
Oct 03 01:54:03 PM UTC 24 |
Oct 03 02:18:17 PM UTC 24 |
93142468978 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2305302357 |
|
|
Oct 03 02:17:25 PM UTC 24 |
Oct 03 02:18:18 PM UTC 24 |
328917607 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.482512300 |
|
|
Oct 03 02:18:09 PM UTC 24 |
Oct 03 02:18:19 PM UTC 24 |
134969934 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1794392293 |
|
|
Oct 03 02:18:13 PM UTC 24 |
Oct 03 02:18:20 PM UTC 24 |
46635478 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3686943283 |
|
|
Oct 03 02:17:46 PM UTC 24 |
Oct 03 02:18:28 PM UTC 24 |
16334542 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3536411345 |
|
|
Oct 03 02:18:26 PM UTC 24 |
Oct 03 02:18:40 PM UTC 24 |
91930326 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.1202629876 |
|
|
Oct 03 01:56:24 PM UTC 24 |
Oct 03 02:18:43 PM UTC 24 |
70776932608 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.1973255244 |
|
|
Oct 03 02:18:25 PM UTC 24 |
Oct 03 02:18:47 PM UTC 24 |
131105582 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.386595919 |
|
|
Oct 03 02:18:45 PM UTC 24 |
Oct 03 02:18:55 PM UTC 24 |
94666632 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3774242106 |
|
|
Oct 03 02:07:55 PM UTC 24 |
Oct 03 02:19:17 PM UTC 24 |
36887410524 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2344228232 |
|
|
Oct 03 02:08:23 PM UTC 24 |
Oct 03 02:19:25 PM UTC 24 |
45648530174 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.550827279 |
|
|
Oct 03 02:13:47 PM UTC 24 |
Oct 03 02:19:26 PM UTC 24 |
9362835777 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.9364960 |
|
|
Oct 03 02:18:53 PM UTC 24 |
Oct 03 02:19:27 PM UTC 24 |
667072238 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1197620196 |
|
|
Oct 03 02:18:08 PM UTC 24 |
Oct 03 02:19:35 PM UTC 24 |
321791569 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.1574630398 |
|
|
Oct 03 02:17:46 PM UTC 24 |
Oct 03 02:19:38 PM UTC 24 |
2606913604 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.944237120 |
|
|
Oct 03 02:18:45 PM UTC 24 |
Oct 03 02:19:44 PM UTC 24 |
2469080077 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.352561082 |
|
|
Oct 03 02:19:41 PM UTC 24 |
Oct 03 02:19:55 PM UTC 24 |
8657198 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2335404565 |
|
|
Oct 03 02:18:25 PM UTC 24 |
Oct 03 02:19:55 PM UTC 24 |
5519034611 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3246656698 |
|
|
Oct 03 02:19:11 PM UTC 24 |
Oct 03 02:20:06 PM UTC 24 |
889077065 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.4138497544 |
|
|
Oct 03 02:19:05 PM UTC 24 |
Oct 03 02:20:08 PM UTC 24 |
1931139125 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1346780546 |
|
|
Oct 03 02:19:17 PM UTC 24 |
Oct 03 02:20:10 PM UTC 24 |
1031924705 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.2107982458 |
|
|
Oct 03 02:11:39 PM UTC 24 |
Oct 03 02:20:11 PM UTC 24 |
4262230200 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3916350711 |
|
|
Oct 03 02:20:02 PM UTC 24 |
Oct 03 02:20:13 PM UTC 24 |
40160373 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.745044321 |
|
|
Oct 03 02:20:05 PM UTC 24 |
Oct 03 02:20:13 PM UTC 24 |
45203993 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.988133468 |
|
|
Oct 03 02:12:35 PM UTC 24 |
Oct 03 02:20:15 PM UTC 24 |
28639329624 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.356013816 |
|
|
Oct 03 02:18:17 PM UTC 24 |
Oct 03 02:20:18 PM UTC 24 |
7495508853 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.991319056 |
|
|
Oct 03 02:06:56 PM UTC 24 |
Oct 03 02:20:27 PM UTC 24 |
5471085525 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2776734191 |
|
|
Oct 03 02:17:51 PM UTC 24 |
Oct 03 02:20:34 PM UTC 24 |
1814223069 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.2329848939 |
|
|
Oct 03 02:16:05 PM UTC 24 |
Oct 03 02:20:34 PM UTC 24 |
5928985721 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1158446136 |
|
|
Oct 03 02:18:44 PM UTC 24 |
Oct 03 02:20:45 PM UTC 24 |
6690192248 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.1716881571 |
|
|
Oct 03 02:16:14 PM UTC 24 |
Oct 03 02:20:49 PM UTC 24 |
2691024347 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2295597510 |
|
|
Oct 03 02:20:45 PM UTC 24 |
Oct 03 02:20:53 PM UTC 24 |
18258759 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1626451180 |
|
|
Oct 03 02:20:21 PM UTC 24 |
Oct 03 02:20:57 PM UTC 24 |
222259673 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.2384638014 |
|
|
Oct 03 02:20:31 PM UTC 24 |
Oct 03 02:21:10 PM UTC 24 |
349142925 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1013094771 |
|
|
Oct 03 02:16:20 PM UTC 24 |
Oct 03 02:21:23 PM UTC 24 |
3674834424 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.2938526145 |
|
|
Oct 03 01:32:45 PM UTC 24 |
Oct 03 02:21:28 PM UTC 24 |
17560486543 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3807473318 |
|
|
Oct 03 02:13:26 PM UTC 24 |
Oct 03 02:21:34 PM UTC 24 |
5367887239 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3498890232 |
|
|
Oct 03 02:21:21 PM UTC 24 |
Oct 03 02:21:34 PM UTC 24 |
184876059 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.559760629 |
|
|
Oct 03 02:20:54 PM UTC 24 |
Oct 03 02:21:35 PM UTC 24 |
811351894 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1457309078 |
|
|
Oct 03 02:21:37 PM UTC 24 |
Oct 03 02:21:49 PM UTC 24 |
41592163 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.3294670044 |
|
|
Oct 03 02:20:40 PM UTC 24 |
Oct 03 02:21:51 PM UTC 24 |
1529411424 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2428339193 |
|
|
Oct 03 02:20:10 PM UTC 24 |
Oct 03 02:21:52 PM UTC 24 |
8844669356 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2607631833 |
|
|
Oct 03 02:20:22 PM UTC 24 |
Oct 03 02:21:53 PM UTC 24 |
5397716700 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.1888344691 |
|
|
Oct 03 02:20:37 PM UTC 24 |
Oct 03 02:21:56 PM UTC 24 |
1470191801 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.2141223021 |
|
|
Oct 03 02:16:57 PM UTC 24 |
Oct 03 02:22:04 PM UTC 24 |
25730062063 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2501906511 |
|
|
Oct 03 02:20:36 PM UTC 24 |
Oct 03 02:22:11 PM UTC 24 |
2454656094 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.3605284355 |
|
|
Oct 03 02:18:12 PM UTC 24 |
Oct 03 02:22:22 PM UTC 24 |
2961526840 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2726706964 |
|
|
Oct 03 02:22:00 PM UTC 24 |
Oct 03 02:22:23 PM UTC 24 |
211697814 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2241007553 |
|
|
Oct 03 02:12:02 PM UTC 24 |
Oct 03 02:22:30 PM UTC 24 |
11514041815 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.2459319045 |
|
|
Oct 03 02:22:21 PM UTC 24 |
Oct 03 02:22:41 PM UTC 24 |
178573900 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2185200285 |
|
|
Oct 03 01:10:45 PM UTC 24 |
Oct 03 02:22:42 PM UTC 24 |
27355593487 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1933663244 |
|
|
Oct 03 02:21:54 PM UTC 24 |
Oct 03 02:22:48 PM UTC 24 |
3244936095 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2438370031 |
|
|
Oct 03 02:16:15 PM UTC 24 |
Oct 03 02:22:51 PM UTC 24 |
6394678437 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2656783015 |
|
|
Oct 03 01:37:58 PM UTC 24 |
Oct 03 02:22:56 PM UTC 24 |
15984755672 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.3427681039 |
|
|
Oct 03 02:22:17 PM UTC 24 |
Oct 03 02:22:58 PM UTC 24 |
822531216 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.2418278227 |
|
|
Oct 03 02:22:20 PM UTC 24 |
Oct 03 02:23:01 PM UTC 24 |
298871338 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.2919740968 |
|
|
Oct 03 02:22:31 PM UTC 24 |
Oct 03 02:23:02 PM UTC 24 |
172011466 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3167569723 |
|
|
Oct 03 02:22:38 PM UTC 24 |
Oct 03 02:23:17 PM UTC 24 |
192382349 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.2111243465 |
|
|
Oct 03 02:22:17 PM UTC 24 |
Oct 03 02:23:22 PM UTC 24 |
4118254817 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1244928742 |
|
|
Oct 03 02:23:18 PM UTC 24 |
Oct 03 02:23:27 PM UTC 24 |
50540168 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.2182729735 |
|
|
Oct 03 02:23:16 PM UTC 24 |
Oct 03 02:23:33 PM UTC 24 |
196822634 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.1193663544 |
|
|
Oct 03 02:21:57 PM UTC 24 |
Oct 03 02:23:34 PM UTC 24 |
2253611338 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.450779650 |
|
|
Oct 03 02:21:49 PM UTC 24 |
Oct 03 02:23:34 PM UTC 24 |
7168954963 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3510185048 |
|
|
Oct 03 02:19:22 PM UTC 24 |
Oct 03 02:23:46 PM UTC 24 |
7200447214 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3501722301 |
|
|
Oct 03 02:21:01 PM UTC 24 |
Oct 03 02:23:51 PM UTC 24 |
1532663094 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3859909177 |
|
|
Oct 03 02:13:19 PM UTC 24 |
Oct 03 02:23:52 PM UTC 24 |
13598537747 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.401668841 |
|
|
Oct 03 02:10:54 PM UTC 24 |
Oct 03 02:23:54 PM UTC 24 |
53264073634 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.387685164 |
|
|
Oct 03 02:23:26 PM UTC 24 |
Oct 03 02:24:08 PM UTC 24 |
412960916 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2342741564 |
|
|
Oct 03 01:47:09 PM UTC 24 |
Oct 03 02:24:08 PM UTC 24 |
142115123308 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2968573923 |
|
|
Oct 03 02:24:00 PM UTC 24 |
Oct 03 02:24:16 PM UTC 24 |
127821685 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.2314413953 |
|
|
Oct 03 02:24:13 PM UTC 24 |
Oct 03 02:24:25 PM UTC 24 |
61405132 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1346381832 |
|
|
Oct 03 02:05:39 PM UTC 24 |
Oct 03 02:24:29 PM UTC 24 |
59207707827 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2672300671 |
|
|
Oct 03 02:24:17 PM UTC 24 |
Oct 03 02:24:33 PM UTC 24 |
92564184 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.2047601412 |
|
|
Oct 03 02:23:29 PM UTC 24 |
Oct 03 02:24:44 PM UTC 24 |
593302993 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2302713014 |
|
|
Oct 03 02:21:04 PM UTC 24 |
Oct 03 02:24:44 PM UTC 24 |
4501942145 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2727859264 |
|
|
Oct 03 02:23:26 PM UTC 24 |
Oct 03 02:24:52 PM UTC 24 |
4765782419 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.122832691 |
|
|
Oct 03 02:23:22 PM UTC 24 |
Oct 03 02:25:00 PM UTC 24 |
10624335161 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3441077077 |
|
|
Oct 03 02:07:04 PM UTC 24 |
Oct 03 02:25:01 PM UTC 24 |
9638534997 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.3119046327 |
|
|
Oct 03 02:24:52 PM UTC 24 |
Oct 03 02:25:02 PM UTC 24 |
54645034 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.149168080 |
|
|
Oct 03 02:24:56 PM UTC 24 |
Oct 03 02:25:09 PM UTC 24 |
48805745 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.674278192 |
|
|
Oct 03 02:23:59 PM UTC 24 |
Oct 03 02:25:17 PM UTC 24 |
1629932206 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2346465192 |
|
|
Oct 03 02:24:18 PM UTC 24 |
Oct 03 02:25:30 PM UTC 24 |
895387717 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2147475780 |
|
|
Oct 03 02:19:51 PM UTC 24 |
Oct 03 02:25:32 PM UTC 24 |
3951128694 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.4132995287 |
|
|
Oct 03 02:12:26 PM UTC 24 |
Oct 03 02:25:44 PM UTC 24 |
37577010647 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2541585823 |
|
|
Oct 03 01:51:25 PM UTC 24 |
Oct 03 02:25:49 PM UTC 24 |
128525738745 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3354131909 |
|
|
Oct 03 02:25:45 PM UTC 24 |
Oct 03 02:26:04 PM UTC 24 |
270818781 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.2283275952 |
|
|
Oct 03 02:14:55 PM UTC 24 |
Oct 03 02:26:05 PM UTC 24 |
39622997195 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2711770478 |
|
|
Oct 03 02:25:00 PM UTC 24 |
Oct 03 02:26:05 PM UTC 24 |
5106405983 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.3811874319 |
|
|
Oct 03 02:22:49 PM UTC 24 |
Oct 03 02:26:09 PM UTC 24 |
5439306763 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3550372017 |
|
|
Oct 03 02:19:49 PM UTC 24 |
Oct 03 02:26:12 PM UTC 24 |
5322331916 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1835510048 |
|
|
Oct 03 01:56:31 PM UTC 24 |
Oct 03 02:26:17 PM UTC 24 |
122419926626 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.2586436340 |
|
|
Oct 03 02:14:53 PM UTC 24 |
Oct 03 02:26:22 PM UTC 24 |
55196792082 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1209928982 |
|
|
Oct 03 02:23:10 PM UTC 24 |
Oct 03 02:26:30 PM UTC 24 |
2518073412 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2383084738 |
|
|
Oct 03 02:25:18 PM UTC 24 |
Oct 03 02:26:30 PM UTC 24 |
609698138 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3856238762 |
|
|
Oct 03 02:25:56 PM UTC 24 |
Oct 03 02:26:34 PM UTC 24 |
723714606 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1240652281 |
|
|
Oct 03 02:19:51 PM UTC 24 |
Oct 03 02:26:41 PM UTC 24 |
11519641283 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1036065469 |
|
|
Oct 03 02:23:53 PM UTC 24 |
Oct 03 02:26:44 PM UTC 24 |
3720169298 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3822075332 |
|
|
Oct 03 02:26:36 PM UTC 24 |
Oct 03 02:26:45 PM UTC 24 |
53706135 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2960770190 |
|
|
Oct 03 02:18:43 PM UTC 24 |
Oct 03 02:26:46 PM UTC 24 |
42923004057 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2962909511 |
|
|
Oct 03 02:26:12 PM UTC 24 |
Oct 03 02:26:46 PM UTC 24 |
236899565 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.3768247546 |
|
|
Oct 03 02:26:34 PM UTC 24 |
Oct 03 02:26:47 PM UTC 24 |
200037484 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2807469087 |
|
|
Oct 03 02:25:11 PM UTC 24 |
Oct 03 02:26:47 PM UTC 24 |
5257154162 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.3901885420 |
|
|
Oct 03 02:25:12 PM UTC 24 |
Oct 03 02:26:48 PM UTC 24 |
2279765504 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.372121085 |
|
|
Oct 03 02:23:09 PM UTC 24 |
Oct 03 02:26:49 PM UTC 24 |
769804132 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2509025467 |
|
|
Oct 03 01:10:45 PM UTC 24 |
Oct 03 02:26:53 PM UTC 24 |
25523233136 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.384357542 |
|
|
Oct 03 02:25:59 PM UTC 24 |
Oct 03 02:26:55 PM UTC 24 |
1002414413 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.195755158 |
|
|
Oct 03 02:25:27 PM UTC 24 |
Oct 03 02:27:01 PM UTC 24 |
959848127 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2858215435 |
|
|
Oct 03 02:24:20 PM UTC 24 |
Oct 03 02:27:02 PM UTC 24 |
239602791 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1600220579 |
|
|
Oct 03 02:22:50 PM UTC 24 |
Oct 03 02:27:04 PM UTC 24 |
508589191 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3531981510 |
|
|
Oct 03 02:26:56 PM UTC 24 |
Oct 03 02:27:17 PM UTC 24 |
160579836 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.790288423 |
|
|
Oct 03 02:27:14 PM UTC 24 |
Oct 03 02:27:29 PM UTC 24 |
67816563 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.2440087634 |
|
|
Oct 03 02:21:13 PM UTC 24 |
Oct 03 02:27:30 PM UTC 24 |
9341493596 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.1147376384 |
|
|
Oct 03 01:25:21 PM UTC 24 |
Oct 03 02:27:31 PM UTC 24 |
31617196124 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3779770413 |
|
|
Oct 03 02:27:25 PM UTC 24 |
Oct 03 02:27:33 PM UTC 24 |
46279146 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.1921317599 |
|
|
Oct 03 02:21:21 PM UTC 24 |
Oct 03 02:27:37 PM UTC 24 |
4221230690 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1839391823 |
|
|
Oct 03 02:26:43 PM UTC 24 |
Oct 03 02:27:40 PM UTC 24 |
5844269798 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.3351353645 |
|
|
Oct 03 02:27:07 PM UTC 24 |
Oct 03 02:27:43 PM UTC 24 |
313176694 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.294327193 |
|
|
Oct 03 02:27:12 PM UTC 24 |
Oct 03 02:27:44 PM UTC 24 |
656670069 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.71595768 |
|
|
Oct 03 02:27:26 PM UTC 24 |
Oct 03 02:27:44 PM UTC 24 |
253289422 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.3440495976 |
|
|
Oct 03 02:27:12 PM UTC 24 |
Oct 03 02:27:59 PM UTC 24 |
949608783 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.3647022902 |
|
|
Oct 03 01:48:31 PM UTC 24 |
Oct 03 02:28:26 PM UTC 24 |
14524374605 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.4001488643 |
|
|
Oct 03 02:28:09 PM UTC 24 |
Oct 03 02:28:31 PM UTC 24 |
113866120 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.1785060174 |
|
|
Oct 03 02:26:54 PM UTC 24 |
Oct 03 02:28:35 PM UTC 24 |
2512163081 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.2226615245 |
|
|
Oct 03 02:28:08 PM UTC 24 |
Oct 03 02:28:38 PM UTC 24 |
515864110 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3100552421 |
|
|
Oct 03 02:27:15 PM UTC 24 |
Oct 03 02:28:43 PM UTC 24 |
1055962808 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2441124358 |
|
|
Oct 03 02:28:02 PM UTC 24 |
Oct 03 02:28:45 PM UTC 24 |
298256926 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3539387908 |
|
|
Oct 03 02:27:42 PM UTC 24 |
Oct 03 02:28:51 PM UTC 24 |
4515792408 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.3857557598 |
|
|
Oct 03 02:27:53 PM UTC 24 |
Oct 03 02:28:53 PM UTC 24 |
406684015 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.712989266 |
|
|
Oct 03 02:26:47 PM UTC 24 |
Oct 03 02:28:56 PM UTC 24 |
5470224425 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.1260191365 |
|
|
Oct 03 02:27:11 PM UTC 24 |
Oct 03 02:29:00 PM UTC 24 |
2058130532 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1681193240 |
|
|
Oct 03 02:26:31 PM UTC 24 |
Oct 03 02:29:08 PM UTC 24 |
397258626 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2669969238 |
|
|
Oct 03 02:28:24 PM UTC 24 |
Oct 03 02:29:08 PM UTC 24 |
902151945 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.4059193526 |
|
|
Oct 03 02:10:50 PM UTC 24 |
Oct 03 02:29:15 PM UTC 24 |
94867324249 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.323154883 |
|
|
Oct 03 02:29:06 PM UTC 24 |
Oct 03 02:29:17 PM UTC 24 |
48508750 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.1274711399 |
|
|
Oct 03 02:28:08 PM UTC 24 |
Oct 03 02:29:18 PM UTC 24 |
1364016965 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2231696364 |
|
|
Oct 03 02:27:26 PM UTC 24 |
Oct 03 02:29:20 PM UTC 24 |
6930603816 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3266152422 |
|
|
Oct 03 02:29:10 PM UTC 24 |
Oct 03 02:29:23 PM UTC 24 |
225971924 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.899128007 |
|
|
Oct 03 02:36:02 PM UTC 24 |
Oct 03 02:37:02 PM UTC 24 |
5109614448 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3407790480 |
|
|
Oct 03 02:27:16 PM UTC 24 |
Oct 03 02:29:36 PM UTC 24 |
324646008 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2078230141 |
|
|
Oct 03 02:27:51 PM UTC 24 |
Oct 03 02:29:44 PM UTC 24 |
2280143210 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.248406583 |
|
|
Oct 03 02:29:48 PM UTC 24 |
Oct 03 02:29:55 PM UTC 24 |
62548483 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.251268126 |
|
|
Oct 03 02:29:42 PM UTC 24 |
Oct 03 02:29:56 PM UTC 24 |
49824145 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.3370150535 |
|
|
Oct 03 02:29:24 PM UTC 24 |
Oct 03 02:30:00 PM UTC 24 |
267161957 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.570927513 |
|
|
Oct 03 02:29:16 PM UTC 24 |
Oct 03 02:30:26 PM UTC 24 |
2914606297 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3428255794 |
|
|
Oct 03 02:30:03 PM UTC 24 |
Oct 03 02:30:27 PM UTC 24 |
165187579 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.416239903 |
|
|
Oct 03 02:24:39 PM UTC 24 |
Oct 03 02:30:28 PM UTC 24 |
4351556900 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.3270746813 |
|
|
Oct 03 02:25:30 PM UTC 24 |
Oct 03 02:30:29 PM UTC 24 |
18474999322 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3684259120 |
|
|
Oct 03 02:22:54 PM UTC 24 |
Oct 03 02:30:32 PM UTC 24 |
11905353308 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.1511717971 |
|
|
Oct 03 02:16:59 PM UTC 24 |
Oct 03 02:30:36 PM UTC 24 |
62616309719 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.4067924929 |
|
|
Oct 03 02:29:45 PM UTC 24 |
Oct 03 02:30:42 PM UTC 24 |
1286546886 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.3394187793 |
|
|
Oct 03 02:26:15 PM UTC 24 |
Oct 03 02:30:44 PM UTC 24 |
7320141705 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.2744214173 |
|
|
Oct 03 02:29:20 PM UTC 24 |
Oct 03 02:30:48 PM UTC 24 |
2193771594 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.986959219 |
|
|
Oct 03 02:30:50 PM UTC 24 |
Oct 03 02:31:01 PM UTC 24 |
187167295 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.398538819 |
|
|
Oct 03 02:30:55 PM UTC 24 |
Oct 03 02:31:05 PM UTC 24 |
48663990 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3384902755 |
|
|
Oct 03 02:29:04 PM UTC 24 |
Oct 03 02:31:13 PM UTC 24 |
666356037 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.2388910826 |
|
|
Oct 03 02:29:16 PM UTC 24 |
Oct 03 02:31:30 PM UTC 24 |
10301401136 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.3748975855 |
|
|
Oct 03 02:31:05 PM UTC 24 |
Oct 03 02:31:39 PM UTC 24 |
346352719 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.857773099 |
|
|
Oct 03 02:29:38 PM UTC 24 |
Oct 03 02:31:52 PM UTC 24 |
2287551618 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3309279138 |
|
|
Oct 03 02:26:30 PM UTC 24 |
Oct 03 02:31:53 PM UTC 24 |
9453868390 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.3766854252 |
|
|
Oct 03 02:28:53 PM UTC 24 |
Oct 03 02:31:54 PM UTC 24 |
3555608884 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.3239699631 |
|
|
Oct 03 02:31:39 PM UTC 24 |
Oct 03 02:31:54 PM UTC 24 |
289494697 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2312556616 |
|
|
Oct 03 02:30:59 PM UTC 24 |
Oct 03 02:31:55 PM UTC 24 |
1141493856 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1284666046 |
|
|
Oct 03 02:27:12 PM UTC 24 |
Oct 03 02:32:14 PM UTC 24 |
1783338662 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.1962567241 |
|
|
Oct 03 02:20:35 PM UTC 24 |
Oct 03 02:32:16 PM UTC 24 |
62406446467 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1227779612 |
|
|
Oct 03 02:30:22 PM UTC 24 |
Oct 03 02:32:16 PM UTC 24 |
136029617 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.974760931 |
|
|
Oct 03 02:31:56 PM UTC 24 |
Oct 03 02:32:25 PM UTC 24 |
152687548 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.2494861570 |
|
|
Oct 03 02:32:21 PM UTC 24 |
Oct 03 02:32:30 PM UTC 24 |
42693836 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.1129590693 |
|
|
Oct 03 02:31:33 PM UTC 24 |
Oct 03 02:32:32 PM UTC 24 |
1606327415 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1785927438 |
|
|
Oct 03 02:30:55 PM UTC 24 |
Oct 03 02:32:33 PM UTC 24 |
5575128936 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1309709119 |
|
|
Oct 03 02:32:18 PM UTC 24 |
Oct 03 02:32:36 PM UTC 24 |
205771080 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.933093596 |
|
|
Oct 03 02:27:11 PM UTC 24 |
Oct 03 02:32:36 PM UTC 24 |
3531673580 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.1966278973 |
|
|
Oct 03 02:30:53 PM UTC 24 |
Oct 03 02:32:39 PM UTC 24 |
8896818985 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.252094366 |
|
|
Oct 03 02:32:19 PM UTC 24 |
Oct 03 02:32:47 PM UTC 24 |
264173681 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.4181377375 |
|
|
Oct 03 02:32:43 PM UTC 24 |
Oct 03 02:32:54 PM UTC 24 |
45483858 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.3041899986 |
|
|
Oct 03 02:20:34 PM UTC 24 |
Oct 03 02:33:03 PM UTC 24 |
41724832018 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.4116512412 |
|
|
Oct 03 02:30:24 PM UTC 24 |
Oct 03 02:33:03 PM UTC 24 |
1367071794 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3113422167 |
|
|
Oct 03 02:32:07 PM UTC 24 |
Oct 03 02:33:10 PM UTC 24 |
1460488031 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3686779053 |
|
|
Oct 03 02:24:36 PM UTC 24 |
Oct 03 02:33:14 PM UTC 24 |
13238906905 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.3567735314 |
|
|
Oct 03 02:32:55 PM UTC 24 |
Oct 03 02:33:32 PM UTC 24 |
239370687 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.152343279 |
|
|
Oct 03 02:25:28 PM UTC 24 |
Oct 03 02:33:36 PM UTC 24 |
33289492052 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1574452112 |
|
|
Oct 03 02:33:27 PM UTC 24 |
Oct 03 02:33:43 PM UTC 24 |
98827302 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.754055358 |
|
|
Oct 03 02:31:15 PM UTC 24 |
Oct 03 02:33:51 PM UTC 24 |
3245338103 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.777780529 |
|
|
Oct 03 02:30:25 PM UTC 24 |
Oct 03 02:33:53 PM UTC 24 |
727085529 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.3215063830 |
|
|
Oct 03 02:33:03 PM UTC 24 |
Oct 03 02:33:56 PM UTC 24 |
1954307555 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.927746564 |
|
|
Oct 03 02:32:53 PM UTC 24 |
Oct 03 02:33:59 PM UTC 24 |
589562876 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2772264194 |
|
|
Oct 03 02:33:39 PM UTC 24 |
Oct 03 02:34:13 PM UTC 24 |
48297816 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1830288983 |
|
|
Oct 03 02:34:01 PM UTC 24 |
Oct 03 02:34:14 PM UTC 24 |
165471752 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.2787978009 |
|
|
Oct 03 02:33:15 PM UTC 24 |
Oct 03 02:34:16 PM UTC 24 |
1140595326 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.3292715825 |
|
|
Oct 03 02:30:10 PM UTC 24 |
Oct 03 02:34:17 PM UTC 24 |
2239541849 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3703326578 |
|
|
Oct 03 02:34:09 PM UTC 24 |
Oct 03 02:34:17 PM UTC 24 |
39843771 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.89897942 |
|
|
Oct 03 02:32:37 PM UTC 24 |
Oct 03 02:34:34 PM UTC 24 |
5524691577 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.3092212492 |
|
|
Oct 03 02:32:42 PM UTC 24 |
Oct 03 02:34:47 PM UTC 24 |
8634208759 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.144076973 |
|
|
Oct 03 01:22:21 PM UTC 24 |
Oct 03 02:34:47 PM UTC 24 |
30756576440 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2733964434 |
|
|
Oct 03 02:34:26 PM UTC 24 |
Oct 03 02:34:56 PM UTC 24 |
227368540 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.3626099539 |
|
|
Oct 03 02:29:00 PM UTC 24 |
Oct 03 02:35:09 PM UTC 24 |
8590983896 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3045438815 |
|
|
Oct 03 02:22:03 PM UTC 24 |
Oct 03 02:35:19 PM UTC 24 |
85439429225 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.3111332135 |
|
|
Oct 03 02:33:32 PM UTC 24 |
Oct 03 02:35:20 PM UTC 24 |
1092637522 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.864386910 |
|
|
Oct 03 02:35:13 PM UTC 24 |
Oct 03 02:35:29 PM UTC 24 |
59269680 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.1210840685 |
|
|
Oct 03 02:34:40 PM UTC 24 |
Oct 03 02:35:29 PM UTC 24 |
447534001 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.107956933 |
|
|
Oct 03 02:33:15 PM UTC 24 |
Oct 03 02:35:37 PM UTC 24 |
2491250281 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.2640444091 |
|
|
Oct 03 02:35:00 PM UTC 24 |
Oct 03 02:35:42 PM UTC 24 |
1011892111 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2863575389 |
|
|
Oct 03 02:34:21 PM UTC 24 |
Oct 03 02:35:50 PM UTC 24 |
2382660373 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.252574040 |
|
|
Oct 03 02:35:14 PM UTC 24 |
Oct 03 02:35:56 PM UTC 24 |
247712259 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1101368882 |
|
|
Oct 03 02:34:19 PM UTC 24 |
Oct 03 02:36:04 PM UTC 24 |
5527559299 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.1021896018 |
|
|
Oct 03 02:34:44 PM UTC 24 |
Oct 03 02:36:08 PM UTC 24 |
2578831451 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3777978697 |
|
|
Oct 03 02:35:59 PM UTC 24 |
Oct 03 02:36:08 PM UTC 24 |
50577322 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.1784284852 |
|
|
Oct 03 02:35:59 PM UTC 24 |
Oct 03 02:36:09 PM UTC 24 |
43657321 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3268705542 |
|
|
Oct 03 02:34:18 PM UTC 24 |
Oct 03 02:36:10 PM UTC 24 |
8636788674 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.970731407 |
|
|
Oct 03 02:33:04 PM UTC 24 |
Oct 03 02:36:21 PM UTC 24 |
3599995996 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1345240520 |
|
|
Oct 03 02:11:08 PM UTC 24 |
Oct 03 02:36:23 PM UTC 24 |
71793223123 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3790502199 |
|
|
Oct 03 02:33:59 PM UTC 24 |
Oct 03 02:36:34 PM UTC 24 |
296116081 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.3171156328 |
|
|
Oct 03 02:36:19 PM UTC 24 |
Oct 03 02:36:34 PM UTC 24 |
106833208 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.1263733767 |
|
|
Oct 03 02:36:10 PM UTC 24 |
Oct 03 02:36:38 PM UTC 24 |
239531783 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.2289317799 |
|
|
Oct 03 02:33:40 PM UTC 24 |
Oct 03 02:36:49 PM UTC 24 |
4352621084 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.3753570704 |
|
|
Oct 03 02:29:32 PM UTC 24 |
Oct 03 02:36:50 PM UTC 24 |
31344968544 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2772986767 |
|
|
Oct 03 02:24:00 PM UTC 24 |
Oct 03 02:36:55 PM UTC 24 |
44027837361 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1056930525 |
|
|
Oct 03 02:36:49 PM UTC 24 |
Oct 03 02:37:12 PM UTC 24 |
376216764 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.346495387 |
|
|
Oct 03 02:26:30 PM UTC 24 |
Oct 03 02:37:12 PM UTC 24 |
9070038445 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.997323326 |
|
|
Oct 03 02:21:16 PM UTC 24 |
Oct 03 02:37:16 PM UTC 24 |
20911805646 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1195142711 |
|
|
Oct 03 02:32:18 PM UTC 24 |
Oct 03 02:37:19 PM UTC 24 |
581811769 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3130768854 |
|
|
Oct 03 02:24:35 PM UTC 24 |
Oct 03 02:37:22 PM UTC 24 |
7616143269 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1446555217 |
|
|
Oct 03 02:36:45 PM UTC 24 |
Oct 03 02:37:27 PM UTC 24 |
666774369 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.771863653 |
|
|
Oct 03 02:37:21 PM UTC 24 |
Oct 03 02:37:29 PM UTC 24 |
42359827 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.859813940 |
|
|
Oct 03 02:36:36 PM UTC 24 |
Oct 03 02:37:31 PM UTC 24 |
475984847 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.912389388 |
|
|
Oct 03 02:36:05 PM UTC 24 |
Oct 03 02:37:31 PM UTC 24 |
4508698131 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.1482888280 |
|
|
Oct 03 02:37:16 PM UTC 24 |
Oct 03 02:37:31 PM UTC 24 |
242200496 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1043558892 |
|
|
Oct 03 02:27:06 PM UTC 24 |
Oct 03 02:37:35 PM UTC 24 |
32589087986 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3366090406 |
|
|
Oct 03 02:38:04 PM UTC 24 |
Oct 03 02:38:15 PM UTC 24 |
62840549 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2559481564 |
|
|
Oct 03 02:32:20 PM UTC 24 |
Oct 03 02:38:15 PM UTC 24 |
5368862740 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.3372289023 |
|
|
Oct 03 02:36:36 PM UTC 24 |
Oct 03 02:38:20 PM UTC 24 |
2374181773 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2957857339 |
|
|
Oct 03 02:37:40 PM UTC 24 |
Oct 03 02:38:22 PM UTC 24 |
389021734 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1475493966 |
|
|
Oct 03 02:37:17 PM UTC 24 |
Oct 03 02:38:38 PM UTC 24 |
199920287 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.1299148235 |
|
|
Oct 03 02:38:00 PM UTC 24 |
Oct 03 02:38:38 PM UTC 24 |
725771802 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.897821534 |
|
|
Oct 03 02:37:54 PM UTC 24 |
Oct 03 02:38:45 PM UTC 24 |
645213655 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.2742544149 |
|
|
Oct 03 02:38:00 PM UTC 24 |
Oct 03 02:38:49 PM UTC 24 |
877994300 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3613804323 |
|
|
Oct 03 02:37:38 PM UTC 24 |
Oct 03 02:38:54 PM UTC 24 |
1965868575 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.2141503279 |
|
|
Oct 03 02:37:29 PM UTC 24 |
Oct 03 02:38:54 PM UTC 24 |
7959426660 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.200048390 |
|
|
Oct 03 02:37:59 PM UTC 24 |
Oct 03 02:39:00 PM UTC 24 |
1205546780 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.821873365 |
|
|
Oct 03 02:36:33 PM UTC 24 |
Oct 03 02:39:01 PM UTC 24 |
2699221188 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.2506751003 |
|
|
Oct 03 02:23:49 PM UTC 24 |
Oct 03 02:39:13 PM UTC 24 |
61695727837 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.3374030220 |
|
|
Oct 03 02:39:03 PM UTC 24 |
Oct 03 02:39:14 PM UTC 24 |
180343462 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1622475286 |
|
|
Oct 03 02:39:05 PM UTC 24 |
Oct 03 02:39:17 PM UTC 24 |
54366659 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2255045736 |
|
|
Oct 03 02:23:44 PM UTC 24 |
Oct 03 02:39:25 PM UTC 24 |
68998849025 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.1160793817 |
|
|
Oct 03 02:34:40 PM UTC 24 |
Oct 03 02:39:29 PM UTC 24 |
19629813909 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1413178905 |
|
|
Oct 03 02:28:56 PM UTC 24 |
Oct 03 02:39:39 PM UTC 24 |
3864937028 ps |