| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3201583041 |
|
|
Oct 03 08:08:41 PM UTC 24 |
Oct 03 08:18:01 PM UTC 24 |
5121378500 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.2064528792 |
|
|
Oct 03 05:41:33 PM UTC 24 |
Oct 03 08:19:34 PM UTC 24 |
56025887568 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.3190825857 |
|
|
Oct 03 08:15:03 PM UTC 24 |
Oct 03 08:19:53 PM UTC 24 |
2981794366 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2318076180 |
|
|
Oct 03 08:08:52 PM UTC 24 |
Oct 03 08:20:23 PM UTC 24 |
5112515252 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.4257113630 |
|
|
Oct 03 08:10:17 PM UTC 24 |
Oct 03 08:20:31 PM UTC 24 |
4442102952 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.1558370741 |
|
|
Oct 03 08:14:51 PM UTC 24 |
Oct 03 08:20:37 PM UTC 24 |
3299457788 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.4031084554 |
|
|
Oct 03 08:09:58 PM UTC 24 |
Oct 03 08:21:11 PM UTC 24 |
3391822296 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.431924742 |
|
|
Oct 03 08:13:14 PM UTC 24 |
Oct 03 08:21:25 PM UTC 24 |
3466389426 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3532308571 |
|
|
Oct 03 08:15:09 PM UTC 24 |
Oct 03 08:21:29 PM UTC 24 |
3701770102 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.1966448514 |
|
|
Oct 03 06:43:26 PM UTC 24 |
Oct 03 08:21:47 PM UTC 24 |
45467714800 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.437951010 |
|
|
Oct 03 08:10:00 PM UTC 24 |
Oct 03 08:21:50 PM UTC 24 |
4974502900 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.4182532658 |
|
|
Oct 03 08:08:39 PM UTC 24 |
Oct 03 08:22:08 PM UTC 24 |
6221235912 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.969819879 |
|
|
Oct 03 08:10:57 PM UTC 24 |
Oct 03 08:24:03 PM UTC 24 |
4732325006 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.285477462 |
|
|
Oct 03 08:17:23 PM UTC 24 |
Oct 03 08:24:10 PM UTC 24 |
3590602463 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2709232398 |
|
|
Oct 03 08:15:04 PM UTC 24 |
Oct 03 08:24:19 PM UTC 24 |
3406107024 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1420673097 |
|
|
Oct 03 08:14:39 PM UTC 24 |
Oct 03 08:24:48 PM UTC 24 |
4496903539 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.8350099 |
|
|
Oct 03 08:16:01 PM UTC 24 |
Oct 03 08:24:59 PM UTC 24 |
4869013661 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.1449020337 |
|
|
Oct 03 08:22:13 PM UTC 24 |
Oct 03 08:27:04 PM UTC 24 |
3040482952 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.2728712909 |
|
|
Oct 03 07:43:27 PM UTC 24 |
Oct 03 08:27:52 PM UTC 24 |
23185695285 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1318849414 |
|
|
Oct 03 08:22:47 PM UTC 24 |
Oct 03 08:28:01 PM UTC 24 |
2624964134 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.887733538 |
|
|
Oct 03 08:15:09 PM UTC 24 |
Oct 03 08:28:06 PM UTC 24 |
6130758349 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.1408231103 |
|
|
Oct 03 08:17:53 PM UTC 24 |
Oct 03 08:28:14 PM UTC 24 |
3897274140 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2578379648 |
|
|
Oct 03 08:21:22 PM UTC 24 |
Oct 03 08:28:31 PM UTC 24 |
2906549160 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1031504043 |
|
|
Oct 03 07:05:26 PM UTC 24 |
Oct 03 08:28:55 PM UTC 24 |
18823644083 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.2729777342 |
|
|
Oct 03 08:14:42 PM UTC 24 |
Oct 03 08:29:05 PM UTC 24 |
5512101336 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1389367563 |
|
|
Oct 03 08:15:08 PM UTC 24 |
Oct 03 08:29:17 PM UTC 24 |
5237251592 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1421065729 |
|
|
Oct 03 08:18:40 PM UTC 24 |
Oct 03 08:29:46 PM UTC 24 |
3828522915 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.614783489 |
|
|
Oct 03 08:25:22 PM UTC 24 |
Oct 03 08:30:25 PM UTC 24 |
2983878330 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2982850953 |
|
|
Oct 03 08:25:04 PM UTC 24 |
Oct 03 08:30:36 PM UTC 24 |
3047202727 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1836360808 |
|
|
Oct 03 08:20:14 PM UTC 24 |
Oct 03 08:30:40 PM UTC 24 |
5219820996 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4138009044 |
|
|
Oct 03 08:29:18 PM UTC 24 |
Oct 03 08:31:15 PM UTC 24 |
2173534490 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2432901366 |
|
|
Oct 03 07:48:32 PM UTC 24 |
Oct 03 08:31:46 PM UTC 24 |
23348334737 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2090459972 |
|
|
Oct 03 08:14:38 PM UTC 24 |
Oct 03 08:32:15 PM UTC 24 |
4572510264 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3159090357 |
|
|
Oct 03 08:29:37 PM UTC 24 |
Oct 03 08:32:27 PM UTC 24 |
2725131340 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1478577856 |
|
|
Oct 03 07:35:33 PM UTC 24 |
Oct 03 08:33:13 PM UTC 24 |
23334080795 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3036663143 |
|
|
Oct 03 08:22:45 PM UTC 24 |
Oct 03 08:33:28 PM UTC 24 |
4474973220 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2680995417 |
|
|
Oct 03 08:29:14 PM UTC 24 |
Oct 03 08:35:16 PM UTC 24 |
2730607694 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.3084775002 |
|
|
Oct 03 08:25:43 PM UTC 24 |
Oct 03 08:35:35 PM UTC 24 |
4403440200 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.3968344258 |
|
|
Oct 03 08:31:39 PM UTC 24 |
Oct 03 08:35:35 PM UTC 24 |
3166131094 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.81005328 |
|
|
Oct 03 08:09:53 PM UTC 24 |
Oct 03 08:35:55 PM UTC 24 |
9829867960 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.3628714337 |
|
|
Oct 03 08:30:25 PM UTC 24 |
Oct 03 08:37:46 PM UTC 24 |
3761659752 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.3194658562 |
|
|
Oct 03 08:20:33 PM UTC 24 |
Oct 03 08:38:17 PM UTC 24 |
5416875344 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.766271830 |
|
|
Oct 03 07:21:22 PM UTC 24 |
Oct 03 08:38:30 PM UTC 24 |
12977540800 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2204307585 |
|
|
Oct 03 07:03:50 PM UTC 24 |
Oct 03 08:38:41 PM UTC 24 |
17121699980 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.2136604880 |
|
|
Oct 03 07:49:57 PM UTC 24 |
Oct 03 08:39:24 PM UTC 24 |
18993388483 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2370908334 |
|
|
Oct 03 08:31:35 PM UTC 24 |
Oct 03 08:39:33 PM UTC 24 |
6914783024 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.2687647409 |
|
|
Oct 03 07:42:46 PM UTC 24 |
Oct 03 08:39:48 PM UTC 24 |
25921507173 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.320036804 |
|
|
Oct 03 08:31:56 PM UTC 24 |
Oct 03 08:40:22 PM UTC 24 |
4426686304 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2246699829 |
|
|
Oct 03 08:22:12 PM UTC 24 |
Oct 03 08:41:16 PM UTC 24 |
6366461241 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.2069540734 |
|
|
Oct 03 08:27:45 PM UTC 24 |
Oct 03 08:41:17 PM UTC 24 |
5230582865 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.1372002499 |
|
|
Oct 03 06:49:40 PM UTC 24 |
Oct 03 08:41:24 PM UTC 24 |
47963963522 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3611370493 |
|
|
Oct 03 06:47:49 PM UTC 24 |
Oct 03 08:41:42 PM UTC 24 |
49864740585 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2659889122 |
|
|
Oct 03 08:21:19 PM UTC 24 |
Oct 03 08:42:07 PM UTC 24 |
6155300494 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1138135388 |
|
|
Oct 03 08:38:54 PM UTC 24 |
Oct 03 08:43:43 PM UTC 24 |
2587425556 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3091176364 |
|
|
Oct 03 08:36:32 PM UTC 24 |
Oct 03 08:44:36 PM UTC 24 |
8158996408 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.3962795093 |
|
|
Oct 03 08:01:08 PM UTC 24 |
Oct 03 08:46:00 PM UTC 24 |
10803294000 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.1023307899 |
|
|
Oct 03 08:39:22 PM UTC 24 |
Oct 03 08:46:04 PM UTC 24 |
2576284870 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1379900119 |
|
|
Oct 03 08:29:17 PM UTC 24 |
Oct 03 08:46:28 PM UTC 24 |
8720362093 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3733611622 |
|
|
Oct 03 08:25:04 PM UTC 24 |
Oct 03 08:46:30 PM UTC 24 |
8123032200 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.2453460532 |
|
|
Oct 03 08:31:40 PM UTC 24 |
Oct 03 08:46:38 PM UTC 24 |
6620795380 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.102407810 |
|
|
Oct 03 08:36:32 PM UTC 24 |
Oct 03 08:47:09 PM UTC 24 |
8087674732 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.53146306 |
|
|
Oct 03 08:25:07 PM UTC 24 |
Oct 03 08:47:12 PM UTC 24 |
6543123960 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3200318294 |
|
|
Oct 03 08:40:27 PM UTC 24 |
Oct 03 08:47:23 PM UTC 24 |
3404799892 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.810076946 |
|
|
Oct 03 08:39:18 PM UTC 24 |
Oct 03 08:47:53 PM UTC 24 |
4512644200 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1875142664 |
|
|
Oct 03 08:41:01 PM UTC 24 |
Oct 03 08:48:55 PM UTC 24 |
5613039692 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2897341632 |
|
|
Oct 03 08:42:29 PM UTC 24 |
Oct 03 08:49:37 PM UTC 24 |
3409220056 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3110816569 |
|
|
Oct 03 08:13:51 PM UTC 24 |
Oct 03 08:49:40 PM UTC 24 |
8850729172 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.2448916276 |
|
|
Oct 03 08:42:30 PM UTC 24 |
Oct 03 08:50:21 PM UTC 24 |
3419379488 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.208145616 |
|
|
Oct 03 08:22:48 PM UTC 24 |
Oct 03 08:50:49 PM UTC 24 |
7731464988 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.915837626 |
|
|
Oct 03 08:42:27 PM UTC 24 |
Oct 03 08:50:53 PM UTC 24 |
6379427880 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.105718991 |
|
|
Oct 03 08:35:55 PM UTC 24 |
Oct 03 08:52:21 PM UTC 24 |
7488341394 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1117187893 |
|
|
Oct 03 08:32:27 PM UTC 24 |
Oct 03 08:52:30 PM UTC 24 |
7631913400 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.3256873972 |
|
|
Oct 03 08:48:07 PM UTC 24 |
Oct 03 08:52:45 PM UTC 24 |
2880554288 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.3844168874 |
|
|
Oct 03 08:49:34 PM UTC 24 |
Oct 03 08:53:17 PM UTC 24 |
3322485040 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.380690221 |
|
|
Oct 03 08:48:33 PM UTC 24 |
Oct 03 08:53:20 PM UTC 24 |
3060183781 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2574409482 |
|
|
Oct 03 07:52:38 PM UTC 24 |
Oct 03 08:54:32 PM UTC 24 |
11895074363 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.1191519510 |
|
|
Oct 03 08:31:38 PM UTC 24 |
Oct 03 08:54:57 PM UTC 24 |
11647510720 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.701220137 |
|
|
Oct 03 08:40:31 PM UTC 24 |
Oct 03 08:55:07 PM UTC 24 |
5005332387 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.2554210140 |
|
|
Oct 03 06:47:50 PM UTC 24 |
Oct 03 08:55:25 PM UTC 24 |
46615088133 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3072530700 |
|
|
Oct 03 08:45:15 PM UTC 24 |
Oct 03 08:55:27 PM UTC 24 |
5575165226 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3952820274 |
|
|
Oct 03 08:34:08 PM UTC 24 |
Oct 03 08:55:53 PM UTC 24 |
9382160904 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3948925296 |
|
|
Oct 03 08:21:19 PM UTC 24 |
Oct 03 08:56:22 PM UTC 24 |
21583259214 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.411807945 |
|
|
Oct 03 08:50:29 PM UTC 24 |
Oct 03 08:56:45 PM UTC 24 |
3190686668 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2597871421 |
|
|
Oct 03 08:47:32 PM UTC 24 |
Oct 03 08:56:55 PM UTC 24 |
3116697200 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.2715983475 |
|
|
Oct 03 08:50:30 PM UTC 24 |
Oct 03 08:57:20 PM UTC 24 |
3420132064 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.2627559627 |
|
|
Oct 03 04:07:53 PM UTC 24 |
Oct 03 08:57:22 PM UTC 24 |
67334541121 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2904294952 |
|
|
Oct 03 08:46:51 PM UTC 24 |
Oct 03 08:57:48 PM UTC 24 |
19059558692 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1393625683 |
|
|
Oct 03 08:44:23 PM UTC 24 |
Oct 03 08:57:50 PM UTC 24 |
5021579492 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3393252216 |
|
|
Oct 03 08:42:46 PM UTC 24 |
Oct 03 08:57:58 PM UTC 24 |
7653790392 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.366925531 |
|
|
Oct 03 08:51:00 PM UTC 24 |
Oct 03 09:00:15 PM UTC 24 |
4482042984 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.4051465991 |
|
|
Oct 03 08:55:11 PM UTC 24 |
Oct 03 09:00:27 PM UTC 24 |
3031604319 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.4207170403 |
|
|
Oct 03 08:55:47 PM UTC 24 |
Oct 03 09:00:27 PM UTC 24 |
2856625306 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.2067350799 |
|
|
Oct 03 08:51:38 PM UTC 24 |
Oct 03 09:00:47 PM UTC 24 |
5060959322 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3153470331 |
|
|
Oct 03 08:53:25 PM UTC 24 |
Oct 03 09:01:17 PM UTC 24 |
3445187892 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2800442926 |
|
|
Oct 03 08:33:53 PM UTC 24 |
Oct 03 09:01:53 PM UTC 24 |
14018535015 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.1542953220 |
|
|
Oct 03 07:52:12 PM UTC 24 |
Oct 03 09:02:03 PM UTC 24 |
14697554417 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.1251687265 |
|
|
Oct 03 08:55:44 PM UTC 24 |
Oct 03 09:02:14 PM UTC 24 |
2744936448 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2665312060 |
|
|
Oct 03 08:48:04 PM UTC 24 |
Oct 03 09:02:47 PM UTC 24 |
4943072392 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.372825770 |
|
|
Oct 03 08:46:51 PM UTC 24 |
Oct 03 09:03:11 PM UTC 24 |
6415198966 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1538913085 |
|
|
Oct 03 07:51:24 PM UTC 24 |
Oct 03 09:03:33 PM UTC 24 |
14326710858 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3528807616 |
|
|
Oct 03 08:58:52 PM UTC 24 |
Oct 03 09:03:50 PM UTC 24 |
2896386680 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.2090328558 |
|
|
Oct 03 08:58:50 PM UTC 24 |
Oct 03 09:04:16 PM UTC 24 |
3435958696 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.207498376 |
|
|
Oct 03 08:33:08 PM UTC 24 |
Oct 03 09:05:21 PM UTC 24 |
10016388582 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.3372963430 |
|
|
Oct 03 08:48:02 PM UTC 24 |
Oct 03 09:05:26 PM UTC 24 |
5472637800 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.909406981 |
|
|
Oct 03 09:01:23 PM UTC 24 |
Oct 03 09:05:30 PM UTC 24 |
3133635076 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1076225861 |
|
|
Oct 03 08:56:14 PM UTC 24 |
Oct 03 09:05:46 PM UTC 24 |
2700337624 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2960728631 |
|
|
Oct 03 08:58:54 PM UTC 24 |
Oct 03 09:06:30 PM UTC 24 |
5385349700 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.1216358488 |
|
|
Oct 03 08:56:32 PM UTC 24 |
Oct 03 09:06:32 PM UTC 24 |
3055389336 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.884577739 |
|
|
Oct 03 09:01:26 PM UTC 24 |
Oct 03 09:06:34 PM UTC 24 |
3373697208 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.3828320073 |
|
|
Oct 03 09:01:29 PM UTC 24 |
Oct 03 09:07:42 PM UTC 24 |
3692119732 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.1506006935 |
|
|
Oct 03 09:01:23 PM UTC 24 |
Oct 03 09:09:14 PM UTC 24 |
3356712700 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1442711499 |
|
|
Oct 03 08:53:29 PM UTC 24 |
Oct 03 09:09:42 PM UTC 24 |
8944444618 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.354693323 |
|
|
Oct 03 08:57:37 PM UTC 24 |
Oct 03 09:09:43 PM UTC 24 |
6404026560 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2227605175 |
|
|
Oct 03 07:52:37 PM UTC 24 |
Oct 03 09:09:48 PM UTC 24 |
15655450877 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.4015007346 |
|
|
Oct 03 09:04:26 PM UTC 24 |
Oct 03 09:10:02 PM UTC 24 |
3455379062 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.1802222010 |
|
|
Oct 03 09:06:32 PM UTC 24 |
Oct 03 09:10:09 PM UTC 24 |
3334025810 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.1108439875 |
|
|
Oct 03 09:06:28 PM UTC 24 |
Oct 03 09:10:36 PM UTC 24 |
2501464000 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.3309835424 |
|
|
Oct 03 09:04:54 PM UTC 24 |
Oct 03 09:10:44 PM UTC 24 |
3305149500 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1956814122 |
|
|
Oct 03 07:53:56 PM UTC 24 |
Oct 03 09:11:55 PM UTC 24 |
15398774056 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2050040442 |
|
|
Oct 03 09:06:27 PM UTC 24 |
Oct 03 09:12:18 PM UTC 24 |
2977706055 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3762154185 |
|
|
Oct 03 08:54:05 PM UTC 24 |
Oct 03 09:12:20 PM UTC 24 |
6175073124 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.1844524034 |
|
|
Oct 03 07:52:58 PM UTC 24 |
Oct 03 09:12:33 PM UTC 24 |
23834937124 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3562810072 |
|
|
Oct 03 08:56:14 PM UTC 24 |
Oct 03 09:12:46 PM UTC 24 |
4206046068 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1962244948 |
|
|
Oct 03 08:29:54 PM UTC 24 |
Oct 03 09:13:20 PM UTC 24 |
30033153856 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.622198022 |
|
|
Oct 03 07:46:52 PM UTC 24 |
Oct 03 09:13:22 PM UTC 24 |
24879837336 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.3581638943 |
|
|
Oct 03 08:58:51 PM UTC 24 |
Oct 03 09:14:13 PM UTC 24 |
6384489912 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.4097343495 |
|
|
Oct 03 07:53:02 PM UTC 24 |
Oct 03 09:14:13 PM UTC 24 |
15106003510 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.1446638703 |
|
|
Oct 03 07:53:06 PM UTC 24 |
Oct 03 09:14:18 PM UTC 24 |
15520144024 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.3750172721 |
|
|
Oct 03 09:11:26 PM UTC 24 |
Oct 03 09:15:04 PM UTC 24 |
2744560902 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.2581857431 |
|
|
Oct 03 07:52:32 PM UTC 24 |
Oct 03 09:15:19 PM UTC 24 |
16092896609 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.3560626245 |
|
|
Oct 03 08:41:23 PM UTC 24 |
Oct 03 09:16:55 PM UTC 24 |
22804172920 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.325583838 |
|
|
Oct 03 09:07:31 PM UTC 24 |
Oct 03 09:17:07 PM UTC 24 |
4761566664 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.140750254 |
|
|
Oct 03 07:53:31 PM UTC 24 |
Oct 03 09:17:19 PM UTC 24 |
15023887540 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.585517412 |
|
|
Oct 03 08:51:39 PM UTC 24 |
Oct 03 09:17:33 PM UTC 24 |
7739788156 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1973467391 |
|
|
Oct 03 09:06:32 PM UTC 24 |
Oct 03 09:17:52 PM UTC 24 |
8342568834 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.2455961313 |
|
|
Oct 03 09:12:31 PM UTC 24 |
Oct 03 09:18:16 PM UTC 24 |
3265898930 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.140066410 |
|
|
Oct 03 07:53:03 PM UTC 24 |
Oct 03 09:18:19 PM UTC 24 |
14919841704 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.4101721001 |
|
|
Oct 03 08:58:57 PM UTC 24 |
Oct 03 09:18:19 PM UTC 24 |
5917585258 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2664213147 |
|
|
Oct 03 09:11:15 PM UTC 24 |
Oct 03 09:18:56 PM UTC 24 |
5747174456 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.328333126 |
|
|
Oct 03 09:08:22 PM UTC 24 |
Oct 03 09:19:00 PM UTC 24 |
7411992326 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.73415855 |
|
|
Oct 03 09:07:30 PM UTC 24 |
Oct 03 09:19:00 PM UTC 24 |
5896466360 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.695828939 |
|
|
Oct 03 09:13:27 PM UTC 24 |
Oct 03 09:19:35 PM UTC 24 |
5210115892 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.801262783 |
|
|
Oct 03 09:13:22 PM UTC 24 |
Oct 03 09:20:40 PM UTC 24 |
4936168864 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2334230061 |
|
|
Oct 03 09:13:27 PM UTC 24 |
Oct 03 09:20:56 PM UTC 24 |
4502642048 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3814731134 |
|
|
Oct 03 08:58:58 PM UTC 24 |
Oct 03 09:21:08 PM UTC 24 |
7486269028 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.538961156 |
|
|
Oct 03 09:14:08 PM UTC 24 |
Oct 03 09:21:12 PM UTC 24 |
4330197092 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.2590429740 |
|
|
Oct 03 07:52:56 PM UTC 24 |
Oct 03 09:21:47 PM UTC 24 |
17058843350 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.3603950230 |
|
|
Oct 03 09:11:27 PM UTC 24 |
Oct 03 09:22:00 PM UTC 24 |
4248184248 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.1705583341 |
|
|
Oct 03 09:18:09 PM UTC 24 |
Oct 03 09:22:09 PM UTC 24 |
3436403358 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1456849946 |
|
|
Oct 03 09:09:54 PM UTC 24 |
Oct 03 09:22:46 PM UTC 24 |
7744730576 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.2105471284 |
|
|
Oct 03 09:07:27 PM UTC 24 |
Oct 03 09:24:24 PM UTC 24 |
7307234754 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2851953086 |
|
|
Oct 03 09:14:08 PM UTC 24 |
Oct 03 09:24:28 PM UTC 24 |
8522633814 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2424064262 |
|
|
Oct 03 09:15:13 PM UTC 24 |
Oct 03 09:24:39 PM UTC 24 |
3866714952 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3644680216 |
|
|
Oct 03 08:54:05 PM UTC 24 |
Oct 03 09:24:43 PM UTC 24 |
9104098568 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.2141152835 |
|
|
Oct 03 09:11:30 PM UTC 24 |
Oct 03 09:24:58 PM UTC 24 |
4555816466 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2071477058 |
|
|
Oct 03 09:18:06 PM UTC 24 |
Oct 03 09:24:58 PM UTC 24 |
3510849932 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.3496253080 |
|
|
Oct 03 09:17:53 PM UTC 24 |
Oct 03 09:25:16 PM UTC 24 |
3483462240 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1952882164 |
|
|
Oct 03 09:15:39 PM UTC 24 |
Oct 03 09:26:05 PM UTC 24 |
4891087560 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2611238120 |
|
|
Oct 03 09:15:10 PM UTC 24 |
Oct 03 09:26:12 PM UTC 24 |
4244428600 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.701358981 |
|
|
Oct 03 09:01:53 PM UTC 24 |
Oct 03 09:26:19 PM UTC 24 |
7212446000 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.1658427804 |
|
|
Oct 03 09:22:00 PM UTC 24 |
Oct 03 09:26:49 PM UTC 24 |
3833015640 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1125973302 |
|
|
Oct 03 09:15:56 PM UTC 24 |
Oct 03 09:27:22 PM UTC 24 |
4475021528 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.1854846119 |
|
|
Oct 03 09:19:55 PM UTC 24 |
Oct 03 09:27:25 PM UTC 24 |
4042919986 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2334132461 |
|
|
Oct 03 09:19:57 PM UTC 24 |
Oct 03 09:27:40 PM UTC 24 |
3921602356 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.58870158 |
|
|
Oct 03 09:18:30 PM UTC 24 |
Oct 03 09:27:44 PM UTC 24 |
4602654856 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2533967487 |
|
|
Oct 03 09:17:53 PM UTC 24 |
Oct 03 09:28:09 PM UTC 24 |
4065726868 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.1164654144 |
|
|
Oct 03 09:11:01 PM UTC 24 |
Oct 03 09:28:13 PM UTC 24 |
6659498996 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1115251626 |
|
|
Oct 03 09:22:21 PM UTC 24 |
Oct 03 09:28:48 PM UTC 24 |
4313806168 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.307267586 |
|
|
Oct 03 09:24:59 PM UTC 24 |
Oct 03 09:28:50 PM UTC 24 |
3669874254 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3380271096 |
|
|
Oct 03 09:15:14 PM UTC 24 |
Oct 03 09:28:50 PM UTC 24 |
4191240264 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1429752413 |
|
|
Oct 03 09:19:56 PM UTC 24 |
Oct 03 09:28:53 PM UTC 24 |
6984046628 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.511577257 |
|
|
Oct 03 09:25:58 PM UTC 24 |
Oct 03 09:29:03 PM UTC 24 |
1857750692 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2526177997 |
|
|
Oct 03 09:21:58 PM UTC 24 |
Oct 03 09:29:03 PM UTC 24 |
5581342824 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3455325888 |
|
|
Oct 03 08:33:12 PM UTC 24 |
Oct 03 09:29:04 PM UTC 24 |
27320819283 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.293087696 |
|
|
Oct 03 09:25:55 PM UTC 24 |
Oct 03 09:29:09 PM UTC 24 |
2894092424 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.285403555 |
|
|
Oct 03 09:23:16 PM UTC 24 |
Oct 03 09:29:28 PM UTC 24 |
3695775656 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.151406432 |
|
|
Oct 03 07:14:16 PM UTC 24 |
Oct 03 09:29:29 PM UTC 24 |
27258224774 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.297987567 |
|
|
Oct 03 09:25:00 PM UTC 24 |
Oct 03 09:30:23 PM UTC 24 |
3309440342 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2654772270 |
|
|
Oct 03 09:22:49 PM UTC 24 |
Oct 03 09:30:24 PM UTC 24 |
6219036858 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.1560226375 |
|
|
Oct 03 08:57:02 PM UTC 24 |
Oct 03 09:30:28 PM UTC 24 |
9110634836 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.999674330 |
|
|
Oct 03 09:21:59 PM UTC 24 |
Oct 03 09:30:39 PM UTC 24 |
5301925306 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2134329500 |
|
|
Oct 03 09:27:08 PM UTC 24 |
Oct 03 09:31:02 PM UTC 24 |
2845821695 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.709971917 |
|
|
Oct 03 09:22:46 PM UTC 24 |
Oct 03 09:31:03 PM UTC 24 |
5869930751 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.487584254 |
|
|
Oct 03 09:11:00 PM UTC 24 |
Oct 03 09:31:15 PM UTC 24 |
6075533208 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3603952527 |
|
|
Oct 03 09:25:38 PM UTC 24 |
Oct 03 09:31:37 PM UTC 24 |
3196057500 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.600152696 |
|
|
Oct 03 09:27:07 PM UTC 24 |
Oct 03 09:32:25 PM UTC 24 |
2586133660 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3113053035 |
|
|
Oct 03 09:02:56 PM UTC 24 |
Oct 03 09:32:28 PM UTC 24 |
9845596824 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2249246663 |
|
|
Oct 03 09:28:33 PM UTC 24 |
Oct 03 09:32:40 PM UTC 24 |
3413359069 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3627166163 |
|
|
Oct 03 09:28:46 PM UTC 24 |
Oct 03 09:32:47 PM UTC 24 |
3134417478 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2423246387 |
|
|
Oct 03 09:28:59 PM UTC 24 |
Oct 03 09:33:15 PM UTC 24 |
3146004110 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.2779743125 |
|
|
Oct 03 09:13:22 PM UTC 24 |
Oct 03 09:33:34 PM UTC 24 |
9032056226 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.2243362898 |
|
|
Oct 03 09:18:58 PM UTC 24 |
Oct 03 09:34:29 PM UTC 24 |
8480576640 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.1077135303 |
|
|
Oct 03 09:25:59 PM UTC 24 |
Oct 03 09:35:24 PM UTC 24 |
4706994450 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.3950053788 |
|
|
Oct 03 09:32:56 PM UTC 24 |
Oct 03 09:35:55 PM UTC 24 |
2406821668 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4254232017 |
|
|
Oct 03 09:02:57 PM UTC 24 |
Oct 03 09:37:23 PM UTC 24 |
10541388273 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.134362157 |
|
|
Oct 03 09:03:26 PM UTC 24 |
Oct 03 09:37:37 PM UTC 24 |
9669878600 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.974154572 |
|
|
Oct 03 09:27:08 PM UTC 24 |
Oct 03 09:37:44 PM UTC 24 |
4967737463 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4091014705 |
|
|
Oct 03 09:29:01 PM UTC 24 |
Oct 03 09:37:54 PM UTC 24 |
4508683170 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.743911668 |
|
|
Oct 03 09:35:30 PM UTC 24 |
Oct 03 09:38:17 PM UTC 24 |
2695314974 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.518059838 |
|
|
Oct 03 09:02:54 PM UTC 24 |
Oct 03 09:38:55 PM UTC 24 |
10231875448 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2870910643 |
|
|
Oct 03 09:36:33 PM UTC 24 |
Oct 03 09:39:49 PM UTC 24 |
2209940618 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.3903159617 |
|
|
Oct 03 09:36:01 PM UTC 24 |
Oct 03 09:40:21 PM UTC 24 |
2659582034 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.4141237839 |
|
|
Oct 03 09:35:28 PM UTC 24 |
Oct 03 09:40:28 PM UTC 24 |
3154980416 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2839430447 |
|
|
Oct 03 09:20:14 PM UTC 24 |
Oct 03 09:41:12 PM UTC 24 |
20414230316 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.909880781 |
|
|
Oct 03 09:35:26 PM UTC 24 |
Oct 03 09:41:16 PM UTC 24 |
6057513759 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.1376619849 |
|
|
Oct 03 09:31:46 PM UTC 24 |
Oct 03 09:41:22 PM UTC 24 |
3670369500 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3753943146 |
|
|
Oct 03 09:35:30 PM UTC 24 |
Oct 03 09:41:35 PM UTC 24 |
3212149400 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.72041740 |
|
|
Oct 03 09:33:15 PM UTC 24 |
Oct 03 09:42:08 PM UTC 24 |
10700758536 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1796950062 |
|
|
Oct 03 09:03:49 PM UTC 24 |
Oct 03 09:42:59 PM UTC 24 |
10175565556 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.3029889896 |
|
|
Oct 03 09:38:38 PM UTC 24 |
Oct 03 09:43:47 PM UTC 24 |
2393563576 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.2819968506 |
|
|
Oct 03 09:38:39 PM UTC 24 |
Oct 03 09:44:39 PM UTC 24 |
3276494973 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.1208703354 |
|
|
Oct 03 09:38:38 PM UTC 24 |
Oct 03 09:45:02 PM UTC 24 |
3424203398 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.360727444 |
|
|
Oct 03 09:41:09 PM UTC 24 |
Oct 03 09:45:02 PM UTC 24 |
2690768346 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.594709672 |
|
|
Oct 03 09:39:33 PM UTC 24 |
Oct 03 09:45:44 PM UTC 24 |
3402084602 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.1045652318 |
|
|
Oct 03 09:42:19 PM UTC 24 |
Oct 03 09:45:49 PM UTC 24 |
2320144792 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.1078253592 |
|
|
Oct 03 09:42:44 PM UTC 24 |
Oct 03 09:46:06 PM UTC 24 |
2970170280 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3560848790 |
|
|
Oct 03 09:27:27 PM UTC 24 |
Oct 03 09:46:12 PM UTC 24 |
7340071118 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.1425519906 |
|
|
Oct 03 09:35:29 PM UTC 24 |
Oct 03 09:47:27 PM UTC 24 |
5308054212 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.2085509231 |
|
|
Oct 03 09:38:01 PM UTC 24 |
Oct 03 09:47:35 PM UTC 24 |
3582516088 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.2096550535 |
|
|
Oct 03 09:42:33 PM UTC 24 |
Oct 03 09:47:48 PM UTC 24 |
3673348784 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2532488436 |
|
|
Oct 03 09:41:09 PM UTC 24 |
Oct 03 09:47:50 PM UTC 24 |
6132163612 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.1128226620 |
|
|
Oct 03 09:42:21 PM UTC 24 |
Oct 03 09:47:59 PM UTC 24 |
3118468082 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.599115617 |
|
|
Oct 03 09:40:29 PM UTC 24 |
Oct 03 09:48:20 PM UTC 24 |
5942545160 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1781598179 |
|
|
Oct 03 09:11:13 PM UTC 24 |
Oct 03 09:48:23 PM UTC 24 |
29938277932 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3319184882 |
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Oct 03 08:42:26 PM UTC 24 |
Oct 03 09:48:35 PM UTC 24 |
21027633382 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1211283570 |
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|
Oct 03 09:31:49 PM UTC 24 |
Oct 03 09:50:34 PM UTC 24 |
5655080040 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.3365633516 |
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Oct 03 09:18:44 PM UTC 24 |
Oct 03 09:52:47 PM UTC 24 |
22923649335 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1398330853 |
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Oct 03 09:21:19 PM UTC 24 |
Oct 03 09:53:44 PM UTC 24 |
24135088100 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3430857893 |
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Oct 03 09:43:39 PM UTC 24 |
Oct 03 09:53:47 PM UTC 24 |
4011919438 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.732524275 |
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|
Oct 03 09:44:27 PM UTC 24 |
Oct 03 09:53:48 PM UTC 24 |
3761351840 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.2081565571 |
|
|
Oct 03 09:18:37 PM UTC 24 |
Oct 03 09:53:53 PM UTC 24 |
16685850474 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1715235538 |
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|
Oct 03 09:45:53 PM UTC 24 |
Oct 03 09:54:22 PM UTC 24 |
4405847032 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3634037243 |
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|
Oct 03 09:47:00 PM UTC 24 |
Oct 03 09:54:33 PM UTC 24 |
6336937400 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.402170664 |
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|
Oct 03 09:48:40 PM UTC 24 |
Oct 03 09:55:33 PM UTC 24 |
4617500267 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.1426454399 |
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|
Oct 03 09:45:18 PM UTC 24 |
Oct 03 09:55:55 PM UTC 24 |
4148192048 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.162919031 |
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|
Oct 03 09:48:30 PM UTC 24 |
Oct 03 09:56:11 PM UTC 24 |
3466279038 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2432531997 |
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|
Oct 03 09:45:53 PM UTC 24 |
Oct 03 09:56:17 PM UTC 24 |
3937244668 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.928050851 |
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|
Oct 03 09:42:49 PM UTC 24 |
Oct 03 09:56:32 PM UTC 24 |
6264834840 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.2058439695 |
|
|
Oct 03 09:48:54 PM UTC 24 |
Oct 03 09:56:43 PM UTC 24 |
5831148500 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.40074914 |
|
|
Oct 03 09:42:49 PM UTC 24 |
Oct 03 09:57:39 PM UTC 24 |
5243691710 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.3611065899 |
|
|
Oct 03 09:48:39 PM UTC 24 |
Oct 03 09:58:32 PM UTC 24 |
7707334275 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.2210697643 |
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|
Oct 03 09:34:04 PM UTC 24 |
Oct 03 09:58:52 PM UTC 24 |
5354394776 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.674419852 |
|
|
Oct 03 09:49:14 PM UTC 24 |
Oct 03 10:00:45 PM UTC 24 |
5731801124 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.583497264 |
|
|
Oct 03 08:21:44 PM UTC 24 |
Oct 03 10:02:12 PM UTC 24 |
42870620780 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1737787737 |
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|
Oct 03 08:47:33 PM UTC 24 |
Oct 03 10:03:18 PM UTC 24 |
18631731905 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2501984730 |
|
|
Oct 03 09:53:27 PM UTC 24 |
Oct 03 10:03:23 PM UTC 24 |
4270014164 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.3115197161 |
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|
Oct 03 09:46:54 PM UTC 24 |
Oct 03 10:03:29 PM UTC 24 |
8551937784 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2011885586 |
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|
Oct 03 09:56:32 PM UTC 24 |
Oct 03 10:04:16 PM UTC 24 |
6764847148 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.1756071051 |
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|
Oct 03 07:55:23 PM UTC 24 |
Oct 03 10:05:02 PM UTC 24 |
26121289396 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1740198452 |
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|
Oct 03 09:28:33 PM UTC 24 |
Oct 03 10:05:03 PM UTC 24 |
13399589814 ps |