| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2874626396 |
|
|
Oct 10 02:48:35 AM UTC 24 |
Oct 10 03:58:50 AM UTC 24 |
14312625238 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3235376233 |
|
|
Oct 10 02:50:16 AM UTC 24 |
Oct 10 03:58:58 AM UTC 24 |
15167893036 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.2840814907 |
|
|
Oct 10 03:52:49 AM UTC 24 |
Oct 10 03:59:02 AM UTC 24 |
3358608340 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2594981077 |
|
|
Oct 10 02:48:51 AM UTC 24 |
Oct 10 03:59:10 AM UTC 24 |
14469495720 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2594636295 |
|
|
Oct 10 02:48:29 AM UTC 24 |
Oct 10 04:00:03 AM UTC 24 |
14619721905 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.739942384 |
|
|
Oct 10 01:57:18 AM UTC 24 |
Oct 10 04:01:03 AM UTC 24 |
46847952523 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1593158529 |
|
|
Oct 10 02:50:05 AM UTC 24 |
Oct 10 04:01:17 AM UTC 24 |
14414809464 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.376439047 |
|
|
Oct 10 03:55:10 AM UTC 24 |
Oct 10 04:01:20 AM UTC 24 |
4431676752 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.3230348161 |
|
|
Oct 10 03:56:09 AM UTC 24 |
Oct 10 04:01:23 AM UTC 24 |
2847433184 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2853799399 |
|
|
Oct 10 02:45:55 AM UTC 24 |
Oct 10 04:01:42 AM UTC 24 |
15081991474 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1527974808 |
|
|
Oct 10 03:55:09 AM UTC 24 |
Oct 10 04:01:46 AM UTC 24 |
2802383118 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2650279698 |
|
|
Oct 10 02:45:26 AM UTC 24 |
Oct 10 04:01:51 AM UTC 24 |
15394273784 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.452018037 |
|
|
Oct 10 03:55:11 AM UTC 24 |
Oct 10 04:02:01 AM UTC 24 |
6025377050 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.2850809453 |
|
|
Oct 10 01:54:50 AM UTC 24 |
Oct 10 04:02:34 AM UTC 24 |
50194421470 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3584876586 |
|
|
Oct 10 02:44:25 AM UTC 24 |
Oct 10 04:02:43 AM UTC 24 |
15260650880 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2659622108 |
|
|
Oct 10 02:43:19 AM UTC 24 |
Oct 10 04:03:26 AM UTC 24 |
15494175038 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.3147145862 |
|
|
Oct 10 03:53:55 AM UTC 24 |
Oct 10 04:04:01 AM UTC 24 |
4933616504 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4237599332 |
|
|
Oct 10 02:44:16 AM UTC 24 |
Oct 10 04:04:09 AM UTC 24 |
15748622920 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1662309646 |
|
|
Oct 10 02:46:41 AM UTC 24 |
Oct 10 04:05:21 AM UTC 24 |
14225238850 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.2308841916 |
|
|
Oct 10 03:54:31 AM UTC 24 |
Oct 10 04:06:37 AM UTC 24 |
5162621880 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.3143998320 |
|
|
Oct 10 01:46:04 AM UTC 24 |
Oct 10 04:06:55 AM UTC 24 |
31921280824 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3671775328 |
|
|
Oct 10 02:44:50 AM UTC 24 |
Oct 10 04:06:59 AM UTC 24 |
15279461320 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3598834428 |
|
|
Oct 10 03:54:31 AM UTC 24 |
Oct 10 04:07:17 AM UTC 24 |
5378289200 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1390074360 |
|
|
Oct 10 04:00:14 AM UTC 24 |
Oct 10 04:07:20 AM UTC 24 |
4229935748 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.3450550401 |
|
|
Oct 10 03:56:24 AM UTC 24 |
Oct 10 04:07:44 AM UTC 24 |
4348254800 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.3615488317 |
|
|
Oct 10 03:56:58 AM UTC 24 |
Oct 10 04:07:47 AM UTC 24 |
4466578520 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.2613277787 |
|
|
Oct 10 03:57:40 AM UTC 24 |
Oct 10 04:07:51 AM UTC 24 |
4561865244 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.710556674 |
|
|
Oct 10 04:02:47 AM UTC 24 |
Oct 10 04:08:18 AM UTC 24 |
3018454129 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2801529109 |
|
|
Oct 10 04:02:41 AM UTC 24 |
Oct 10 04:08:37 AM UTC 24 |
4094769705 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1066755868 |
|
|
Oct 10 03:58:07 AM UTC 24 |
Oct 10 04:08:50 AM UTC 24 |
4466385320 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.2240418687 |
|
|
Oct 10 04:02:48 AM UTC 24 |
Oct 10 04:08:57 AM UTC 24 |
2480938480 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2011831027 |
|
|
Oct 10 04:01:39 AM UTC 24 |
Oct 10 04:09:19 AM UTC 24 |
3235761000 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2207145661 |
|
|
Oct 10 02:47:15 AM UTC 24 |
Oct 10 04:09:29 AM UTC 24 |
15684337024 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1509337082 |
|
|
Oct 10 04:00:04 AM UTC 24 |
Oct 10 04:10:07 AM UTC 24 |
5075788899 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2845407653 |
|
|
Oct 10 04:04:50 AM UTC 24 |
Oct 10 04:10:39 AM UTC 24 |
3118113824 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4126807577 |
|
|
Oct 10 04:00:15 AM UTC 24 |
Oct 10 04:10:51 AM UTC 24 |
4657841150 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.2668685436 |
|
|
Oct 10 04:03:00 AM UTC 24 |
Oct 10 04:11:05 AM UTC 24 |
4742596905 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.706139148 |
|
|
Oct 10 03:13:46 AM UTC 24 |
Oct 10 04:11:26 AM UTC 24 |
31316094628 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3326931115 |
|
|
Oct 10 04:03:25 AM UTC 24 |
Oct 10 04:11:29 AM UTC 24 |
5103838904 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3769338935 |
|
|
Oct 10 02:46:16 AM UTC 24 |
Oct 10 04:11:42 AM UTC 24 |
16228996520 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.2693515337 |
|
|
Oct 10 04:08:09 AM UTC 24 |
Oct 10 04:12:09 AM UTC 24 |
2826144606 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.631480574 |
|
|
Oct 10 02:44:59 AM UTC 24 |
Oct 10 04:12:23 AM UTC 24 |
16127369744 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4076028230 |
|
|
Oct 10 04:09:36 AM UTC 24 |
Oct 10 04:12:40 AM UTC 24 |
2645837226 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.667590539 |
|
|
Oct 10 04:09:07 AM UTC 24 |
Oct 10 04:13:06 AM UTC 24 |
2678497604 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1316736655 |
|
|
Oct 10 04:11:24 AM UTC 24 |
Oct 10 04:13:35 AM UTC 24 |
2239731814 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.233518551 |
|
|
Oct 10 04:11:27 AM UTC 24 |
Oct 10 04:13:41 AM UTC 24 |
2591225007 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.758068997 |
|
|
Oct 10 04:08:55 AM UTC 24 |
Oct 10 04:13:44 AM UTC 24 |
2688748043 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.523364753 |
|
|
Oct 10 04:08:46 AM UTC 24 |
Oct 10 04:13:58 AM UTC 24 |
2752432688 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.4206260499 |
|
|
Oct 10 04:03:08 AM UTC 24 |
Oct 10 04:13:59 AM UTC 24 |
4644495495 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.1627967858 |
|
|
Oct 10 04:02:45 AM UTC 24 |
Oct 10 04:14:01 AM UTC 24 |
6257058310 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2515149356 |
|
|
Oct 10 04:03:25 AM UTC 24 |
Oct 10 04:14:29 AM UTC 24 |
4313692562 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.1374941739 |
|
|
Oct 10 03:44:37 AM UTC 24 |
Oct 10 04:15:45 AM UTC 24 |
8243746408 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.2215412202 |
|
|
Oct 10 04:03:24 AM UTC 24 |
Oct 10 04:15:48 AM UTC 24 |
4615056680 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3037102081 |
|
|
Oct 10 02:58:37 AM UTC 24 |
Oct 10 04:15:54 AM UTC 24 |
15700648830 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.423454292 |
|
|
Oct 10 04:00:15 AM UTC 24 |
Oct 10 04:16:06 AM UTC 24 |
5456364360 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.774632069 |
|
|
Oct 10 04:00:44 AM UTC 24 |
Oct 10 04:16:29 AM UTC 24 |
5442263044 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.911901617 |
|
|
Oct 10 04:12:21 AM UTC 24 |
Oct 10 04:16:31 AM UTC 24 |
2364723906 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3901001387 |
|
|
Oct 10 03:00:53 AM UTC 24 |
Oct 10 04:17:13 AM UTC 24 |
14994831957 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.725325138 |
|
|
Oct 10 04:12:16 AM UTC 24 |
Oct 10 04:18:48 AM UTC 24 |
3696650232 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3952939272 |
|
|
Oct 10 03:56:08 AM UTC 24 |
Oct 10 04:19:25 AM UTC 24 |
9992143962 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.836599044 |
|
|
Oct 10 04:09:37 AM UTC 24 |
Oct 10 04:19:26 AM UTC 24 |
3371762734 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1509928617 |
|
|
Oct 10 04:08:45 AM UTC 24 |
Oct 10 04:19:39 AM UTC 24 |
4013695352 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1235749106 |
|
|
Oct 10 04:17:16 AM UTC 24 |
Oct 10 04:20:43 AM UTC 24 |
2853893026 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1437224194 |
|
|
Oct 10 04:04:50 AM UTC 24 |
Oct 10 04:20:52 AM UTC 24 |
6542360129 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.3317909017 |
|
|
Oct 10 02:59:48 AM UTC 24 |
Oct 10 04:20:56 AM UTC 24 |
16048518840 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1043811626 |
|
|
Oct 10 04:13:16 AM UTC 24 |
Oct 10 04:20:57 AM UTC 24 |
7857732750 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2652885905 |
|
|
Oct 10 04:04:01 AM UTC 24 |
Oct 10 04:22:01 AM UTC 24 |
6356324108 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2417198865 |
|
|
Oct 10 04:13:43 AM UTC 24 |
Oct 10 04:22:06 AM UTC 24 |
4984863900 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2974119111 |
|
|
Oct 10 04:17:11 AM UTC 24 |
Oct 10 04:22:47 AM UTC 24 |
2952872334 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1243416166 |
|
|
Oct 10 04:16:52 AM UTC 24 |
Oct 10 04:23:58 AM UTC 24 |
7506238372 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1341685611 |
|
|
Oct 10 02:46:41 AM UTC 24 |
Oct 10 04:24:23 AM UTC 24 |
17899106470 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.3483163604 |
|
|
Oct 10 02:59:48 AM UTC 24 |
Oct 10 04:24:32 AM UTC 24 |
15757272600 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3512582692 |
|
|
Oct 10 02:46:23 AM UTC 24 |
Oct 10 04:25:15 AM UTC 24 |
18006409032 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3302491985 |
|
|
Oct 10 04:17:17 AM UTC 24 |
Oct 10 04:25:33 AM UTC 24 |
4071587192 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2355887638 |
|
|
Oct 10 04:15:18 AM UTC 24 |
Oct 10 04:25:51 AM UTC 24 |
9850361060 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2902479024 |
|
|
Oct 10 04:19:26 AM UTC 24 |
Oct 10 04:26:11 AM UTC 24 |
3075316844 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.1888609274 |
|
|
Oct 10 04:13:00 AM UTC 24 |
Oct 10 04:26:15 AM UTC 24 |
6594201504 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2622984279 |
|
|
Oct 10 04:09:38 AM UTC 24 |
Oct 10 04:26:20 AM UTC 24 |
13257126265 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1226680381 |
|
|
Oct 10 04:07:57 AM UTC 24 |
Oct 10 04:26:32 AM UTC 24 |
5633683440 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1191622087 |
|
|
Oct 10 04:10:42 AM UTC 24 |
Oct 10 04:26:52 AM UTC 24 |
11744157264 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4155757173 |
|
|
Oct 10 04:08:36 AM UTC 24 |
Oct 10 04:27:40 AM UTC 24 |
6405341576 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.703566333 |
|
|
Oct 10 04:20:23 AM UTC 24 |
Oct 10 04:27:43 AM UTC 24 |
6073768730 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2866385606 |
|
|
Oct 10 04:21:53 AM UTC 24 |
Oct 10 04:27:48 AM UTC 24 |
6308277340 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1902790474 |
|
|
Oct 10 04:00:11 AM UTC 24 |
Oct 10 04:28:07 AM UTC 24 |
7398070612 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3450783074 |
|
|
Oct 10 04:15:20 AM UTC 24 |
Oct 10 04:28:21 AM UTC 24 |
7624179575 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3731954310 |
|
|
Oct 10 04:21:51 AM UTC 24 |
Oct 10 04:29:09 AM UTC 24 |
3364528798 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1106518685 |
|
|
Oct 10 04:21:53 AM UTC 24 |
Oct 10 04:29:27 AM UTC 24 |
3700220758 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3239811604 |
|
|
Oct 10 04:23:23 AM UTC 24 |
Oct 10 04:30:47 AM UTC 24 |
18635992700 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.1376003888 |
|
|
Oct 10 04:27:17 AM UTC 24 |
Oct 10 04:31:12 AM UTC 24 |
2436470087 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.3513167167 |
|
|
Oct 10 04:27:28 AM UTC 24 |
Oct 10 04:31:13 AM UTC 24 |
2025317048 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1849447576 |
|
|
Oct 10 04:08:47 AM UTC 24 |
Oct 10 04:31:16 AM UTC 24 |
9300144736 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1240510800 |
|
|
Oct 10 04:20:25 AM UTC 24 |
Oct 10 04:31:51 AM UTC 24 |
5098640921 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3522588047 |
|
|
Oct 10 04:08:56 AM UTC 24 |
Oct 10 04:32:10 AM UTC 24 |
8333837806 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.507445286 |
|
|
Oct 10 04:22:59 AM UTC 24 |
Oct 10 04:33:10 AM UTC 24 |
3934197960 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.3095134206 |
|
|
Oct 10 04:27:29 AM UTC 24 |
Oct 10 04:33:21 AM UTC 24 |
3107690766 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.2659548201 |
|
|
Oct 10 04:27:11 AM UTC 24 |
Oct 10 04:33:34 AM UTC 24 |
3493094050 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1062980064 |
|
|
Oct 10 04:27:32 AM UTC 24 |
Oct 10 04:34:18 AM UTC 24 |
3155629714 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1757392071 |
|
|
Oct 10 04:22:56 AM UTC 24 |
Oct 10 04:34:36 AM UTC 24 |
5646956360 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1626828027 |
|
|
Oct 10 04:15:10 AM UTC 24 |
Oct 10 04:35:38 AM UTC 24 |
7875463322 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.3451061532 |
|
|
Oct 10 04:32:06 AM UTC 24 |
Oct 10 04:35:44 AM UTC 24 |
2317507540 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3415076815 |
|
|
Oct 10 04:22:55 AM UTC 24 |
Oct 10 04:35:52 AM UTC 24 |
9518875440 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.1859739355 |
|
|
Oct 10 04:25:51 AM UTC 24 |
Oct 10 04:36:12 AM UTC 24 |
3687655982 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1169362989 |
|
|
Oct 10 04:32:06 AM UTC 24 |
Oct 10 04:36:23 AM UTC 24 |
2968740760 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2453457734 |
|
|
Oct 10 04:29:06 AM UTC 24 |
Oct 10 04:36:29 AM UTC 24 |
3454088800 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.1507752604 |
|
|
Oct 10 04:29:00 AM UTC 24 |
Oct 10 04:37:08 AM UTC 24 |
3670996506 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.1326746444 |
|
|
Oct 10 04:05:50 AM UTC 24 |
Oct 10 04:37:43 AM UTC 24 |
19341554366 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.62189504 |
|
|
Oct 10 04:29:03 AM UTC 24 |
Oct 10 04:38:44 AM UTC 24 |
5206386428 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.2326916036 |
|
|
Oct 10 04:32:09 AM UTC 24 |
Oct 10 04:38:58 AM UTC 24 |
3531133155 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1266312426 |
|
|
Oct 10 04:12:46 AM UTC 24 |
Oct 10 04:39:16 AM UTC 24 |
13566942584 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.3003226673 |
|
|
Oct 10 04:24:34 AM UTC 24 |
Oct 10 04:39:48 AM UTC 24 |
5242564680 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.2078856970 |
|
|
Oct 10 04:35:13 AM UTC 24 |
Oct 10 04:40:19 AM UTC 24 |
3001452624 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2340382352 |
|
|
Oct 10 03:09:40 AM UTC 24 |
Oct 10 04:40:20 AM UTC 24 |
30955470790 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3238904887 |
|
|
Oct 10 04:26:28 AM UTC 24 |
Oct 10 04:40:32 AM UTC 24 |
4742749922 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.471816591 |
|
|
Oct 10 04:15:13 AM UTC 24 |
Oct 10 04:41:07 AM UTC 24 |
13829504302 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1399297278 |
|
|
Oct 10 04:36:44 AM UTC 24 |
Oct 10 04:41:11 AM UTC 24 |
2919044888 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.363603357 |
|
|
Oct 10 03:21:24 AM UTC 24 |
Oct 10 04:41:21 AM UTC 24 |
15077064896 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.457412182 |
|
|
Oct 10 04:32:46 AM UTC 24 |
Oct 10 04:41:53 AM UTC 24 |
2484682968 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.1284093249 |
|
|
Oct 10 04:37:13 AM UTC 24 |
Oct 10 04:41:57 AM UTC 24 |
2869274024 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.552497311 |
|
|
Oct 10 04:37:45 AM UTC 24 |
Oct 10 04:42:06 AM UTC 24 |
2593857289 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4288931511 |
|
|
Oct 10 03:24:15 AM UTC 24 |
Oct 10 04:42:23 AM UTC 24 |
15052461608 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.410445422 |
|
|
Oct 10 03:15:42 AM UTC 24 |
Oct 10 04:42:49 AM UTC 24 |
17430703476 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.2710701783 |
|
|
Oct 10 04:26:09 AM UTC 24 |
Oct 10 04:42:52 AM UTC 24 |
5115491390 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3171880918 |
|
|
Oct 10 02:40:44 AM UTC 24 |
Oct 10 04:43:43 AM UTC 24 |
35036312484 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4249518671 |
|
|
Oct 10 04:15:17 AM UTC 24 |
Oct 10 04:44:05 AM UTC 24 |
10210288372 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.1905346968 |
|
|
Oct 10 04:33:57 AM UTC 24 |
Oct 10 04:44:33 AM UTC 24 |
3176725128 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.1831358090 |
|
|
Oct 10 04:38:19 AM UTC 24 |
Oct 10 04:44:40 AM UTC 24 |
3280474188 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1879410511 |
|
|
Oct 10 04:15:11 AM UTC 24 |
Oct 10 04:45:57 AM UTC 24 |
12553841131 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.703192273 |
|
|
Oct 10 04:34:12 AM UTC 24 |
Oct 10 04:45:58 AM UTC 24 |
5665874476 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.797994232 |
|
|
Oct 10 04:42:04 AM UTC 24 |
Oct 10 04:46:06 AM UTC 24 |
2907171448 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.833627263 |
|
|
Oct 10 03:24:19 AM UTC 24 |
Oct 10 04:46:20 AM UTC 24 |
15099215648 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.1606460536 |
|
|
Oct 10 04:39:20 AM UTC 24 |
Oct 10 04:46:35 AM UTC 24 |
3689228454 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.2570686404 |
|
|
Oct 10 04:42:56 AM UTC 24 |
Oct 10 04:47:02 AM UTC 24 |
2425659208 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.525004020 |
|
|
Oct 10 04:20:25 AM UTC 24 |
Oct 10 04:47:07 AM UTC 24 |
23947617144 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4033276582 |
|
|
Oct 10 04:36:32 AM UTC 24 |
Oct 10 04:47:12 AM UTC 24 |
3883899618 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1538845262 |
|
|
Oct 10 04:42:57 AM UTC 24 |
Oct 10 04:48:27 AM UTC 24 |
3099343155 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3939183556 |
|
|
Oct 10 04:42:58 AM UTC 24 |
Oct 10 04:48:29 AM UTC 24 |
3121804234 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.3230891723 |
|
|
Oct 10 04:42:03 AM UTC 24 |
Oct 10 04:48:30 AM UTC 24 |
3144013688 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2333737608 |
|
|
Oct 10 02:46:05 AM UTC 24 |
Oct 10 04:48:31 AM UTC 24 |
25284214784 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2620130668 |
|
|
Oct 10 02:48:41 AM UTC 24 |
Oct 10 04:48:31 AM UTC 24 |
23329144704 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3270207206 |
|
|
Oct 10 04:29:47 AM UTC 24 |
Oct 10 04:50:07 AM UTC 24 |
11264186056 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4080265180 |
|
|
Oct 10 04:43:01 AM UTC 24 |
Oct 10 04:51:50 AM UTC 24 |
8783586078 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.2978168890 |
|
|
Oct 10 04:47:09 AM UTC 24 |
Oct 10 04:52:32 AM UTC 24 |
3058906342 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.2941800548 |
|
|
Oct 10 04:48:01 AM UTC 24 |
Oct 10 04:53:09 AM UTC 24 |
3117887880 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1067666881 |
|
|
Oct 10 04:43:36 AM UTC 24 |
Oct 10 04:54:04 AM UTC 24 |
5311016520 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1801599763 |
|
|
Oct 10 04:47:14 AM UTC 24 |
Oct 10 04:55:15 AM UTC 24 |
5475578288 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2135192742 |
|
|
Oct 10 04:31:24 AM UTC 24 |
Oct 10 04:55:21 AM UTC 24 |
5785911512 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.4184172038 |
|
|
Oct 10 04:43:37 AM UTC 24 |
Oct 10 04:55:27 AM UTC 24 |
5156018899 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2998029614 |
|
|
Oct 10 04:12:21 AM UTC 24 |
Oct 10 04:55:27 AM UTC 24 |
22886569193 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3995844702 |
|
|
Oct 10 04:28:59 AM UTC 24 |
Oct 10 04:55:38 AM UTC 24 |
7841151774 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.127857045 |
|
|
Oct 10 04:15:21 AM UTC 24 |
Oct 10 04:55:50 AM UTC 24 |
23770315152 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2879554937 |
|
|
Oct 10 04:49:46 AM UTC 24 |
Oct 10 04:56:02 AM UTC 24 |
4200395100 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2705958202 |
|
|
Oct 10 04:41:18 AM UTC 24 |
Oct 10 04:56:08 AM UTC 24 |
6065288254 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.4281304040 |
|
|
Oct 10 04:37:08 AM UTC 24 |
Oct 10 04:56:29 AM UTC 24 |
6074966818 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.213023218 |
|
|
Oct 10 04:49:43 AM UTC 24 |
Oct 10 04:57:00 AM UTC 24 |
3799488936 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1457526317 |
|
|
Oct 10 04:47:20 AM UTC 24 |
Oct 10 04:57:12 AM UTC 24 |
3610189344 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.115138342 |
|
|
Oct 10 04:49:45 AM UTC 24 |
Oct 10 04:57:25 AM UTC 24 |
4711289812 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2835044699 |
|
|
Oct 10 04:44:40 AM UTC 24 |
Oct 10 04:57:36 AM UTC 24 |
6828588568 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.23061023 |
|
|
Oct 10 04:45:20 AM UTC 24 |
Oct 10 04:58:28 AM UTC 24 |
7428265000 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.897620314 |
|
|
Oct 10 04:30:04 AM UTC 24 |
Oct 10 04:58:54 AM UTC 24 |
7242665768 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.1252208870 |
|
|
Oct 10 04:44:19 AM UTC 24 |
Oct 10 04:59:03 AM UTC 24 |
9986207971 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.4124032552 |
|
|
Oct 10 04:45:20 AM UTC 24 |
Oct 10 04:59:14 AM UTC 24 |
6434174562 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1331962470 |
|
|
Oct 10 02:48:39 AM UTC 24 |
Oct 10 04:59:21 AM UTC 24 |
23584591099 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.840586563 |
|
|
Oct 10 04:32:26 AM UTC 24 |
Oct 10 04:59:43 AM UTC 24 |
5878474280 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.1783699643 |
|
|
Oct 10 04:34:08 AM UTC 24 |
Oct 10 04:59:52 AM UTC 24 |
7063514004 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4078506496 |
|
|
Oct 10 04:37:12 AM UTC 24 |
Oct 10 05:00:00 AM UTC 24 |
8244589841 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2783644630 |
|
|
Oct 10 02:44:37 AM UTC 24 |
Oct 10 05:00:08 AM UTC 24 |
24607715412 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.3397388614 |
|
|
Oct 10 04:56:39 AM UTC 24 |
Oct 10 05:00:34 AM UTC 24 |
2459426060 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3621929772 |
|
|
Oct 10 02:46:00 AM UTC 24 |
Oct 10 05:00:51 AM UTC 24 |
25024135616 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1390055526 |
|
|
Oct 10 04:49:43 AM UTC 24 |
Oct 10 05:01:04 AM UTC 24 |
5167999024 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3054344388 |
|
|
Oct 10 02:47:45 AM UTC 24 |
Oct 10 05:01:05 AM UTC 24 |
24034414474 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1947768969 |
|
|
Oct 10 02:46:03 AM UTC 24 |
Oct 10 05:01:57 AM UTC 24 |
23737090610 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1324946537 |
|
|
Oct 10 04:52:27 AM UTC 24 |
Oct 10 05:02:18 AM UTC 24 |
4527500634 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.913423114 |
|
|
Oct 10 04:36:31 AM UTC 24 |
Oct 10 05:02:25 AM UTC 24 |
6856674466 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.826243416 |
|
|
Oct 10 04:56:17 AM UTC 24 |
Oct 10 05:02:44 AM UTC 24 |
3233128120 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4107362835 |
|
|
Oct 10 04:50:44 AM UTC 24 |
Oct 10 05:03:20 AM UTC 24 |
4582176146 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.3149663208 |
|
|
Oct 10 05:00:23 AM UTC 24 |
Oct 10 05:03:24 AM UTC 24 |
2845720528 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1975296015 |
|
|
Oct 10 04:48:01 AM UTC 24 |
Oct 10 05:03:43 AM UTC 24 |
4718829924 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2924166516 |
|
|
Oct 10 04:57:06 AM UTC 24 |
Oct 10 05:04:01 AM UTC 24 |
4004296142 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.3698799497 |
|
|
Oct 10 05:01:03 AM UTC 24 |
Oct 10 05:04:21 AM UTC 24 |
3113846710 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3416295733 |
|
|
Oct 10 04:56:44 AM UTC 24 |
Oct 10 05:04:23 AM UTC 24 |
3220930240 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2592944053 |
|
|
Oct 10 04:57:46 AM UTC 24 |
Oct 10 05:04:28 AM UTC 24 |
7569957940 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2294893935 |
|
|
Oct 10 04:54:40 AM UTC 24 |
Oct 10 05:04:44 AM UTC 24 |
4003602418 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1047133021 |
|
|
Oct 10 04:53:47 AM UTC 24 |
Oct 10 05:05:01 AM UTC 24 |
4944439208 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.100667943 |
|
|
Oct 10 04:53:10 AM UTC 24 |
Oct 10 05:05:07 AM UTC 24 |
4554065040 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.899390021 |
|
|
Oct 10 04:57:49 AM UTC 24 |
Oct 10 05:05:22 AM UTC 24 |
3354452452 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2728348071 |
|
|
Oct 10 05:01:51 AM UTC 24 |
Oct 10 05:05:51 AM UTC 24 |
2465073601 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.905312193 |
|
|
Oct 10 04:41:17 AM UTC 24 |
Oct 10 05:05:52 AM UTC 24 |
8600907800 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3706493632 |
|
|
Oct 10 02:47:46 AM UTC 24 |
Oct 10 05:06:09 AM UTC 24 |
23634643032 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.245316984 |
|
|
Oct 10 05:03:03 AM UTC 24 |
Oct 10 05:06:26 AM UTC 24 |
2208332236 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1158275546 |
|
|
Oct 10 05:00:36 AM UTC 24 |
Oct 10 05:06:38 AM UTC 24 |
4388025359 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.1071503718 |
|
|
Oct 10 04:59:59 AM UTC 24 |
Oct 10 05:07:01 AM UTC 24 |
4225128876 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1938195112 |
|
|
Oct 10 04:59:58 AM UTC 24 |
Oct 10 05:07:27 AM UTC 24 |
5234476876 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1635847269 |
|
|
Oct 10 04:56:50 AM UTC 24 |
Oct 10 05:07:29 AM UTC 24 |
4784389880 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.369738246 |
|
|
Oct 10 05:01:46 AM UTC 24 |
Oct 10 05:07:37 AM UTC 24 |
2974764640 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2156208475 |
|
|
Oct 10 04:41:18 AM UTC 24 |
Oct 10 05:08:08 AM UTC 24 |
7973169208 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.438349230 |
|
|
Oct 10 05:03:03 AM UTC 24 |
Oct 10 05:08:24 AM UTC 24 |
2605672100 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3396947789 |
|
|
Oct 10 04:56:43 AM UTC 24 |
Oct 10 05:08:32 AM UTC 24 |
5310543636 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.789131340 |
|
|
Oct 10 05:00:35 AM UTC 24 |
Oct 10 05:08:48 AM UTC 24 |
6166505630 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3317964658 |
|
|
Oct 10 05:00:05 AM UTC 24 |
Oct 10 05:08:48 AM UTC 24 |
5729152750 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3994824076 |
|
|
Oct 10 04:47:20 AM UTC 24 |
Oct 10 05:08:49 AM UTC 24 |
6054979678 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3802733929 |
|
|
Oct 10 04:59:06 AM UTC 24 |
Oct 10 05:08:49 AM UTC 24 |
7058730356 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3446175788 |
|
|
Oct 10 05:00:05 AM UTC 24 |
Oct 10 05:08:49 AM UTC 24 |
4156558504 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.991417759 |
|
|
Oct 10 05:04:19 AM UTC 24 |
Oct 10 05:09:09 AM UTC 24 |
3547935737 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3393412436 |
|
|
Oct 10 05:00:23 AM UTC 24 |
Oct 10 05:09:25 AM UTC 24 |
4677654303 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.883414502 |
|
|
Oct 10 05:05:21 AM UTC 24 |
Oct 10 05:10:00 AM UTC 24 |
3390262587 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1704380694 |
|
|
Oct 10 05:04:36 AM UTC 24 |
Oct 10 05:10:10 AM UTC 24 |
3497467400 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2502065654 |
|
|
Oct 10 04:49:46 AM UTC 24 |
Oct 10 05:10:31 AM UTC 24 |
13514175091 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2777810589 |
|
|
Oct 10 04:48:02 AM UTC 24 |
Oct 10 05:11:23 AM UTC 24 |
12825138218 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.129812684 |
|
|
Oct 10 04:39:54 AM UTC 24 |
Oct 10 05:11:43 AM UTC 24 |
10309420200 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.121327799 |
|
|
Oct 10 05:08:00 AM UTC 24 |
Oct 10 05:11:57 AM UTC 24 |
2665530584 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.930254792 |
|
|
Oct 10 04:56:49 AM UTC 24 |
Oct 10 05:13:16 AM UTC 24 |
8275408536 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.1266491749 |
|
|
Oct 10 05:02:32 AM UTC 24 |
Oct 10 05:13:39 AM UTC 24 |
5981347324 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.1345983315 |
|
|
Oct 10 05:11:57 AM UTC 24 |
Oct 10 05:13:59 AM UTC 24 |
2424266446 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.4258252538 |
|
|
Oct 10 04:39:36 AM UTC 24 |
Oct 10 05:14:09 AM UTC 24 |
8796730286 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4117652049 |
|
|
Oct 10 04:40:25 AM UTC 24 |
Oct 10 05:15:46 AM UTC 24 |
9454224046 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2277484587 |
|
|
Oct 10 05:11:54 AM UTC 24 |
Oct 10 05:15:54 AM UTC 24 |
2955108290 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3438017412 |
|
|
Oct 10 05:05:24 AM UTC 24 |
Oct 10 05:16:02 AM UTC 24 |
4719510374 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1609255551 |
|
|
Oct 10 05:03:21 AM UTC 24 |
Oct 10 05:16:05 AM UTC 24 |
5032685609 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.520560292 |
|
|
Oct 10 05:11:58 AM UTC 24 |
Oct 10 05:16:10 AM UTC 24 |
3884034149 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.1307040572 |
|
|
Oct 10 05:12:08 AM UTC 24 |
Oct 10 05:16:23 AM UTC 24 |
2864044368 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.86608641 |
|
|
Oct 10 05:12:20 AM UTC 24 |
Oct 10 05:16:28 AM UTC 24 |
2883449408 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.2133395301 |
|
|
Oct 10 05:12:34 AM UTC 24 |
Oct 10 05:16:42 AM UTC 24 |
3351482488 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.1063879627 |
|
|
Oct 10 05:06:02 AM UTC 24 |
Oct 10 05:17:03 AM UTC 24 |
4256807990 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.3132156662 |
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Oct 10 05:06:02 AM UTC 24 |
Oct 10 05:17:08 AM UTC 24 |
9952791152 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1693568255 |
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Oct 10 05:12:07 AM UTC 24 |
Oct 10 05:17:09 AM UTC 24 |
3481515300 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.957760112 |
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Oct 10 04:47:13 AM UTC 24 |
Oct 10 05:17:54 AM UTC 24 |
21843087880 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.284874125 |
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Oct 10 05:13:52 AM UTC 24 |
Oct 10 05:19:10 AM UTC 24 |
2917184870 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.3850974196 |
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Oct 10 05:14:13 AM UTC 24 |
Oct 10 05:19:13 AM UTC 24 |
3733796556 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3242456521 |
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Oct 10 05:14:45 AM UTC 24 |
Oct 10 05:19:59 AM UTC 24 |
2695250040 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.799252186 |
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Oct 10 04:56:23 AM UTC 24 |
Oct 10 05:20:10 AM UTC 24 |
13681690737 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.920746383 |
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Oct 10 04:56:11 AM UTC 24 |
Oct 10 05:20:22 AM UTC 24 |
12729361470 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.1340832018 |
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Oct 10 05:17:46 AM UTC 24 |
Oct 10 05:20:28 AM UTC 24 |
1952220730 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.335712708 |
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Oct 10 05:17:45 AM UTC 24 |
Oct 10 05:20:57 AM UTC 24 |
2186731392 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.3037657871 |
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Oct 10 05:11:58 AM UTC 24 |
Oct 10 05:21:09 AM UTC 24 |
4991011720 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.668630574 |
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Oct 10 05:17:15 AM UTC 24 |
Oct 10 05:21:26 AM UTC 24 |
3278415312 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3212592818 |
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Oct 10 05:04:16 AM UTC 24 |
Oct 10 05:21:53 AM UTC 24 |
6843233427 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.1093504607 |
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Oct 10 05:17:28 AM UTC 24 |
Oct 10 05:22:01 AM UTC 24 |
2175543236 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2918508586 |
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Oct 10 05:12:32 AM UTC 24 |
Oct 10 05:22:20 AM UTC 24 |
3638959200 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.4108868363 |
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Oct 10 05:18:04 AM UTC 24 |
Oct 10 05:22:35 AM UTC 24 |
2885169500 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1223559623 |
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Oct 10 04:58:16 AM UTC 24 |
Oct 10 05:22:41 AM UTC 24 |
24730864408 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3828803242 |
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Oct 10 05:17:58 AM UTC 24 |
Oct 10 05:22:53 AM UTC 24 |
2748236080 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3293359598 |
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Oct 10 05:17:30 AM UTC 24 |
Oct 10 05:22:58 AM UTC 24 |
2771397888 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.1989003595 |
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Oct 10 05:18:01 AM UTC 24 |
Oct 10 05:23:10 AM UTC 24 |
2995614952 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.909660201 |
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Oct 10 05:17:58 AM UTC 24 |
Oct 10 05:23:14 AM UTC 24 |
3458749848 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.277856825 |
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Oct 10 05:18:26 AM UTC 24 |
Oct 10 05:23:27 AM UTC 24 |
2578058852 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.463490605 |
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Oct 10 05:17:20 AM UTC 24 |
Oct 10 05:23:57 AM UTC 24 |
6152258860 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.1831288779 |
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Oct 10 05:21:48 AM UTC 24 |
Oct 10 05:25:42 AM UTC 24 |
3193121630 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.1329516983 |
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Oct 10 05:21:11 AM UTC 24 |
Oct 10 05:25:43 AM UTC 24 |
3580045840 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2339607432 |
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Oct 10 05:21:04 AM UTC 24 |
Oct 10 05:26:59 AM UTC 24 |
2700744383 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2216153550 |
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Oct 10 05:07:19 AM UTC 24 |
Oct 10 05:27:24 AM UTC 24 |
5964760316 ps |