| T1054 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.2006953079 |
|
|
Oct 10 05:17:39 AM UTC 24 |
Oct 10 05:27:42 AM UTC 24 |
6392481392 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1375965111 |
|
|
Oct 10 05:19:56 AM UTC 24 |
Oct 10 05:27:49 AM UTC 24 |
4973173400 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.957032760 |
|
|
Oct 10 05:21:11 AM UTC 24 |
Oct 10 05:28:44 AM UTC 24 |
4178603400 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3431618023 |
|
|
Oct 10 04:21:48 AM UTC 24 |
Oct 10 05:29:31 AM UTC 24 |
20175629450 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1626657577 |
|
|
Oct 10 05:05:18 AM UTC 24 |
Oct 10 05:31:32 AM UTC 24 |
11005331528 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.3861880522 |
|
|
Oct 10 05:07:53 AM UTC 24 |
Oct 10 05:32:13 AM UTC 24 |
5934864448 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4283086736 |
|
|
Oct 10 05:27:36 AM UTC 24 |
Oct 10 05:32:59 AM UTC 24 |
3721817983 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.1990618537 |
|
|
Oct 10 05:22:03 AM UTC 24 |
Oct 10 05:33:00 AM UTC 24 |
5092151840 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3936664338 |
|
|
Oct 10 05:19:56 AM UTC 24 |
Oct 10 05:33:06 AM UTC 24 |
5898641538 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3683930435 |
|
|
Oct 10 05:26:23 AM UTC 24 |
Oct 10 05:33:12 AM UTC 24 |
3202709280 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1115838874 |
|
|
Oct 10 05:26:24 AM UTC 24 |
Oct 10 05:33:17 AM UTC 24 |
3759285550 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.2826596880 |
|
|
Oct 10 05:22:40 AM UTC 24 |
Oct 10 05:33:27 AM UTC 24 |
3846913218 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.320683443 |
|
|
Oct 10 04:58:13 AM UTC 24 |
Oct 10 05:33:40 AM UTC 24 |
27987639544 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.3002379084 |
|
|
Oct 10 05:20:44 AM UTC 24 |
Oct 10 05:33:42 AM UTC 24 |
5926208050 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.739906335 |
|
|
Oct 10 05:23:05 AM UTC 24 |
Oct 10 05:33:42 AM UTC 24 |
4388132312 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.2096046212 |
|
|
Oct 10 05:23:36 AM UTC 24 |
Oct 10 05:33:51 AM UTC 24 |
4186470324 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2457284784 |
|
|
Oct 10 05:25:00 AM UTC 24 |
Oct 10 05:34:27 AM UTC 24 |
4278147530 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1310026151 |
|
|
Oct 10 04:25:11 AM UTC 24 |
Oct 10 05:35:40 AM UTC 24 |
19001121504 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3786842826 |
|
|
Oct 10 05:25:01 AM UTC 24 |
Oct 10 05:36:36 AM UTC 24 |
4825383328 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1377042139 |
|
|
Oct 10 05:28:30 AM UTC 24 |
Oct 10 05:37:06 AM UTC 24 |
3703621916 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4011076208 |
|
|
Oct 10 05:24:17 AM UTC 24 |
Oct 10 05:37:24 AM UTC 24 |
5370434160 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.2892408899 |
|
|
Oct 10 05:28:29 AM UTC 24 |
Oct 10 05:38:01 AM UTC 24 |
4916365808 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.737285737 |
|
|
Oct 10 05:24:30 AM UTC 24 |
Oct 10 05:38:58 AM UTC 24 |
4930682254 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2908864877 |
|
|
Oct 10 05:32:10 AM UTC 24 |
Oct 10 05:39:12 AM UTC 24 |
4775914019 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.2786133476 |
|
|
Oct 10 05:29:22 AM UTC 24 |
Oct 10 05:39:24 AM UTC 24 |
4335681260 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1609657568 |
|
|
Oct 10 05:36:16 AM UTC 24 |
Oct 10 05:39:33 AM UTC 24 |
2771688419 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1693113949 |
|
|
Oct 10 05:35:14 AM UTC 24 |
Oct 10 05:39:59 AM UTC 24 |
2672701400 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.2289290211 |
|
|
Oct 10 05:35:14 AM UTC 24 |
Oct 10 05:40:40 AM UTC 24 |
2981718064 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.477639547 |
|
|
Oct 10 05:24:03 AM UTC 24 |
Oct 10 05:40:44 AM UTC 24 |
9066083064 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2378526814 |
|
|
Oct 10 05:37:12 AM UTC 24 |
Oct 10 05:41:13 AM UTC 24 |
3063894737 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2408769123 |
|
|
Oct 10 05:35:12 AM UTC 24 |
Oct 10 05:41:36 AM UTC 24 |
3660235188 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.4258132201 |
|
|
Oct 10 05:25:00 AM UTC 24 |
Oct 10 05:41:44 AM UTC 24 |
5683469682 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.533611953 |
|
|
Oct 10 05:38:37 AM UTC 24 |
Oct 10 05:42:13 AM UTC 24 |
3013276493 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2234729032 |
|
|
Oct 10 05:40:33 AM UTC 24 |
Oct 10 05:42:33 AM UTC 24 |
2056838158 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2554276859 |
|
|
Oct 10 05:30:09 AM UTC 24 |
Oct 10 05:42:40 AM UTC 24 |
4286980509 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.3598732745 |
|
|
Oct 10 05:28:01 AM UTC 24 |
Oct 10 05:43:31 AM UTC 24 |
7373453482 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1669490720 |
|
|
Oct 10 05:40:12 AM UTC 24 |
Oct 10 05:43:33 AM UTC 24 |
2440481155 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2915805935 |
|
|
Oct 10 05:21:44 AM UTC 24 |
Oct 10 05:44:48 AM UTC 24 |
8635123628 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.886474948 |
|
|
Oct 10 05:05:21 AM UTC 24 |
Oct 10 05:45:40 AM UTC 24 |
19045548251 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2968304171 |
|
|
Oct 10 05:35:17 AM UTC 24 |
Oct 10 05:46:25 AM UTC 24 |
4652959440 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_descrambling.1311027134 |
|
|
Oct 10 05:37:45 AM UTC 24 |
Oct 10 05:46:56 AM UTC 24 |
3931242038 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.675393688 |
|
|
Oct 10 05:42:22 AM UTC 24 |
Oct 10 05:47:46 AM UTC 24 |
2498483296 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.1474978293 |
|
|
Oct 10 05:41:49 AM UTC 24 |
Oct 10 05:48:47 AM UTC 24 |
4507358218 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4294962118 |
|
|
Oct 10 04:25:11 AM UTC 24 |
Oct 10 05:48:55 AM UTC 24 |
16607843868 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.88630195 |
|
|
Oct 10 05:32:49 AM UTC 24 |
Oct 10 05:49:00 AM UTC 24 |
5510786908 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.2720360537 |
|
|
Oct 10 03:30:23 AM UTC 24 |
Oct 10 05:50:18 AM UTC 24 |
25983845902 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.571418271 |
|
|
Oct 10 05:43:16 AM UTC 24 |
Oct 10 05:51:02 AM UTC 24 |
7024047898 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.254533576 |
|
|
Oct 10 05:43:17 AM UTC 24 |
Oct 10 05:52:03 AM UTC 24 |
5242320288 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3955119665 |
|
|
Oct 10 05:34:50 AM UTC 24 |
Oct 10 05:53:04 AM UTC 24 |
6520959932 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4209207203 |
|
|
Oct 10 05:34:30 AM UTC 24 |
Oct 10 05:53:31 AM UTC 24 |
5730472742 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1023648025 |
|
|
Oct 10 05:35:13 AM UTC 24 |
Oct 10 05:53:39 AM UTC 24 |
6537090632 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.3105691249 |
|
|
Oct 10 05:42:49 AM UTC 24 |
Oct 10 05:54:08 AM UTC 24 |
6941250920 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.782131193 |
|
|
Oct 10 05:37:59 AM UTC 24 |
Oct 10 05:54:13 AM UTC 24 |
9185401864 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.10209581 |
|
|
Oct 10 05:48:22 AM UTC 24 |
Oct 10 05:54:56 AM UTC 24 |
5842107608 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1111234021 |
|
|
Oct 10 05:50:54 AM UTC 24 |
Oct 10 05:55:56 AM UTC 24 |
2861288484 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3924256527 |
|
|
Oct 10 05:49:47 AM UTC 24 |
Oct 10 05:56:16 AM UTC 24 |
5510341320 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3874982370 |
|
|
Oct 10 05:52:38 AM UTC 24 |
Oct 10 05:56:59 AM UTC 24 |
2657753668 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3526439511 |
|
|
Oct 10 05:47:32 AM UTC 24 |
Oct 10 05:57:59 AM UTC 24 |
8324993980 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.376852411 |
|
|
Oct 10 05:14:41 AM UTC 24 |
Oct 10 05:58:09 AM UTC 24 |
10523951070 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.904257982 |
|
|
Oct 10 05:44:19 AM UTC 24 |
Oct 10 05:59:01 AM UTC 24 |
8115382012 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1940302452 |
|
|
Oct 10 05:35:21 AM UTC 24 |
Oct 10 05:59:32 AM UTC 24 |
9374709792 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2548950963 |
|
|
Oct 10 05:51:40 AM UTC 24 |
Oct 10 05:59:56 AM UTC 24 |
5429048948 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.4110767861 |
|
|
Oct 10 04:07:05 AM UTC 24 |
Oct 10 06:01:16 AM UTC 24 |
42865103816 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4149604926 |
|
|
Oct 10 05:54:20 AM UTC 24 |
Oct 10 06:01:55 AM UTC 24 |
3044786429 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2355067266 |
|
|
Oct 10 05:55:00 AM UTC 24 |
Oct 10 06:01:59 AM UTC 24 |
3820251351 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.1145086099 |
|
|
Oct 10 05:40:11 AM UTC 24 |
Oct 10 06:02:38 AM UTC 24 |
11952642320 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1676726197 |
|
|
Oct 10 05:47:02 AM UTC 24 |
Oct 10 06:04:07 AM UTC 24 |
12589022653 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.2232964844 |
|
|
Oct 10 05:56:32 AM UTC 24 |
Oct 10 06:04:29 AM UTC 24 |
4352055000 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1855499593 |
|
|
Oct 10 05:35:20 AM UTC 24 |
Oct 10 06:04:59 AM UTC 24 |
9281282408 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.4207841618 |
|
|
Oct 10 04:10:02 AM UTC 24 |
Oct 10 06:05:27 AM UTC 24 |
46726914932 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3277762733 |
|
|
Oct 10 05:56:52 AM UTC 24 |
Oct 10 06:05:39 AM UTC 24 |
6875924020 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1151342020 |
|
|
Oct 10 05:54:20 AM UTC 24 |
Oct 10 06:05:41 AM UTC 24 |
4626344127 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.23629081 |
|
|
Oct 10 05:58:44 AM UTC 24 |
Oct 10 06:05:58 AM UTC 24 |
5219623720 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.882367174 |
|
|
Oct 10 05:55:00 AM UTC 24 |
Oct 10 06:07:35 AM UTC 24 |
6619153808 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.705966950 |
|
|
Oct 10 05:44:18 AM UTC 24 |
Oct 10 06:07:46 AM UTC 24 |
8950901619 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.406639190 |
|
|
Oct 10 05:10:24 AM UTC 24 |
Oct 10 06:07:57 AM UTC 24 |
11241781973 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1646353644 |
|
|
Oct 10 05:07:47 AM UTC 24 |
Oct 10 06:08:09 AM UTC 24 |
20436964408 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3953970946 |
|
|
Oct 10 05:57:35 AM UTC 24 |
Oct 10 06:09:38 AM UTC 24 |
8391164052 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.1512232580 |
|
|
Oct 10 04:42:05 AM UTC 24 |
Oct 10 06:09:56 AM UTC 24 |
16175197000 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_mem_scramble.2186246840 |
|
|
Oct 10 06:02:41 AM UTC 24 |
Oct 10 06:10:21 AM UTC 24 |
3852940220 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.2235261709 |
|
|
Oct 10 06:04:44 AM UTC 24 |
Oct 10 06:10:23 AM UTC 24 |
2517510200 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.2077459867 |
|
|
Oct 10 06:05:06 AM UTC 24 |
Oct 10 06:10:24 AM UTC 24 |
2982256273 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.1080077450 |
|
|
Oct 10 04:10:05 AM UTC 24 |
Oct 10 06:10:30 AM UTC 24 |
47867595885 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3347146047 |
|
|
Oct 10 05:58:48 AM UTC 24 |
Oct 10 06:10:36 AM UTC 24 |
4269597192 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.4086429304 |
|
|
Oct 10 06:05:35 AM UTC 24 |
Oct 10 06:10:39 AM UTC 24 |
3285236972 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.3956622182 |
|
|
Oct 10 05:34:02 AM UTC 24 |
Oct 10 06:10:54 AM UTC 24 |
19835771390 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.4010691603 |
|
|
Oct 10 05:24:31 AM UTC 24 |
Oct 10 06:11:24 AM UTC 24 |
13432570890 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2734312266 |
|
|
Oct 10 06:06:35 AM UTC 24 |
Oct 10 06:11:55 AM UTC 24 |
2632633512 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.1921250553 |
|
|
Oct 10 06:06:41 AM UTC 24 |
Oct 10 06:12:10 AM UTC 24 |
2867830466 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.1466348410 |
|
|
Oct 10 06:06:41 AM UTC 24 |
Oct 10 06:13:06 AM UTC 24 |
4473006620 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.1036997562 |
|
|
Oct 10 01:44:58 AM UTC 24 |
Oct 10 06:13:25 AM UTC 24 |
68105548235 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1526711098 |
|
|
Oct 10 05:59:38 AM UTC 24 |
Oct 10 06:14:01 AM UTC 24 |
19755960432 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.753981416 |
|
|
Oct 10 05:46:18 AM UTC 24 |
Oct 10 06:14:17 AM UTC 24 |
16956915809 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3982274151 |
|
|
Oct 10 06:10:31 AM UTC 24 |
Oct 10 06:14:21 AM UTC 24 |
2560549164 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.2942970118 |
|
|
Oct 10 04:11:41 AM UTC 24 |
Oct 10 06:14:35 AM UTC 24 |
48238178055 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.809691225 |
|
|
Oct 10 06:08:44 AM UTC 24 |
Oct 10 06:15:12 AM UTC 24 |
4273002512 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.811997965 |
|
|
Oct 10 05:42:23 AM UTC 24 |
Oct 10 06:15:24 AM UTC 24 |
14850337160 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.1167999814 |
|
|
Oct 10 06:00:09 AM UTC 24 |
Oct 10 06:15:39 AM UTC 24 |
6165872322 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.1254215052 |
|
|
Oct 10 06:11:19 AM UTC 24 |
Oct 10 06:15:54 AM UTC 24 |
2857637640 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.3772700716 |
|
|
Oct 10 06:12:12 AM UTC 24 |
Oct 10 06:16:36 AM UTC 24 |
2665088300 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3964168410 |
|
|
Oct 10 06:12:43 AM UTC 24 |
Oct 10 06:16:48 AM UTC 24 |
2415124198 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.154328014 |
|
|
Oct 10 06:10:15 AM UTC 24 |
Oct 10 06:17:00 AM UTC 24 |
3464041184 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.1432497269 |
|
|
Oct 10 06:06:42 AM UTC 24 |
Oct 10 06:17:47 AM UTC 24 |
4462012524 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1328976256 |
|
|
Oct 10 06:03:13 AM UTC 24 |
Oct 10 06:18:27 AM UTC 24 |
4720287430 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.3589594317 |
|
|
Oct 10 06:15:08 AM UTC 24 |
Oct 10 06:18:56 AM UTC 24 |
2867363424 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.2341832104 |
|
|
Oct 10 06:02:41 AM UTC 24 |
Oct 10 06:19:50 AM UTC 24 |
4974262692 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.408981775 |
|
|
Oct 10 05:45:25 AM UTC 24 |
Oct 10 06:19:55 AM UTC 24 |
18995045933 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.3388136016 |
|
|
Oct 10 06:15:14 AM UTC 24 |
Oct 10 06:20:37 AM UTC 24 |
3499423836 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1047543531 |
|
|
Oct 10 06:12:31 AM UTC 24 |
Oct 10 06:20:46 AM UTC 24 |
5057254280 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.2565298847 |
|
|
Oct 10 05:11:55 AM UTC 24 |
Oct 10 06:20:50 AM UTC 24 |
15026463443 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2308789478 |
|
|
Oct 10 06:15:14 AM UTC 24 |
Oct 10 06:20:52 AM UTC 24 |
2988816152 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.1938618125 |
|
|
Oct 10 05:09:22 AM UTC 24 |
Oct 10 06:21:12 AM UTC 24 |
15152399640 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2337216924 |
|
|
Oct 10 05:12:01 AM UTC 24 |
Oct 10 06:21:57 AM UTC 24 |
15084601640 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.3089753127 |
|
|
Oct 10 06:12:14 AM UTC 24 |
Oct 10 06:22:01 AM UTC 24 |
2950655520 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.1745237477 |
|
|
Oct 10 05:10:24 AM UTC 24 |
Oct 10 06:22:03 AM UTC 24 |
29687895955 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.1504664128 |
|
|
Oct 10 06:18:23 AM UTC 24 |
Oct 10 06:22:26 AM UTC 24 |
2394064498 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.2684845084 |
|
|
Oct 10 06:16:00 AM UTC 24 |
Oct 10 06:22:37 AM UTC 24 |
3779865732 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1519832233 |
|
|
Oct 10 05:41:28 AM UTC 24 |
Oct 10 06:22:56 AM UTC 24 |
34881095192 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3765857229 |
|
|
Oct 10 06:12:14 AM UTC 24 |
Oct 10 06:23:29 AM UTC 24 |
3294763920 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1168725812 |
|
|
Oct 10 05:11:41 AM UTC 24 |
Oct 10 06:24:46 AM UTC 24 |
15215321240 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.1229381651 |
|
|
Oct 10 06:20:36 AM UTC 24 |
Oct 10 06:24:47 AM UTC 24 |
3423091000 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4179044995 |
|
|
Oct 10 06:19:30 AM UTC 24 |
Oct 10 06:24:58 AM UTC 24 |
3017570658 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2756352071 |
|
|
Oct 10 06:12:01 AM UTC 24 |
Oct 10 06:25:02 AM UTC 24 |
7653798120 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.220285387 |
|
|
Oct 10 06:19:04 AM UTC 24 |
Oct 10 06:25:23 AM UTC 24 |
3702061060 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.1236263568 |
|
|
Oct 10 05:11:06 AM UTC 24 |
Oct 10 06:25:43 AM UTC 24 |
15600207910 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.4135520599 |
|
|
Oct 10 05:08:31 AM UTC 24 |
Oct 10 06:26:53 AM UTC 24 |
14576418580 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2992758665 |
|
|
Oct 10 05:04:15 AM UTC 24 |
Oct 10 06:27:21 AM UTC 24 |
25330222107 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.2692332665 |
|
|
Oct 10 06:20:36 AM UTC 24 |
Oct 10 06:27:39 AM UTC 24 |
2983888632 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.3960504023 |
|
|
Oct 10 06:12:16 AM UTC 24 |
Oct 10 06:27:50 AM UTC 24 |
4243095538 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.4270752649 |
|
|
Oct 10 06:23:14 AM UTC 24 |
Oct 10 06:28:18 AM UTC 24 |
2660818459 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.1321448205 |
|
|
Oct 10 05:55:01 AM UTC 24 |
Oct 10 06:29:32 AM UTC 24 |
25233110360 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.2072265708 |
|
|
Oct 10 06:26:15 AM UTC 24 |
Oct 10 06:30:13 AM UTC 24 |
3004212672 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.834138074 |
|
|
Oct 10 06:14:46 AM UTC 24 |
Oct 10 06:30:15 AM UTC 24 |
6193276150 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2148465250 |
|
|
Oct 10 06:21:51 AM UTC 24 |
Oct 10 06:30:31 AM UTC 24 |
9480558040 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2275278415 |
|
|
Oct 10 06:07:18 AM UTC 24 |
Oct 10 06:31:02 AM UTC 24 |
7792085570 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.1359815936 |
|
|
Oct 10 05:11:05 AM UTC 24 |
Oct 10 06:31:37 AM UTC 24 |
15507358083 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3058810844 |
|
|
Oct 10 06:21:57 AM UTC 24 |
Oct 10 06:31:37 AM UTC 24 |
5095546912 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1928637712 |
|
|
Oct 10 05:11:30 AM UTC 24 |
Oct 10 06:32:04 AM UTC 24 |
16051287752 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.610567511 |
|
|
Oct 10 06:09:00 AM UTC 24 |
Oct 10 06:32:53 AM UTC 24 |
11794154108 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1131203341 |
|
|
Oct 10 06:27:30 AM UTC 24 |
Oct 10 06:32:57 AM UTC 24 |
3763887864 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4204643981 |
|
|
Oct 10 06:23:19 AM UTC 24 |
Oct 10 06:33:08 AM UTC 24 |
5352982830 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1504641449 |
|
|
Oct 10 06:24:07 AM UTC 24 |
Oct 10 06:33:30 AM UTC 24 |
3621366500 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.225557851 |
|
|
Oct 10 06:08:56 AM UTC 24 |
Oct 10 06:33:56 AM UTC 24 |
7873581204 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3514328899 |
|
|
Oct 10 06:21:59 AM UTC 24 |
Oct 10 06:33:58 AM UTC 24 |
3987062347 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1152991473 |
|
|
Oct 10 06:26:06 AM UTC 24 |
Oct 10 06:34:40 AM UTC 24 |
5428328000 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3742076593 |
|
|
Oct 10 06:22:00 AM UTC 24 |
Oct 10 06:35:06 AM UTC 24 |
7321669012 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.2460596472 |
|
|
Oct 10 06:14:02 AM UTC 24 |
Oct 10 06:35:48 AM UTC 24 |
6678287688 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.265546921 |
|
|
Oct 10 06:09:03 AM UTC 24 |
Oct 10 06:36:35 AM UTC 24 |
8036413488 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1603518373 |
|
|
Oct 10 06:23:15 AM UTC 24 |
Oct 10 06:36:38 AM UTC 24 |
7691695190 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2720179575 |
|
|
Oct 10 06:32:21 AM UTC 24 |
Oct 10 06:36:47 AM UTC 24 |
3232294264 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.596170473 |
|
|
Oct 10 06:26:14 AM UTC 24 |
Oct 10 06:36:53 AM UTC 24 |
4745542532 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.562990173 |
|
|
Oct 10 05:11:43 AM UTC 24 |
Oct 10 06:37:28 AM UTC 24 |
14987823208 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.1502955482 |
|
|
Oct 10 06:22:00 AM UTC 24 |
Oct 10 06:38:07 AM UTC 24 |
7652311293 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2271804403 |
|
|
Oct 10 06:26:19 AM UTC 24 |
Oct 10 06:38:07 AM UTC 24 |
5935550488 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.4144673795 |
|
|
Oct 10 06:13:44 AM UTC 24 |
Oct 10 06:38:10 AM UTC 24 |
6031714920 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.196844995 |
|
|
Oct 10 06:28:13 AM UTC 24 |
Oct 10 06:38:28 AM UTC 24 |
4292457110 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3681013869 |
|
|
Oct 10 06:23:10 AM UTC 24 |
Oct 10 06:38:42 AM UTC 24 |
7880697214 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3801421684 |
|
|
Oct 10 06:28:27 AM UTC 24 |
Oct 10 06:38:46 AM UTC 24 |
4607769010 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.4222081427 |
|
|
Oct 10 05:10:48 AM UTC 24 |
Oct 10 06:39:08 AM UTC 24 |
17516715262 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.110697521 |
|
|
Oct 10 06:25:58 AM UTC 24 |
Oct 10 06:39:16 AM UTC 24 |
4639328008 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1013581450 |
|
|
Oct 10 06:31:13 AM UTC 24 |
Oct 10 06:39:21 AM UTC 24 |
3283454940 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.478936851 |
|
|
Oct 10 06:31:37 AM UTC 24 |
Oct 10 06:39:43 AM UTC 24 |
3038005530 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1566207380 |
|
|
Oct 10 06:28:55 AM UTC 24 |
Oct 10 06:40:32 AM UTC 24 |
3794041440 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2123416654 |
|
|
Oct 10 06:34:44 AM UTC 24 |
Oct 10 06:40:51 AM UTC 24 |
3569034066 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2975919590 |
|
|
Oct 10 06:33:47 AM UTC 24 |
Oct 10 06:41:34 AM UTC 24 |
5522429110 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3808378602 |
|
|
Oct 10 06:31:09 AM UTC 24 |
Oct 10 06:41:36 AM UTC 24 |
4847758468 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.181009426 |
|
|
Oct 10 06:34:08 AM UTC 24 |
Oct 10 06:41:45 AM UTC 24 |
6838329348 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1027802923 |
|
|
Oct 10 06:31:12 AM UTC 24 |
Oct 10 06:41:48 AM UTC 24 |
4417490352 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.163518294 |
|
|
Oct 10 06:23:34 AM UTC 24 |
Oct 10 06:42:07 AM UTC 24 |
6335162926 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1415390655 |
|
|
Oct 10 06:30:09 AM UTC 24 |
Oct 10 06:42:46 AM UTC 24 |
4836594836 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2669154137 |
|
|
Oct 10 06:27:56 AM UTC 24 |
Oct 10 06:42:47 AM UTC 24 |
13365330497 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2857391014 |
|
|
Oct 10 06:35:43 AM UTC 24 |
Oct 10 06:43:18 AM UTC 24 |
5651267706 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2228887414 |
|
|
Oct 10 06:32:20 AM UTC 24 |
Oct 10 06:43:20 AM UTC 24 |
4703026944 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.3214525712 |
|
|
Oct 10 06:38:44 AM UTC 24 |
Oct 10 06:43:21 AM UTC 24 |
3464616017 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1117635916 |
|
|
Oct 10 06:17:22 AM UTC 24 |
Oct 10 06:44:09 AM UTC 24 |
8844126260 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2581167694 |
|
|
Oct 10 06:40:19 AM UTC 24 |
Oct 10 06:44:34 AM UTC 24 |
3429247039 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.190015629 |
|
|
Oct 10 06:39:28 AM UTC 24 |
Oct 10 06:44:57 AM UTC 24 |
2548968857 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2396879285 |
|
|
Oct 10 06:39:02 AM UTC 24 |
Oct 10 06:45:06 AM UTC 24 |
3086823180 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.4230612978 |
|
|
Oct 10 06:12:09 AM UTC 24 |
Oct 10 06:46:00 AM UTC 24 |
9061845960 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1182816058 |
|
|
Oct 10 06:16:13 AM UTC 24 |
Oct 10 06:46:32 AM UTC 24 |
7196737160 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.2531031838 |
|
|
Oct 10 06:40:07 AM UTC 24 |
Oct 10 06:46:44 AM UTC 24 |
2868495380 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3341208998 |
|
|
Oct 10 06:37:44 AM UTC 24 |
Oct 10 06:46:50 AM UTC 24 |
6631249780 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3331469242 |
|
|
Oct 10 06:37:39 AM UTC 24 |
Oct 10 06:46:54 AM UTC 24 |
4292013296 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation.761202608 |
|
|
Oct 10 06:16:25 AM UTC 24 |
Oct 10 06:47:22 AM UTC 24 |
9141234214 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4240086469 |
|
|
Oct 10 06:42:59 AM UTC 24 |
Oct 10 06:47:26 AM UTC 24 |
3130065638 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2305148249 |
|
|
Oct 10 06:42:58 AM UTC 24 |
Oct 10 06:47:47 AM UTC 24 |
2876497413 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2777561717 |
|
|
Oct 10 06:37:38 AM UTC 24 |
Oct 10 06:47:56 AM UTC 24 |
5124607452 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2192412017 |
|
|
Oct 10 06:36:24 AM UTC 24 |
Oct 10 06:48:04 AM UTC 24 |
6894087796 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3508776066 |
|
|
Oct 10 06:42:50 AM UTC 24 |
Oct 10 06:48:27 AM UTC 24 |
3822360623 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.3005696749 |
|
|
Oct 10 06:44:54 AM UTC 24 |
Oct 10 06:48:56 AM UTC 24 |
2834707598 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.918610945 |
|
|
Oct 10 06:37:43 AM UTC 24 |
Oct 10 06:49:02 AM UTC 24 |
6324204949 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1683093436 |
|
|
Oct 10 06:32:26 AM UTC 24 |
Oct 10 06:49:25 AM UTC 24 |
8903257784 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.2361315398 |
|
|
Oct 10 06:33:44 AM UTC 24 |
Oct 10 06:51:28 AM UTC 24 |
7613695124 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.3935470261 |
|
|
Oct 10 06:26:15 AM UTC 24 |
Oct 10 06:51:29 AM UTC 24 |
13481860820 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2241130353 |
|
|
Oct 10 06:49:23 AM UTC 24 |
Oct 10 06:51:54 AM UTC 24 |
2249027941 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2500836294 |
|
|
Oct 10 06:40:22 AM UTC 24 |
Oct 10 06:52:26 AM UTC 24 |
5298097216 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.3229746981 |
|
|
Oct 10 06:38:43 AM UTC 24 |
Oct 10 06:52:36 AM UTC 24 |
8587659553 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1889360020 |
|
|
Oct 10 06:43:01 AM UTC 24 |
Oct 10 06:53:14 AM UTC 24 |
4938025240 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1411941744 |
|
|
Oct 10 05:05:57 AM UTC 24 |
Oct 10 06:53:29 AM UTC 24 |
30004986457 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.635487168 |
|
|
Oct 10 06:43:30 AM UTC 24 |
Oct 10 06:53:42 AM UTC 24 |
4448537984 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.3931009896 |
|
|
Oct 10 06:40:17 AM UTC 24 |
Oct 10 06:53:51 AM UTC 24 |
6282258900 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.903442748 |
|
|
Oct 10 06:50:23 AM UTC 24 |
Oct 10 06:54:14 AM UTC 24 |
4514213124 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.1823129515 |
|
|
Oct 10 06:44:30 AM UTC 24 |
Oct 10 06:54:37 AM UTC 24 |
10730569854 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.3391319249 |
|
|
Oct 10 06:52:14 AM UTC 24 |
Oct 10 06:55:54 AM UTC 24 |
3118802016 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.1025144977 |
|
|
Oct 10 06:52:30 AM UTC 24 |
Oct 10 06:56:19 AM UTC 24 |
2983384590 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2641880231 |
|
|
Oct 10 06:37:58 AM UTC 24 |
Oct 10 06:56:45 AM UTC 24 |
10427804324 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2532099321 |
|
|
Oct 10 06:53:09 AM UTC 24 |
Oct 10 06:56:50 AM UTC 24 |
2360701708 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.215593715 |
|
|
Oct 10 06:33:16 AM UTC 24 |
Oct 10 06:57:14 AM UTC 24 |
13596790422 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.2462169801 |
|
|
Oct 10 06:53:50 AM UTC 24 |
Oct 10 06:57:29 AM UTC 24 |
2816048090 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.3880201162 |
|
|
Oct 10 06:52:14 AM UTC 24 |
Oct 10 06:57:50 AM UTC 24 |
3551695312 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1505164136 |
|
|
Oct 10 06:41:09 AM UTC 24 |
Oct 10 06:58:26 AM UTC 24 |
6892032136 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2779500517 |
|
|
Oct 10 06:38:44 AM UTC 24 |
Oct 10 06:59:21 AM UTC 24 |
10809180549 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.1039895431 |
|
|
Oct 10 06:17:49 AM UTC 24 |
Oct 10 06:59:29 AM UTC 24 |
12372786220 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.4023186601 |
|
|
Oct 10 06:54:30 AM UTC 24 |
Oct 10 07:00:12 AM UTC 24 |
3508017962 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2294046980 |
|
|
Oct 10 06:54:49 AM UTC 24 |
Oct 10 07:00:31 AM UTC 24 |
2835155048 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.83984137 |
|
|
Oct 10 06:53:13 AM UTC 24 |
Oct 10 07:00:38 AM UTC 24 |
3609093792 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.2593510113 |
|
|
Oct 10 06:17:35 AM UTC 24 |
Oct 10 07:00:57 AM UTC 24 |
10211889688 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.3794024822 |
|
|
Oct 10 06:56:55 AM UTC 24 |
Oct 10 07:01:13 AM UTC 24 |
2285667072 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.2566181770 |
|
|
Oct 10 06:50:22 AM UTC 24 |
Oct 10 07:01:23 AM UTC 24 |
5152435340 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.1024046351 |
|
|
Oct 10 06:54:05 AM UTC 24 |
Oct 10 07:01:23 AM UTC 24 |
3739293800 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.667868633 |
|
|
Oct 10 06:57:51 AM UTC 24 |
Oct 10 07:01:25 AM UTC 24 |
3081377132 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.242920848 |
|
|
Oct 10 06:57:29 AM UTC 24 |
Oct 10 07:01:27 AM UTC 24 |
3042747640 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.2949000033 |
|
|
Oct 10 06:57:30 AM UTC 24 |
Oct 10 07:02:01 AM UTC 24 |
2656492560 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.344848486 |
|
|
Oct 10 06:55:14 AM UTC 24 |
Oct 10 07:02:16 AM UTC 24 |
5565245876 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.3214688291 |
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Oct 10 06:58:05 AM UTC 24 |
Oct 10 07:02:16 AM UTC 24 |
2667716496 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2057256857 |
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Oct 10 05:55:32 AM UTC 24 |
Oct 10 07:03:10 AM UTC 24 |
20125399269 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.505547330 |
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Oct 10 06:56:30 AM UTC 24 |
Oct 10 07:04:50 AM UTC 24 |
5474503428 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2054663025 |
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|
Oct 10 06:45:11 AM UTC 24 |
Oct 10 07:05:00 AM UTC 24 |
5678198350 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1986155495 |
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Oct 10 06:23:29 AM UTC 24 |
Oct 10 07:05:19 AM UTC 24 |
26294603423 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.997288341 |
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Oct 10 07:02:59 AM UTC 24 |
Oct 10 07:05:28 AM UTC 24 |
3425594076 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3287713192 |
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Oct 10 06:35:18 AM UTC 24 |
Oct 10 07:06:54 AM UTC 24 |
26506533096 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.4122010990 |
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|
Oct 10 07:02:55 AM UTC 24 |
Oct 10 07:07:31 AM UTC 24 |
2922312348 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1658788504 |
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Oct 10 06:16:30 AM UTC 24 |
Oct 10 07:07:56 AM UTC 24 |
12239216000 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2890263796 |
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|
Oct 10 07:00:12 AM UTC 24 |
Oct 10 07:10:28 AM UTC 24 |
4128215458 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.776500383 |
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|
Oct 10 06:34:44 AM UTC 24 |
Oct 10 07:10:45 AM UTC 24 |
26721707260 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.2028361557 |
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|
Oct 10 07:02:37 AM UTC 24 |
Oct 10 07:11:14 AM UTC 24 |
6392796936 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.3834357605 |
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|
Oct 10 07:00:12 AM UTC 24 |
Oct 10 07:11:17 AM UTC 24 |
4406767192 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.623662474 |
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|
Oct 10 07:02:38 AM UTC 24 |
Oct 10 07:11:20 AM UTC 24 |
6416927190 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1782101447 |
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|
Oct 10 07:01:18 AM UTC 24 |
Oct 10 07:11:40 AM UTC 24 |
4232218264 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.2683236176 |
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|
Oct 10 06:59:03 AM UTC 24 |
Oct 10 07:11:55 AM UTC 24 |
4539273748 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.3268824622 |
|
|
Oct 10 06:58:27 AM UTC 24 |
Oct 10 07:12:02 AM UTC 24 |
4988421292 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.366487263 |
|
|
Oct 10 07:00:50 AM UTC 24 |
Oct 10 07:12:11 AM UTC 24 |
4216011166 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.1334676143 |
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|
Oct 10 06:44:49 AM UTC 24 |
Oct 10 07:12:23 AM UTC 24 |
5681945840 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3438193420 |
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|
Oct 10 07:02:58 AM UTC 24 |
Oct 10 07:12:59 AM UTC 24 |
4197899964 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.1773894741 |
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|
Oct 10 07:05:38 AM UTC 24 |
Oct 10 07:14:01 AM UTC 24 |
5278149990 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4112255068 |
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|
Oct 10 06:00:27 AM UTC 24 |
Oct 10 07:15:24 AM UTC 24 |
17086316268 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.2576218525 |
|
|
Oct 10 07:03:38 AM UTC 24 |
Oct 10 07:15:26 AM UTC 24 |
6442474918 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.617100765 |
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|
Oct 10 06:43:00 AM UTC 24 |
Oct 10 07:15:37 AM UTC 24 |
12491351509 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.2392619832 |
|
|
Oct 10 07:13:08 AM UTC 24 |
Oct 10 07:15:51 AM UTC 24 |
2906094859 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.2623252976 |
|
|
Oct 10 07:12:58 AM UTC 24 |
Oct 10 07:16:30 AM UTC 24 |
2725283565 ps |