| T2513 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2126746932 |
|
|
Oct 10 01:15:02 AM UTC 24 |
Oct 10 01:15:53 AM UTC 24 |
852532276 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3468918886 |
|
|
Oct 10 01:15:20 AM UTC 24 |
Oct 10 01:15:55 AM UTC 24 |
308304163 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.2012536799 |
|
|
Oct 10 01:15:47 AM UTC 24 |
Oct 10 01:15:57 AM UTC 24 |
45244801 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.2987963931 |
|
|
Oct 10 01:13:43 AM UTC 24 |
Oct 10 01:16:01 AM UTC 24 |
12745226368 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.650079395 |
|
|
Oct 10 01:15:52 AM UTC 24 |
Oct 10 01:16:02 AM UTC 24 |
46948986 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.2109830640 |
|
|
Oct 10 01:07:54 AM UTC 24 |
Oct 10 01:16:04 AM UTC 24 |
27453106666 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3859918121 |
|
|
Oct 10 01:15:00 AM UTC 24 |
Oct 10 01:16:06 AM UTC 24 |
2032956576 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.2509055381 |
|
|
Oct 10 01:15:18 AM UTC 24 |
Oct 10 01:16:15 AM UTC 24 |
1162705449 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1539936873 |
|
|
Oct 10 01:14:52 AM UTC 24 |
Oct 10 01:16:16 AM UTC 24 |
4873643310 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.172437406 |
|
|
Oct 10 01:16:13 AM UTC 24 |
Oct 10 01:16:24 AM UTC 24 |
37719402 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1752126022 |
|
|
Oct 10 01:15:14 AM UTC 24 |
Oct 10 01:16:27 AM UTC 24 |
2293059896 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.4229632716 |
|
|
Oct 10 01:11:21 AM UTC 24 |
Oct 10 01:16:31 AM UTC 24 |
30628930493 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.3820557791 |
|
|
Oct 10 01:14:51 AM UTC 24 |
Oct 10 01:16:57 AM UTC 24 |
9725182969 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3372310585 |
|
|
Oct 10 01:16:18 AM UTC 24 |
Oct 10 01:16:59 AM UTC 24 |
512105370 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3127685234 |
|
|
Oct 10 12:56:48 AM UTC 24 |
Oct 10 01:17:06 AM UTC 24 |
83131088425 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.905384904 |
|
|
Oct 10 01:12:56 AM UTC 24 |
Oct 10 01:17:06 AM UTC 24 |
3854395249 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2740627034 |
|
|
Oct 10 01:01:39 AM UTC 24 |
Oct 10 01:17:08 AM UTC 24 |
64891196149 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.581404954 |
|
|
Oct 10 01:08:44 AM UTC 24 |
Oct 10 01:17:10 AM UTC 24 |
13076149671 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2938931785 |
|
|
Oct 10 01:16:39 AM UTC 24 |
Oct 10 01:17:13 AM UTC 24 |
510797471 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.4069937864 |
|
|
Oct 10 01:16:29 AM UTC 24 |
Oct 10 01:17:27 AM UTC 24 |
1478631914 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.413630474 |
|
|
Oct 10 01:16:40 AM UTC 24 |
Oct 10 01:17:31 AM UTC 24 |
882676011 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.1205267661 |
|
|
Oct 10 01:16:28 AM UTC 24 |
Oct 10 01:17:34 AM UTC 24 |
1918676071 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.2647917742 |
|
|
Oct 10 01:17:24 AM UTC 24 |
Oct 10 01:17:38 AM UTC 24 |
200872735 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.4187585595 |
|
|
Oct 10 01:15:45 AM UTC 24 |
Oct 10 01:17:38 AM UTC 24 |
494717912 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1924022879 |
|
|
Oct 10 01:06:49 AM UTC 24 |
Oct 10 01:17:38 AM UTC 24 |
46298918225 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.185638394 |
|
|
Oct 10 01:17:31 AM UTC 24 |
Oct 10 01:17:42 AM UTC 24 |
52106032 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.970762835 |
|
|
Oct 10 01:16:08 AM UTC 24 |
Oct 10 01:17:43 AM UTC 24 |
4767884449 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.447126025 |
|
|
Oct 10 01:16:25 AM UTC 24 |
Oct 10 01:17:49 AM UTC 24 |
1749530965 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2087089622 |
|
|
Oct 10 01:15:55 AM UTC 24 |
Oct 10 01:17:49 AM UTC 24 |
7832156854 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.808549431 |
|
|
Oct 10 01:17:34 AM UTC 24 |
Oct 10 01:17:52 AM UTC 24 |
245276707 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.590890242 |
|
|
Oct 10 01:17:59 AM UTC 24 |
Oct 10 01:18:23 AM UTC 24 |
660611057 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1444870181 |
|
|
Oct 10 01:18:04 AM UTC 24 |
Oct 10 01:18:25 AM UTC 24 |
372360872 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.1317905076 |
|
|
Oct 10 01:18:00 AM UTC 24 |
Oct 10 01:18:30 AM UTC 24 |
545748427 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.2507104843 |
|
|
Oct 10 01:17:57 AM UTC 24 |
Oct 10 01:18:34 AM UTC 24 |
330929338 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1887297707 |
|
|
Oct 10 01:13:01 AM UTC 24 |
Oct 10 01:18:35 AM UTC 24 |
7237880919 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.213507439 |
|
|
Oct 10 01:18:01 AM UTC 24 |
Oct 10 01:18:39 AM UTC 24 |
586888959 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.2646635612 |
|
|
Oct 10 01:17:36 AM UTC 24 |
Oct 10 01:18:40 AM UTC 24 |
590338314 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.1532528551 |
|
|
Oct 10 01:07:16 AM UTC 24 |
Oct 10 01:18:45 AM UTC 24 |
17977108351 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1505018463 |
|
|
Oct 10 01:17:31 AM UTC 24 |
Oct 10 01:18:55 AM UTC 24 |
8289811688 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.1302926558 |
|
|
Oct 10 12:59:54 AM UTC 24 |
Oct 10 01:18:57 AM UTC 24 |
63183417545 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.3421689130 |
|
|
Oct 10 01:18:49 AM UTC 24 |
Oct 10 01:19:01 AM UTC 24 |
152967290 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.3290112076 |
|
|
Oct 10 01:12:34 AM UTC 24 |
Oct 10 01:19:02 AM UTC 24 |
28353569341 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.41646408 |
|
|
Oct 10 01:18:54 AM UTC 24 |
Oct 10 01:19:04 AM UTC 24 |
53320023 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.444511244 |
|
|
Oct 10 01:17:31 AM UTC 24 |
Oct 10 01:19:08 AM UTC 24 |
5116678748 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1527468038 |
|
|
Oct 10 01:18:15 AM UTC 24 |
Oct 10 01:19:15 AM UTC 24 |
1171333895 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.712621720 |
|
|
Oct 10 01:16:56 AM UTC 24 |
Oct 10 01:19:17 AM UTC 24 |
1609112368 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.3497509449 |
|
|
Oct 10 01:15:25 AM UTC 24 |
Oct 10 01:19:32 AM UTC 24 |
2447797075 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3160056196 |
|
|
Oct 10 12:40:13 AM UTC 24 |
Oct 10 01:19:53 AM UTC 24 |
141018110804 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.553009183 |
|
|
Oct 10 01:19:04 AM UTC 24 |
Oct 10 01:19:53 AM UTC 24 |
525441368 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3120742895 |
|
|
Oct 10 01:19:26 AM UTC 24 |
Oct 10 01:19:56 AM UTC 24 |
265646295 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2132158361 |
|
|
Oct 10 01:19:37 AM UTC 24 |
Oct 10 01:20:11 AM UTC 24 |
604739050 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3966822893 |
|
|
Oct 10 01:11:54 AM UTC 24 |
Oct 10 01:20:12 AM UTC 24 |
3172440376 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.1688104861 |
|
|
Oct 10 01:19:27 AM UTC 24 |
Oct 10 01:20:12 AM UTC 24 |
1383559666 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1018955707 |
|
|
Oct 10 01:18:57 AM UTC 24 |
Oct 10 01:20:13 AM UTC 24 |
4235559720 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1068224077 |
|
|
Oct 10 01:18:59 AM UTC 24 |
Oct 10 01:20:16 AM UTC 24 |
1774489140 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.1297643409 |
|
|
Oct 10 01:19:32 AM UTC 24 |
Oct 10 01:20:26 AM UTC 24 |
952624354 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1644941014 |
|
|
Oct 10 01:14:34 AM UTC 24 |
Oct 10 01:20:27 AM UTC 24 |
2656504237 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.2821536097 |
|
|
Oct 10 01:20:21 AM UTC 24 |
Oct 10 01:20:30 AM UTC 24 |
44576917 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.3295725118 |
|
|
Oct 10 01:06:46 AM UTC 24 |
Oct 10 01:20:35 AM UTC 24 |
77673350474 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.2041423089 |
|
|
Oct 10 01:18:56 AM UTC 24 |
Oct 10 01:20:38 AM UTC 24 |
8033523334 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3627421641 |
|
|
Oct 10 01:05:26 AM UTC 24 |
Oct 10 01:20:45 AM UTC 24 |
62501668082 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.2371629315 |
|
|
Oct 10 01:10:28 AM UTC 24 |
Oct 10 01:20:46 AM UTC 24 |
56986116349 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3593942784 |
|
|
Oct 10 01:20:36 AM UTC 24 |
Oct 10 01:20:46 AM UTC 24 |
47335769 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.621576075 |
|
|
Oct 10 01:15:33 AM UTC 24 |
Oct 10 01:20:55 AM UTC 24 |
8761324614 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2641362931 |
|
|
Oct 10 12:44:56 AM UTC 24 |
Oct 10 01:20:59 AM UTC 24 |
127536081492 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.716787281 |
|
|
Oct 10 01:19:19 AM UTC 24 |
Oct 10 01:21:01 AM UTC 24 |
925502529 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.602690673 |
|
|
Oct 10 01:21:01 AM UTC 24 |
Oct 10 01:21:39 AM UTC 24 |
857272281 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.2487612912 |
|
|
Oct 10 01:16:21 AM UTC 24 |
Oct 10 01:21:05 AM UTC 24 |
17360018113 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.55664493 |
|
|
Oct 10 01:20:40 AM UTC 24 |
Oct 10 01:21:15 AM UTC 24 |
342126434 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.3128860644 |
|
|
Oct 10 01:21:10 AM UTC 24 |
Oct 10 01:21:19 AM UTC 24 |
20068206 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.148121253 |
|
|
Oct 10 01:09:38 AM UTC 24 |
Oct 10 01:21:21 AM UTC 24 |
4561570895 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1160302411 |
|
|
Oct 10 12:52:50 AM UTC 24 |
Oct 10 01:21:33 AM UTC 24 |
104426068026 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2256424249 |
|
|
Oct 10 01:21:30 AM UTC 24 |
Oct 10 01:21:37 AM UTC 24 |
7773869 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1926178890 |
|
|
Oct 10 01:21:09 AM UTC 24 |
Oct 10 01:21:42 AM UTC 24 |
771545452 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.635363696 |
|
|
Oct 10 01:14:14 AM UTC 24 |
Oct 10 01:21:46 AM UTC 24 |
11761853670 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.406111566 |
|
|
Oct 10 01:20:38 AM UTC 24 |
Oct 10 01:21:47 AM UTC 24 |
2025719017 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2999443554 |
|
|
Oct 10 01:21:40 AM UTC 24 |
Oct 10 01:21:52 AM UTC 24 |
58209383 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.2821020226 |
|
|
Oct 10 01:12:58 AM UTC 24 |
Oct 10 01:21:52 AM UTC 24 |
16416492539 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.2963528259 |
|
|
Oct 10 01:21:39 AM UTC 24 |
Oct 10 01:21:54 AM UTC 24 |
239894611 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2057180251 |
|
|
Oct 10 01:16:52 AM UTC 24 |
Oct 10 01:22:02 AM UTC 24 |
5403579093 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.1653397844 |
|
|
Oct 10 01:21:08 AM UTC 24 |
Oct 10 01:22:08 AM UTC 24 |
535319665 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4293451925 |
|
|
Oct 10 01:18:00 AM UTC 24 |
Oct 10 01:22:28 AM UTC 24 |
18732413422 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3579008610 |
|
|
Oct 10 01:20:18 AM UTC 24 |
Oct 10 01:22:29 AM UTC 24 |
375649861 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1455604130 |
|
|
Oct 10 01:18:14 AM UTC 24 |
Oct 10 01:22:30 AM UTC 24 |
5897924983 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.4192698452 |
|
|
Oct 10 01:07:54 AM UTC 24 |
Oct 10 01:22:35 AM UTC 24 |
71409247238 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.468893209 |
|
|
Oct 10 01:11:43 AM UTC 24 |
Oct 10 01:22:37 AM UTC 24 |
40764212054 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.354338166 |
|
|
Oct 10 01:22:33 AM UTC 24 |
Oct 10 01:22:45 AM UTC 24 |
38412896 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1895629965 |
|
|
Oct 10 01:19:57 AM UTC 24 |
Oct 10 01:22:45 AM UTC 24 |
251475400 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.3379740388 |
|
|
Oct 10 01:20:37 AM UTC 24 |
Oct 10 01:22:45 AM UTC 24 |
10014034533 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3088380040 |
|
|
Oct 10 01:20:37 AM UTC 24 |
Oct 10 01:22:46 AM UTC 24 |
5916566536 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2813342610 |
|
|
Oct 10 01:18:47 AM UTC 24 |
Oct 10 01:22:49 AM UTC 24 |
515957484 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.1148051234 |
|
|
Oct 10 01:22:16 AM UTC 24 |
Oct 10 01:22:50 AM UTC 24 |
673366704 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.3022328903 |
|
|
Oct 10 01:22:02 AM UTC 24 |
Oct 10 01:22:53 AM UTC 24 |
543183628 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.4216321710 |
|
|
Oct 10 01:20:54 AM UTC 24 |
Oct 10 01:22:56 AM UTC 24 |
2891353658 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1993968465 |
|
|
Oct 10 01:19:39 AM UTC 24 |
Oct 10 01:22:59 AM UTC 24 |
2000506594 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3498432704 |
|
|
Oct 10 01:22:24 AM UTC 24 |
Oct 10 01:23:04 AM UTC 24 |
294271283 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1005627078 |
|
|
Oct 10 01:09:25 AM UTC 24 |
Oct 10 01:23:05 AM UTC 24 |
55660357871 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.1466552132 |
|
|
Oct 10 01:22:59 AM UTC 24 |
Oct 10 01:23:07 AM UTC 24 |
43873071 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.3657043653 |
|
|
Oct 10 01:20:18 AM UTC 24 |
Oct 10 01:23:16 AM UTC 24 |
4360669215 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.361251891 |
|
|
Oct 10 01:23:09 AM UTC 24 |
Oct 10 01:23:17 AM UTC 24 |
38607269 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1285051005 |
|
|
Oct 10 01:21:44 AM UTC 24 |
Oct 10 01:23:19 AM UTC 24 |
8156797688 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2516737038 |
|
|
Oct 10 01:23:09 AM UTC 24 |
Oct 10 01:23:20 AM UTC 24 |
39784858 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3711015305 |
|
|
Oct 10 01:21:57 AM UTC 24 |
Oct 10 01:23:21 AM UTC 24 |
5400759936 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.1417924718 |
|
|
Oct 10 01:22:01 AM UTC 24 |
Oct 10 01:23:24 AM UTC 24 |
1863915257 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2746473033 |
|
|
Oct 10 01:17:22 AM UTC 24 |
Oct 10 01:23:25 AM UTC 24 |
8031718294 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.4199331763 |
|
|
Oct 10 01:23:19 AM UTC 24 |
Oct 10 01:23:29 AM UTC 24 |
16555393 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3473085494 |
|
|
Oct 10 01:22:16 AM UTC 24 |
Oct 10 01:23:30 AM UTC 24 |
1509279926 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1220869994 |
|
|
Oct 10 01:14:24 AM UTC 24 |
Oct 10 01:23:32 AM UTC 24 |
8423153632 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.4271973343 |
|
|
Oct 10 01:23:27 AM UTC 24 |
Oct 10 01:23:34 AM UTC 24 |
39157444 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.1532583140 |
|
|
Oct 10 01:22:54 AM UTC 24 |
Oct 10 01:23:38 AM UTC 24 |
482447708 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.92160131 |
|
|
Oct 10 01:10:32 AM UTC 24 |
Oct 10 01:23:39 AM UTC 24 |
51459657982 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3021307231 |
|
|
Oct 10 01:23:30 AM UTC 24 |
Oct 10 01:23:39 AM UTC 24 |
100701004 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.2304554235 |
|
|
Oct 10 01:11:54 AM UTC 24 |
Oct 10 01:23:41 AM UTC 24 |
15816551165 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.456061297 |
|
|
Oct 10 01:23:03 AM UTC 24 |
Oct 10 01:23:45 AM UTC 24 |
2917063157 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.2687645231 |
|
|
Oct 10 01:23:12 AM UTC 24 |
Oct 10 01:23:55 AM UTC 24 |
520653867 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1666434463 |
|
|
Oct 10 01:23:35 AM UTC 24 |
Oct 10 01:23:56 AM UTC 24 |
284172913 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.858705947 |
|
|
Oct 10 01:23:46 AM UTC 24 |
Oct 10 01:23:57 AM UTC 24 |
229123603 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1948744638 |
|
|
Oct 10 01:23:46 AM UTC 24 |
Oct 10 01:23:57 AM UTC 24 |
52456159 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1636857961 |
|
|
Oct 10 01:23:53 AM UTC 24 |
Oct 10 01:24:07 AM UTC 24 |
149787251 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.3080643973 |
|
|
Oct 10 01:22:11 AM UTC 24 |
Oct 10 01:24:09 AM UTC 24 |
2521625785 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.2774982505 |
|
|
Oct 10 01:17:52 AM UTC 24 |
Oct 10 01:24:10 AM UTC 24 |
17888214547 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3854144463 |
|
|
Oct 10 01:23:58 AM UTC 24 |
Oct 10 01:24:24 AM UTC 24 |
246461776 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.389461393 |
|
|
Oct 10 01:24:16 AM UTC 24 |
Oct 10 01:24:27 AM UTC 24 |
85750653 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.2613601361 |
|
|
Oct 10 01:23:26 AM UTC 24 |
Oct 10 01:24:32 AM UTC 24 |
2203853347 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3792837839 |
|
|
Oct 10 01:24:20 AM UTC 24 |
Oct 10 01:24:38 AM UTC 24 |
97220321 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.439542666 |
|
|
Oct 10 01:04:08 AM UTC 24 |
Oct 10 01:24:39 AM UTC 24 |
83866911364 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3134445924 |
|
|
Oct 10 01:21:19 AM UTC 24 |
Oct 10 01:24:45 AM UTC 24 |
5452652433 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.1021400517 |
|
|
Oct 10 01:24:07 AM UTC 24 |
Oct 10 01:24:48 AM UTC 24 |
1196898714 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3128975538 |
|
|
Oct 10 01:24:17 AM UTC 24 |
Oct 10 01:24:51 AM UTC 24 |
379299763 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.2398362821 |
|
|
Oct 10 01:24:47 AM UTC 24 |
Oct 10 01:25:02 AM UTC 24 |
199530904 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2784336077 |
|
|
Oct 10 01:24:51 AM UTC 24 |
Oct 10 01:25:02 AM UTC 24 |
46380520 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2064122305 |
|
|
Oct 10 01:23:50 AM UTC 24 |
Oct 10 01:25:07 AM UTC 24 |
5615626654 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3829873222 |
|
|
Oct 10 01:15:01 AM UTC 24 |
Oct 10 01:25:08 AM UTC 24 |
36284853949 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1606209287 |
|
|
Oct 10 01:23:43 AM UTC 24 |
Oct 10 01:25:13 AM UTC 24 |
65911010 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.4035569457 |
|
|
Oct 10 01:21:24 AM UTC 24 |
Oct 10 01:25:18 AM UTC 24 |
2632611389 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.1187750612 |
|
|
Oct 10 01:23:50 AM UTC 24 |
Oct 10 01:25:20 AM UTC 24 |
8025757737 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.889541062 |
|
|
Oct 10 01:23:09 AM UTC 24 |
Oct 10 01:25:26 AM UTC 24 |
10263120512 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.2337779220 |
|
|
Oct 10 01:25:11 AM UTC 24 |
Oct 10 01:25:27 AM UTC 24 |
100236040 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.463396641 |
|
|
Oct 10 01:25:03 AM UTC 24 |
Oct 10 01:25:32 AM UTC 24 |
606368744 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2561631222 |
|
|
Oct 10 01:16:47 AM UTC 24 |
Oct 10 01:25:33 AM UTC 24 |
14807763976 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.1997411345 |
|
|
Oct 10 01:24:01 AM UTC 24 |
Oct 10 01:25:35 AM UTC 24 |
6473822179 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.3448620235 |
|
|
Oct 10 01:24:02 AM UTC 24 |
Oct 10 01:25:44 AM UTC 24 |
2536443660 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.2069713478 |
|
|
Oct 10 01:23:43 AM UTC 24 |
Oct 10 01:25:50 AM UTC 24 |
1586392508 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.195074311 |
|
|
Oct 10 01:25:24 AM UTC 24 |
Oct 10 01:25:51 AM UTC 24 |
331313635 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.4089369948 |
|
|
Oct 10 01:25:35 AM UTC 24 |
Oct 10 01:25:51 AM UTC 24 |
72445075 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.1723097965 |
|
|
Oct 10 01:23:41 AM UTC 24 |
Oct 10 01:26:03 AM UTC 24 |
1683162513 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.404360591 |
|
|
Oct 10 01:25:55 AM UTC 24 |
Oct 10 01:26:03 AM UTC 24 |
163527554 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2507178174 |
|
|
Oct 10 01:25:59 AM UTC 24 |
Oct 10 01:26:07 AM UTC 24 |
42505546 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2613761049 |
|
|
Oct 10 01:15:32 AM UTC 24 |
Oct 10 01:26:10 AM UTC 24 |
3678407940 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.4050755603 |
|
|
Oct 10 12:43:31 AM UTC 24 |
Oct 10 01:26:17 AM UTC 24 |
157619280648 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.1299499457 |
|
|
Oct 10 01:22:08 AM UTC 24 |
Oct 10 01:26:18 AM UTC 24 |
15182706192 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.374800003 |
|
|
Oct 10 01:22:49 AM UTC 24 |
Oct 10 01:26:18 AM UTC 24 |
663715170 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.9525656 |
|
|
Oct 10 01:25:31 AM UTC 24 |
Oct 10 01:26:19 AM UTC 24 |
1639431117 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2039775300 |
|
|
Oct 10 01:25:42 AM UTC 24 |
Oct 10 01:26:20 AM UTC 24 |
730777712 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1025712659 |
|
|
Oct 10 01:25:03 AM UTC 24 |
Oct 10 01:26:23 AM UTC 24 |
3998529943 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.193171195 |
|
|
Oct 10 01:20:51 AM UTC 24 |
Oct 10 01:26:24 AM UTC 24 |
21065338612 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3885298292 |
|
|
Oct 10 01:25:33 AM UTC 24 |
Oct 10 01:26:25 AM UTC 24 |
468204752 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2212684848 |
|
|
Oct 10 01:24:27 AM UTC 24 |
Oct 10 01:26:26 AM UTC 24 |
707258023 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.1253622014 |
|
|
Oct 10 01:24:56 AM UTC 24 |
Oct 10 01:26:31 AM UTC 24 |
7888858080 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.4163081309 |
|
|
Oct 10 01:26:15 AM UTC 24 |
Oct 10 01:26:51 AM UTC 24 |
1049531964 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.3351839367 |
|
|
Oct 10 01:26:27 AM UTC 24 |
Oct 10 01:26:52 AM UTC 24 |
354288749 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.92675283 |
|
|
Oct 10 01:26:42 AM UTC 24 |
Oct 10 01:26:57 AM UTC 24 |
79091598 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.2473372462 |
|
|
Oct 10 01:26:48 AM UTC 24 |
Oct 10 01:26:58 AM UTC 24 |
47922656 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3719031733 |
|
|
Oct 10 01:08:02 AM UTC 24 |
Oct 10 01:27:02 AM UTC 24 |
76421227098 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1195407064 |
|
|
Oct 10 01:26:54 AM UTC 24 |
Oct 10 01:27:05 AM UTC 24 |
54949472 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2318826573 |
|
|
Oct 10 01:26:39 AM UTC 24 |
Oct 10 01:27:05 AM UTC 24 |
394730957 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1104895701 |
|
|
Oct 10 01:26:25 AM UTC 24 |
Oct 10 01:27:07 AM UTC 24 |
2744032480 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1883584872 |
|
|
Oct 10 01:26:15 AM UTC 24 |
Oct 10 01:27:09 AM UTC 24 |
479328478 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.1664118096 |
|
|
Oct 10 01:19:07 AM UTC 24 |
Oct 10 01:27:12 AM UTC 24 |
42564919232 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.1817699811 |
|
|
Oct 10 01:26:08 AM UTC 24 |
Oct 10 01:27:22 AM UTC 24 |
6600711415 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.2600555853 |
|
|
Oct 10 01:26:40 AM UTC 24 |
Oct 10 01:27:23 AM UTC 24 |
596052749 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.4263086416 |
|
|
Oct 10 01:26:13 AM UTC 24 |
Oct 10 01:27:29 AM UTC 24 |
4240186100 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.3961820353 |
|
|
Oct 10 01:27:18 AM UTC 24 |
Oct 10 01:27:33 AM UTC 24 |
95937142 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1467027250 |
|
|
Oct 10 01:27:22 AM UTC 24 |
Oct 10 01:27:39 AM UTC 24 |
160564588 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.505291265 |
|
|
Oct 10 01:26:37 AM UTC 24 |
Oct 10 01:27:40 AM UTC 24 |
2112013935 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.512980225 |
|
|
Oct 10 01:25:50 AM UTC 24 |
Oct 10 01:27:43 AM UTC 24 |
791866031 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.2828917430 |
|
|
Oct 10 01:24:16 AM UTC 24 |
Oct 10 01:27:59 AM UTC 24 |
6965308849 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3419685282 |
|
|
Oct 10 01:24:30 AM UTC 24 |
Oct 10 01:28:01 AM UTC 24 |
650135327 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.73559823 |
|
|
Oct 10 01:24:29 AM UTC 24 |
Oct 10 01:28:03 AM UTC 24 |
2791044353 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2944843010 |
|
|
Oct 10 01:27:15 AM UTC 24 |
Oct 10 01:28:03 AM UTC 24 |
4597218044 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.13249025 |
|
|
Oct 10 01:23:11 AM UTC 24 |
Oct 10 01:28:12 AM UTC 24 |
25400308868 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1332663780 |
|
|
Oct 10 01:28:06 AM UTC 24 |
Oct 10 01:28:16 AM UTC 24 |
254946651 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1275712218 |
|
|
Oct 10 01:27:17 AM UTC 24 |
Oct 10 01:28:21 AM UTC 24 |
3783306406 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.4039034156 |
|
|
Oct 10 01:27:47 AM UTC 24 |
Oct 10 01:28:24 AM UTC 24 |
227939427 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.2244701401 |
|
|
Oct 10 01:27:46 AM UTC 24 |
Oct 10 01:28:24 AM UTC 24 |
288343885 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.1507657858 |
|
|
Oct 10 01:27:31 AM UTC 24 |
Oct 10 01:28:30 AM UTC 24 |
1634812451 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.175931588 |
|
|
Oct 10 01:28:24 AM UTC 24 |
Oct 10 01:28:31 AM UTC 24 |
46159463 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.1798827985 |
|
|
Oct 10 01:27:29 AM UTC 24 |
Oct 10 01:28:44 AM UTC 24 |
887263418 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1167915957 |
|
|
Oct 10 01:18:10 AM UTC 24 |
Oct 10 01:28:55 AM UTC 24 |
7475453635 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.157062529 |
|
|
Oct 10 01:27:35 AM UTC 24 |
Oct 10 01:28:57 AM UTC 24 |
1637885572 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.1006147815 |
|
|
Oct 10 01:28:47 AM UTC 24 |
Oct 10 01:28:58 AM UTC 24 |
253388929 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.1452089917 |
|
|
Oct 10 01:12:27 AM UTC 24 |
Oct 10 01:29:01 AM UTC 24 |
89292814695 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.3331520704 |
|
|
Oct 10 01:26:45 AM UTC 24 |
Oct 10 01:29:09 AM UTC 24 |
1872694278 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.622063625 |
|
|
Oct 10 01:25:51 AM UTC 24 |
Oct 10 01:29:09 AM UTC 24 |
2354947837 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.907377899 |
|
|
Oct 10 01:28:55 AM UTC 24 |
Oct 10 01:29:11 AM UTC 24 |
280665603 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.3224879433 |
|
|
Oct 10 01:28:54 AM UTC 24 |
Oct 10 01:29:28 AM UTC 24 |
1155854610 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3989069564 |
|
|
Oct 10 01:26:40 AM UTC 24 |
Oct 10 01:29:29 AM UTC 24 |
2047935365 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1767246792 |
|
|
Oct 10 01:28:34 AM UTC 24 |
Oct 10 01:29:33 AM UTC 24 |
572584324 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.689469479 |
|
|
Oct 10 01:29:33 AM UTC 24 |
Oct 10 01:29:40 AM UTC 24 |
40503021 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2059664804 |
|
|
Oct 10 01:29:35 AM UTC 24 |
Oct 10 01:29:46 AM UTC 24 |
49468992 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.3450503947 |
|
|
Oct 10 01:22:51 AM UTC 24 |
Oct 10 01:29:47 AM UTC 24 |
12064620418 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3038611188 |
|
|
Oct 10 01:25:54 AM UTC 24 |
Oct 10 01:29:47 AM UTC 24 |
3066823052 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1102088206 |
|
|
Oct 10 01:29:19 AM UTC 24 |
Oct 10 01:29:53 AM UTC 24 |
725696803 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.927571016 |
|
|
Oct 10 01:24:02 AM UTC 24 |
Oct 10 01:29:54 AM UTC 24 |
32816095137 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.661520871 |
|
|
Oct 10 01:28:27 AM UTC 24 |
Oct 10 01:29:56 AM UTC 24 |
2544427795 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.804915294 |
|
|
Oct 10 01:23:13 AM UTC 24 |
Oct 10 01:30:00 AM UTC 24 |
28901836168 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1792480443 |
|
|
Oct 10 12:59:11 AM UTC 24 |
Oct 10 01:30:06 AM UTC 24 |
107949575067 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.297842440 |
|
|
Oct 10 01:29:04 AM UTC 24 |
Oct 10 01:30:12 AM UTC 24 |
1258368506 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.4152433458 |
|
|
Oct 10 01:30:04 AM UTC 24 |
Oct 10 01:30:15 AM UTC 24 |
76590514 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2785620674 |
|
|
Oct 10 01:28:45 AM UTC 24 |
Oct 10 01:30:16 AM UTC 24 |
6334630887 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.3493130952 |
|
|
Oct 10 01:30:24 AM UTC 24 |
Oct 10 01:30:33 AM UTC 24 |
18599750 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2972658658 |
|
|
Oct 10 01:29:32 AM UTC 24 |
Oct 10 01:30:35 AM UTC 24 |
186489724 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.1212886131 |
|
|
Oct 10 01:28:26 AM UTC 24 |
Oct 10 01:30:38 AM UTC 24 |
9576078002 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3452881044 |
|
|
Oct 10 01:30:16 AM UTC 24 |
Oct 10 01:30:46 AM UTC 24 |
247237011 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.3439381826 |
|
|
Oct 10 01:29:58 AM UTC 24 |
Oct 10 01:30:54 AM UTC 24 |
1672669706 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1808727108 |
|
|
Oct 10 01:23:39 AM UTC 24 |
Oct 10 01:30:55 AM UTC 24 |
8015420858 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.334154013 |
|
|
Oct 10 01:28:28 AM UTC 24 |
Oct 10 01:30:57 AM UTC 24 |
6443585576 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.3338315129 |
|
|
Oct 10 01:30:12 AM UTC 24 |
Oct 10 01:31:04 AM UTC 24 |
819621804 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1211494084 |
|
|
Oct 10 01:27:57 AM UTC 24 |
Oct 10 01:31:05 AM UTC 24 |
5367636197 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.1578636268 |
|
|
Oct 10 01:30:58 AM UTC 24 |
Oct 10 01:31:07 AM UTC 24 |
57949300 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2020552318 |
|
|
Oct 10 01:31:02 AM UTC 24 |
Oct 10 01:31:13 AM UTC 24 |
39287724 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3076039737 |
|
|
Oct 10 01:30:31 AM UTC 24 |
Oct 10 01:31:21 AM UTC 24 |
1360752136 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.964466947 |
|
|
Oct 10 01:29:50 AM UTC 24 |
Oct 10 01:31:27 AM UTC 24 |
5827642216 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.238696229 |
|
|
Oct 10 01:29:50 AM UTC 24 |
Oct 10 01:31:34 AM UTC 24 |
8860264328 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.1453477626 |
|
|
Oct 10 01:13:46 AM UTC 24 |
Oct 10 01:31:44 AM UTC 24 |
69873736548 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.1466784266 |
|
|
Oct 10 01:29:23 AM UTC 24 |
Oct 10 01:31:45 AM UTC 24 |
3040646386 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3861316873 |
|
|
Oct 10 01:19:26 AM UTC 24 |
Oct 10 01:31:53 AM UTC 24 |
42287978113 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3687683650 |
|
|
Oct 10 01:31:21 AM UTC 24 |
Oct 10 01:31:57 AM UTC 24 |
437085213 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.1505675149 |
|
|
Oct 10 01:31:32 AM UTC 24 |
Oct 10 01:32:01 AM UTC 24 |
312258449 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.112412567 |
|
|
Oct 10 01:31:47 AM UTC 24 |
Oct 10 01:32:10 AM UTC 24 |
228529491 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.3042942927 |
|
|
Oct 10 01:30:17 AM UTC 24 |
Oct 10 01:32:11 AM UTC 24 |
2650427803 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2957195807 |
|
|
Oct 10 01:30:40 AM UTC 24 |
Oct 10 01:32:22 AM UTC 24 |
202341215 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2195632867 |
|
|
Oct 10 01:22:59 AM UTC 24 |
Oct 10 01:32:26 AM UTC 24 |
3711267404 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2333628248 |
|
|
Oct 10 01:31:20 AM UTC 24 |
Oct 10 01:32:30 AM UTC 24 |
1584626689 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.222344763 |
|
|
Oct 10 01:31:50 AM UTC 24 |
Oct 10 01:32:31 AM UTC 24 |
480482902 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.1333851695 |
|
|
Oct 10 01:31:57 AM UTC 24 |
Oct 10 01:32:34 AM UTC 24 |
558953494 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3910572767 |
|
|
Oct 10 01:29:18 AM UTC 24 |
Oct 10 01:32:41 AM UTC 24 |
3892510554 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.1711932107 |
|
|
Oct 10 01:32:32 AM UTC 24 |
Oct 10 01:32:42 AM UTC 24 |
54163835 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.689526432 |
|
|
Oct 10 01:28:00 AM UTC 24 |
Oct 10 01:32:43 AM UTC 24 |
2811450461 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.3376191788 |
|
|
Oct 10 01:27:25 AM UTC 24 |
Oct 10 01:32:44 AM UTC 24 |
21167573052 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2683172965 |
|
|
Oct 10 01:32:37 AM UTC 24 |
Oct 10 01:32:46 AM UTC 24 |
45147419 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.166884478 |
|
|
Oct 10 01:27:51 AM UTC 24 |
Oct 10 01:32:48 AM UTC 24 |
8503119432 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1863124006 |
|
|
Oct 10 01:32:26 AM UTC 24 |
Oct 10 01:32:48 AM UTC 24 |
90907859 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.845643430 |
|
|
Oct 10 01:30:57 AM UTC 24 |
Oct 10 01:32:51 AM UTC 24 |
159660848 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1933937869 |
|
|
Oct 10 01:32:09 AM UTC 24 |
Oct 10 01:32:55 AM UTC 24 |
909852247 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3238151614 |
|
|
Oct 10 01:21:21 AM UTC 24 |
Oct 10 01:33:00 AM UTC 24 |
4132145604 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1822978489 |
|
|
Oct 10 01:32:55 AM UTC 24 |
Oct 10 01:33:16 AM UTC 24 |
142230760 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.725104755 |
|
|
Oct 10 01:33:04 AM UTC 24 |
Oct 10 01:33:17 AM UTC 24 |
119743237 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1111526776 |
|
|
Oct 10 01:31:09 AM UTC 24 |
Oct 10 01:33:19 AM UTC 24 |
8130133881 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.867854196 |
|
|
Oct 10 01:31:17 AM UTC 24 |
Oct 10 01:33:20 AM UTC 24 |
6183783988 ps |