| T1783 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3892431726 |
|
|
Oct 09 11:47:15 PM UTC 24 |
Oct 10 12:23:34 AM UTC 24 |
17023072811 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.74714083 |
|
|
Oct 09 11:43:43 PM UTC 24 |
Oct 10 12:23:35 AM UTC 24 |
131576994828 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1985729667 |
|
|
Oct 10 12:22:06 AM UTC 24 |
Oct 10 12:23:37 AM UTC 24 |
4717047689 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.2209991834 |
|
|
Oct 10 12:22:06 AM UTC 24 |
Oct 10 12:23:41 AM UTC 24 |
7925426145 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2073390485 |
|
|
Oct 10 12:21:32 AM UTC 24 |
Oct 10 12:23:43 AM UTC 24 |
315452030 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3548451572 |
|
|
Oct 10 12:22:53 AM UTC 24 |
Oct 10 12:23:49 AM UTC 24 |
536383459 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.3680991772 |
|
|
Oct 10 12:21:11 AM UTC 24 |
Oct 10 12:23:55 AM UTC 24 |
1527785536 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.15011138 |
|
|
Oct 09 11:17:51 PM UTC 24 |
Oct 10 12:24:11 AM UTC 24 |
28872320676 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.2152980605 |
|
|
Oct 10 12:23:58 AM UTC 24 |
Oct 10 12:24:12 AM UTC 24 |
213253800 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.442379017 |
|
|
Oct 10 12:23:59 AM UTC 24 |
Oct 10 12:24:14 AM UTC 24 |
298503480 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.433175186 |
|
|
Oct 10 12:23:56 AM UTC 24 |
Oct 10 12:24:15 AM UTC 24 |
126767439 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2439265436 |
|
|
Oct 10 12:03:45 AM UTC 24 |
Oct 10 12:24:19 AM UTC 24 |
73423832006 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.3884392382 |
|
|
Oct 10 12:23:39 AM UTC 24 |
Oct 10 12:24:28 AM UTC 24 |
1424237527 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3783656707 |
|
|
Oct 10 12:21:39 AM UTC 24 |
Oct 10 12:24:30 AM UTC 24 |
372031660 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.666428945 |
|
|
Oct 10 12:20:37 AM UTC 24 |
Oct 10 12:24:34 AM UTC 24 |
18764435305 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.1951318087 |
|
|
Oct 10 12:23:46 AM UTC 24 |
Oct 10 12:24:38 AM UTC 24 |
470794005 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.1192515589 |
|
|
Oct 10 12:23:20 AM UTC 24 |
Oct 10 12:24:38 AM UTC 24 |
6620608584 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.2988837630 |
|
|
Oct 10 12:24:35 AM UTC 24 |
Oct 10 12:24:45 AM UTC 24 |
211091857 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3705791857 |
|
|
Oct 10 12:24:35 AM UTC 24 |
Oct 10 12:24:46 AM UTC 24 |
47063222 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.3778093096 |
|
|
Oct 10 12:22:41 AM UTC 24 |
Oct 10 12:24:46 AM UTC 24 |
1048780440 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4275843718 |
|
|
Oct 10 12:10:31 AM UTC 24 |
Oct 10 12:24:49 AM UTC 24 |
51744305426 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4243257853 |
|
|
Oct 10 12:24:02 AM UTC 24 |
Oct 10 12:24:58 AM UTC 24 |
996645221 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.631376140 |
|
|
Oct 10 12:23:53 AM UTC 24 |
Oct 10 12:25:15 AM UTC 24 |
1058010798 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3090111444 |
|
|
Oct 10 12:23:34 AM UTC 24 |
Oct 10 12:25:22 AM UTC 24 |
4486298726 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.67017211 |
|
|
Oct 10 12:25:07 AM UTC 24 |
Oct 10 12:25:23 AM UTC 24 |
61661292 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.3157594805 |
|
|
Oct 10 12:24:51 AM UTC 24 |
Oct 10 12:25:28 AM UTC 24 |
273061638 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.3907558823 |
|
|
Oct 10 12:24:42 AM UTC 24 |
Oct 10 12:25:31 AM UTC 24 |
518855809 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3863950468 |
|
|
Oct 10 12:24:07 AM UTC 24 |
Oct 10 12:25:32 AM UTC 24 |
297987922 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.3816289585 |
|
|
Oct 10 12:18:11 AM UTC 24 |
Oct 10 12:25:35 AM UTC 24 |
9711062551 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.945013699 |
|
|
Oct 10 12:25:13 AM UTC 24 |
Oct 10 12:25:39 AM UTC 24 |
491355276 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.640484919 |
|
|
Oct 10 12:18:06 AM UTC 24 |
Oct 10 12:25:53 AM UTC 24 |
3474550296 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1903363553 |
|
|
Oct 10 12:20:19 AM UTC 24 |
Oct 10 12:25:57 AM UTC 24 |
807681372 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4206697419 |
|
|
Oct 10 12:25:51 AM UTC 24 |
Oct 10 12:26:00 AM UTC 24 |
34611117 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2897126132 |
|
|
Oct 10 12:22:12 AM UTC 24 |
Oct 10 12:26:01 AM UTC 24 |
20052682493 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.213939889 |
|
|
Oct 10 12:12:07 AM UTC 24 |
Oct 10 12:26:03 AM UTC 24 |
82301884545 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.983731047 |
|
|
Oct 10 12:25:52 AM UTC 24 |
Oct 10 12:26:05 AM UTC 24 |
157924805 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.417603285 |
|
|
Oct 10 12:22:47 AM UTC 24 |
Oct 10 12:26:08 AM UTC 24 |
3443628825 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2742515861 |
|
|
Oct 10 12:24:38 AM UTC 24 |
Oct 10 12:26:11 AM UTC 24 |
4614389392 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.1460101633 |
|
|
Oct 10 12:09:45 AM UTC 24 |
Oct 10 12:26:13 AM UTC 24 |
23200133216 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.592676125 |
|
|
Oct 10 12:23:04 AM UTC 24 |
Oct 10 12:26:13 AM UTC 24 |
4023823783 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.4277853579 |
|
|
Oct 10 12:25:38 AM UTC 24 |
Oct 10 12:26:17 AM UTC 24 |
30264488 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.1928699292 |
|
|
Oct 10 12:24:34 AM UTC 24 |
Oct 10 12:26:19 AM UTC 24 |
9706972271 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.3778420379 |
|
|
Oct 10 12:25:09 AM UTC 24 |
Oct 10 12:26:19 AM UTC 24 |
1874631431 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3771959126 |
|
|
Oct 10 12:25:09 AM UTC 24 |
Oct 10 12:26:24 AM UTC 24 |
1841256134 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.2930159736 |
|
|
Oct 10 12:26:02 AM UTC 24 |
Oct 10 12:26:26 AM UTC 24 |
432709019 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.854282926 |
|
|
Oct 10 12:24:04 AM UTC 24 |
Oct 10 12:26:27 AM UTC 24 |
3730462930 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.2293705035 |
|
|
Oct 09 11:04:33 PM UTC 24 |
Oct 10 12:26:27 AM UTC 24 |
27239070168 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.1549482183 |
|
|
Oct 10 12:26:17 AM UTC 24 |
Oct 10 12:26:27 AM UTC 24 |
33804054 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.542680050 |
|
|
Oct 10 12:25:02 AM UTC 24 |
Oct 10 12:26:48 AM UTC 24 |
2138384038 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2684155429 |
|
|
Oct 10 12:26:30 AM UTC 24 |
Oct 10 12:26:57 AM UTC 24 |
453584438 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.761953741 |
|
|
Oct 10 12:26:46 AM UTC 24 |
Oct 10 12:26:58 AM UTC 24 |
161789479 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.156433542 |
|
|
Oct 10 12:26:48 AM UTC 24 |
Oct 10 12:26:59 AM UTC 24 |
40147723 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2797991594 |
|
|
Oct 10 12:25:57 AM UTC 24 |
Oct 10 12:27:00 AM UTC 24 |
4034946687 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.3537416260 |
|
|
Oct 10 12:26:26 AM UTC 24 |
Oct 10 12:27:08 AM UTC 24 |
1220178902 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3649952225 |
|
|
Oct 10 12:25:51 AM UTC 24 |
Oct 10 12:27:21 AM UTC 24 |
8906500855 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2128861870 |
|
|
Oct 09 11:48:55 PM UTC 24 |
Oct 10 12:27:21 AM UTC 24 |
146247547497 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.944951315 |
|
|
Oct 10 12:24:57 AM UTC 24 |
Oct 10 12:27:22 AM UTC 24 |
9608588092 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.1146570065 |
|
|
Oct 10 12:26:22 AM UTC 24 |
Oct 10 12:27:24 AM UTC 24 |
724258721 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3637409075 |
|
|
Oct 10 12:26:50 AM UTC 24 |
Oct 10 12:27:28 AM UTC 24 |
792281003 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2417166844 |
|
|
Oct 10 12:25:00 AM UTC 24 |
Oct 10 12:27:32 AM UTC 24 |
9029439821 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.885562574 |
|
|
Oct 10 12:26:31 AM UTC 24 |
Oct 10 12:27:35 AM UTC 24 |
1416853227 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1351145561 |
|
|
Oct 10 12:26:34 AM UTC 24 |
Oct 10 12:27:35 AM UTC 24 |
1113679402 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.4185585065 |
|
|
Oct 10 12:13:47 AM UTC 24 |
Oct 10 12:27:50 AM UTC 24 |
50317271870 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.2982309524 |
|
|
Oct 10 12:12:13 AM UTC 24 |
Oct 10 12:28:02 AM UTC 24 |
56007404355 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.744025671 |
|
|
Oct 10 12:27:12 AM UTC 24 |
Oct 10 12:28:04 AM UTC 24 |
389048210 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.2240326224 |
|
|
Oct 10 12:26:48 AM UTC 24 |
Oct 10 12:28:13 AM UTC 24 |
8307659801 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.147311057 |
|
|
Oct 10 12:27:59 AM UTC 24 |
Oct 10 12:28:14 AM UTC 24 |
214215919 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1356201518 |
|
|
Oct 09 11:05:40 PM UTC 24 |
Oct 10 12:28:16 AM UTC 24 |
29124954170 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.1761065961 |
|
|
Oct 10 12:21:41 AM UTC 24 |
Oct 10 12:28:19 AM UTC 24 |
12372097105 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3910968906 |
|
|
Oct 10 12:28:11 AM UTC 24 |
Oct 10 12:28:20 AM UTC 24 |
35000790 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.2214918954 |
|
|
Oct 10 12:27:33 AM UTC 24 |
Oct 10 12:28:22 AM UTC 24 |
469280386 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.559606152 |
|
|
Oct 10 12:27:47 AM UTC 24 |
Oct 10 12:28:25 AM UTC 24 |
600168521 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2137575819 |
|
|
Oct 10 12:26:48 AM UTC 24 |
Oct 10 12:28:27 AM UTC 24 |
5363025045 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.3926298548 |
|
|
Oct 10 12:27:47 AM UTC 24 |
Oct 10 12:28:36 AM UTC 24 |
846169574 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.1870998208 |
|
|
Oct 10 12:26:19 AM UTC 24 |
Oct 10 12:28:40 AM UTC 24 |
8814091166 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.950929528 |
|
|
Oct 10 12:27:23 AM UTC 24 |
Oct 10 12:28:44 AM UTC 24 |
1226484460 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.853384650 |
|
|
Oct 10 12:27:59 AM UTC 24 |
Oct 10 12:28:58 AM UTC 24 |
74599650 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.3981638783 |
|
|
Oct 10 12:28:38 AM UTC 24 |
Oct 10 12:28:58 AM UTC 24 |
180636506 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.997031218 |
|
|
Oct 10 12:28:37 AM UTC 24 |
Oct 10 12:28:59 AM UTC 24 |
130453998 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.1961439622 |
|
|
Oct 10 12:27:43 AM UTC 24 |
Oct 10 12:28:59 AM UTC 24 |
2415325506 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.789757392 |
|
|
Oct 10 12:29:00 AM UTC 24 |
Oct 10 12:29:10 AM UTC 24 |
21716688 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.1523958884 |
|
|
Oct 10 12:28:47 AM UTC 24 |
Oct 10 12:29:17 AM UTC 24 |
819212070 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.2324674676 |
|
|
Oct 10 12:27:23 AM UTC 24 |
Oct 10 12:29:25 AM UTC 24 |
6417154520 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2755947068 |
|
|
Oct 10 12:29:04 AM UTC 24 |
Oct 10 12:29:32 AM UTC 24 |
177893800 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1561495830 |
|
|
Oct 10 12:29:22 AM UTC 24 |
Oct 10 12:29:36 AM UTC 24 |
195979965 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.719758758 |
|
|
Oct 10 12:08:40 AM UTC 24 |
Oct 10 12:29:37 AM UTC 24 |
115446421785 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2424890659 |
|
|
Oct 10 12:29:35 AM UTC 24 |
Oct 10 12:29:45 AM UTC 24 |
39786061 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1522804281 |
|
|
Oct 10 12:28:25 AM UTC 24 |
Oct 10 12:29:57 AM UTC 24 |
5475300266 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.1819769351 |
|
|
Oct 10 12:28:50 AM UTC 24 |
Oct 10 12:29:58 AM UTC 24 |
1409931113 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.4094080600 |
|
|
Oct 10 12:28:26 AM UTC 24 |
Oct 10 12:29:58 AM UTC 24 |
8127179459 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.802283544 |
|
|
Oct 10 12:26:34 AM UTC 24 |
Oct 10 12:30:11 AM UTC 24 |
2126993881 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.2083762133 |
|
|
Oct 10 12:25:19 AM UTC 24 |
Oct 10 12:30:16 AM UTC 24 |
7524052147 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3457265854 |
|
|
Oct 10 12:13:58 AM UTC 24 |
Oct 10 12:30:22 AM UTC 24 |
66671369772 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.4114018903 |
|
|
Oct 10 12:30:00 AM UTC 24 |
Oct 10 12:30:24 AM UTC 24 |
141900367 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.290854152 |
|
|
Oct 10 12:26:39 AM UTC 24 |
Oct 10 12:30:36 AM UTC 24 |
2975702378 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.317656272 |
|
|
Oct 10 12:30:22 AM UTC 24 |
Oct 10 12:30:50 AM UTC 24 |
764805802 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2872260379 |
|
|
Oct 10 12:30:22 AM UTC 24 |
Oct 10 12:30:58 AM UTC 24 |
360340505 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3569260771 |
|
|
Oct 10 12:24:19 AM UTC 24 |
Oct 10 12:31:06 AM UTC 24 |
8630829671 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2278450587 |
|
|
Oct 10 12:13:38 AM UTC 24 |
Oct 10 12:31:07 AM UTC 24 |
107261959451 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.2452478558 |
|
|
Oct 10 12:30:36 AM UTC 24 |
Oct 10 12:31:21 AM UTC 24 |
1190733731 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.77594075 |
|
|
Oct 10 12:19:00 AM UTC 24 |
Oct 10 12:31:23 AM UTC 24 |
55806863103 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2087057740 |
|
|
Oct 10 12:30:46 AM UTC 24 |
Oct 10 12:31:27 AM UTC 24 |
911795009 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.4257910806 |
|
|
Oct 10 12:28:44 AM UTC 24 |
Oct 10 12:31:27 AM UTC 24 |
2802266811 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.3943486901 |
|
|
Oct 10 12:30:40 AM UTC 24 |
Oct 10 12:31:38 AM UTC 24 |
834441537 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.2376904928 |
|
|
Oct 09 11:07:39 PM UTC 24 |
Oct 10 12:31:38 AM UTC 24 |
59165605180 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.1612423087 |
|
|
Oct 10 12:29:57 AM UTC 24 |
Oct 10 12:31:38 AM UTC 24 |
2574593200 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.3845432378 |
|
|
Oct 10 12:31:30 AM UTC 24 |
Oct 10 12:31:39 AM UTC 24 |
51078847 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.648227390 |
|
|
Oct 10 12:31:30 AM UTC 24 |
Oct 10 12:31:40 AM UTC 24 |
47561675 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2773483430 |
|
|
Oct 10 12:29:49 AM UTC 24 |
Oct 10 12:31:41 AM UTC 24 |
6111588405 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.3297053410 |
|
|
Oct 10 12:29:04 AM UTC 24 |
Oct 10 12:31:44 AM UTC 24 |
3649028990 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1066919312 |
|
|
Oct 10 12:26:43 AM UTC 24 |
Oct 10 12:31:47 AM UTC 24 |
2893386392 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.2920128023 |
|
|
Oct 10 12:29:41 AM UTC 24 |
Oct 10 12:31:49 AM UTC 24 |
9834994796 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3439535415 |
|
|
Oct 10 12:29:23 AM UTC 24 |
Oct 10 12:31:58 AM UTC 24 |
360043191 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.1242782906 |
|
|
Oct 09 11:25:20 PM UTC 24 |
Oct 10 12:32:01 AM UTC 24 |
29155019453 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2224281081 |
|
|
Oct 10 12:08:55 AM UTC 24 |
Oct 10 12:32:03 AM UTC 24 |
82917805807 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.3912641305 |
|
|
Oct 10 12:31:51 AM UTC 24 |
Oct 10 12:32:11 AM UTC 24 |
283537279 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.3338628927 |
|
|
Oct 10 12:31:50 AM UTC 24 |
Oct 10 12:32:29 AM UTC 24 |
395512917 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.1293399065 |
|
|
Oct 10 12:25:46 AM UTC 24 |
Oct 10 12:32:32 AM UTC 24 |
9750742548 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.415339588 |
|
|
Oct 10 12:32:06 AM UTC 24 |
Oct 10 12:32:40 AM UTC 24 |
781579268 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.2538463597 |
|
|
Oct 10 12:32:01 AM UTC 24 |
Oct 10 12:32:43 AM UTC 24 |
745738405 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.1045982281 |
|
|
Oct 10 12:32:35 AM UTC 24 |
Oct 10 12:32:50 AM UTC 24 |
230599267 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.4162295567 |
|
|
Oct 10 12:17:28 AM UTC 24 |
Oct 10 12:32:53 AM UTC 24 |
61564612621 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.1233848765 |
|
|
Oct 10 12:31:59 AM UTC 24 |
Oct 10 12:32:56 AM UTC 24 |
1381844631 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.2778883473 |
|
|
Oct 10 12:24:12 AM UTC 24 |
Oct 10 12:32:59 AM UTC 24 |
13666286086 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2247776423 |
|
|
Oct 10 12:01:57 AM UTC 24 |
Oct 10 12:33:02 AM UTC 24 |
104464074113 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2535070103 |
|
|
Oct 10 12:32:53 AM UTC 24 |
Oct 10 12:33:03 AM UTC 24 |
36266383 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.3220194417 |
|
|
Oct 10 12:27:56 AM UTC 24 |
Oct 10 12:33:03 AM UTC 24 |
3580590792 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3155439940 |
|
|
Oct 10 12:15:57 AM UTC 24 |
Oct 10 12:33:03 AM UTC 24 |
63622281016 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.4050131429 |
|
|
Oct 10 12:32:01 AM UTC 24 |
Oct 10 12:33:04 AM UTC 24 |
1494116354 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3800240682 |
|
|
Oct 10 12:32:08 AM UTC 24 |
Oct 10 12:33:15 AM UTC 24 |
1207554211 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2469335379 |
|
|
Oct 10 12:31:44 AM UTC 24 |
Oct 10 12:33:25 AM UTC 24 |
5041633750 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.2500090894 |
|
|
Oct 09 11:14:02 PM UTC 24 |
Oct 10 12:33:27 AM UTC 24 |
31642186723 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.2332647062 |
|
|
Oct 10 12:33:14 AM UTC 24 |
Oct 10 12:33:28 AM UTC 24 |
69259199 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3797127088 |
|
|
Oct 10 12:27:52 AM UTC 24 |
Oct 10 12:33:30 AM UTC 24 |
491928084 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.572986149 |
|
|
Oct 10 12:31:45 AM UTC 24 |
Oct 10 12:33:34 AM UTC 24 |
9540647716 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2756148561 |
|
|
Oct 09 11:03:05 PM UTC 24 |
Oct 10 12:33:37 AM UTC 24 |
28956994475 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3960768090 |
|
|
Oct 10 12:33:27 AM UTC 24 |
Oct 10 12:33:40 AM UTC 24 |
54292692 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1059210122 |
|
|
Oct 10 12:20:41 AM UTC 24 |
Oct 10 12:33:48 AM UTC 24 |
54222607729 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.1245921469 |
|
|
Oct 10 12:33:22 AM UTC 24 |
Oct 10 12:33:53 AM UTC 24 |
537889777 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3597752371 |
|
|
Oct 10 12:21:01 AM UTC 24 |
Oct 10 12:33:54 AM UTC 24 |
52356477234 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2996405743 |
|
|
Oct 10 12:32:20 AM UTC 24 |
Oct 10 12:33:54 AM UTC 24 |
99280805 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.71537735 |
|
|
Oct 10 12:33:08 AM UTC 24 |
Oct 10 12:34:04 AM UTC 24 |
511330409 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2199495131 |
|
|
Oct 10 12:33:58 AM UTC 24 |
Oct 10 12:34:07 AM UTC 24 |
50356148 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.3388385559 |
|
|
Oct 10 12:33:52 AM UTC 24 |
Oct 10 12:34:07 AM UTC 24 |
254104705 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2963092087 |
|
|
Oct 10 12:33:27 AM UTC 24 |
Oct 10 12:34:13 AM UTC 24 |
1249098465 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2689346834 |
|
|
Oct 09 11:54:00 PM UTC 24 |
Oct 10 12:34:18 AM UTC 24 |
156149121927 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.582261772 |
|
|
Oct 10 12:34:16 AM UTC 24 |
Oct 10 12:34:26 AM UTC 24 |
31979769 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.4162423245 |
|
|
Oct 10 12:33:25 AM UTC 24 |
Oct 10 12:34:28 AM UTC 24 |
1351546040 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.3243138407 |
|
|
Oct 10 12:32:13 AM UTC 24 |
Oct 10 12:34:29 AM UTC 24 |
1670885966 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2755467862 |
|
|
Oct 10 12:25:46 AM UTC 24 |
Oct 10 12:34:29 AM UTC 24 |
9260157453 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2047073634 |
|
|
Oct 10 12:32:56 AM UTC 24 |
Oct 10 12:34:29 AM UTC 24 |
9603561283 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3354744340 |
|
|
Oct 10 12:27:48 AM UTC 24 |
Oct 10 12:34:33 AM UTC 24 |
11027948125 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.3928899226 |
|
|
Oct 10 12:33:27 AM UTC 24 |
Oct 10 12:34:41 AM UTC 24 |
2063818963 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.786334107 |
|
|
Oct 10 12:34:27 AM UTC 24 |
Oct 10 12:34:46 AM UTC 24 |
310577683 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1314936931 |
|
|
Oct 10 12:30:59 AM UTC 24 |
Oct 10 12:34:48 AM UTC 24 |
481824041 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2690422596 |
|
|
Oct 10 12:34:48 AM UTC 24 |
Oct 10 12:35:02 AM UTC 24 |
67648009 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.74693768 |
|
|
Oct 10 12:34:56 AM UTC 24 |
Oct 10 12:35:07 AM UTC 24 |
41389699 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.1011722812 |
|
|
Oct 10 12:34:17 AM UTC 24 |
Oct 10 12:35:08 AM UTC 24 |
3591347991 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.2191884988 |
|
|
Oct 10 12:33:02 AM UTC 24 |
Oct 10 12:35:11 AM UTC 24 |
5452285322 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.4094999257 |
|
|
Oct 10 12:23:52 AM UTC 24 |
Oct 10 12:35:12 AM UTC 24 |
37349424554 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.3654133376 |
|
|
Oct 10 12:33:52 AM UTC 24 |
Oct 10 12:35:16 AM UTC 24 |
1145111725 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3188495569 |
|
|
Oct 10 12:35:06 AM UTC 24 |
Oct 10 12:35:17 AM UTC 24 |
42068686 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2416098248 |
|
|
Oct 10 12:31:14 AM UTC 24 |
Oct 10 12:35:20 AM UTC 24 |
5991449149 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.579984946 |
|
|
Oct 10 12:34:32 AM UTC 24 |
Oct 10 12:35:25 AM UTC 24 |
1547929983 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.244826990 |
|
|
Oct 10 12:32:26 AM UTC 24 |
Oct 10 12:35:26 AM UTC 24 |
2291056950 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.361620047 |
|
|
Oct 10 12:34:40 AM UTC 24 |
Oct 10 12:35:30 AM UTC 24 |
962140513 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.992186837 |
|
|
Oct 10 12:34:12 AM UTC 24 |
Oct 10 12:35:30 AM UTC 24 |
2116793570 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.143084716 |
|
|
Oct 10 12:26:40 AM UTC 24 |
Oct 10 12:35:31 AM UTC 24 |
9242640374 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2804488113 |
|
|
Oct 10 12:34:03 AM UTC 24 |
Oct 10 12:35:37 AM UTC 24 |
4958419764 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.2269606719 |
|
|
Oct 10 12:33:59 AM UTC 24 |
Oct 10 12:35:38 AM UTC 24 |
7826786974 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.3280002998 |
|
|
Oct 10 12:24:52 AM UTC 24 |
Oct 10 12:35:52 AM UTC 24 |
58794688368 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1316877295 |
|
|
Oct 10 12:23:49 AM UTC 24 |
Oct 10 12:35:56 AM UTC 24 |
71121845717 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2496672831 |
|
|
Oct 10 12:35:40 AM UTC 24 |
Oct 10 12:35:58 AM UTC 24 |
290292341 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3348439429 |
|
|
Oct 10 12:32:00 AM UTC 24 |
Oct 10 12:35:59 AM UTC 24 |
12591599267 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.2088089725 |
|
|
Oct 10 12:35:27 AM UTC 24 |
Oct 10 12:36:03 AM UTC 24 |
332005239 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1208954529 |
|
|
Oct 10 12:35:56 AM UTC 24 |
Oct 10 12:36:11 AM UTC 24 |
294344284 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.855203732 |
|
|
Oct 10 12:35:26 AM UTC 24 |
Oct 10 12:36:12 AM UTC 24 |
912668058 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.4284091198 |
|
|
Oct 10 12:36:03 AM UTC 24 |
Oct 10 12:36:12 AM UTC 24 |
229274911 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.2147472913 |
|
|
Oct 10 12:34:35 AM UTC 24 |
Oct 10 12:36:13 AM UTC 24 |
2408471083 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2243898361 |
|
|
Oct 10 12:35:08 AM UTC 24 |
Oct 10 12:36:17 AM UTC 24 |
6789374246 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1830299221 |
|
|
Oct 10 12:36:15 AM UTC 24 |
Oct 10 12:36:23 AM UTC 24 |
42157620 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.1933543147 |
|
|
Oct 10 12:35:41 AM UTC 24 |
Oct 10 12:36:27 AM UTC 24 |
539818101 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.3063609929 |
|
|
Oct 10 12:35:51 AM UTC 24 |
Oct 10 12:36:35 AM UTC 24 |
841998057 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.279068923 |
|
|
Oct 10 12:35:13 AM UTC 24 |
Oct 10 12:36:46 AM UTC 24 |
4604789311 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1530323004 |
|
|
Oct 10 12:35:50 AM UTC 24 |
Oct 10 12:36:48 AM UTC 24 |
1403317319 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3512400590 |
|
|
Oct 10 12:36:46 AM UTC 24 |
Oct 10 12:36:54 AM UTC 24 |
129568891 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.2870993513 |
|
|
Oct 10 12:35:36 AM UTC 24 |
Oct 10 12:37:00 AM UTC 24 |
1720874377 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2313524334 |
|
|
Oct 10 12:22:16 AM UTC 24 |
Oct 10 12:37:03 AM UTC 24 |
48691926146 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.584895757 |
|
|
Oct 10 12:36:37 AM UTC 24 |
Oct 10 12:37:10 AM UTC 24 |
229141242 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.1054413180 |
|
|
Oct 10 12:36:20 AM UTC 24 |
Oct 10 12:37:10 AM UTC 24 |
1480379819 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.1543706766 |
|
|
Oct 10 12:36:24 AM UTC 24 |
Oct 10 12:37:14 AM UTC 24 |
495530286 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3906396393 |
|
|
Oct 10 12:33:37 AM UTC 24 |
Oct 10 12:37:14 AM UTC 24 |
5514984133 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.4110472538 |
|
|
Oct 10 12:36:50 AM UTC 24 |
Oct 10 12:37:17 AM UTC 24 |
366639824 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3462330509 |
|
|
Oct 10 12:34:53 AM UTC 24 |
Oct 10 12:37:18 AM UTC 24 |
3503689778 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2557381470 |
|
|
Oct 10 12:36:59 AM UTC 24 |
Oct 10 12:37:18 AM UTC 24 |
125914442 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3109742460 |
|
|
Oct 10 12:31:23 AM UTC 24 |
Oct 10 12:37:23 AM UTC 24 |
2387283331 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1191699645 |
|
|
Oct 10 12:36:31 AM UTC 24 |
Oct 10 12:37:23 AM UTC 24 |
4446069083 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4075534352 |
|
|
Oct 10 12:28:44 AM UTC 24 |
Oct 10 12:37:23 AM UTC 24 |
28996788459 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.234839249 |
|
|
Oct 10 12:36:18 AM UTC 24 |
Oct 10 12:37:30 AM UTC 24 |
6324901061 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3017819349 |
|
|
Oct 10 12:32:27 AM UTC 24 |
Oct 10 12:37:32 AM UTC 24 |
3910172879 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.1912964179 |
|
|
Oct 10 12:37:25 AM UTC 24 |
Oct 10 12:37:34 AM UTC 24 |
175869827 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3757483589 |
|
|
Oct 10 12:36:19 AM UTC 24 |
Oct 10 12:37:34 AM UTC 24 |
5599666677 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1735825257 |
|
|
Oct 10 12:37:33 AM UTC 24 |
Oct 10 12:37:42 AM UTC 24 |
49055482 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1802749784 |
|
|
Oct 10 12:35:53 AM UTC 24 |
Oct 10 12:37:43 AM UTC 24 |
162892595 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.152570028 |
|
|
Oct 10 12:32:00 AM UTC 24 |
Oct 10 12:37:44 AM UTC 24 |
24220923598 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2068117274 |
|
|
Oct 10 12:33:19 AM UTC 24 |
Oct 10 12:37:52 AM UTC 24 |
17830125264 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.3572542501 |
|
|
Oct 10 12:30:48 AM UTC 24 |
Oct 10 12:37:53 AM UTC 24 |
4286388676 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3262868957 |
|
|
Oct 10 12:17:31 AM UTC 24 |
Oct 10 12:38:05 AM UTC 24 |
76185944600 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.3873121105 |
|
|
Oct 10 12:37:40 AM UTC 24 |
Oct 10 12:38:16 AM UTC 24 |
379673774 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.2869445359 |
|
|
Oct 10 12:37:37 AM UTC 24 |
Oct 10 12:38:18 AM UTC 24 |
353463249 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.2849689272 |
|
|
Oct 10 12:27:20 AM UTC 24 |
Oct 10 12:38:20 AM UTC 24 |
58830926398 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3251185237 |
|
|
Oct 10 12:37:46 AM UTC 24 |
Oct 10 12:38:21 AM UTC 24 |
753338748 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.2526414364 |
|
|
Oct 10 12:36:41 AM UTC 24 |
Oct 10 12:38:21 AM UTC 24 |
2524115241 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.4000554381 |
|
|
Oct 10 12:38:17 AM UTC 24 |
Oct 10 12:38:27 AM UTC 24 |
47275476 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3838047871 |
|
|
Oct 10 12:38:17 AM UTC 24 |
Oct 10 12:38:31 AM UTC 24 |
193594329 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2482048212 |
|
|
Oct 10 12:33:51 AM UTC 24 |
Oct 10 12:38:35 AM UTC 24 |
1860110992 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.3376002878 |
|
|
Oct 10 12:37:55 AM UTC 24 |
Oct 10 12:38:35 AM UTC 24 |
716077352 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.1019297371 |
|
|
Oct 10 12:37:55 AM UTC 24 |
Oct 10 12:38:37 AM UTC 24 |
445350926 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.4211735574 |
|
|
Oct 10 12:37:55 AM UTC 24 |
Oct 10 12:38:42 AM UTC 24 |
974403769 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.4206092248 |
|
|
Oct 10 12:34:50 AM UTC 24 |
Oct 10 12:38:42 AM UTC 24 |
670291295 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2293397744 |
|
|
Oct 10 12:35:53 AM UTC 24 |
Oct 10 12:38:51 AM UTC 24 |
4742240644 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.309972714 |
|
|
Oct 10 12:37:44 AM UTC 24 |
Oct 10 12:38:54 AM UTC 24 |
693938085 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.3836107074 |
|
|
Oct 10 12:38:43 AM UTC 24 |
Oct 10 12:38:56 AM UTC 24 |
120200585 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.1036842540 |
|
|
Oct 10 12:37:34 AM UTC 24 |
Oct 10 12:39:09 AM UTC 24 |
8827601882 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.1775771868 |
|
|
Oct 10 12:38:08 AM UTC 24 |
Oct 10 12:39:14 AM UTC 24 |
1944280107 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.3596718349 |
|
|
Oct 10 12:38:58 AM UTC 24 |
Oct 10 12:39:19 AM UTC 24 |
339252473 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.306695909 |
|
|
Oct 10 12:37:58 AM UTC 24 |
Oct 10 12:39:21 AM UTC 24 |
1006333246 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.3290216176 |
|
|
Oct 10 12:34:51 AM UTC 24 |
Oct 10 12:39:24 AM UTC 24 |
2930195679 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.2079974354 |
|
|
Oct 10 12:37:42 AM UTC 24 |
Oct 10 12:39:26 AM UTC 24 |
7241497794 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3979175011 |
|
|
Oct 10 12:39:04 AM UTC 24 |
Oct 10 12:39:33 AM UTC 24 |
426956856 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2059364121 |
|
|
Oct 10 12:37:36 AM UTC 24 |
Oct 10 12:39:34 AM UTC 24 |
6359467608 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.55646474 |
|
|
Oct 10 12:38:58 AM UTC 24 |
Oct 10 12:39:45 AM UTC 24 |
1232603795 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3016209511 |
|
|
Oct 10 12:39:37 AM UTC 24 |
Oct 10 12:39:48 AM UTC 24 |
50855124 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1034156903 |
|
|
Oct 10 12:39:34 AM UTC 24 |
Oct 10 12:39:48 AM UTC 24 |
200014632 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.517160611 |
|
|
Oct 10 12:38:28 AM UTC 24 |
Oct 10 12:39:54 AM UTC 24 |
8223430586 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2121631784 |
|
|
Oct 10 12:38:50 AM UTC 24 |
Oct 10 12:39:55 AM UTC 24 |
1390378964 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.3711574638 |
|
|
Oct 10 12:39:18 AM UTC 24 |
Oct 10 12:39:56 AM UTC 24 |
356324071 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.936048277 |
|
|
Oct 10 12:38:39 AM UTC 24 |
Oct 10 12:40:10 AM UTC 24 |
2345757194 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.382166052 |
|
|
Oct 10 12:39:02 AM UTC 24 |
Oct 10 12:40:22 AM UTC 24 |
1328507117 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.1265703543 |
|
|
Oct 10 12:39:47 AM UTC 24 |
Oct 10 12:40:23 AM UTC 24 |
797694762 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.1918677149 |
|
|
Oct 10 12:38:45 AM UTC 24 |
Oct 10 12:40:23 AM UTC 24 |
8050562435 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3488442509 |
|
|
Oct 10 12:34:51 AM UTC 24 |
Oct 10 12:40:27 AM UTC 24 |
1137000771 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.867157374 |
|
|
Oct 10 12:37:41 AM UTC 24 |
Oct 10 12:40:28 AM UTC 24 |
12261516940 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.953489635 |
|
|
Oct 10 12:40:11 AM UTC 24 |
Oct 10 12:40:32 AM UTC 24 |
173423236 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.1209959787 |
|
|
Oct 10 12:40:10 AM UTC 24 |
Oct 10 12:40:33 AM UTC 24 |
231003501 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.1095521849 |
|
|
Oct 10 12:39:51 AM UTC 24 |
Oct 10 12:40:36 AM UTC 24 |
357901533 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3539082356 |
|
|
Oct 10 12:38:40 AM UTC 24 |
Oct 10 12:40:39 AM UTC 24 |
5953596809 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.3386740627 |
|
|
Oct 10 12:40:20 AM UTC 24 |
Oct 10 12:40:47 AM UTC 24 |
148512729 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.132503535 |
|
|
Oct 10 12:40:20 AM UTC 24 |
Oct 10 12:40:56 AM UTC 24 |
739290524 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.3647549400 |
|
|
Oct 10 12:40:51 AM UTC 24 |
Oct 10 12:40:58 AM UTC 24 |
45119851 ps |