| T1321 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.4276749453 |
|
|
Oct 10 07:13:06 AM UTC 24 |
Oct 10 09:07:22 AM UTC 24 |
27747326668 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2527487738 |
|
|
Oct 10 03:58:37 AM UTC 24 |
Oct 10 09:17:07 AM UTC 24 |
82568987656 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2114088684 |
|
|
Oct 10 07:17:07 AM UTC 24 |
Oct 10 09:27:22 AM UTC 24 |
34556973976 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.1732209964 |
|
|
Oct 10 06:12:17 AM UTC 24 |
Oct 10 09:33:02 AM UTC 24 |
42628913076 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.2193230762 |
|
|
Oct 10 07:19:10 AM UTC 24 |
Oct 10 09:34:38 AM UTC 24 |
35237942048 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.3151034397 |
|
|
Oct 10 05:24:53 AM UTC 24 |
Oct 10 09:37:54 AM UTC 24 |
66194297974 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2842113985 |
|
|
Oct 10 05:23:57 AM UTC 24 |
Oct 10 09:55:08 AM UTC 24 |
82453475900 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2890711009 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:03:16 PM UTC 24 |
47603794 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.849247758 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:03:18 PM UTC 24 |
47461436 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3534869393 |
|
|
Oct 09 11:03:05 PM UTC 24 |
Oct 09 11:03:18 PM UTC 24 |
110430123 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.1560924674 |
|
|
Oct 09 11:03:15 PM UTC 24 |
Oct 09 11:03:24 PM UTC 24 |
41723319 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2033198908 |
|
|
Oct 09 11:03:16 PM UTC 24 |
Oct 09 11:03:26 PM UTC 24 |
43448304 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3954314092 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:03:28 PM UTC 24 |
253419558 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3958783033 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:03:41 PM UTC 24 |
263838574 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4096490687 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:03:42 PM UTC 24 |
809222047 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3980442905 |
|
|
Oct 09 11:03:07 PM UTC 24 |
Oct 09 11:03:49 PM UTC 24 |
1189596758 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3284765941 |
|
|
Oct 09 11:03:11 PM UTC 24 |
Oct 09 11:03:54 PM UTC 24 |
1232215472 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2203927853 |
|
|
Oct 09 11:03:32 PM UTC 24 |
Oct 09 11:03:57 PM UTC 24 |
213387747 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.647557173 |
|
|
Oct 09 11:03:50 PM UTC 24 |
Oct 09 11:04:11 PM UTC 24 |
299881114 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.397395083 |
|
|
Oct 09 11:03:38 PM UTC 24 |
Oct 09 11:04:13 PM UTC 24 |
1203170559 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1804284465 |
|
|
Oct 09 11:03:33 PM UTC 24 |
Oct 09 11:04:26 PM UTC 24 |
513653203 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.3331512030 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:04:36 PM UTC 24 |
2382609724 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1301760472 |
|
|
Oct 09 11:03:27 PM UTC 24 |
Oct 09 11:04:41 PM UTC 24 |
4917614004 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1519948007 |
|
|
Oct 09 11:03:44 PM UTC 24 |
Oct 09 11:04:44 PM UTC 24 |
1359577874 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.766595874 |
|
|
Oct 09 11:03:49 PM UTC 24 |
Oct 09 11:04:46 PM UTC 24 |
981216656 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2944445023 |
|
|
Oct 09 11:03:39 PM UTC 24 |
Oct 09 11:04:55 PM UTC 24 |
4165929999 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3249522732 |
|
|
Oct 09 11:03:40 PM UTC 24 |
Oct 09 11:04:55 PM UTC 24 |
1539599229 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3001606727 |
|
|
Oct 09 11:03:15 PM UTC 24 |
Oct 09 11:04:55 PM UTC 24 |
9015183823 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3076844110 |
|
|
Oct 09 11:03:51 PM UTC 24 |
Oct 09 11:04:55 PM UTC 24 |
325197276 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3686535022 |
|
|
Oct 09 11:03:47 PM UTC 24 |
Oct 09 11:04:56 PM UTC 24 |
1398597153 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2871985277 |
|
|
Oct 09 11:04:50 PM UTC 24 |
Oct 09 11:04:59 PM UTC 24 |
52566716 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.3418037558 |
|
|
Oct 09 11:04:50 PM UTC 24 |
Oct 09 11:05:00 PM UTC 24 |
151375483 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3633544686 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:05:11 PM UTC 24 |
8658976193 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.524645495 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:05:12 PM UTC 24 |
6618696604 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.2758074815 |
|
|
Oct 09 11:04:54 PM UTC 24 |
Oct 09 11:05:18 PM UTC 24 |
683978931 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.3467485092 |
|
|
Oct 09 11:05:12 PM UTC 24 |
Oct 09 11:05:32 PM UTC 24 |
479334256 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.4284409133 |
|
|
Oct 09 11:04:56 PM UTC 24 |
Oct 09 11:05:38 PM UTC 24 |
455247666 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.121559051 |
|
|
Oct 09 11:05:15 PM UTC 24 |
Oct 09 11:05:40 PM UTC 24 |
472962321 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.2956982845 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:05:46 PM UTC 24 |
4569221724 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2355309139 |
|
|
Oct 09 11:03:10 PM UTC 24 |
Oct 09 11:05:52 PM UTC 24 |
523991076 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2255379715 |
|
|
Oct 09 11:05:02 PM UTC 24 |
Oct 09 11:06:04 PM UTC 24 |
549104531 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.250660984 |
|
|
Oct 09 11:05:58 PM UTC 24 |
Oct 09 11:06:07 PM UTC 24 |
54507277 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1389367866 |
|
|
Oct 09 11:05:17 PM UTC 24 |
Oct 09 11:06:08 PM UTC 24 |
342675433 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3087563788 |
|
|
Oct 09 11:06:02 PM UTC 24 |
Oct 09 11:06:12 PM UTC 24 |
46576714 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.4063161417 |
|
|
Oct 09 11:05:16 PM UTC 24 |
Oct 09 11:06:20 PM UTC 24 |
1268713331 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2513607317 |
|
|
Oct 09 11:04:52 PM UTC 24 |
Oct 09 11:06:22 PM UTC 24 |
5638712133 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.3747951834 |
|
|
Oct 09 11:04:56 PM UTC 24 |
Oct 09 11:06:31 PM UTC 24 |
6197951153 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3681683417 |
|
|
Oct 09 11:03:12 PM UTC 24 |
Oct 09 11:06:40 PM UTC 24 |
3250145700 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.1033887215 |
|
|
Oct 09 11:03:11 PM UTC 24 |
Oct 09 11:06:47 PM UTC 24 |
6311275396 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.461355753 |
|
|
Oct 09 11:05:19 PM UTC 24 |
Oct 09 11:06:54 PM UTC 24 |
1358495505 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.3750326902 |
|
|
Oct 09 11:06:35 PM UTC 24 |
Oct 09 11:07:02 PM UTC 24 |
193321810 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.3126501247 |
|
|
Oct 09 11:06:47 PM UTC 24 |
Oct 09 11:07:04 PM UTC 24 |
73909229 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2693287945 |
|
|
Oct 09 11:06:43 PM UTC 24 |
Oct 09 11:07:06 PM UTC 24 |
499801134 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.629881285 |
|
|
Oct 09 11:06:17 PM UTC 24 |
Oct 09 11:07:08 PM UTC 24 |
1324855464 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3831566462 |
|
|
Oct 09 11:06:27 PM UTC 24 |
Oct 09 11:07:16 PM UTC 24 |
513628413 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.410333745 |
|
|
Oct 09 11:06:54 PM UTC 24 |
Oct 09 11:07:28 PM UTC 24 |
550889167 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.1672336681 |
|
|
Oct 09 11:06:08 PM UTC 24 |
Oct 09 11:07:47 PM UTC 24 |
7286272584 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.3930571861 |
|
|
Oct 09 11:03:11 PM UTC 24 |
Oct 09 11:07:53 PM UTC 24 |
7848187952 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.37442986 |
|
|
Oct 09 11:04:36 PM UTC 24 |
Oct 09 11:07:56 PM UTC 24 |
3628854852 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.3975095595 |
|
|
Oct 09 11:07:17 PM UTC 24 |
Oct 09 11:08:00 PM UTC 24 |
274589110 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1114105163 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:08:09 PM UTC 24 |
4105466023 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2791622826 |
|
|
Oct 09 11:06:14 PM UTC 24 |
Oct 09 11:08:13 PM UTC 24 |
5322582581 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1970421884 |
|
|
Oct 09 11:05:22 PM UTC 24 |
Oct 09 11:08:19 PM UTC 24 |
662413004 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.4116043713 |
|
|
Oct 09 11:06:47 PM UTC 24 |
Oct 09 11:08:20 PM UTC 24 |
2485072389 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.675653291 |
|
|
Oct 09 11:08:18 PM UTC 24 |
Oct 09 11:08:32 PM UTC 24 |
192593721 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.4040139099 |
|
|
Oct 09 11:08:23 PM UTC 24 |
Oct 09 11:08:32 PM UTC 24 |
36016020 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.2724267911 |
|
|
Oct 09 11:03:10 PM UTC 24 |
Oct 09 11:09:05 PM UTC 24 |
5106548236 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.2727331385 |
|
|
Oct 09 11:08:43 PM UTC 24 |
Oct 09 11:09:07 PM UTC 24 |
265537879 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3850900018 |
|
|
Oct 09 11:05:59 PM UTC 24 |
Oct 09 11:09:09 PM UTC 24 |
3225067666 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.2732466332 |
|
|
Oct 09 11:04:42 PM UTC 24 |
Oct 09 11:09:17 PM UTC 24 |
5099170135 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.3113869902 |
|
|
Oct 09 11:08:56 PM UTC 24 |
Oct 09 11:09:36 PM UTC 24 |
158643815 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.1897016986 |
|
|
Oct 09 11:04:11 PM UTC 24 |
Oct 09 11:09:54 PM UTC 24 |
5695482725 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1883842493 |
|
|
Oct 09 11:09:41 PM UTC 24 |
Oct 09 11:09:56 PM UTC 24 |
192278027 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.1017662334 |
|
|
Oct 09 11:08:41 PM UTC 24 |
Oct 09 11:10:06 PM UTC 24 |
2421437695 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2478044198 |
|
|
Oct 09 11:04:18 PM UTC 24 |
Oct 09 11:10:12 PM UTC 24 |
3913386250 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2300460173 |
|
|
Oct 09 11:08:35 PM UTC 24 |
Oct 09 11:10:15 PM UTC 24 |
6062477723 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2482879358 |
|
|
Oct 09 11:09:59 PM UTC 24 |
Oct 09 11:10:28 PM UTC 24 |
185045340 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.599762315 |
|
|
Oct 09 11:03:10 PM UTC 24 |
Oct 09 11:10:43 PM UTC 24 |
6732962277 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1476798524 |
|
|
Oct 09 11:09:30 PM UTC 24 |
Oct 09 11:10:43 PM UTC 24 |
1683976464 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.2991425044 |
|
|
Oct 09 11:08:32 PM UTC 24 |
Oct 09 11:10:48 PM UTC 24 |
7537018927 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.2466353031 |
|
|
Oct 09 11:03:05 PM UTC 24 |
Oct 09 11:10:56 PM UTC 24 |
6178150516 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1802325029 |
|
|
Oct 09 11:07:26 PM UTC 24 |
Oct 09 11:11:00 PM UTC 24 |
3945818360 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.495840413 |
|
|
Oct 09 11:05:15 PM UTC 24 |
Oct 09 11:11:08 PM UTC 24 |
3986908333 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3999688865 |
|
|
Oct 09 11:05:33 PM UTC 24 |
Oct 09 11:11:23 PM UTC 24 |
4035030096 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2973268916 |
|
|
Oct 09 11:11:19 PM UTC 24 |
Oct 09 11:11:29 PM UTC 24 |
208071676 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2094047045 |
|
|
Oct 09 11:11:23 PM UTC 24 |
Oct 09 11:11:32 PM UTC 24 |
40248748 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.4242056621 |
|
|
Oct 09 11:09:32 PM UTC 24 |
Oct 09 11:11:39 PM UTC 24 |
2407294505 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2175842322 |
|
|
Oct 09 11:03:07 PM UTC 24 |
Oct 09 11:11:54 PM UTC 24 |
11825791750 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2203789115 |
|
|
Oct 09 11:11:52 PM UTC 24 |
Oct 09 11:12:03 PM UTC 24 |
41233001 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.34605470 |
|
|
Oct 09 11:04:04 PM UTC 24 |
Oct 09 11:12:04 PM UTC 24 |
13360424205 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1526585726 |
|
|
Oct 09 11:07:25 PM UTC 24 |
Oct 09 11:12:27 PM UTC 24 |
2425451139 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.1071515385 |
|
|
Oct 09 11:08:54 PM UTC 24 |
Oct 09 11:12:30 PM UTC 24 |
18014502850 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.4107628954 |
|
|
Oct 09 11:05:24 PM UTC 24 |
Oct 09 11:12:40 PM UTC 24 |
5595186880 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4109851683 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:12:55 PM UTC 24 |
12370600487 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1725110856 |
|
|
Oct 09 11:11:56 PM UTC 24 |
Oct 09 11:12:58 PM UTC 24 |
585215902 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.2370035441 |
|
|
Oct 09 11:10:15 PM UTC 24 |
Oct 09 11:13:17 PM UTC 24 |
4594885380 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3804847533 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:13:24 PM UTC 24 |
10521615412 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.917656952 |
|
|
Oct 09 11:04:49 PM UTC 24 |
Oct 09 11:13:27 PM UTC 24 |
10711776775 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2967299617 |
|
|
Oct 09 11:07:29 PM UTC 24 |
Oct 09 11:13:34 PM UTC 24 |
4219440580 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.909046198 |
|
|
Oct 09 11:13:20 PM UTC 24 |
Oct 09 11:13:36 PM UTC 24 |
255741757 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.3056369116 |
|
|
Oct 09 11:05:02 PM UTC 24 |
Oct 09 11:13:41 PM UTC 24 |
47021019405 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.3618715579 |
|
|
Oct 09 11:11:32 PM UTC 24 |
Oct 09 11:13:43 PM UTC 24 |
9098374987 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.539965298 |
|
|
Oct 09 11:11:46 PM UTC 24 |
Oct 09 11:13:44 PM UTC 24 |
5740769450 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.97086509 |
|
|
Oct 09 11:05:35 PM UTC 24 |
Oct 09 11:13:47 PM UTC 24 |
7193717134 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3063078577 |
|
|
Oct 09 11:03:37 PM UTC 24 |
Oct 09 11:13:52 PM UTC 24 |
48011481014 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.433331612 |
|
|
Oct 09 11:13:04 PM UTC 24 |
Oct 09 11:13:58 PM UTC 24 |
310040136 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.3672005057 |
|
|
Oct 09 11:12:53 PM UTC 24 |
Oct 09 11:14:01 PM UTC 24 |
1310873608 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.2686926682 |
|
|
Oct 09 11:13:47 PM UTC 24 |
Oct 09 11:14:02 PM UTC 24 |
105429679 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.883540733 |
|
|
Oct 09 11:11:12 PM UTC 24 |
Oct 09 11:14:12 PM UTC 24 |
2403001756 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.4093555522 |
|
|
Oct 09 11:12:51 PM UTC 24 |
Oct 09 11:14:14 PM UTC 24 |
2405110210 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.2437892856 |
|
|
Oct 09 11:14:06 PM UTC 24 |
Oct 09 11:14:17 PM UTC 24 |
169444107 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2574983661 |
|
|
Oct 09 11:14:11 PM UTC 24 |
Oct 09 11:14:20 PM UTC 24 |
44501633 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2573654108 |
|
|
Oct 09 11:10:36 PM UTC 24 |
Oct 09 11:14:25 PM UTC 24 |
1701635797 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.422028523 |
|
|
Oct 09 11:14:20 PM UTC 24 |
Oct 09 11:14:38 PM UTC 24 |
108547450 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.3879269705 |
|
|
Oct 09 11:14:21 PM UTC 24 |
Oct 09 11:14:38 PM UTC 24 |
207334777 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.946641444 |
|
|
Oct 09 11:08:55 PM UTC 24 |
Oct 09 11:14:42 PM UTC 24 |
23147958895 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.347146507 |
|
|
Oct 09 11:12:25 PM UTC 24 |
Oct 09 11:14:42 PM UTC 24 |
2720152529 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2801140955 |
|
|
Oct 09 11:10:18 PM UTC 24 |
Oct 09 11:14:48 PM UTC 24 |
2700496187 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1867702500 |
|
|
Oct 09 11:03:12 PM UTC 24 |
Oct 09 11:14:48 PM UTC 24 |
17534424823 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.3487941232 |
|
|
Oct 09 11:10:38 PM UTC 24 |
Oct 09 11:15:07 PM UTC 24 |
5781767144 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1449819264 |
|
|
Oct 09 11:15:02 PM UTC 24 |
Oct 09 11:15:18 PM UTC 24 |
233764520 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4189899582 |
|
|
Oct 09 11:04:02 PM UTC 24 |
Oct 09 11:15:19 PM UTC 24 |
7567237132 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.4194794540 |
|
|
Oct 09 11:14:12 PM UTC 24 |
Oct 09 11:15:20 PM UTC 24 |
4019787763 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.1584231713 |
|
|
Oct 09 11:14:49 PM UTC 24 |
Oct 09 11:15:28 PM UTC 24 |
826464928 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.2045102117 |
|
|
Oct 09 11:08:16 PM UTC 24 |
Oct 09 11:15:32 PM UTC 24 |
4316549834 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.3947072337 |
|
|
Oct 09 11:14:43 PM UTC 24 |
Oct 09 11:15:34 PM UTC 24 |
570361812 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.4156907081 |
|
|
Oct 09 11:14:50 PM UTC 24 |
Oct 09 11:15:35 PM UTC 24 |
1012474575 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1074960779 |
|
|
Oct 09 11:05:21 PM UTC 24 |
Oct 09 11:15:43 PM UTC 24 |
8660401458 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3722764684 |
|
|
Oct 09 11:14:14 PM UTC 24 |
Oct 09 11:15:48 PM UTC 24 |
9457491483 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.3432669212 |
|
|
Oct 09 11:15:41 PM UTC 24 |
Oct 09 11:15:54 PM UTC 24 |
186252879 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.1252238934 |
|
|
Oct 09 11:14:37 PM UTC 24 |
Oct 09 11:15:57 PM UTC 24 |
754291246 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.700542339 |
|
|
Oct 09 11:15:51 PM UTC 24 |
Oct 09 11:16:01 PM UTC 24 |
46300945 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1335213831 |
|
|
Oct 09 11:07:03 PM UTC 24 |
Oct 09 11:16:02 PM UTC 24 |
13429579080 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3148716772 |
|
|
Oct 09 11:03:05 PM UTC 24 |
Oct 09 11:16:09 PM UTC 24 |
51186746873 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.2740249865 |
|
|
Oct 09 11:16:05 PM UTC 24 |
Oct 09 11:16:35 PM UTC 24 |
213672821 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3067636640 |
|
|
Oct 09 11:15:05 PM UTC 24 |
Oct 09 11:16:56 PM UTC 24 |
3445674298 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3316322745 |
|
|
Oct 09 11:05:06 PM UTC 24 |
Oct 09 11:16:57 PM UTC 24 |
47367608168 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.262182105 |
|
|
Oct 09 11:15:56 PM UTC 24 |
Oct 09 11:17:05 PM UTC 24 |
6788013880 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.313132729 |
|
|
Oct 09 11:15:55 PM UTC 24 |
Oct 09 11:17:15 PM UTC 24 |
5757200462 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2306289640 |
|
|
Oct 09 11:15:05 PM UTC 24 |
Oct 09 11:17:16 PM UTC 24 |
179845740 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.940941969 |
|
|
Oct 09 11:10:52 PM UTC 24 |
Oct 09 11:17:19 PM UTC 24 |
4394900490 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2355762617 |
|
|
Oct 09 11:17:17 PM UTC 24 |
Oct 09 11:17:27 PM UTC 24 |
22884323 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.560590260 |
|
|
Oct 09 11:16:25 PM UTC 24 |
Oct 09 11:17:28 PM UTC 24 |
573554788 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.2979399986 |
|
|
Oct 09 11:16:58 PM UTC 24 |
Oct 09 11:17:34 PM UTC 24 |
758114665 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.1625612459 |
|
|
Oct 09 11:15:59 PM UTC 24 |
Oct 09 11:17:38 PM UTC 24 |
2145479156 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2267985017 |
|
|
Oct 09 11:07:28 PM UTC 24 |
Oct 09 11:17:48 PM UTC 24 |
5262820256 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.651475806 |
|
|
Oct 09 11:06:43 PM UTC 24 |
Oct 09 11:18:01 PM UTC 24 |
38845899575 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.309518365 |
|
|
Oct 09 11:18:00 PM UTC 24 |
Oct 09 11:18:12 PM UTC 24 |
204173124 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3641830950 |
|
|
Oct 09 11:13:21 PM UTC 24 |
Oct 09 11:18:17 PM UTC 24 |
2879815182 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.740400359 |
|
|
Oct 09 11:16:31 PM UTC 24 |
Oct 09 11:18:19 PM UTC 24 |
2392897305 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3481642654 |
|
|
Oct 09 11:18:12 PM UTC 24 |
Oct 09 11:18:22 PM UTC 24 |
51866270 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1309814332 |
|
|
Oct 09 11:03:09 PM UTC 24 |
Oct 09 11:18:25 PM UTC 24 |
8802592036 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.87570495 |
|
|
Oct 09 11:05:03 PM UTC 24 |
Oct 09 11:18:40 PM UTC 24 |
55693675223 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.1768320390 |
|
|
Oct 09 11:16:21 PM UTC 24 |
Oct 09 11:18:46 PM UTC 24 |
3119220852 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3887355772 |
|
|
Oct 09 11:18:41 PM UTC 24 |
Oct 09 11:19:01 PM UTC 24 |
190569461 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.189243755 |
|
|
Oct 09 11:06:31 PM UTC 24 |
Oct 09 11:19:07 PM UTC 24 |
47905417183 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1738332556 |
|
|
Oct 09 11:12:02 PM UTC 24 |
Oct 09 11:19:33 PM UTC 24 |
44142834127 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1924085143 |
|
|
Oct 09 11:11:07 PM UTC 24 |
Oct 09 11:19:35 PM UTC 24 |
7212884840 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.1594055222 |
|
|
Oct 09 11:18:43 PM UTC 24 |
Oct 09 11:19:48 PM UTC 24 |
571459881 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.4148433060 |
|
|
Oct 09 11:10:27 PM UTC 24 |
Oct 09 11:19:51 PM UTC 24 |
18467677354 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3066138805 |
|
|
Oct 09 11:04:22 PM UTC 24 |
Oct 09 11:19:59 PM UTC 24 |
8884794090 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3881264361 |
|
|
Oct 09 11:18:36 PM UTC 24 |
Oct 09 11:20:28 PM UTC 24 |
4954946173 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.580810195 |
|
|
Oct 09 11:19:03 PM UTC 24 |
Oct 09 11:20:31 PM UTC 24 |
1556266362 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1687471598 |
|
|
Oct 09 11:03:06 PM UTC 24 |
Oct 09 11:20:39 PM UTC 24 |
109545427189 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.307697051 |
|
|
Oct 09 11:13:56 PM UTC 24 |
Oct 09 11:20:40 PM UTC 24 |
4623008932 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.84973186 |
|
|
Oct 09 11:19:25 PM UTC 24 |
Oct 09 11:20:44 PM UTC 24 |
2574207675 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.758489557 |
|
|
Oct 09 11:19:55 PM UTC 24 |
Oct 09 11:20:52 PM UTC 24 |
856169442 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.2733111295 |
|
|
Oct 09 11:14:02 PM UTC 24 |
Oct 09 11:20:57 PM UTC 24 |
5326182084 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.3869813051 |
|
|
Oct 09 11:15:43 PM UTC 24 |
Oct 09 11:20:58 PM UTC 24 |
4025391984 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.1233058560 |
|
|
Oct 09 11:19:30 PM UTC 24 |
Oct 09 11:21:01 PM UTC 24 |
1870718849 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.2521082796 |
|
|
Oct 09 11:18:25 PM UTC 24 |
Oct 09 11:21:05 PM UTC 24 |
10276768360 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1818732517 |
|
|
Oct 09 11:07:09 PM UTC 24 |
Oct 09 11:21:12 PM UTC 24 |
15846775594 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.4218359537 |
|
|
Oct 09 11:15:02 PM UTC 24 |
Oct 09 11:21:14 PM UTC 24 |
4302935097 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1648453383 |
|
|
Oct 09 11:19:59 PM UTC 24 |
Oct 09 11:21:19 PM UTC 24 |
1539897086 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3039485301 |
|
|
Oct 09 11:13:38 PM UTC 24 |
Oct 09 11:21:24 PM UTC 24 |
3681746293 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.4063229359 |
|
|
Oct 09 11:15:11 PM UTC 24 |
Oct 09 11:21:27 PM UTC 24 |
4619917463 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.1717943795 |
|
|
Oct 09 11:21:15 PM UTC 24 |
Oct 09 11:21:28 PM UTC 24 |
226389921 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2252470105 |
|
|
Oct 09 11:21:19 PM UTC 24 |
Oct 09 11:21:30 PM UTC 24 |
50596559 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.808677062 |
|
|
Oct 09 11:17:38 PM UTC 24 |
Oct 09 11:21:50 PM UTC 24 |
6974773781 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.2211998237 |
|
|
Oct 09 11:21:40 PM UTC 24 |
Oct 09 11:22:09 PM UTC 24 |
213028384 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.1444720619 |
|
|
Oct 09 11:21:35 PM UTC 24 |
Oct 09 11:22:17 PM UTC 24 |
308432508 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2365159929 |
|
|
Oct 09 11:21:51 PM UTC 24 |
Oct 09 11:22:17 PM UTC 24 |
228700352 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1489783751 |
|
|
Oct 09 11:21:27 PM UTC 24 |
Oct 09 11:22:19 PM UTC 24 |
1159253934 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.940467419 |
|
|
Oct 09 11:21:53 PM UTC 24 |
Oct 09 11:22:21 PM UTC 24 |
383470469 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3120867120 |
|
|
Oct 09 11:17:38 PM UTC 24 |
Oct 09 11:22:23 PM UTC 24 |
2860647465 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2476529752 |
|
|
Oct 09 11:21:50 PM UTC 24 |
Oct 09 11:22:27 PM UTC 24 |
285509543 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2030758530 |
|
|
Oct 09 11:17:19 PM UTC 24 |
Oct 09 11:22:33 PM UTC 24 |
2786551247 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2161386881 |
|
|
Oct 09 11:21:21 PM UTC 24 |
Oct 09 11:22:38 PM UTC 24 |
7342446001 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1193649852 |
|
|
Oct 09 11:21:22 PM UTC 24 |
Oct 09 11:22:58 PM UTC 24 |
5267965629 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3257462789 |
|
|
Oct 09 11:22:14 PM UTC 24 |
Oct 09 11:23:03 PM UTC 24 |
1253618007 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.4043278700 |
|
|
Oct 09 11:23:02 PM UTC 24 |
Oct 09 11:23:12 PM UTC 24 |
42185000 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2228867775 |
|
|
Oct 09 11:20:49 PM UTC 24 |
Oct 09 11:23:19 PM UTC 24 |
382928599 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1139507244 |
|
|
Oct 09 11:15:29 PM UTC 24 |
Oct 09 11:23:25 PM UTC 24 |
7798114587 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.1175399253 |
|
|
Oct 09 11:17:58 PM UTC 24 |
Oct 09 11:23:27 PM UTC 24 |
3817451220 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3875085225 |
|
|
Oct 09 11:06:28 PM UTC 24 |
Oct 09 11:23:28 PM UTC 24 |
78602567922 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3665709065 |
|
|
Oct 09 11:23:21 PM UTC 24 |
Oct 09 11:23:31 PM UTC 24 |
52088758 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.500037009 |
|
|
Oct 09 11:16:14 PM UTC 24 |
Oct 09 11:23:43 PM UTC 24 |
22095310909 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1402137787 |
|
|
Oct 09 11:22:42 PM UTC 24 |
Oct 09 11:23:55 PM UTC 24 |
240940895 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1731883223 |
|
|
Oct 09 11:20:14 PM UTC 24 |
Oct 09 11:23:56 PM UTC 24 |
306182616 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.406516797 |
|
|
Oct 09 11:14:26 PM UTC 24 |
Oct 09 11:23:56 PM UTC 24 |
48460928338 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.202234382 |
|
|
Oct 09 11:23:39 PM UTC 24 |
Oct 09 11:24:14 PM UTC 24 |
264735004 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3314085334 |
|
|
Oct 09 11:21:06 PM UTC 24 |
Oct 09 11:24:18 PM UTC 24 |
2705135002 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4107646526 |
|
|
Oct 09 11:15:09 PM UTC 24 |
Oct 09 11:24:28 PM UTC 24 |
7070704558 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1324537667 |
|
|
Oct 09 11:23:53 PM UTC 24 |
Oct 09 11:24:30 PM UTC 24 |
275765530 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3014930638 |
|
|
Oct 09 11:23:49 PM UTC 24 |
Oct 09 11:24:39 PM UTC 24 |
414811750 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3217749159 |
|
|
Oct 09 11:24:18 PM UTC 24 |
Oct 09 11:24:46 PM UTC 24 |
251529371 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2083542911 |
|
|
Oct 09 11:22:32 PM UTC 24 |
Oct 09 11:24:55 PM UTC 24 |
1454044536 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.3839180129 |
|
|
Oct 09 11:05:37 PM UTC 24 |
Oct 09 11:24:58 PM UTC 24 |
8532912752 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.718101520 |
|
|
Oct 09 11:23:35 PM UTC 24 |
Oct 09 11:25:01 PM UTC 24 |
6043683168 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3186158398 |
|
|
Oct 09 11:24:37 PM UTC 24 |
Oct 09 11:25:04 PM UTC 24 |
505686807 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1720676018 |
|
|
Oct 09 11:17:23 PM UTC 24 |
Oct 09 11:25:05 PM UTC 24 |
4228902254 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.3136441366 |
|
|
Oct 09 11:23:26 PM UTC 24 |
Oct 09 11:25:09 PM UTC 24 |
7284503811 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2754097408 |
|
|
Oct 09 11:24:20 PM UTC 24 |
Oct 09 11:25:09 PM UTC 24 |
934141449 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.676311531 |
|
|
Oct 09 11:03:04 PM UTC 24 |
Oct 09 11:25:27 PM UTC 24 |
11231919742 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3282785318 |
|
|
Oct 09 11:25:26 PM UTC 24 |
Oct 09 11:25:35 PM UTC 24 |
39100963 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3047837160 |
|
|
Oct 09 11:25:27 PM UTC 24 |
Oct 09 11:25:37 PM UTC 24 |
41458699 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3552714323 |
|
|
Oct 09 11:24:19 PM UTC 24 |
Oct 09 11:25:49 PM UTC 24 |
2624345943 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.1468733340 |
|
|
Oct 09 11:22:40 PM UTC 24 |
Oct 09 11:26:11 PM UTC 24 |
2967637871 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.3752834286 |
|
|
Oct 09 11:25:58 PM UTC 24 |
Oct 09 11:26:15 PM UTC 24 |
113174422 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.2224286659 |
|
|
Oct 09 11:20:23 PM UTC 24 |
Oct 09 11:26:19 PM UTC 24 |
11265290751 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.840644128 |
|
|
Oct 09 11:25:51 PM UTC 24 |
Oct 09 11:26:27 PM UTC 24 |
380522877 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.1166090399 |
|
|
Oct 09 11:25:31 PM UTC 24 |
Oct 09 11:26:47 PM UTC 24 |
7699375779 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3286965033 |
|
|
Oct 09 11:20:53 PM UTC 24 |
Oct 09 11:27:01 PM UTC 24 |
4229294840 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.324325472 |
|
|
Oct 09 11:12:16 PM UTC 24 |
Oct 09 11:27:03 PM UTC 24 |
50028603715 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.504474624 |
|
|
Oct 09 11:24:53 PM UTC 24 |
Oct 09 11:27:04 PM UTC 24 |
1663615117 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3203468858 |
|
|
Oct 09 11:26:43 PM UTC 24 |
Oct 09 11:27:11 PM UTC 24 |
282118880 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3046110762 |
|
|
Oct 09 11:27:08 PM UTC 24 |
Oct 09 11:27:22 PM UTC 24 |
52884069 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.63658859 |
|
|
Oct 09 11:25:32 PM UTC 24 |
Oct 09 11:27:23 PM UTC 24 |
5847554947 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1163016200 |
|
|
Oct 09 11:13:58 PM UTC 24 |
Oct 09 11:27:43 PM UTC 24 |
10539327243 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.439294372 |
|
|
Oct 09 11:21:40 PM UTC 24 |
Oct 09 11:27:48 PM UTC 24 |
24190528634 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2759691942 |
|
|
Oct 09 11:26:34 PM UTC 24 |
Oct 09 11:27:59 PM UTC 24 |
889768407 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1689655408 |
|
|
Oct 09 11:27:21 PM UTC 24 |
Oct 09 11:28:03 PM UTC 24 |
777285054 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.3793571361 |
|
|
Oct 09 11:20:11 PM UTC 24 |
Oct 09 11:28:13 PM UTC 24 |
4495427802 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1729776633 |
|
|
Oct 09 11:26:50 PM UTC 24 |
Oct 09 11:28:14 PM UTC 24 |
2278729045 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2104853306 |
|
|
Oct 09 11:27:26 PM UTC 24 |
Oct 09 11:28:28 PM UTC 24 |
1411829751 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.3615450557 |
|
|
Oct 09 11:28:26 PM UTC 24 |
Oct 09 11:28:36 PM UTC 24 |
164079372 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2372799545 |
|
|
Oct 09 11:28:37 PM UTC 24 |
Oct 09 11:28:47 PM UTC 24 |
40157441 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2341860986 |
|
|
Oct 09 11:14:36 PM UTC 24 |
Oct 09 11:30:47 PM UTC 24 |
66546405840 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.1582527641 |
|
|
Oct 09 11:16:12 PM UTC 24 |
Oct 09 11:28:55 PM UTC 24 |
76339246864 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1039117122 |
|
|
Oct 09 11:16:24 PM UTC 24 |
Oct 09 11:29:10 PM UTC 24 |
51307851027 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.1302092013 |
|
|
Oct 09 11:18:49 PM UTC 24 |
Oct 09 11:29:12 PM UTC 24 |
30690821924 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1766614744 |
|
|
Oct 09 11:13:50 PM UTC 24 |
Oct 09 11:29:19 PM UTC 24 |
16665375866 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.4066955137 |
|
|
Oct 09 11:29:00 PM UTC 24 |
Oct 09 11:29:56 PM UTC 24 |
1041792352 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.4930639 |
|
|
Oct 09 11:21:00 PM UTC 24 |
Oct 09 11:30:03 PM UTC 24 |
6350360110 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.2130524392 |
|
|
Oct 09 11:28:37 PM UTC 24 |
Oct 09 11:30:12 PM UTC 24 |
9371330791 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3419424422 |
|
|
Oct 09 11:28:51 PM UTC 24 |
Oct 09 11:30:13 PM UTC 24 |
5436046709 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.4080318528 |
|
|
Oct 09 11:24:41 PM UTC 24 |
Oct 09 11:30:15 PM UTC 24 |
3579046549 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.3019660326 |
|
|
Oct 09 11:17:40 PM UTC 24 |
Oct 09 11:30:17 PM UTC 24 |
6016611956 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1005102123 |
|
|
Oct 09 11:22:53 PM UTC 24 |
Oct 09 11:30:22 PM UTC 24 |
4780815900 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.3050945687 |
|
|
Oct 09 11:29:10 PM UTC 24 |
Oct 09 11:30:24 PM UTC 24 |
601184444 ps |