| T1563 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1417900807 |
|
|
Oct 09 11:42:03 PM UTC 24 |
Oct 10 12:00:56 AM UTC 24 |
9897020206 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3530906715 |
|
|
Oct 09 11:50:12 PM UTC 24 |
Oct 10 12:00:58 AM UTC 24 |
5521200973 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.1928950 |
|
|
Oct 10 12:00:05 AM UTC 24 |
Oct 10 12:00:59 AM UTC 24 |
422635935 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.2542064634 |
|
|
Oct 10 12:00:22 AM UTC 24 |
Oct 10 12:01:02 AM UTC 24 |
194571258 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.167790083 |
|
|
Oct 10 12:00:34 AM UTC 24 |
Oct 10 12:01:04 AM UTC 24 |
659020301 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2193790279 |
|
|
Oct 09 11:54:46 PM UTC 24 |
Oct 10 12:01:20 AM UTC 24 |
8812317934 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2426965567 |
|
|
Oct 09 11:59:46 PM UTC 24 |
Oct 10 12:01:26 AM UTC 24 |
8914839371 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2788621375 |
|
|
Oct 09 11:38:58 PM UTC 24 |
Oct 10 12:01:30 AM UTC 24 |
88986290072 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.270434108 |
|
|
Oct 10 12:01:22 AM UTC 24 |
Oct 10 12:01:32 AM UTC 24 |
43766033 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.3377195295 |
|
|
Oct 10 12:01:21 AM UTC 24 |
Oct 10 12:01:34 AM UTC 24 |
168723267 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.218208923 |
|
|
Oct 10 12:00:08 AM UTC 24 |
Oct 10 12:01:35 AM UTC 24 |
2193461662 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.245837406 |
|
|
Oct 10 12:00:15 AM UTC 24 |
Oct 10 12:01:37 AM UTC 24 |
3122998307 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.2341911841 |
|
|
Oct 10 12:00:18 AM UTC 24 |
Oct 10 12:01:41 AM UTC 24 |
2394051677 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2761926512 |
|
|
Oct 10 12:00:11 AM UTC 24 |
Oct 10 12:01:42 AM UTC 24 |
1605089489 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3195897241 |
|
|
Oct 09 11:59:53 PM UTC 24 |
Oct 10 12:01:53 AM UTC 24 |
6106199726 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.2134664654 |
|
|
Oct 10 12:02:06 AM UTC 24 |
Oct 10 12:02:21 AM UTC 24 |
58732373 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.4263010541 |
|
|
Oct 09 11:58:12 PM UTC 24 |
Oct 10 12:02:30 AM UTC 24 |
22118592835 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1776615707 |
|
|
Oct 10 12:01:05 AM UTC 24 |
Oct 10 12:02:33 AM UTC 24 |
1029323141 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1866264217 |
|
|
Oct 10 12:02:14 AM UTC 24 |
Oct 10 12:02:36 AM UTC 24 |
110377194 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.668206386 |
|
|
Oct 09 11:57:41 PM UTC 24 |
Oct 10 12:02:42 AM UTC 24 |
3858669088 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.495677118 |
|
|
Oct 10 12:01:54 AM UTC 24 |
Oct 10 12:02:45 AM UTC 24 |
688730085 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3086308990 |
|
|
Oct 10 12:01:47 AM UTC 24 |
Oct 10 12:02:47 AM UTC 24 |
500201429 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.3323823075 |
|
|
Oct 10 12:01:42 AM UTC 24 |
Oct 10 12:03:01 AM UTC 24 |
1847537401 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.161568828 |
|
|
Oct 09 11:45:47 PM UTC 24 |
Oct 10 12:03:08 AM UTC 24 |
92985151749 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.3257070521 |
|
|
Oct 10 12:01:58 AM UTC 24 |
Oct 10 12:03:13 AM UTC 24 |
1849331771 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1875660740 |
|
|
Oct 10 12:02:52 AM UTC 24 |
Oct 10 12:03:16 AM UTC 24 |
48428300 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.2125940984 |
|
|
Oct 10 12:02:01 AM UTC 24 |
Oct 10 12:03:17 AM UTC 24 |
2105906642 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1971327087 |
|
|
Oct 10 12:01:26 AM UTC 24 |
Oct 10 12:03:18 AM UTC 24 |
6537273406 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3975122351 |
|
|
Oct 10 12:03:10 AM UTC 24 |
Oct 10 12:03:19 AM UTC 24 |
44111059 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.825959728 |
|
|
Oct 10 12:01:24 AM UTC 24 |
Oct 10 12:03:23 AM UTC 24 |
7472683675 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.3429653693 |
|
|
Oct 10 12:03:09 AM UTC 24 |
Oct 10 12:03:23 AM UTC 24 |
203785383 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1332312119 |
|
|
Oct 09 11:54:35 PM UTC 24 |
Oct 10 12:03:24 AM UTC 24 |
5400339799 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3571807300 |
|
|
Oct 09 11:56:36 PM UTC 24 |
Oct 10 12:03:38 AM UTC 24 |
22534882192 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.3189728583 |
|
|
Oct 10 12:03:39 AM UTC 24 |
Oct 10 12:03:53 AM UTC 24 |
77537744 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.2211039933 |
|
|
Oct 10 12:02:56 AM UTC 24 |
Oct 10 12:03:56 AM UTC 24 |
1454299726 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.3129520845 |
|
|
Oct 10 12:03:42 AM UTC 24 |
Oct 10 12:03:58 AM UTC 24 |
157042838 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.1373484958 |
|
|
Oct 10 12:03:42 AM UTC 24 |
Oct 10 12:04:11 AM UTC 24 |
318027969 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.3612842492 |
|
|
Oct 09 11:59:05 PM UTC 24 |
Oct 10 12:04:20 AM UTC 24 |
3455179936 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2327641988 |
|
|
Oct 10 12:04:16 AM UTC 24 |
Oct 10 12:04:28 AM UTC 24 |
36482915 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2357900322 |
|
|
Oct 09 11:59:16 PM UTC 24 |
Oct 10 12:04:40 AM UTC 24 |
835636052 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.2519812976 |
|
|
Oct 10 12:02:43 AM UTC 24 |
Oct 10 12:04:47 AM UTC 24 |
3136870508 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1082030322 |
|
|
Oct 10 12:03:34 AM UTC 24 |
Oct 10 12:04:48 AM UTC 24 |
2056951495 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2526667004 |
|
|
Oct 10 12:04:01 AM UTC 24 |
Oct 10 12:04:52 AM UTC 24 |
1173916592 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1073466632 |
|
|
Oct 10 12:03:31 AM UTC 24 |
Oct 10 12:04:57 AM UTC 24 |
6003831436 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.4104122028 |
|
|
Oct 10 12:03:24 AM UTC 24 |
Oct 10 12:04:58 AM UTC 24 |
7240102999 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.2731948447 |
|
|
Oct 10 12:03:46 AM UTC 24 |
Oct 10 12:05:06 AM UTC 24 |
2175075235 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.247126894 |
|
|
Oct 09 11:53:48 PM UTC 24 |
Oct 10 12:05:08 AM UTC 24 |
73556433492 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3014331770 |
|
|
Oct 09 11:59:16 PM UTC 24 |
Oct 10 12:05:09 AM UTC 24 |
7946288119 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1819312762 |
|
|
Oct 10 12:01:19 AM UTC 24 |
Oct 10 12:05:12 AM UTC 24 |
3340460054 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3514118311 |
|
|
Oct 10 12:04:59 AM UTC 24 |
Oct 10 12:05:13 AM UTC 24 |
207861850 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2846398791 |
|
|
Oct 09 11:08:11 PM UTC 24 |
Oct 10 12:05:16 AM UTC 24 |
25848234946 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.3477394153 |
|
|
Oct 10 12:00:10 AM UTC 24 |
Oct 10 12:05:20 AM UTC 24 |
17748584789 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3421895909 |
|
|
Oct 10 12:05:09 AM UTC 24 |
Oct 10 12:05:21 AM UTC 24 |
54328957 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.457595058 |
|
|
Oct 10 12:00:36 AM UTC 24 |
Oct 10 12:05:29 AM UTC 24 |
2816874247 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2864534928 |
|
|
Oct 10 12:05:22 AM UTC 24 |
Oct 10 12:05:43 AM UTC 24 |
218805051 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.1990408379 |
|
|
Oct 09 11:59:30 PM UTC 24 |
Oct 10 12:05:44 AM UTC 24 |
3902798168 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.2732311790 |
|
|
Oct 09 11:56:16 PM UTC 24 |
Oct 10 12:05:49 AM UTC 24 |
31288904148 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.972385228 |
|
|
Oct 09 11:29:43 PM UTC 24 |
Oct 10 12:05:54 AM UTC 24 |
110165028747 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.610928273 |
|
|
Oct 10 12:05:36 AM UTC 24 |
Oct 10 12:06:09 AM UTC 24 |
862085826 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1315763618 |
|
|
Oct 09 11:57:33 PM UTC 24 |
Oct 10 12:06:09 AM UTC 24 |
10047363272 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1470853083 |
|
|
Oct 10 12:03:01 AM UTC 24 |
Oct 10 12:06:17 AM UTC 24 |
2948885790 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.4080105151 |
|
|
Oct 10 12:05:44 AM UTC 24 |
Oct 10 12:06:19 AM UTC 24 |
567079219 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.408280827 |
|
|
Oct 10 12:05:42 AM UTC 24 |
Oct 10 12:06:20 AM UTC 24 |
218063141 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.36208692 |
|
|
Oct 10 12:05:21 AM UTC 24 |
Oct 10 12:06:28 AM UTC 24 |
2058163908 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2533174441 |
|
|
Oct 10 12:05:15 AM UTC 24 |
Oct 10 12:06:37 AM UTC 24 |
5822975281 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.1512594689 |
|
|
Oct 10 12:06:33 AM UTC 24 |
Oct 10 12:06:41 AM UTC 24 |
43463050 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1473121430 |
|
|
Oct 10 12:06:33 AM UTC 24 |
Oct 10 12:06:41 AM UTC 24 |
42838873 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1968179948 |
|
|
Oct 09 11:50:10 PM UTC 24 |
Oct 10 12:06:46 AM UTC 24 |
17579452710 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.1800288672 |
|
|
Oct 10 12:04:18 AM UTC 24 |
Oct 10 12:06:57 AM UTC 24 |
1855966857 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.3535964549 |
|
|
Oct 10 12:06:41 AM UTC 24 |
Oct 10 12:07:05 AM UTC 24 |
178175763 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.3606589691 |
|
|
Oct 10 12:05:38 AM UTC 24 |
Oct 10 12:07:08 AM UTC 24 |
2377862779 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1143366866 |
|
|
Oct 09 11:05:53 PM UTC 24 |
Oct 10 12:07:14 AM UTC 24 |
29727572999 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.2360842307 |
|
|
Oct 10 12:04:35 AM UTC 24 |
Oct 10 12:07:16 AM UTC 24 |
5093988607 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.3292629126 |
|
|
Oct 10 12:06:51 AM UTC 24 |
Oct 10 12:07:20 AM UTC 24 |
176199221 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.4175098416 |
|
|
Oct 10 12:05:11 AM UTC 24 |
Oct 10 12:07:27 AM UTC 24 |
10458418448 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.1098571916 |
|
|
Oct 10 12:05:32 AM UTC 24 |
Oct 10 12:07:32 AM UTC 24 |
2484232092 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3437666845 |
|
|
Oct 09 11:51:25 PM UTC 24 |
Oct 10 12:07:32 AM UTC 24 |
58042369402 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.2239669580 |
|
|
Oct 10 12:07:21 AM UTC 24 |
Oct 10 12:07:34 AM UTC 24 |
273038748 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.179589616 |
|
|
Oct 10 12:18:00 AM UTC 24 |
Oct 10 12:21:40 AM UTC 24 |
4636918379 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1765528645 |
|
|
Oct 10 12:07:37 AM UTC 24 |
Oct 10 12:07:45 AM UTC 24 |
86316521 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.3625808636 |
|
|
Oct 10 12:06:07 AM UTC 24 |
Oct 10 12:07:49 AM UTC 24 |
1104324031 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1610305667 |
|
|
Oct 10 12:07:58 AM UTC 24 |
Oct 10 12:08:10 AM UTC 24 |
163331522 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3843389756 |
|
|
Oct 10 12:04:21 AM UTC 24 |
Oct 10 12:08:11 AM UTC 24 |
704078518 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3418012908 |
|
|
Oct 10 12:07:32 AM UTC 24 |
Oct 10 12:08:16 AM UTC 24 |
207083597 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2480947992 |
|
|
Oct 10 12:08:09 AM UTC 24 |
Oct 10 12:08:19 AM UTC 24 |
42370198 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1957758493 |
|
|
Oct 10 12:07:05 AM UTC 24 |
Oct 10 12:08:23 AM UTC 24 |
1148828854 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1142014299 |
|
|
Oct 10 12:06:41 AM UTC 24 |
Oct 10 12:08:30 AM UTC 24 |
7471402704 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1048486841 |
|
|
Oct 10 12:06:41 AM UTC 24 |
Oct 10 12:08:32 AM UTC 24 |
4318978671 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3291108762 |
|
|
Oct 10 12:06:14 AM UTC 24 |
Oct 10 12:08:36 AM UTC 24 |
725343485 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.2733122627 |
|
|
Oct 10 12:08:36 AM UTC 24 |
Oct 10 12:08:47 AM UTC 24 |
145570983 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.313937849 |
|
|
Oct 10 12:07:28 AM UTC 24 |
Oct 10 12:08:53 AM UTC 24 |
2242874481 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.4284708503 |
|
|
Oct 09 11:57:17 PM UTC 24 |
Oct 10 12:09:20 AM UTC 24 |
16940355424 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.673245559 |
|
|
Oct 09 11:59:08 PM UTC 24 |
Oct 10 12:09:22 AM UTC 24 |
8593179301 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.2543906827 |
|
|
Oct 10 12:08:54 AM UTC 24 |
Oct 10 12:09:22 AM UTC 24 |
237027036 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1612200784 |
|
|
Oct 10 12:06:03 AM UTC 24 |
Oct 10 12:09:23 AM UTC 24 |
1185164926 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3458041099 |
|
|
Oct 10 12:01:09 AM UTC 24 |
Oct 10 12:09:26 AM UTC 24 |
4568922296 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.797782755 |
|
|
Oct 10 12:00:10 AM UTC 24 |
Oct 10 12:09:31 AM UTC 24 |
54825159602 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.4002471236 |
|
|
Oct 10 12:08:39 AM UTC 24 |
Oct 10 12:09:31 AM UTC 24 |
531401551 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.2132319295 |
|
|
Oct 10 12:04:51 AM UTC 24 |
Oct 10 12:09:41 AM UTC 24 |
4000141128 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.3593308952 |
|
|
Oct 10 12:08:57 AM UTC 24 |
Oct 10 12:09:51 AM UTC 24 |
1480746613 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.3169990318 |
|
|
Oct 10 12:09:07 AM UTC 24 |
Oct 10 12:09:54 AM UTC 24 |
404178185 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.3628221030 |
|
|
Oct 10 12:07:51 AM UTC 24 |
Oct 10 12:09:57 AM UTC 24 |
3019062278 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.4076225544 |
|
|
Oct 10 12:09:52 AM UTC 24 |
Oct 10 12:10:02 AM UTC 24 |
46766622 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3810648776 |
|
|
Oct 10 12:09:45 AM UTC 24 |
Oct 10 12:10:05 AM UTC 24 |
249410658 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.3925787501 |
|
|
Oct 10 12:09:16 AM UTC 24 |
Oct 10 12:10:06 AM UTC 24 |
798928220 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.920675566 |
|
|
Oct 10 12:09:56 AM UTC 24 |
Oct 10 12:10:07 AM UTC 24 |
46615491 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3992156819 |
|
|
Oct 10 12:03:04 AM UTC 24 |
Oct 10 12:10:15 AM UTC 24 |
4664906593 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4235113084 |
|
|
Oct 10 12:01:01 AM UTC 24 |
Oct 10 12:10:16 AM UTC 24 |
9220546672 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2184594922 |
|
|
Oct 10 12:08:11 AM UTC 24 |
Oct 10 12:10:20 AM UTC 24 |
10822480333 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.4275711458 |
|
|
Oct 10 12:08:34 AM UTC 24 |
Oct 10 12:10:27 AM UTC 24 |
5210235210 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3969198917 |
|
|
Oct 10 12:07:44 AM UTC 24 |
Oct 10 12:10:30 AM UTC 24 |
410442883 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.3232494744 |
|
|
Oct 09 11:04:25 PM UTC 24 |
Oct 10 12:10:32 AM UTC 24 |
41271038743 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.1064508886 |
|
|
Oct 10 12:10:40 AM UTC 24 |
Oct 10 12:10:57 AM UTC 24 |
226335181 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.3819650759 |
|
|
Oct 10 12:10:18 AM UTC 24 |
Oct 10 12:11:09 AM UTC 24 |
466657336 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3057865919 |
|
|
Oct 10 12:07:55 AM UTC 24 |
Oct 10 12:11:16 AM UTC 24 |
3848027288 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.751135312 |
|
|
Oct 10 12:10:30 AM UTC 24 |
Oct 10 12:11:18 AM UTC 24 |
754847556 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.3110897588 |
|
|
Oct 10 12:05:53 AM UTC 24 |
Oct 10 12:11:20 AM UTC 24 |
8408109074 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2297839000 |
|
|
Oct 10 12:10:43 AM UTC 24 |
Oct 10 12:11:24 AM UTC 24 |
285620005 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.18678721 |
|
|
Oct 10 12:10:21 AM UTC 24 |
Oct 10 12:11:29 AM UTC 24 |
566068471 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.3096175726 |
|
|
Oct 10 12:10:39 AM UTC 24 |
Oct 10 12:11:31 AM UTC 24 |
1716824234 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3544905539 |
|
|
Oct 10 12:11:37 AM UTC 24 |
Oct 10 12:11:45 AM UTC 24 |
50597870 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2430162834 |
|
|
Oct 10 12:11:36 AM UTC 24 |
Oct 10 12:11:50 AM UTC 24 |
192964052 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.1307684588 |
|
|
Oct 10 12:10:53 AM UTC 24 |
Oct 10 12:11:52 AM UTC 24 |
320327096 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3720483414 |
|
|
Oct 10 12:10:52 AM UTC 24 |
Oct 10 12:11:53 AM UTC 24 |
958926065 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3317456111 |
|
|
Oct 10 12:04:43 AM UTC 24 |
Oct 10 12:11:55 AM UTC 24 |
3546365244 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.748361550 |
|
|
Oct 10 12:01:54 AM UTC 24 |
Oct 10 12:11:56 AM UTC 24 |
40830854669 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.2583254946 |
|
|
Oct 10 12:06:18 AM UTC 24 |
Oct 10 12:11:57 AM UTC 24 |
4081726352 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1135702184 |
|
|
Oct 10 12:10:13 AM UTC 24 |
Oct 10 12:12:11 AM UTC 24 |
5014123265 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.1611984514 |
|
|
Oct 10 12:11:52 AM UTC 24 |
Oct 10 12:12:14 AM UTC 24 |
192536247 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1006272316 |
|
|
Oct 10 12:11:29 AM UTC 24 |
Oct 10 12:12:43 AM UTC 24 |
218594906 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.2718634650 |
|
|
Oct 09 11:56:09 PM UTC 24 |
Oct 10 12:12:47 AM UTC 24 |
101320567891 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.311839753 |
|
|
Oct 10 12:12:16 AM UTC 24 |
Oct 10 12:12:49 AM UTC 24 |
809643530 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.4177932922 |
|
|
Oct 10 12:10:01 AM UTC 24 |
Oct 10 12:12:54 AM UTC 24 |
9690762000 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.3096838041 |
|
|
Oct 10 12:12:19 AM UTC 24 |
Oct 10 12:13:01 AM UTC 24 |
223565488 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.3552429019 |
|
|
Oct 10 12:12:12 AM UTC 24 |
Oct 10 12:13:03 AM UTC 24 |
840547486 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.1477254847 |
|
|
Oct 10 12:08:46 AM UTC 24 |
Oct 10 12:13:15 AM UTC 24 |
16912727582 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.2819412518 |
|
|
Oct 10 12:12:20 AM UTC 24 |
Oct 10 12:13:15 AM UTC 24 |
1373825642 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.2924241317 |
|
|
Oct 10 12:11:50 AM UTC 24 |
Oct 10 12:13:17 AM UTC 24 |
2479714946 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4122435397 |
|
|
Oct 10 12:11:44 AM UTC 24 |
Oct 10 12:13:17 AM UTC 24 |
6769424040 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2695726360 |
|
|
Oct 10 12:12:35 AM UTC 24 |
Oct 10 12:13:24 AM UTC 24 |
1042938942 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1138924274 |
|
|
Oct 10 12:13:23 AM UTC 24 |
Oct 10 12:13:31 AM UTC 24 |
42712977 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.530940727 |
|
|
Oct 10 12:13:19 AM UTC 24 |
Oct 10 12:13:34 AM UTC 24 |
223190774 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.608326554 |
|
|
Oct 10 12:07:56 AM UTC 24 |
Oct 10 12:13:37 AM UTC 24 |
4346059175 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.4094636117 |
|
|
Oct 10 12:11:40 AM UTC 24 |
Oct 10 12:14:07 AM UTC 24 |
9372048537 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.97734588 |
|
|
Oct 09 11:58:12 PM UTC 24 |
Oct 10 12:14:14 AM UTC 24 |
61115576171 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.623283967 |
|
|
Oct 10 12:10:54 AM UTC 24 |
Oct 10 12:14:28 AM UTC 24 |
2999392457 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3604549960 |
|
|
Oct 10 12:13:28 AM UTC 24 |
Oct 10 12:14:30 AM UTC 24 |
6403813628 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.3223553471 |
|
|
Oct 10 12:11:20 AM UTC 24 |
Oct 10 12:14:34 AM UTC 24 |
3019210328 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.155432871 |
|
|
Oct 10 12:13:39 AM UTC 24 |
Oct 10 12:14:43 AM UTC 24 |
548990095 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.3475458293 |
|
|
Oct 10 12:01:52 AM UTC 24 |
Oct 10 12:14:43 AM UTC 24 |
76735308916 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.4032148167 |
|
|
Oct 10 12:13:40 AM UTC 24 |
Oct 10 12:14:46 AM UTC 24 |
600044118 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.331087763 |
|
|
Oct 10 12:14:01 AM UTC 24 |
Oct 10 12:14:59 AM UTC 24 |
2125270321 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.152751115 |
|
|
Oct 10 12:07:40 AM UTC 24 |
Oct 10 12:15:01 AM UTC 24 |
8775447611 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.1034161023 |
|
|
Oct 10 12:14:29 AM UTC 24 |
Oct 10 12:15:09 AM UTC 24 |
370531502 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3257093715 |
|
|
Oct 10 12:12:16 AM UTC 24 |
Oct 10 12:15:10 AM UTC 24 |
12261894708 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.3060400564 |
|
|
Oct 10 12:14:37 AM UTC 24 |
Oct 10 12:15:16 AM UTC 24 |
225481904 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3590171757 |
|
|
Oct 10 12:14:52 AM UTC 24 |
Oct 10 12:15:19 AM UTC 24 |
142741662 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.595026089 |
|
|
Oct 10 12:15:09 AM UTC 24 |
Oct 10 12:15:20 AM UTC 24 |
142100518 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.1767773675 |
|
|
Oct 10 12:13:52 AM UTC 24 |
Oct 10 12:15:27 AM UTC 24 |
2146735163 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2725407626 |
|
|
Oct 10 12:13:35 AM UTC 24 |
Oct 10 12:15:32 AM UTC 24 |
4719325571 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3070333191 |
|
|
Oct 10 12:15:23 AM UTC 24 |
Oct 10 12:15:33 AM UTC 24 |
47191529 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.2491123501 |
|
|
Oct 10 12:15:06 AM UTC 24 |
Oct 10 12:15:46 AM UTC 24 |
255650121 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1461293507 |
|
|
Oct 09 11:52:00 PM UTC 24 |
Oct 10 12:15:46 AM UTC 24 |
94556075487 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.1062943737 |
|
|
Oct 10 12:09:47 AM UTC 24 |
Oct 10 12:16:07 AM UTC 24 |
2691962403 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.446271969 |
|
|
Oct 10 12:05:28 AM UTC 24 |
Oct 10 12:16:13 AM UTC 24 |
54058415781 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.4025590017 |
|
|
Oct 10 12:15:58 AM UTC 24 |
Oct 10 12:16:15 AM UTC 24 |
261855824 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.3852801218 |
|
|
Oct 10 12:10:26 AM UTC 24 |
Oct 10 12:16:16 AM UTC 24 |
21973069041 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1673344245 |
|
|
Oct 10 12:15:39 AM UTC 24 |
Oct 10 12:16:20 AM UTC 24 |
322934837 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.248426726 |
|
|
Oct 10 12:16:10 AM UTC 24 |
Oct 10 12:16:29 AM UTC 24 |
210553241 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1769305891 |
|
|
Oct 10 12:16:09 AM UTC 24 |
Oct 10 12:16:31 AM UTC 24 |
213374773 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.923182702 |
|
|
Oct 10 12:05:32 AM UTC 24 |
Oct 10 12:16:32 AM UTC 24 |
39008040267 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.2401564450 |
|
|
Oct 10 12:07:00 AM UTC 24 |
Oct 10 12:16:42 AM UTC 24 |
59725680754 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.2758398589 |
|
|
Oct 10 12:15:51 AM UTC 24 |
Oct 10 12:16:45 AM UTC 24 |
556785701 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.1647999792 |
|
|
Oct 10 12:15:33 AM UTC 24 |
Oct 10 12:16:57 AM UTC 24 |
2550142114 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2274675305 |
|
|
Oct 10 12:15:23 AM UTC 24 |
Oct 10 12:17:03 AM UTC 24 |
10359697755 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.4061413148 |
|
|
Oct 10 12:16:54 AM UTC 24 |
Oct 10 12:17:05 AM UTC 24 |
39397387 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.3831224115 |
|
|
Oct 10 12:16:55 AM UTC 24 |
Oct 10 12:17:05 AM UTC 24 |
43749028 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1292158227 |
|
|
Oct 10 12:09:45 AM UTC 24 |
Oct 10 12:17:06 AM UTC 24 |
6071372243 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.834103950 |
|
|
Oct 09 11:11:07 PM UTC 24 |
Oct 10 12:17:07 AM UTC 24 |
31307594513 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.2362570874 |
|
|
Oct 10 12:16:31 AM UTC 24 |
Oct 10 12:17:10 AM UTC 24 |
261354000 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3409517176 |
|
|
Oct 10 12:15:31 AM UTC 24 |
Oct 10 12:17:21 AM UTC 24 |
5441842558 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3283804583 |
|
|
Oct 10 12:17:09 AM UTC 24 |
Oct 10 12:17:29 AM UTC 24 |
125730971 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.430248865 |
|
|
Oct 09 11:40:00 PM UTC 24 |
Oct 10 12:17:38 AM UTC 24 |
17297318270 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2817096417 |
|
|
Oct 10 12:16:42 AM UTC 24 |
Oct 10 12:17:44 AM UTC 24 |
328039152 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.2867417949 |
|
|
Oct 10 12:17:21 AM UTC 24 |
Oct 10 12:17:47 AM UTC 24 |
230258296 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.1364691257 |
|
|
Oct 10 12:17:29 AM UTC 24 |
Oct 10 12:17:51 AM UTC 24 |
161718470 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.250270121 |
|
|
Oct 10 12:17:26 AM UTC 24 |
Oct 10 12:18:03 AM UTC 24 |
3228847195 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.1630872952 |
|
|
Oct 10 12:17:44 AM UTC 24 |
Oct 10 12:18:08 AM UTC 24 |
345357539 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1141555470 |
|
|
Oct 10 12:17:33 AM UTC 24 |
Oct 10 12:18:13 AM UTC 24 |
792419355 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1265886180 |
|
|
Oct 10 12:12:36 AM UTC 24 |
Oct 10 12:18:24 AM UTC 24 |
8577411331 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3917817494 |
|
|
Oct 10 12:17:53 AM UTC 24 |
Oct 10 12:18:32 AM UTC 24 |
754589767 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3392293766 |
|
|
Oct 10 12:09:45 AM UTC 24 |
Oct 10 12:18:35 AM UTC 24 |
13003945664 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.749284602 |
|
|
Oct 10 12:17:29 AM UTC 24 |
Oct 10 12:18:36 AM UTC 24 |
896713081 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.3549151272 |
|
|
Oct 10 12:18:29 AM UTC 24 |
Oct 10 12:18:42 AM UTC 24 |
162543832 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1435142366 |
|
|
Oct 10 12:18:32 AM UTC 24 |
Oct 10 12:18:42 AM UTC 24 |
37544766 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.3327704713 |
|
|
Oct 10 12:03:41 AM UTC 24 |
Oct 10 12:18:45 AM UTC 24 |
80557521565 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.114982420 |
|
|
Oct 10 12:17:06 AM UTC 24 |
Oct 10 12:18:46 AM UTC 24 |
6609848564 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2158338 |
|
|
Oct 10 12:16:55 AM UTC 24 |
Oct 10 12:18:57 AM UTC 24 |
8079013777 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1557570446 |
|
|
Oct 10 12:14:58 AM UTC 24 |
Oct 10 12:19:01 AM UTC 24 |
4272324619 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.1379425435 |
|
|
Oct 10 12:10:28 AM UTC 24 |
Oct 10 12:19:11 AM UTC 24 |
27362574435 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4153274190 |
|
|
Oct 09 11:15:36 PM UTC 24 |
Oct 10 12:19:33 AM UTC 24 |
28408468048 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.518000379 |
|
|
Oct 10 12:16:36 AM UTC 24 |
Oct 10 12:19:50 AM UTC 24 |
4899463494 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1622854567 |
|
|
Oct 10 12:19:36 AM UTC 24 |
Oct 10 12:19:52 AM UTC 24 |
322939844 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2907512694 |
|
|
Oct 10 12:19:23 AM UTC 24 |
Oct 10 12:19:55 AM UTC 24 |
149502199 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3363981503 |
|
|
Oct 10 12:18:36 AM UTC 24 |
Oct 10 12:19:56 AM UTC 24 |
8042104768 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.1210555257 |
|
|
Oct 10 12:19:21 AM UTC 24 |
Oct 10 12:20:06 AM UTC 24 |
396298050 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.2726600308 |
|
|
Oct 10 12:19:08 AM UTC 24 |
Oct 10 12:20:07 AM UTC 24 |
1188062965 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1237230335 |
|
|
Oct 10 12:14:54 AM UTC 24 |
Oct 10 12:20:11 AM UTC 24 |
7953920025 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.24701559 |
|
|
Oct 10 12:18:59 AM UTC 24 |
Oct 10 12:20:11 AM UTC 24 |
614319641 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1680664639 |
|
|
Oct 10 12:18:56 AM UTC 24 |
Oct 10 12:20:13 AM UTC 24 |
1501419284 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4182871977 |
|
|
Oct 10 12:18:49 AM UTC 24 |
Oct 10 12:20:13 AM UTC 24 |
4915350400 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.3252207405 |
|
|
Oct 10 12:13:07 AM UTC 24 |
Oct 10 12:20:18 AM UTC 24 |
10465284102 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.3928807069 |
|
|
Oct 10 12:20:19 AM UTC 24 |
Oct 10 12:20:29 AM UTC 24 |
44292772 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.2285903760 |
|
|
Oct 10 12:15:41 AM UTC 24 |
Oct 10 12:20:36 AM UTC 24 |
27682465659 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.647615244 |
|
|
Oct 10 12:20:30 AM UTC 24 |
Oct 10 12:20:39 AM UTC 24 |
44761423 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.1141575144 |
|
|
Oct 10 12:03:42 AM UTC 24 |
Oct 10 12:20:40 AM UTC 24 |
61235040879 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2492111701 |
|
|
Oct 10 12:19:06 AM UTC 24 |
Oct 10 12:20:42 AM UTC 24 |
913103992 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.2706329177 |
|
|
Oct 09 11:04:35 PM UTC 24 |
Oct 10 12:20:46 AM UTC 24 |
28337210006 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.1627059481 |
|
|
Oct 10 12:20:34 AM UTC 24 |
Oct 10 12:20:49 AM UTC 24 |
340064592 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.1365899123 |
|
|
Oct 10 12:20:53 AM UTC 24 |
Oct 10 12:21:08 AM UTC 24 |
241241665 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.690082134 |
|
|
Oct 10 12:21:00 AM UTC 24 |
Oct 10 12:21:15 AM UTC 24 |
226458874 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.2525004382 |
|
|
Oct 10 12:20:37 AM UTC 24 |
Oct 10 12:21:16 AM UTC 24 |
410105454 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2631661124 |
|
|
Oct 10 12:13:00 AM UTC 24 |
Oct 10 12:21:36 AM UTC 24 |
5084738541 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.1333062674 |
|
|
Oct 10 12:21:05 AM UTC 24 |
Oct 10 12:21:42 AM UTC 24 |
685651898 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.2388928755 |
|
|
Oct 10 12:16:40 AM UTC 24 |
Oct 10 12:21:44 AM UTC 24 |
8048636754 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.1177023451 |
|
|
Oct 10 12:21:03 AM UTC 24 |
Oct 10 12:21:46 AM UTC 24 |
1102602687 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.309460122 |
|
|
Oct 10 12:20:13 AM UTC 24 |
Oct 10 12:21:50 AM UTC 24 |
217529389 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.823646705 |
|
|
Oct 10 12:07:05 AM UTC 24 |
Oct 10 12:21:50 AM UTC 24 |
61423411905 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3111179948 |
|
|
Oct 10 12:16:40 AM UTC 24 |
Oct 10 12:21:52 AM UTC 24 |
6415438531 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3912531661 |
|
|
Oct 10 12:19:57 AM UTC 24 |
Oct 10 12:22:00 AM UTC 24 |
3364718749 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.2705613840 |
|
|
Oct 10 12:19:04 AM UTC 24 |
Oct 10 12:22:05 AM UTC 24 |
12000534219 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.4288242724 |
|
|
Oct 10 12:21:10 AM UTC 24 |
Oct 10 12:22:07 AM UTC 24 |
1208657083 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.3247931954 |
|
|
Oct 10 12:22:01 AM UTC 24 |
Oct 10 12:22:11 AM UTC 24 |
42602359 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3205228949 |
|
|
Oct 10 12:22:03 AM UTC 24 |
Oct 10 12:22:14 AM UTC 24 |
52182878 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2888643772 |
|
|
Oct 10 12:13:13 AM UTC 24 |
Oct 10 12:22:17 AM UTC 24 |
4524739145 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.3490632427 |
|
|
Oct 10 12:20:30 AM UTC 24 |
Oct 10 12:22:18 AM UTC 24 |
9872967279 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1835520561 |
|
|
Oct 10 12:20:34 AM UTC 24 |
Oct 10 12:22:23 AM UTC 24 |
5133844436 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.3936670038 |
|
|
Oct 10 12:22:06 AM UTC 24 |
Oct 10 12:22:28 AM UTC 24 |
143568971 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.2884281568 |
|
|
Oct 10 12:15:40 AM UTC 24 |
Oct 10 12:22:39 AM UTC 24 |
28471975140 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3173889305 |
|
|
Oct 10 12:22:37 AM UTC 24 |
Oct 10 12:22:53 AM UTC 24 |
117279218 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.995332740 |
|
|
Oct 10 12:15:07 AM UTC 24 |
Oct 10 12:22:56 AM UTC 24 |
4129249260 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.2177537960 |
|
|
Oct 10 12:22:12 AM UTC 24 |
Oct 10 12:22:57 AM UTC 24 |
469309730 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.3044665963 |
|
|
Oct 10 12:22:32 AM UTC 24 |
Oct 10 12:23:10 AM UTC 24 |
296418606 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.611180532 |
|
|
Oct 10 12:20:15 AM UTC 24 |
Oct 10 12:23:18 AM UTC 24 |
1771846148 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.1764270290 |
|
|
Oct 10 12:22:22 AM UTC 24 |
Oct 10 12:23:22 AM UTC 24 |
950617541 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2908133647 |
|
|
Oct 10 12:18:16 AM UTC 24 |
Oct 10 12:23:25 AM UTC 24 |
1342979728 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3584087296 |
|
|
Oct 10 12:22:33 AM UTC 24 |
Oct 10 12:23:29 AM UTC 24 |
1272623903 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2118338445 |
|
|
Oct 10 12:23:17 AM UTC 24 |
Oct 10 12:23:30 AM UTC 24 |
199552867 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3795341028 |
|
|
Oct 10 12:23:21 AM UTC 24 |
Oct 10 12:23:33 AM UTC 24 |
55976416 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1227631238 |
|
|
Oct 10 12:22:38 AM UTC 24 |
Oct 10 12:23:33 AM UTC 24 |
1222508019 ps |