| T2025 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1434369703 |
|
|
Oct 10 12:40:50 AM UTC 24 |
Oct 10 12:41:00 AM UTC 24 |
43851805 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1237833633 |
|
|
Oct 10 12:36:03 AM UTC 24 |
Oct 10 12:41:02 AM UTC 24 |
1061342443 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.2856158047 |
|
|
Oct 10 12:26:24 AM UTC 24 |
Oct 10 12:41:09 AM UTC 24 |
58820804455 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.641096715 |
|
|
Oct 10 12:37:16 AM UTC 24 |
Oct 10 12:41:23 AM UTC 24 |
2638382648 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.71741360 |
|
|
Oct 10 12:29:20 AM UTC 24 |
Oct 10 12:41:24 AM UTC 24 |
22319657845 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.535506218 |
|
|
Oct 10 12:37:45 AM UTC 24 |
Oct 10 12:41:24 AM UTC 24 |
14572875716 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2619321648 |
|
|
Oct 10 12:39:45 AM UTC 24 |
Oct 10 12:41:29 AM UTC 24 |
6050106489 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4004585182 |
|
|
Oct 10 12:40:47 AM UTC 24 |
Oct 10 12:41:34 AM UTC 24 |
48209044 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2771783096 |
|
|
Oct 10 12:41:01 AM UTC 24 |
Oct 10 12:41:37 AM UTC 24 |
876075130 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.4294360927 |
|
|
Oct 10 12:39:43 AM UTC 24 |
Oct 10 12:41:41 AM UTC 24 |
7586597355 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.2744876231 |
|
|
Oct 10 12:39:05 AM UTC 24 |
Oct 10 12:41:44 AM UTC 24 |
1857506979 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.108924449 |
|
|
Oct 10 12:41:26 AM UTC 24 |
Oct 10 12:41:49 AM UTC 24 |
180284575 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.344401461 |
|
|
Oct 10 12:37:11 AM UTC 24 |
Oct 10 12:41:51 AM UTC 24 |
609667727 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1728278160 |
|
|
Oct 10 12:33:49 AM UTC 24 |
Oct 10 12:41:53 AM UTC 24 |
2089077411 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.139324816 |
|
|
Oct 10 12:41:01 AM UTC 24 |
Oct 10 12:41:54 AM UTC 24 |
567706418 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.1969909764 |
|
|
Oct 10 12:41:47 AM UTC 24 |
Oct 10 12:41:58 AM UTC 24 |
95573184 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.4287663060 |
|
|
Oct 10 12:41:47 AM UTC 24 |
Oct 10 12:41:59 AM UTC 24 |
249660069 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.484901743 |
|
|
Oct 10 12:41:32 AM UTC 24 |
Oct 10 12:42:01 AM UTC 24 |
691574751 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3796052494 |
|
|
Oct 10 12:40:55 AM UTC 24 |
Oct 10 12:42:07 AM UTC 24 |
4027044742 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.3832998296 |
|
|
Oct 10 12:42:03 AM UTC 24 |
Oct 10 12:42:13 AM UTC 24 |
53490088 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.3097731793 |
|
|
Oct 10 12:33:14 AM UTC 24 |
Oct 10 12:42:19 AM UTC 24 |
55511022292 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2887169430 |
|
|
Oct 10 12:42:08 AM UTC 24 |
Oct 10 12:42:19 AM UTC 24 |
57892047 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.772663943 |
|
|
Oct 10 12:19:09 AM UTC 24 |
Oct 10 12:42:21 AM UTC 24 |
86504728961 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.1618612974 |
|
|
Oct 10 12:40:17 AM UTC 24 |
Oct 10 12:42:22 AM UTC 24 |
2781462119 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.797401715 |
|
|
Oct 10 12:05:36 AM UTC 24 |
Oct 10 12:42:32 AM UTC 24 |
139231554862 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.2301842233 |
|
|
Oct 10 12:42:17 AM UTC 24 |
Oct 10 12:42:43 AM UTC 24 |
188579090 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.1690345493 |
|
|
Oct 09 11:03:11 PM UTC 24 |
Oct 10 12:42:45 AM UTC 24 |
35714571480 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3833724751 |
|
|
Oct 10 12:39:22 AM UTC 24 |
Oct 10 12:42:48 AM UTC 24 |
2055561575 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4095848831 |
|
|
Oct 10 12:07:08 AM UTC 24 |
Oct 10 12:42:48 AM UTC 24 |
123008178184 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2852639107 |
|
|
Oct 10 12:40:56 AM UTC 24 |
Oct 10 12:42:49 AM UTC 24 |
10191114901 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.954220209 |
|
|
Oct 10 12:41:22 AM UTC 24 |
Oct 10 12:42:53 AM UTC 24 |
2342343790 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2350998420 |
|
|
Oct 10 12:40:47 AM UTC 24 |
Oct 10 12:42:53 AM UTC 24 |
1509193694 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.4245282148 |
|
|
Oct 10 12:41:11 AM UTC 24 |
Oct 10 12:42:54 AM UTC 24 |
6769361936 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.2539167154 |
|
|
Oct 10 12:42:37 AM UTC 24 |
Oct 10 12:42:56 AM UTC 24 |
146584368 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.3098071400 |
|
|
Oct 10 12:42:46 AM UTC 24 |
Oct 10 12:42:57 AM UTC 24 |
92783674 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.906771449 |
|
|
Oct 10 12:39:15 AM UTC 24 |
Oct 10 12:43:09 AM UTC 24 |
5032743256 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.2001499397 |
|
|
Oct 10 12:42:18 AM UTC 24 |
Oct 10 12:43:10 AM UTC 24 |
1056797130 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3765001652 |
|
|
Oct 10 12:43:10 AM UTC 24 |
Oct 10 12:43:19 AM UTC 24 |
43796674 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1788939351 |
|
|
Oct 10 12:42:44 AM UTC 24 |
Oct 10 12:43:20 AM UTC 24 |
582173155 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.2930517769 |
|
|
Oct 10 12:43:11 AM UTC 24 |
Oct 10 12:43:21 AM UTC 24 |
232991488 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.722301243 |
|
|
Oct 10 12:34:16 AM UTC 24 |
Oct 10 12:43:22 AM UTC 24 |
51755624797 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.98344093 |
|
|
Oct 10 12:42:40 AM UTC 24 |
Oct 10 12:43:25 AM UTC 24 |
1401640039 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.3751442262 |
|
|
Oct 10 12:43:18 AM UTC 24 |
Oct 10 12:43:27 AM UTC 24 |
42300008 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.3308234046 |
|
|
Oct 10 12:42:44 AM UTC 24 |
Oct 10 12:43:44 AM UTC 24 |
908545191 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2181382710 |
|
|
Oct 10 12:42:14 AM UTC 24 |
Oct 10 12:43:49 AM UTC 24 |
6113941510 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.731008303 |
|
|
Oct 10 12:42:12 AM UTC 24 |
Oct 10 12:43:49 AM UTC 24 |
10534760120 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1766556914 |
|
|
Oct 10 12:43:33 AM UTC 24 |
Oct 10 12:43:52 AM UTC 24 |
349368427 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1181158360 |
|
|
Oct 10 12:43:19 AM UTC 24 |
Oct 10 12:44:00 AM UTC 24 |
1703200434 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.3508822148 |
|
|
Oct 10 12:42:23 AM UTC 24 |
Oct 10 12:44:01 AM UTC 24 |
1070103157 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.723525603 |
|
|
Oct 10 12:35:35 AM UTC 24 |
Oct 10 12:44:15 AM UTC 24 |
25846277564 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.925353425 |
|
|
Oct 10 12:44:11 AM UTC 24 |
Oct 10 12:44:21 AM UTC 24 |
46754862 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.2038799960 |
|
|
Oct 10 12:30:02 AM UTC 24 |
Oct 10 12:44:23 AM UTC 24 |
70595717585 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3578072537 |
|
|
Oct 10 12:43:45 AM UTC 24 |
Oct 10 12:44:25 AM UTC 24 |
328379726 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1597838577 |
|
|
Oct 10 12:44:16 AM UTC 24 |
Oct 10 12:44:26 AM UTC 24 |
46689998 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.3534659497 |
|
|
Oct 10 12:28:39 AM UTC 24 |
Oct 10 12:44:35 AM UTC 24 |
87837621417 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.2994105678 |
|
|
Oct 10 12:43:43 AM UTC 24 |
Oct 10 12:44:46 AM UTC 24 |
1742222794 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.963006786 |
|
|
Oct 10 12:43:17 AM UTC 24 |
Oct 10 12:44:53 AM UTC 24 |
2320342626 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.834694239 |
|
|
Oct 10 12:43:45 AM UTC 24 |
Oct 10 12:44:53 AM UTC 24 |
2038337021 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.2054016668 |
|
|
Oct 10 12:44:37 AM UTC 24 |
Oct 10 12:44:56 AM UTC 24 |
141295714 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.554850150 |
|
|
Oct 10 12:43:13 AM UTC 24 |
Oct 10 12:44:58 AM UTC 24 |
8412577142 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.4105054720 |
|
|
Oct 10 12:38:05 AM UTC 24 |
Oct 10 12:45:02 AM UTC 24 |
5322495356 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.1488649604 |
|
|
Oct 10 12:28:44 AM UTC 24 |
Oct 10 12:45:03 AM UTC 24 |
62620215336 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4119210895 |
|
|
Oct 10 12:43:15 AM UTC 24 |
Oct 10 12:45:14 AM UTC 24 |
4803297165 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3689486121 |
|
|
Oct 10 12:43:48 AM UTC 24 |
Oct 10 12:45:17 AM UTC 24 |
1515749470 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.710299801 |
|
|
Oct 10 12:45:09 AM UTC 24 |
Oct 10 12:45:20 AM UTC 24 |
39655644 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3987098632 |
|
|
Oct 10 12:29:22 AM UTC 24 |
Oct 10 12:45:27 AM UTC 24 |
16546507816 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.148224662 |
|
|
Oct 10 12:44:44 AM UTC 24 |
Oct 10 12:45:31 AM UTC 24 |
482142169 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3662007295 |
|
|
Oct 10 12:45:20 AM UTC 24 |
Oct 10 12:45:36 AM UTC 24 |
182450571 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.322651572 |
|
|
Oct 10 12:45:14 AM UTC 24 |
Oct 10 12:45:44 AM UTC 24 |
155661207 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2531151907 |
|
|
Oct 10 12:35:31 AM UTC 24 |
Oct 10 12:45:44 AM UTC 24 |
47688240069 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.2295368395 |
|
|
Oct 10 12:30:08 AM UTC 24 |
Oct 10 12:45:51 AM UTC 24 |
59021220304 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.4131867616 |
|
|
Oct 10 12:45:42 AM UTC 24 |
Oct 10 12:45:52 AM UTC 24 |
51192440 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2149467523 |
|
|
Oct 10 12:37:22 AM UTC 24 |
Oct 10 12:45:52 AM UTC 24 |
8348392269 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3458712988 |
|
|
Oct 10 12:45:43 AM UTC 24 |
Oct 10 12:45:55 AM UTC 24 |
55969521 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2567441093 |
|
|
Oct 10 12:44:06 AM UTC 24 |
Oct 10 12:45:58 AM UTC 24 |
1570366258 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.883694822 |
|
|
Oct 10 12:45:15 AM UTC 24 |
Oct 10 12:46:11 AM UTC 24 |
610084267 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.4094408187 |
|
|
Oct 10 12:44:23 AM UTC 24 |
Oct 10 12:46:16 AM UTC 24 |
6654680335 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.2051138829 |
|
|
Oct 10 12:44:49 AM UTC 24 |
Oct 10 12:46:30 AM UTC 24 |
1167427686 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.2370317806 |
|
|
Oct 10 12:42:21 AM UTC 24 |
Oct 10 12:46:37 AM UTC 24 |
27759008685 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.4000994103 |
|
|
Oct 10 12:46:08 AM UTC 24 |
Oct 10 12:46:39 AM UTC 24 |
217260581 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.1672066051 |
|
|
Oct 10 12:45:59 AM UTC 24 |
Oct 10 12:46:40 AM UTC 24 |
840032239 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3733432127 |
|
|
Oct 10 12:44:24 AM UTC 24 |
Oct 10 12:46:41 AM UTC 24 |
5942675263 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.1437685412 |
|
|
Oct 10 12:40:33 AM UTC 24 |
Oct 10 12:46:41 AM UTC 24 |
8798084256 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2367863961 |
|
|
Oct 10 12:46:36 AM UTC 24 |
Oct 10 12:46:51 AM UTC 24 |
157573687 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2348976247 |
|
|
Oct 10 12:43:51 AM UTC 24 |
Oct 10 12:46:54 AM UTC 24 |
4426228770 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4057433431 |
|
|
Oct 10 12:46:20 AM UTC 24 |
Oct 10 12:46:58 AM UTC 24 |
342463008 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1927017520 |
|
|
Oct 10 12:42:00 AM UTC 24 |
Oct 10 12:47:02 AM UTC 24 |
4985567675 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3440189817 |
|
|
Oct 10 12:41:46 AM UTC 24 |
Oct 10 12:47:07 AM UTC 24 |
6483791149 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.1221766832 |
|
|
Oct 10 12:36:33 AM UTC 24 |
Oct 10 12:47:10 AM UTC 24 |
39364703820 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.658217278 |
|
|
Oct 10 12:46:39 AM UTC 24 |
Oct 10 12:47:11 AM UTC 24 |
513623940 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.4254116925 |
|
|
Oct 10 12:43:07 AM UTC 24 |
Oct 10 12:47:13 AM UTC 24 |
6669983427 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.843694186 |
|
|
Oct 10 12:26:25 AM UTC 24 |
Oct 10 12:47:14 AM UTC 24 |
80703460469 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3003648536 |
|
|
Oct 10 12:47:06 AM UTC 24 |
Oct 10 12:47:17 AM UTC 24 |
50812678 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3825210956 |
|
|
Oct 10 12:47:05 AM UTC 24 |
Oct 10 12:47:20 AM UTC 24 |
222624077 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.89516515 |
|
|
Oct 10 12:46:22 AM UTC 24 |
Oct 10 12:47:23 AM UTC 24 |
565973019 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4252348001 |
|
|
Oct 10 12:47:00 AM UTC 24 |
Oct 10 12:47:40 AM UTC 24 |
108642524 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3289040235 |
|
|
Oct 10 12:45:53 AM UTC 24 |
Oct 10 12:47:41 AM UTC 24 |
10849422596 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.3726792585 |
|
|
Oct 10 12:47:23 AM UTC 24 |
Oct 10 12:47:42 AM UTC 24 |
393235126 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3251908578 |
|
|
Oct 10 12:41:52 AM UTC 24 |
Oct 10 12:47:43 AM UTC 24 |
691981205 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.4281735628 |
|
|
Oct 10 12:45:52 AM UTC 24 |
Oct 10 12:47:43 AM UTC 24 |
4709837746 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.1257418405 |
|
|
Oct 10 12:46:16 AM UTC 24 |
Oct 10 12:47:45 AM UTC 24 |
1100042301 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2988745284 |
|
|
Oct 10 12:45:29 AM UTC 24 |
Oct 10 12:47:52 AM UTC 24 |
1884170559 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.473864404 |
|
|
Oct 10 12:47:39 AM UTC 24 |
Oct 10 12:47:55 AM UTC 24 |
151334566 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.3023290615 |
|
|
Oct 10 12:47:26 AM UTC 24 |
Oct 10 12:47:59 AM UTC 24 |
324019286 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.25683296 |
|
|
Oct 10 12:47:41 AM UTC 24 |
Oct 10 12:48:02 AM UTC 24 |
211390241 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2907311490 |
|
|
Oct 10 12:43:07 AM UTC 24 |
Oct 10 12:48:02 AM UTC 24 |
1562880354 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.299435206 |
|
|
Oct 10 12:47:43 AM UTC 24 |
Oct 10 12:48:10 AM UTC 24 |
160589051 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.215227938 |
|
|
Oct 10 12:48:04 AM UTC 24 |
Oct 10 12:48:14 AM UTC 24 |
40130421 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.451662676 |
|
|
Oct 10 12:48:06 AM UTC 24 |
Oct 10 12:48:15 AM UTC 24 |
44248172 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1791026924 |
|
|
Oct 10 12:40:47 AM UTC 24 |
Oct 10 12:48:21 AM UTC 24 |
3277587907 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.4000324698 |
|
|
Oct 10 12:37:10 AM UTC 24 |
Oct 10 12:48:24 AM UTC 24 |
17119671177 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2370827722 |
|
|
Oct 10 12:43:53 AM UTC 24 |
Oct 10 12:48:34 AM UTC 24 |
518341993 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.255507326 |
|
|
Oct 10 12:47:10 AM UTC 24 |
Oct 10 12:48:40 AM UTC 24 |
7375662615 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3358578591 |
|
|
Oct 10 12:47:47 AM UTC 24 |
Oct 10 12:48:42 AM UTC 24 |
1334140431 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2984801464 |
|
|
Oct 10 12:41:59 AM UTC 24 |
Oct 10 12:48:57 AM UTC 24 |
10782073072 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.1952554904 |
|
|
Oct 10 12:46:54 AM UTC 24 |
Oct 10 12:49:03 AM UTC 24 |
1379752218 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1451985956 |
|
|
Oct 10 12:47:15 AM UTC 24 |
Oct 10 12:49:04 AM UTC 24 |
7139251908 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.699119342 |
|
|
Oct 10 12:48:44 AM UTC 24 |
Oct 10 12:49:06 AM UTC 24 |
468434570 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.856106430 |
|
|
Oct 10 12:48:49 AM UTC 24 |
Oct 10 12:49:08 AM UTC 24 |
123685818 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.1380733212 |
|
|
Oct 10 12:48:18 AM UTC 24 |
Oct 10 12:49:16 AM UTC 24 |
575088778 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.2242759163 |
|
|
Oct 10 12:48:25 AM UTC 24 |
Oct 10 12:49:21 AM UTC 24 |
577601980 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.515760899 |
|
|
Oct 10 12:47:33 AM UTC 24 |
Oct 10 12:49:21 AM UTC 24 |
2886935897 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3767571349 |
|
|
Oct 10 12:49:04 AM UTC 24 |
Oct 10 12:49:22 AM UTC 24 |
107740880 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.3555557435 |
|
|
Oct 10 12:48:34 AM UTC 24 |
Oct 10 12:49:23 AM UTC 24 |
794851447 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.117023024 |
|
|
Oct 10 12:47:04 AM UTC 24 |
Oct 10 12:49:23 AM UTC 24 |
630849876 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1438889520 |
|
|
Oct 10 12:49:14 AM UTC 24 |
Oct 10 12:49:27 AM UTC 24 |
7642487 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.2603099433 |
|
|
Oct 10 12:49:27 AM UTC 24 |
Oct 10 12:49:38 AM UTC 24 |
215317273 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.888655534 |
|
|
Oct 10 12:49:31 AM UTC 24 |
Oct 10 12:49:39 AM UTC 24 |
57950782 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1255189008 |
|
|
Oct 10 12:48:03 AM UTC 24 |
Oct 10 12:49:42 AM UTC 24 |
1068788731 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.159884325 |
|
|
Oct 10 12:48:16 AM UTC 24 |
Oct 10 12:49:50 AM UTC 24 |
4618194141 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.1684329264 |
|
|
Oct 10 12:48:57 AM UTC 24 |
Oct 10 12:49:57 AM UTC 24 |
990501998 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.460746143 |
|
|
Oct 10 12:48:13 AM UTC 24 |
Oct 10 12:50:01 AM UTC 24 |
9111774858 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.434625707 |
|
|
Oct 10 12:48:05 AM UTC 24 |
Oct 10 12:50:13 AM UTC 24 |
1408733549 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2650884949 |
|
|
Oct 10 12:49:42 AM UTC 24 |
Oct 10 12:50:15 AM UTC 24 |
398648355 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3999311587 |
|
|
Oct 10 12:49:45 AM UTC 24 |
Oct 10 12:50:17 AM UTC 24 |
774980159 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.279736989 |
|
|
Oct 10 12:32:00 AM UTC 24 |
Oct 10 12:50:17 AM UTC 24 |
94387763759 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3573217030 |
|
|
Oct 10 12:49:51 AM UTC 24 |
Oct 10 12:50:33 AM UTC 24 |
824451376 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3892515085 |
|
|
Oct 10 12:50:22 AM UTC 24 |
Oct 10 12:50:35 AM UTC 24 |
135291576 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3861862234 |
|
|
Oct 10 12:39:55 AM UTC 24 |
Oct 10 12:50:38 AM UTC 24 |
49662743385 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.2696285645 |
|
|
Oct 10 12:50:42 AM UTC 24 |
Oct 10 12:50:50 AM UTC 24 |
52965335 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2407937320 |
|
|
Oct 10 12:48:05 AM UTC 24 |
Oct 10 12:50:55 AM UTC 24 |
585058509 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.582696880 |
|
|
Oct 10 12:45:22 AM UTC 24 |
Oct 10 12:50:58 AM UTC 24 |
7702691941 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.1492664104 |
|
|
Oct 10 12:50:15 AM UTC 24 |
Oct 10 12:50:58 AM UTC 24 |
872772088 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.714655852 |
|
|
Oct 10 12:44:44 AM UTC 24 |
Oct 10 12:50:59 AM UTC 24 |
37769354810 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2293865900 |
|
|
Oct 10 12:41:23 AM UTC 24 |
Oct 10 12:51:06 AM UTC 24 |
41226229923 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.182898169 |
|
|
Oct 10 12:49:39 AM UTC 24 |
Oct 10 12:51:07 AM UTC 24 |
9152125710 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1851650355 |
|
|
Oct 10 12:50:57 AM UTC 24 |
Oct 10 12:51:08 AM UTC 24 |
52461526 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.4257598764 |
|
|
Oct 10 12:50:02 AM UTC 24 |
Oct 10 12:51:09 AM UTC 24 |
1786567951 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3852026404 |
|
|
Oct 10 12:49:25 AM UTC 24 |
Oct 10 12:51:10 AM UTC 24 |
277588515 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.432265759 |
|
|
Oct 10 12:49:42 AM UTC 24 |
Oct 10 12:51:22 AM UTC 24 |
5601009663 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.911755165 |
|
|
Oct 10 12:50:03 AM UTC 24 |
Oct 10 12:51:31 AM UTC 24 |
2464199404 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.1814357366 |
|
|
Oct 10 12:51:14 AM UTC 24 |
Oct 10 12:51:35 AM UTC 24 |
120627874 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.4221593326 |
|
|
Oct 10 12:51:21 AM UTC 24 |
Oct 10 12:51:38 AM UTC 24 |
40941413 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.3842628778 |
|
|
Oct 10 12:51:32 AM UTC 24 |
Oct 10 12:51:53 AM UTC 24 |
109252429 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.43551825 |
|
|
Oct 10 12:51:21 AM UTC 24 |
Oct 10 12:51:54 AM UTC 24 |
247057453 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2556888065 |
|
|
Oct 10 12:51:33 AM UTC 24 |
Oct 10 12:51:56 AM UTC 24 |
108370770 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1133860129 |
|
|
Oct 10 12:22:28 AM UTC 24 |
Oct 10 12:51:58 AM UTC 24 |
110088069244 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2631815797 |
|
|
Oct 10 12:23:54 AM UTC 24 |
Oct 10 12:52:03 AM UTC 24 |
103576238607 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2300672802 |
|
|
Oct 10 12:45:39 AM UTC 24 |
Oct 10 12:52:12 AM UTC 24 |
3088520048 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.292096653 |
|
|
Oct 10 12:44:13 AM UTC 24 |
Oct 10 12:52:17 AM UTC 24 |
4004711987 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1087134194 |
|
|
Oct 10 12:42:30 AM UTC 24 |
Oct 10 12:52:19 AM UTC 24 |
31677008150 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3434199628 |
|
|
Oct 10 12:52:14 AM UTC 24 |
Oct 10 12:52:25 AM UTC 24 |
185985410 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.2316838270 |
|
|
Oct 10 12:50:59 AM UTC 24 |
Oct 10 12:52:26 AM UTC 24 |
8910309115 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.261827984 |
|
|
Oct 10 12:51:29 AM UTC 24 |
Oct 10 12:52:26 AM UTC 24 |
1303176815 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3107513378 |
|
|
Oct 10 12:52:19 AM UTC 24 |
Oct 10 12:52:29 AM UTC 24 |
45976616 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3702838598 |
|
|
Oct 10 12:51:02 AM UTC 24 |
Oct 10 12:52:31 AM UTC 24 |
4864549376 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.1770930013 |
|
|
Oct 10 12:47:04 AM UTC 24 |
Oct 10 12:52:34 AM UTC 24 |
9025491141 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.2431240852 |
|
|
Oct 10 12:52:28 AM UTC 24 |
Oct 10 12:52:47 AM UTC 24 |
109551077 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.3906397153 |
|
|
Oct 10 12:43:18 AM UTC 24 |
Oct 10 12:52:55 AM UTC 24 |
58404195159 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1994665237 |
|
|
Oct 10 12:51:32 AM UTC 24 |
Oct 10 12:52:58 AM UTC 24 |
1823702882 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.466212437 |
|
|
Oct 10 12:52:54 AM UTC 24 |
Oct 10 12:53:16 AM UTC 24 |
121259438 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3359140040 |
|
|
Oct 10 12:27:24 AM UTC 24 |
Oct 10 12:53:18 AM UTC 24 |
97668520070 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.3435396006 |
|
|
Oct 10 12:52:49 AM UTC 24 |
Oct 10 12:53:21 AM UTC 24 |
257101349 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.3686461860 |
|
|
Oct 10 12:51:59 AM UTC 24 |
Oct 10 12:53:24 AM UTC 24 |
646230868 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.1649246517 |
|
|
Oct 10 12:52:47 AM UTC 24 |
Oct 10 12:53:25 AM UTC 24 |
891173157 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.686952477 |
|
|
Oct 10 12:53:22 AM UTC 24 |
Oct 10 12:53:31 AM UTC 24 |
52204865 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.941586647 |
|
|
Oct 10 12:52:36 AM UTC 24 |
Oct 10 12:53:31 AM UTC 24 |
598276142 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.764391738 |
|
|
Oct 10 12:51:59 AM UTC 24 |
Oct 10 12:53:35 AM UTC 24 |
505917159 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.1033310750 |
|
|
Oct 09 11:34:04 PM UTC 24 |
Oct 10 12:53:35 AM UTC 24 |
30121941783 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2240649262 |
|
|
Oct 10 12:52:19 AM UTC 24 |
Oct 10 12:53:42 AM UTC 24 |
5213251997 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.564823580 |
|
|
Oct 10 12:50:37 AM UTC 24 |
Oct 10 12:53:46 AM UTC 24 |
4683028142 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.144011913 |
|
|
Oct 10 12:50:25 AM UTC 24 |
Oct 10 12:53:53 AM UTC 24 |
2242637521 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.1666955838 |
|
|
Oct 10 12:52:55 AM UTC 24 |
Oct 10 12:53:53 AM UTC 24 |
1210021974 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1830083293 |
|
|
Oct 10 12:53:44 AM UTC 24 |
Oct 10 12:53:55 AM UTC 24 |
53023562 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.722681068 |
|
|
Oct 10 12:53:43 AM UTC 24 |
Oct 10 12:53:59 AM UTC 24 |
208720312 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1005898167 |
|
|
Oct 10 12:52:22 AM UTC 24 |
Oct 10 12:53:59 AM UTC 24 |
6394307467 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.934937179 |
|
|
Oct 10 12:52:54 AM UTC 24 |
Oct 10 12:54:06 AM UTC 24 |
1534092141 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3798538734 |
|
|
Oct 10 12:38:07 AM UTC 24 |
Oct 10 12:54:34 AM UTC 24 |
19898710252 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.4040654939 |
|
|
Oct 10 12:53:54 AM UTC 24 |
Oct 10 12:54:43 AM UTC 24 |
522576603 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.309379651 |
|
|
Oct 10 12:54:04 AM UTC 24 |
Oct 10 12:54:49 AM UTC 24 |
801779361 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.282011326 |
|
|
Oct 10 12:53:54 AM UTC 24 |
Oct 10 12:54:55 AM UTC 24 |
1221864363 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2082962894 |
|
|
Oct 10 12:45:27 AM UTC 24 |
Oct 10 12:55:00 AM UTC 24 |
2535940098 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1344666672 |
|
|
Oct 10 12:54:24 AM UTC 24 |
Oct 10 12:55:04 AM UTC 24 |
581022896 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.123203666 |
|
|
Oct 10 12:49:47 AM UTC 24 |
Oct 10 12:55:06 AM UTC 24 |
20111922136 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.3621944475 |
|
|
Oct 10 12:54:18 AM UTC 24 |
Oct 10 12:55:12 AM UTC 24 |
637139863 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.2188594112 |
|
|
Oct 10 12:53:48 AM UTC 24 |
Oct 10 12:55:14 AM UTC 24 |
9385334735 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.1979836649 |
|
|
Oct 10 12:54:21 AM UTC 24 |
Oct 10 12:55:16 AM UTC 24 |
1265291413 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.2990028819 |
|
|
Oct 10 12:54:24 AM UTC 24 |
Oct 10 12:55:19 AM UTC 24 |
487542440 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1770220790 |
|
|
Oct 10 12:42:22 AM UTC 24 |
Oct 10 12:55:22 AM UTC 24 |
47045871578 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.1734350626 |
|
|
Oct 10 12:55:13 AM UTC 24 |
Oct 10 12:55:22 AM UTC 24 |
45014116 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3895929860 |
|
|
Oct 09 11:37:54 PM UTC 24 |
Oct 10 12:55:24 AM UTC 24 |
28620624689 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2228673266 |
|
|
Oct 10 12:55:18 AM UTC 24 |
Oct 10 12:55:25 AM UTC 24 |
52661479 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1656902085 |
|
|
Oct 10 12:49:59 AM UTC 24 |
Oct 10 12:55:32 AM UTC 24 |
21293905933 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.2495930727 |
|
|
Oct 10 12:41:20 AM UTC 24 |
Oct 10 12:55:37 AM UTC 24 |
52318627573 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1025733063 |
|
|
Oct 10 12:53:50 AM UTC 24 |
Oct 10 12:55:42 AM UTC 24 |
5655606325 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.581435346 |
|
|
Oct 10 12:47:31 AM UTC 24 |
Oct 10 12:55:47 AM UTC 24 |
47231666134 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1837848297 |
|
|
Oct 10 12:38:45 AM UTC 24 |
Oct 10 12:55:51 AM UTC 24 |
66338726824 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1426291576 |
|
|
Oct 10 12:55:44 AM UTC 24 |
Oct 10 12:55:58 AM UTC 24 |
67707001 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.2731911953 |
|
|
Oct 10 12:49:02 AM UTC 24 |
Oct 10 12:55:58 AM UTC 24 |
10808278553 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2953703816 |
|
|
Oct 10 12:54:18 AM UTC 24 |
Oct 10 12:55:58 AM UTC 24 |
2649017476 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.3975980782 |
|
|
Oct 10 12:55:33 AM UTC 24 |
Oct 10 12:56:11 AM UTC 24 |
271767335 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2616249511 |
|
|
Oct 10 12:55:07 AM UTC 24 |
Oct 10 12:56:12 AM UTC 24 |
120244399 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3798519754 |
|
|
Oct 10 12:55:47 AM UTC 24 |
Oct 10 12:56:12 AM UTC 24 |
155294539 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.1706817430 |
|
|
Oct 10 12:53:12 AM UTC 24 |
Oct 10 12:56:16 AM UTC 24 |
2234351508 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1945689391 |
|
|
Oct 10 12:49:24 AM UTC 24 |
Oct 10 12:56:17 AM UTC 24 |
9911911834 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2151563595 |
|
|
Oct 10 12:53:38 AM UTC 24 |
Oct 10 12:56:22 AM UTC 24 |
364434355 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1623068861 |
|
|
Oct 10 12:55:52 AM UTC 24 |
Oct 10 12:56:24 AM UTC 24 |
686001118 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2079140411 |
|
|
Oct 10 12:51:32 AM UTC 24 |
Oct 10 12:56:25 AM UTC 24 |
17974239752 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3286711121 |
|
|
Oct 10 12:55:30 AM UTC 24 |
Oct 10 12:56:26 AM UTC 24 |
1332330994 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1741354592 |
|
|
Oct 10 12:51:54 AM UTC 24 |
Oct 10 12:56:29 AM UTC 24 |
604735291 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1232324105 |
|
|
Oct 10 12:56:22 AM UTC 24 |
Oct 10 12:56:32 AM UTC 24 |
206989017 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3977705398 |
|
|
Oct 10 12:56:23 AM UTC 24 |
Oct 10 12:56:33 AM UTC 24 |
42284122 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3803509868 |
|
|
Oct 10 12:54:31 AM UTC 24 |
Oct 10 12:56:39 AM UTC 24 |
294408928 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3074980072 |
|
|
Oct 10 12:56:36 AM UTC 24 |
Oct 10 12:56:52 AM UTC 24 |
127622253 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2837884761 |
|
|
Oct 10 12:48:01 AM UTC 24 |
Oct 10 12:56:53 AM UTC 24 |
6208060261 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.789614410 |
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|
Oct 10 12:33:26 AM UTC 24 |
Oct 10 12:56:58 AM UTC 24 |
99872882771 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.340541293 |
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|
Oct 10 12:56:16 AM UTC 24 |
Oct 10 12:57:08 AM UTC 24 |
202589421 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.632542425 |
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|
Oct 10 12:55:29 AM UTC 24 |
Oct 10 12:57:08 AM UTC 24 |
4336767421 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.3673233913 |
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|
Oct 10 12:55:46 AM UTC 24 |
Oct 10 12:57:08 AM UTC 24 |
2350079769 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2978062661 |
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|
Oct 10 12:56:56 AM UTC 24 |
Oct 10 12:57:23 AM UTC 24 |
421311303 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.2902819313 |
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|
Oct 10 12:55:20 AM UTC 24 |
Oct 10 12:57:25 AM UTC 24 |
10386284750 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.167765038 |
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|
Oct 10 12:56:37 AM UTC 24 |
Oct 10 12:57:29 AM UTC 24 |
1373005336 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.369840585 |
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|
Oct 10 12:38:53 AM UTC 24 |
Oct 10 12:57:34 AM UTC 24 |
70467608554 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.229739700 |
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|
Oct 10 12:57:23 AM UTC 24 |
Oct 10 12:57:37 AM UTC 24 |
217033096 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.1785061547 |
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|
Oct 10 12:56:50 AM UTC 24 |
Oct 10 12:57:42 AM UTC 24 |
1520246433 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.99019500 |
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|
Oct 10 12:39:59 AM UTC 24 |
Oct 10 12:57:42 AM UTC 24 |
61973754453 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2015905750 |
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|
Oct 10 12:57:32 AM UTC 24 |
Oct 10 12:57:43 AM UTC 24 |
49093052 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3494098170 |
|
|
Oct 10 12:57:19 AM UTC 24 |
Oct 10 12:57:49 AM UTC 24 |
149551889 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1756088491 |
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|
Oct 10 12:55:39 AM UTC 24 |
Oct 10 12:57:56 AM UTC 24 |
3381900874 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.370215434 |
|
|
Oct 10 12:56:50 AM UTC 24 |
Oct 10 12:57:56 AM UTC 24 |
2053485452 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.3709634287 |
|
|
Oct 10 12:56:54 AM UTC 24 |
Oct 10 12:57:58 AM UTC 24 |
1004239542 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3268449643 |
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|
Oct 10 12:53:19 AM UTC 24 |
Oct 10 12:57:58 AM UTC 24 |
6322115342 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2333248338 |
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|
Oct 10 12:50:41 AM UTC 24 |
Oct 10 12:58:00 AM UTC 24 |
8118735113 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.686660000 |
|
|
Oct 10 12:56:46 AM UTC 24 |
Oct 10 12:58:13 AM UTC 24 |
2631689820 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.3334449814 |
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|
Oct 10 12:57:50 AM UTC 24 |
Oct 10 12:58:17 AM UTC 24 |
257286565 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2464071800 |
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|
Oct 10 12:57:46 AM UTC 24 |
Oct 10 12:58:19 AM UTC 24 |
299491031 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.1771964153 |
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|
Oct 10 12:56:41 AM UTC 24 |
Oct 10 12:58:21 AM UTC 24 |
6616933213 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.3003074474 |
|
|
Oct 10 12:58:03 AM UTC 24 |
Oct 10 12:58:22 AM UTC 24 |
665061155 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.2605250475 |
|
|
Oct 10 12:56:55 AM UTC 24 |
Oct 10 12:58:26 AM UTC 24 |
808380594 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.2236271809 |
|
|
Oct 10 12:58:12 AM UTC 24 |
Oct 10 12:58:29 AM UTC 24 |
67657652 ps |