| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.3615470168 |
|
|
Oct 10 07:06:10 AM UTC 24 |
Oct 10 07:17:02 AM UTC 24 |
4929296456 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.1286619369 |
|
|
Oct 10 07:08:09 AM UTC 24 |
Oct 10 07:17:48 AM UTC 24 |
4646945800 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.1478990285 |
|
|
Oct 10 07:07:31 AM UTC 24 |
Oct 10 07:18:16 AM UTC 24 |
3836502880 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.984229189 |
|
|
Oct 10 05:34:13 AM UTC 24 |
Oct 10 07:18:28 AM UTC 24 |
44031139336 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091861065 |
|
|
Oct 10 07:12:45 AM UTC 24 |
Oct 10 07:19:55 AM UTC 24 |
4032587738 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.2074082926 |
|
|
Oct 10 07:08:33 AM UTC 24 |
Oct 10 07:20:12 AM UTC 24 |
3679544420 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3243961267 |
|
|
Oct 10 07:02:47 AM UTC 24 |
Oct 10 07:20:16 AM UTC 24 |
8450988313 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.1366862962 |
|
|
Oct 10 07:12:43 AM UTC 24 |
Oct 10 07:20:32 AM UTC 24 |
6027686232 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.2689573902 |
|
|
Oct 10 07:11:06 AM UTC 24 |
Oct 10 07:20:33 AM UTC 24 |
4158410296 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3744511685 |
|
|
Oct 10 07:12:31 AM UTC 24 |
Oct 10 07:20:55 AM UTC 24 |
6961441992 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.3982899111 |
|
|
Oct 10 06:42:50 AM UTC 24 |
Oct 10 07:21:02 AM UTC 24 |
23356474527 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2450318010 |
|
|
Oct 10 06:17:53 AM UTC 24 |
Oct 10 07:21:15 AM UTC 24 |
13695255304 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.432422678 |
|
|
Oct 10 07:06:09 AM UTC 24 |
Oct 10 07:21:20 AM UTC 24 |
6085931000 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.3150879020 |
|
|
Oct 10 07:05:19 AM UTC 24 |
Oct 10 07:21:41 AM UTC 24 |
9333137309 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2626279802 |
|
|
Oct 10 07:11:24 AM UTC 24 |
Oct 10 07:21:58 AM UTC 24 |
4311574040 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2976618424 |
|
|
Oct 10 04:34:56 AM UTC 24 |
Oct 10 07:22:10 AM UTC 24 |
31704102200 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379505422 |
|
|
Oct 10 07:16:37 AM UTC 24 |
Oct 10 07:23:18 AM UTC 24 |
3466071080 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.3307607896 |
|
|
Oct 10 07:16:35 AM UTC 24 |
Oct 10 07:23:35 AM UTC 24 |
6339752259 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3983798293 |
|
|
Oct 10 07:19:09 AM UTC 24 |
Oct 10 07:25:17 AM UTC 24 |
3536603688 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.4100780639 |
|
|
Oct 10 07:19:09 AM UTC 24 |
Oct 10 07:25:55 AM UTC 24 |
4684901229 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.3336419152 |
|
|
Oct 10 07:17:41 AM UTC 24 |
Oct 10 07:27:51 AM UTC 24 |
4679570420 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1076204960 |
|
|
Oct 10 06:01:54 AM UTC 24 |
Oct 10 07:28:07 AM UTC 24 |
18354858756 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1479334628 |
|
|
Oct 10 07:14:39 AM UTC 24 |
Oct 10 07:28:10 AM UTC 24 |
6159241040 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1747647647 |
|
|
Oct 10 07:16:20 AM UTC 24 |
Oct 10 07:28:34 AM UTC 24 |
5545706880 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687474899 |
|
|
Oct 10 07:22:22 AM UTC 24 |
Oct 10 07:29:01 AM UTC 24 |
3352334804 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1392124238 |
|
|
Oct 10 06:44:31 AM UTC 24 |
Oct 10 07:29:14 AM UTC 24 |
16676051626 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.776528235 |
|
|
Oct 10 07:22:57 AM UTC 24 |
Oct 10 07:30:32 AM UTC 24 |
3281563028 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879100317 |
|
|
Oct 10 07:24:12 AM UTC 24 |
Oct 10 07:30:59 AM UTC 24 |
3709895170 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2933338460 |
|
|
Oct 10 07:22:21 AM UTC 24 |
Oct 10 07:32:20 AM UTC 24 |
5680793920 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2437903544 |
|
|
Oct 10 07:12:44 AM UTC 24 |
Oct 10 07:32:26 AM UTC 24 |
8975843713 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.1016317672 |
|
|
Oct 10 07:13:07 AM UTC 24 |
Oct 10 07:32:37 AM UTC 24 |
7143718880 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.200498265 |
|
|
Oct 10 07:20:34 AM UTC 24 |
Oct 10 07:33:27 AM UTC 24 |
5813893200 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.379109752 |
|
|
Oct 10 07:22:57 AM UTC 24 |
Oct 10 07:33:41 AM UTC 24 |
5207264952 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.3596327870 |
|
|
Oct 10 07:01:18 AM UTC 24 |
Oct 10 07:33:52 AM UTC 24 |
8271416778 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.308529871 |
|
|
Oct 10 07:22:10 AM UTC 24 |
Oct 10 07:34:18 AM UTC 24 |
4837342556 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.1732901287 |
|
|
Oct 10 05:41:27 AM UTC 24 |
Oct 10 07:36:39 AM UTC 24 |
45678868413 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.3232231482 |
|
|
Oct 10 07:23:53 AM UTC 24 |
Oct 10 07:36:47 AM UTC 24 |
12936755941 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127463789 |
|
|
Oct 10 07:28:53 AM UTC 24 |
Oct 10 07:37:00 AM UTC 24 |
4313463760 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.4017109277 |
|
|
Oct 10 07:21:31 AM UTC 24 |
Oct 10 07:37:38 AM UTC 24 |
10827745445 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.954548579 |
|
|
Oct 10 05:12:08 AM UTC 24 |
Oct 10 07:37:38 AM UTC 24 |
25869865990 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.36792037 |
|
|
Oct 10 07:26:34 AM UTC 24 |
Oct 10 07:37:41 AM UTC 24 |
4724826312 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2505494647 |
|
|
Oct 10 07:31:10 AM UTC 24 |
Oct 10 07:39:09 AM UTC 24 |
3863586664 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.2540877329 |
|
|
Oct 10 07:29:45 AM UTC 24 |
Oct 10 07:39:23 AM UTC 24 |
3863333220 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.392288781 |
|
|
Oct 10 07:13:25 AM UTC 24 |
Oct 10 07:39:26 AM UTC 24 |
14165373817 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.2687461710 |
|
|
Oct 10 06:54:30 AM UTC 24 |
Oct 10 07:39:34 AM UTC 24 |
10568750880 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.3220287166 |
|
|
Oct 10 07:31:34 AM UTC 24 |
Oct 10 07:40:09 AM UTC 24 |
5754753680 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.3758956019 |
|
|
Oct 10 07:29:50 AM UTC 24 |
Oct 10 07:40:21 AM UTC 24 |
7793786607 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.907407549 |
|
|
Oct 10 07:29:09 AM UTC 24 |
Oct 10 07:40:58 AM UTC 24 |
5324416960 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.351263824 |
|
|
Oct 10 07:33:19 AM UTC 24 |
Oct 10 07:41:15 AM UTC 24 |
3550882592 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2309881013 |
|
|
Oct 10 07:22:56 AM UTC 24 |
Oct 10 07:41:33 AM UTC 24 |
12964196959 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1493618630 |
|
|
Oct 10 01:44:11 AM UTC 24 |
Oct 10 07:41:54 AM UTC 24 |
80985135369 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.118708386 |
|
|
Oct 10 07:33:18 AM UTC 24 |
Oct 10 07:42:13 AM UTC 24 |
6662810912 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.1978615175 |
|
|
Oct 10 05:39:57 AM UTC 24 |
Oct 10 07:42:45 AM UTC 24 |
49939894476 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1216056097 |
|
|
Oct 10 07:34:55 AM UTC 24 |
Oct 10 07:42:51 AM UTC 24 |
3725062680 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.1907694586 |
|
|
Oct 10 07:12:58 AM UTC 24 |
Oct 10 07:43:51 AM UTC 24 |
15780410342 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.3928759565 |
|
|
Oct 10 05:39:34 AM UTC 24 |
Oct 10 07:44:09 AM UTC 24 |
49871928512 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4214539843 |
|
|
Oct 10 07:38:58 AM UTC 24 |
Oct 10 07:45:10 AM UTC 24 |
4178372370 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1013953215 |
|
|
Oct 10 07:34:24 AM UTC 24 |
Oct 10 07:45:50 AM UTC 24 |
5733244086 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4154647788 |
|
|
Oct 10 07:38:40 AM UTC 24 |
Oct 10 07:46:03 AM UTC 24 |
3296320992 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.658189902 |
|
|
Oct 10 07:37:40 AM UTC 24 |
Oct 10 07:46:26 AM UTC 24 |
5219776755 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400101923 |
|
|
Oct 10 07:40:26 AM UTC 24 |
Oct 10 07:46:42 AM UTC 24 |
3881002682 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.2399520517 |
|
|
Oct 10 07:34:30 AM UTC 24 |
Oct 10 07:47:19 AM UTC 24 |
4797902924 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.529288888 |
|
|
Oct 10 07:16:19 AM UTC 24 |
Oct 10 07:47:47 AM UTC 24 |
8281799012 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2030297549 |
|
|
Oct 10 06:47:45 AM UTC 24 |
Oct 10 07:48:26 AM UTC 24 |
10735933900 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.3406653958 |
|
|
Oct 10 07:38:39 AM UTC 24 |
Oct 10 07:48:54 AM UTC 24 |
4612655244 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.3318341853 |
|
|
Oct 10 07:28:53 AM UTC 24 |
Oct 10 07:49:01 AM UTC 24 |
13053426739 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.416644006 |
|
|
Oct 10 07:21:19 AM UTC 24 |
Oct 10 07:49:20 AM UTC 24 |
7344275382 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2593470905 |
|
|
Oct 10 07:39:46 AM UTC 24 |
Oct 10 07:49:33 AM UTC 24 |
4109827322 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592014188 |
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|
Oct 10 07:40:59 AM UTC 24 |
Oct 10 07:49:40 AM UTC 24 |
3394250008 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.412104565 |
|
|
Oct 10 07:42:10 AM UTC 24 |
Oct 10 07:49:53 AM UTC 24 |
3098573000 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.2500164944 |
|
|
Oct 10 07:37:37 AM UTC 24 |
Oct 10 07:50:08 AM UTC 24 |
5556263220 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.1554951920 |
|
|
Oct 10 07:18:27 AM UTC 24 |
Oct 10 07:50:30 AM UTC 24 |
9411931530 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262617271 |
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|
Oct 10 07:43:34 AM UTC 24 |
Oct 10 07:50:36 AM UTC 24 |
4237488100 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.104823591 |
|
|
Oct 10 07:38:40 AM UTC 24 |
Oct 10 07:50:52 AM UTC 24 |
6556638120 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.4050404096 |
|
|
Oct 10 07:34:30 AM UTC 24 |
Oct 10 07:51:06 AM UTC 24 |
11108307644 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.284710693 |
|
|
Oct 10 07:01:34 AM UTC 24 |
Oct 10 07:51:22 AM UTC 24 |
13188056347 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.677814731 |
|
|
Oct 10 07:40:27 AM UTC 24 |
Oct 10 07:51:22 AM UTC 24 |
3954620168 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948424470 |
|
|
Oct 10 07:44:31 AM UTC 24 |
Oct 10 07:52:06 AM UTC 24 |
3364517080 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.353188917 |
|
|
Oct 10 07:41:51 AM UTC 24 |
Oct 10 07:52:07 AM UTC 24 |
3881455384 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2902215730 |
|
|
Oct 10 07:41:36 AM UTC 24 |
Oct 10 07:53:34 AM UTC 24 |
5493352088 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.2854351579 |
|
|
Oct 10 07:42:30 AM UTC 24 |
Oct 10 07:53:44 AM UTC 24 |
4174421798 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.1530841587 |
|
|
Oct 10 07:40:27 AM UTC 24 |
Oct 10 07:54:07 AM UTC 24 |
5438669760 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303197667 |
|
|
Oct 10 07:46:45 AM UTC 24 |
Oct 10 07:54:27 AM UTC 24 |
4463490024 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914345312 |
|
|
Oct 10 07:45:50 AM UTC 24 |
Oct 10 07:54:32 AM UTC 24 |
3887901248 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.3659307708 |
|
|
Oct 10 06:46:43 AM UTC 24 |
Oct 10 07:54:41 AM UTC 24 |
30580306237 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.5254849 |
|
|
Oct 10 07:22:56 AM UTC 24 |
Oct 10 07:55:01 AM UTC 24 |
8704472172 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.546083517 |
|
|
Oct 10 07:47:20 AM UTC 24 |
Oct 10 07:55:26 AM UTC 24 |
3945300320 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3066854849 |
|
|
Oct 10 07:49:44 AM UTC 24 |
Oct 10 07:56:11 AM UTC 24 |
3506313600 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1690645857 |
|
|
Oct 10 07:43:35 AM UTC 24 |
Oct 10 07:56:15 AM UTC 24 |
4977359008 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.3736764664 |
|
|
Oct 10 07:28:29 AM UTC 24 |
Oct 10 07:56:25 AM UTC 24 |
8053039954 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.426392893 |
|
|
Oct 10 07:48:26 AM UTC 24 |
Oct 10 07:57:05 AM UTC 24 |
3945452756 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.3186078894 |
|
|
Oct 10 07:44:48 AM UTC 24 |
Oct 10 07:57:15 AM UTC 24 |
6109551086 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.188695724 |
|
|
Oct 10 06:41:28 AM UTC 24 |
Oct 10 07:57:41 AM UTC 24 |
24754217144 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.58232884 |
|
|
Oct 10 07:46:44 AM UTC 24 |
Oct 10 07:57:59 AM UTC 24 |
3883072452 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1898856546 |
|
|
Oct 10 07:50:52 AM UTC 24 |
Oct 10 07:58:11 AM UTC 24 |
4258683032 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.1377484075 |
|
|
Oct 10 07:49:05 AM UTC 24 |
Oct 10 07:58:19 AM UTC 24 |
4444535480 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.721254218 |
|
|
Oct 10 07:50:52 AM UTC 24 |
Oct 10 07:58:20 AM UTC 24 |
4122341340 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1104190532 |
|
|
Oct 10 07:47:05 AM UTC 24 |
Oct 10 07:58:30 AM UTC 24 |
5955846594 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.232057039 |
|
|
Oct 10 06:45:51 AM UTC 24 |
Oct 10 07:58:58 AM UTC 24 |
14623138039 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.288270651 |
|
|
Oct 10 07:50:52 AM UTC 24 |
Oct 10 07:59:10 AM UTC 24 |
4285235288 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.1701578081 |
|
|
Oct 10 07:49:45 AM UTC 24 |
Oct 10 07:59:14 AM UTC 24 |
3966929734 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.190871631 |
|
|
Oct 10 06:45:50 AM UTC 24 |
Oct 10 07:59:32 AM UTC 24 |
15506277900 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3308237534 |
|
|
Oct 10 07:52:20 AM UTC 24 |
Oct 10 07:59:45 AM UTC 24 |
3504395140 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1346158724 |
|
|
Oct 10 07:52:58 AM UTC 24 |
Oct 10 07:59:56 AM UTC 24 |
3619874488 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2354917191 |
|
|
Oct 10 07:52:12 AM UTC 24 |
Oct 10 08:00:19 AM UTC 24 |
4007886950 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193222170 |
|
|
Oct 10 07:52:20 AM UTC 24 |
Oct 10 08:01:22 AM UTC 24 |
3936933640 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.376837774 |
|
|
Oct 10 07:55:06 AM UTC 24 |
Oct 10 08:01:36 AM UTC 24 |
3492124986 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.4277131081 |
|
|
Oct 10 07:33:19 AM UTC 24 |
Oct 10 08:01:39 AM UTC 24 |
8808537592 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.163196560 |
|
|
Oct 10 07:55:42 AM UTC 24 |
Oct 10 08:01:59 AM UTC 24 |
3542124954 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2509649480 |
|
|
Oct 10 06:50:31 AM UTC 24 |
Oct 10 08:02:18 AM UTC 24 |
15165971000 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.534738264 |
|
|
Oct 10 07:50:44 AM UTC 24 |
Oct 10 08:02:24 AM UTC 24 |
5384819884 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.1780258400 |
|
|
Oct 10 07:51:31 AM UTC 24 |
Oct 10 08:02:32 AM UTC 24 |
5303321176 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050622703 |
|
|
Oct 10 07:55:45 AM UTC 24 |
Oct 10 08:02:36 AM UTC 24 |
3904485868 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.3923950604 |
|
|
Oct 10 07:51:15 AM UTC 24 |
Oct 10 08:02:38 AM UTC 24 |
4864719750 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1199413865 |
|
|
Oct 10 07:52:13 AM UTC 24 |
Oct 10 08:03:18 AM UTC 24 |
4648137828 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.1545092924 |
|
|
Oct 10 07:37:39 AM UTC 24 |
Oct 10 08:03:29 AM UTC 24 |
7582584824 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1905397460 |
|
|
Oct 10 07:56:03 AM UTC 24 |
Oct 10 08:03:36 AM UTC 24 |
4132229440 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2487084611 |
|
|
Oct 10 07:54:50 AM UTC 24 |
Oct 10 08:04:01 AM UTC 24 |
3618003860 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.1713180443 |
|
|
Oct 10 07:54:51 AM UTC 24 |
Oct 10 08:04:24 AM UTC 24 |
4683036024 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1711923837 |
|
|
Oct 10 07:57:15 AM UTC 24 |
Oct 10 08:04:27 AM UTC 24 |
3057792232 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066722066 |
|
|
Oct 10 07:58:19 AM UTC 24 |
Oct 10 08:04:37 AM UTC 24 |
3125805988 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4114435879 |
|
|
Oct 10 07:57:55 AM UTC 24 |
Oct 10 08:05:08 AM UTC 24 |
3380395086 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990940172 |
|
|
Oct 10 07:59:21 AM UTC 24 |
Oct 10 08:05:51 AM UTC 24 |
3151403840 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.2780703550 |
|
|
Oct 10 07:52:58 AM UTC 24 |
Oct 10 08:05:51 AM UTC 24 |
6241017020 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.325684604 |
|
|
Oct 10 06:49:52 AM UTC 24 |
Oct 10 08:05:54 AM UTC 24 |
15482122814 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.3657547582 |
|
|
Oct 10 07:52:21 AM UTC 24 |
Oct 10 08:06:02 AM UTC 24 |
5058761128 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.656083257 |
|
|
Oct 10 07:53:47 AM UTC 24 |
Oct 10 08:06:02 AM UTC 24 |
4982492948 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.1525643800 |
|
|
Oct 10 06:49:33 AM UTC 24 |
Oct 10 08:06:19 AM UTC 24 |
16186515275 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3329790272 |
|
|
Oct 10 07:02:53 AM UTC 24 |
Oct 10 08:06:23 AM UTC 24 |
12735048376 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.740215737 |
|
|
Oct 10 07:59:33 AM UTC 24 |
Oct 10 08:06:40 AM UTC 24 |
3079135624 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2600854547 |
|
|
Oct 10 07:55:05 AM UTC 24 |
Oct 10 08:06:44 AM UTC 24 |
5257329836 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1650310017 |
|
|
Oct 10 07:57:14 AM UTC 24 |
Oct 10 08:07:20 AM UTC 24 |
4411807452 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2008557787 |
|
|
Oct 10 08:01:04 AM UTC 24 |
Oct 10 08:07:32 AM UTC 24 |
3794759200 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.3692369897 |
|
|
Oct 10 07:55:45 AM UTC 24 |
Oct 10 08:07:53 AM UTC 24 |
5625010772 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391523190 |
|
|
Oct 10 08:01:10 AM UTC 24 |
Oct 10 08:07:59 AM UTC 24 |
3874889100 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.626635143 |
|
|
Oct 10 06:50:19 AM UTC 24 |
Oct 10 08:08:29 AM UTC 24 |
15841158398 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2901640149 |
|
|
Oct 10 08:01:06 AM UTC 24 |
Oct 10 08:08:46 AM UTC 24 |
3249705032 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.3317378642 |
|
|
Oct 10 07:55:59 AM UTC 24 |
Oct 10 08:08:57 AM UTC 24 |
5432692600 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.2090049293 |
|
|
Oct 10 07:57:57 AM UTC 24 |
Oct 10 08:09:32 AM UTC 24 |
5507967496 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639146307 |
|
|
Oct 10 08:01:09 AM UTC 24 |
Oct 10 08:09:32 AM UTC 24 |
3566228750 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.3767327095 |
|
|
Oct 10 08:00:59 AM UTC 24 |
Oct 10 08:09:52 AM UTC 24 |
4570143002 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.316020543 |
|
|
Oct 10 07:57:13 AM UTC 24 |
Oct 10 08:09:54 AM UTC 24 |
5085633820 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142189764 |
|
|
Oct 10 08:04:10 AM UTC 24 |
Oct 10 08:10:15 AM UTC 24 |
3618919870 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601955049 |
|
|
Oct 10 08:03:46 AM UTC 24 |
Oct 10 08:10:23 AM UTC 24 |
4199617536 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3016434704 |
|
|
Oct 10 07:42:51 AM UTC 24 |
Oct 10 08:10:38 AM UTC 24 |
8686404930 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.4173337592 |
|
|
Oct 10 08:01:02 AM UTC 24 |
Oct 10 08:10:42 AM UTC 24 |
5837017096 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.1026570036 |
|
|
Oct 10 07:40:56 AM UTC 24 |
Oct 10 08:10:59 AM UTC 24 |
8256235290 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1585710898 |
|
|
Oct 10 07:59:33 AM UTC 24 |
Oct 10 08:11:45 AM UTC 24 |
6509702740 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1264144273 |
|
|
Oct 10 08:03:36 AM UTC 24 |
Oct 10 08:11:53 AM UTC 24 |
3842100700 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.2082998751 |
|
|
Oct 10 08:00:41 AM UTC 24 |
Oct 10 08:12:03 AM UTC 24 |
4619753566 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.73736116 |
|
|
Oct 10 08:04:43 AM UTC 24 |
Oct 10 08:12:13 AM UTC 24 |
3989195856 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3242126341 |
|
|
Oct 10 06:50:09 AM UTC 24 |
Oct 10 08:12:21 AM UTC 24 |
14715326900 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.1338264161 |
|
|
Oct 10 07:59:20 AM UTC 24 |
Oct 10 08:12:26 AM UTC 24 |
6014574228 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3718578131 |
|
|
Oct 10 08:04:27 AM UTC 24 |
Oct 10 08:12:41 AM UTC 24 |
3646176782 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1730940397 |
|
|
Oct 10 08:02:35 AM UTC 24 |
Oct 10 08:12:42 AM UTC 24 |
4504300860 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.1243127833 |
|
|
Oct 10 08:04:22 AM UTC 24 |
Oct 10 08:13:19 AM UTC 24 |
4996258280 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055359889 |
|
|
Oct 10 08:05:27 AM UTC 24 |
Oct 10 08:13:20 AM UTC 24 |
3845959538 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.213753802 |
|
|
Oct 10 08:05:27 AM UTC 24 |
Oct 10 08:13:20 AM UTC 24 |
3622022376 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3013495715 |
|
|
Oct 10 08:01:09 AM UTC 24 |
Oct 10 08:13:51 AM UTC 24 |
6193967736 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.4077757422 |
|
|
Oct 10 06:50:30 AM UTC 24 |
Oct 10 08:13:54 AM UTC 24 |
17775833384 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.462190850 |
|
|
Oct 10 08:02:26 AM UTC 24 |
Oct 10 08:14:26 AM UTC 24 |
4837756536 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.3522174427 |
|
|
Oct 10 08:03:37 AM UTC 24 |
Oct 10 08:14:39 AM UTC 24 |
4500293592 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060238638 |
|
|
Oct 10 08:08:04 AM UTC 24 |
Oct 10 08:14:52 AM UTC 24 |
3916379090 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2693759201 |
|
|
Oct 10 08:08:38 AM UTC 24 |
Oct 10 08:14:52 AM UTC 24 |
3853423740 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.1824500839 |
|
|
Oct 10 08:04:28 AM UTC 24 |
Oct 10 08:14:55 AM UTC 24 |
4651694272 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2722483289 |
|
|
Oct 10 08:07:35 AM UTC 24 |
Oct 10 08:15:07 AM UTC 24 |
3769652384 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.1665268856 |
|
|
Oct 10 06:49:09 AM UTC 24 |
Oct 10 08:15:14 AM UTC 24 |
15884195245 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451162138 |
|
|
Oct 10 08:09:03 AM UTC 24 |
Oct 10 08:15:18 AM UTC 24 |
3111896802 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1457037803 |
|
|
Oct 10 06:48:57 AM UTC 24 |
Oct 10 08:15:27 AM UTC 24 |
15214488910 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069797338 |
|
|
Oct 10 08:09:08 AM UTC 24 |
Oct 10 08:15:47 AM UTC 24 |
3842209532 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3102600456 |
|
|
Oct 10 08:04:09 AM UTC 24 |
Oct 10 08:15:47 AM UTC 24 |
5596873886 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380706714 |
|
|
Oct 10 08:09:04 AM UTC 24 |
Oct 10 08:15:52 AM UTC 24 |
4061962180 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839841540 |
|
|
Oct 10 08:09:03 AM UTC 24 |
Oct 10 08:16:18 AM UTC 24 |
3650458160 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.217744452 |
|
|
Oct 10 08:10:57 AM UTC 24 |
Oct 10 08:16:35 AM UTC 24 |
3475423128 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2862853242 |
|
|
Oct 10 08:04:46 AM UTC 24 |
Oct 10 08:17:13 AM UTC 24 |
5378220104 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.416632256 |
|
|
Oct 10 08:05:45 AM UTC 24 |
Oct 10 08:17:18 AM UTC 24 |
4695633916 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.3251527192 |
|
|
Oct 10 08:08:23 AM UTC 24 |
Oct 10 08:17:41 AM UTC 24 |
5688701684 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4003971919 |
|
|
Oct 10 08:12:02 AM UTC 24 |
Oct 10 08:17:43 AM UTC 24 |
4021225916 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969728475 |
|
|
Oct 10 08:12:03 AM UTC 24 |
Oct 10 08:17:48 AM UTC 24 |
3784464648 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3258023752 |
|
|
Oct 10 06:43:30 AM UTC 24 |
Oct 10 08:17:56 AM UTC 24 |
23284218501 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.1469910135 |
|
|
Oct 10 08:08:03 AM UTC 24 |
Oct 10 08:18:01 AM UTC 24 |
5394370872 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.3001715497 |
|
|
Oct 10 08:09:10 AM UTC 24 |
Oct 10 08:18:05 AM UTC 24 |
5363767640 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169745454 |
|
|
Oct 10 08:12:07 AM UTC 24 |
Oct 10 08:18:10 AM UTC 24 |
3530017058 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.4161083927 |
|
|
Oct 10 08:08:34 AM UTC 24 |
Oct 10 08:18:29 AM UTC 24 |
5814143366 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.501453644 |
|
|
Oct 10 08:05:26 AM UTC 24 |
Oct 10 08:18:49 AM UTC 24 |
6161389724 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888386722 |
|
|
Oct 10 08:13:22 AM UTC 24 |
Oct 10 08:19:05 AM UTC 24 |
3029420868 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3718729485 |
|
|
Oct 10 08:09:08 AM UTC 24 |
Oct 10 08:19:06 AM UTC 24 |
5866951080 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.1596250518 |
|
|
Oct 10 08:09:34 AM UTC 24 |
Oct 10 08:19:08 AM UTC 24 |
5622119500 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.2111063661 |
|
|
Oct 10 08:09:02 AM UTC 24 |
Oct 10 08:19:14 AM UTC 24 |
4618620640 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1669904732 |
|
|
Oct 10 08:14:06 AM UTC 24 |
Oct 10 08:19:58 AM UTC 24 |
3805281608 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285925286 |
|
|
Oct 10 08:13:41 AM UTC 24 |
Oct 10 08:20:10 AM UTC 24 |
4125290684 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.439590754 |
|
|
Oct 10 08:14:50 AM UTC 24 |
Oct 10 08:20:15 AM UTC 24 |
3832139250 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2482757809 |
|
|
Oct 10 08:09:38 AM UTC 24 |
Oct 10 08:20:32 AM UTC 24 |
4605319954 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.1216797606 |
|
|
Oct 10 08:12:02 AM UTC 24 |
Oct 10 08:21:05 AM UTC 24 |
5064225384 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.4254429399 |
|
|
Oct 10 08:11:22 AM UTC 24 |
Oct 10 08:21:06 AM UTC 24 |
6010859400 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424453409 |
|
|
Oct 10 08:14:22 AM UTC 24 |
Oct 10 08:21:12 AM UTC 24 |
3885206844 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.612700802 |
|
|
Oct 10 08:12:05 AM UTC 24 |
Oct 10 08:21:13 AM UTC 24 |
4931268728 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.631642310 |
|
|
Oct 10 08:13:01 AM UTC 24 |
Oct 10 08:21:27 AM UTC 24 |
4228582150 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2686022640 |
|
|
Oct 10 08:10:44 AM UTC 24 |
Oct 10 08:21:30 AM UTC 24 |
5189648350 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3576588953 |
|
|
Oct 10 08:16:03 AM UTC 24 |
Oct 10 08:21:45 AM UTC 24 |
3870723630 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1103341871 |
|
|
Oct 10 08:13:39 AM UTC 24 |
Oct 10 08:21:49 AM UTC 24 |
5218311344 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1884539066 |
|
|
Oct 10 08:15:29 AM UTC 24 |
Oct 10 08:22:27 AM UTC 24 |
3659812140 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2722149628 |
|
|
Oct 10 08:13:02 AM UTC 24 |
Oct 10 08:22:31 AM UTC 24 |
4881343900 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.3954156527 |
|
|
Oct 10 08:13:42 AM UTC 24 |
Oct 10 08:22:46 AM UTC 24 |
4397104340 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1126866006 |
|
|
Oct 10 08:17:40 AM UTC 24 |
Oct 10 08:23:19 AM UTC 24 |
3492109428 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.388351929 |
|
|
Oct 10 08:14:47 AM UTC 24 |
Oct 10 08:24:06 AM UTC 24 |
4794301224 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258410671 |
|
|
Oct 10 08:18:16 AM UTC 24 |
Oct 10 08:24:22 AM UTC 24 |
4186735016 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243703630 |
|
|
Oct 10 08:19:39 AM UTC 24 |
Oct 10 08:24:44 AM UTC 24 |
3354974594 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2388290513 |
|
|
Oct 10 08:19:21 AM UTC 24 |
Oct 10 08:24:59 AM UTC 24 |
3319182422 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.134700869 |
|
|
Oct 10 08:14:05 AM UTC 24 |
Oct 10 08:25:03 AM UTC 24 |
5360877720 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.464205669 |
|
|
Oct 10 08:16:36 AM UTC 24 |
Oct 10 08:25:07 AM UTC 24 |
5692645000 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246761196 |
|
|
Oct 10 08:18:27 AM UTC 24 |
Oct 10 08:26:03 AM UTC 24 |
4554590090 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1691004158 |
|
|
Oct 10 08:17:00 AM UTC 24 |
Oct 10 08:26:16 AM UTC 24 |
4440463450 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3146476249 |
|
|
Oct 10 08:19:02 AM UTC 24 |
Oct 10 08:26:17 AM UTC 24 |
3609818536 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2641127488 |
|
|
Oct 10 08:21:31 AM UTC 24 |
Oct 10 08:26:26 AM UTC 24 |
3233512648 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3998375695 |
|
|
Oct 10 08:15:06 AM UTC 24 |
Oct 10 08:26:28 AM UTC 24 |
5941789700 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144752577 |
|
|
Oct 10 08:20:42 AM UTC 24 |
Oct 10 08:26:53 AM UTC 24 |
3733745596 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3253652391 |
|
|
Oct 10 08:16:03 AM UTC 24 |
Oct 10 08:27:00 AM UTC 24 |
4755656700 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069001756 |
|
|
Oct 10 08:21:09 AM UTC 24 |
Oct 10 08:27:09 AM UTC 24 |
3794318748 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.3579991962 |
|
|
Oct 10 08:18:50 AM UTC 24 |
Oct 10 08:27:11 AM UTC 24 |
5488056902 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.315037259 |
|
|
Oct 10 08:21:17 AM UTC 24 |
Oct 10 08:27:14 AM UTC 24 |
3779440272 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703655848 |
|
|
Oct 10 08:21:54 AM UTC 24 |
Oct 10 08:27:21 AM UTC 24 |
3413376120 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.63449308 |
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|
Oct 10 08:21:12 AM UTC 24 |
Oct 10 08:27:25 AM UTC 24 |
4005583034 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.3286064977 |
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|
Oct 10 08:18:50 AM UTC 24 |
Oct 10 08:28:04 AM UTC 24 |
4803528910 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.4241105748 |
|
|
Oct 10 08:18:13 AM UTC 24 |
Oct 10 08:29:03 AM UTC 24 |
5804296604 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3338695575 |
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|
Oct 10 08:21:55 AM UTC 24 |
Oct 10 08:29:06 AM UTC 24 |
3431205854 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.3617013163 |
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|
Oct 10 08:20:55 AM UTC 24 |
Oct 10 08:29:06 AM UTC 24 |
4058966548 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3397592315 |
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|
Oct 10 08:22:19 AM UTC 24 |
Oct 10 08:29:09 AM UTC 24 |
4042215080 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.1090702688 |
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|
Oct 10 08:19:13 AM UTC 24 |
Oct 10 08:29:29 AM UTC 24 |
5314094122 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.250897112 |
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|
Oct 10 08:21:20 AM UTC 24 |
Oct 10 08:30:04 AM UTC 24 |
5789538800 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.2232510153 |
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|
Oct 10 08:21:16 AM UTC 24 |
Oct 10 08:30:28 AM UTC 24 |
5487684040 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.967979999 |
|
|
Oct 10 08:22:48 AM UTC 24 |
Oct 10 08:31:04 AM UTC 24 |
6103992808 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.963512038 |
|
|
Oct 10 08:22:57 AM UTC 24 |
Oct 10 08:31:13 AM UTC 24 |
4906453602 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.1156849534 |
|
|
Oct 10 08:20:45 AM UTC 24 |
Oct 10 08:31:39 AM UTC 24 |
5461852616 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.2946680354 |
|
|
Oct 10 08:20:50 AM UTC 24 |
Oct 10 08:31:41 AM UTC 24 |
6283267312 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.1433395049 |
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|
Oct 10 08:20:47 AM UTC 24 |
Oct 10 08:31:44 AM UTC 24 |
6404053164 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.2281789076 |
|
|
Oct 10 08:21:54 AM UTC 24 |
Oct 10 08:31:51 AM UTC 24 |
4830587322 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2679189536 |
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|
Oct 10 08:22:41 AM UTC 24 |
Oct 10 08:31:53 AM UTC 24 |
4285008192 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.3527376741 |
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|
Oct 10 07:22:55 AM UTC 24 |
Oct 10 08:31:54 AM UTC 24 |
15615890984 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.811929512 |
|
|
Oct 10 08:22:58 AM UTC 24 |
Oct 10 08:32:02 AM UTC 24 |
4021858646 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3468470699 |
|
|
Oct 10 08:22:55 AM UTC 24 |
Oct 10 08:32:04 AM UTC 24 |
4762606174 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1149779018 |
|
|
Oct 10 08:23:02 AM UTC 24 |
Oct 10 08:32:07 AM UTC 24 |
5681649620 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3345595170 |
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|
Oct 10 07:22:04 AM UTC 24 |
Oct 10 08:32:07 AM UTC 24 |
14727263456 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.1345859585 |
|
|
Oct 10 08:21:17 AM UTC 24 |
Oct 10 08:32:11 AM UTC 24 |
4322899828 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.721422454 |
|
|
Oct 10 08:21:12 AM UTC 24 |
Oct 10 08:32:36 AM UTC 24 |
5272445376 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.3817777363 |
|
|
Oct 10 08:22:59 AM UTC 24 |
Oct 10 08:32:56 AM UTC 24 |
5888474950 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2687396940 |
|
|
Oct 10 08:23:01 AM UTC 24 |
Oct 10 08:33:46 AM UTC 24 |
5425040920 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.2696962496 |
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|
Oct 10 07:25:55 AM UTC 24 |
Oct 10 08:48:31 AM UTC 24 |
18960020684 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.3744497351 |
|
|
Oct 10 03:58:38 AM UTC 24 |
Oct 10 08:53:54 AM UTC 24 |
67733169074 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.320211291 |
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|
Oct 10 06:50:25 AM UTC 24 |
Oct 10 08:56:15 AM UTC 24 |
26039085208 ps |