| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.765900565 |
|
|
Oct 09 11:25:08 PM UTC 24 |
Oct 09 11:30:29 PM UTC 24 |
4511409150 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2884542380 |
|
|
Oct 09 11:30:23 PM UTC 24 |
Oct 09 11:30:33 PM UTC 24 |
41538716 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3188808659 |
|
|
Oct 09 11:25:02 PM UTC 24 |
Oct 09 11:30:42 PM UTC 24 |
3767205105 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.757822416 |
|
|
Oct 09 11:30:37 PM UTC 24 |
Oct 09 11:30:51 PM UTC 24 |
60252608 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1594486410 |
|
|
Oct 09 11:12:28 PM UTC 24 |
Oct 09 11:31:06 PM UTC 24 |
76306520088 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2136643750 |
|
|
Oct 09 11:03:37 PM UTC 24 |
Oct 09 11:31:10 PM UTC 24 |
105496215846 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1666300659 |
|
|
Oct 09 11:25:22 PM UTC 24 |
Oct 09 11:31:11 PM UTC 24 |
3583540769 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.4007958237 |
|
|
Oct 09 11:30:20 PM UTC 24 |
Oct 09 11:31:17 PM UTC 24 |
594018858 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3368581136 |
|
|
Oct 09 11:31:13 PM UTC 24 |
Oct 09 11:31:24 PM UTC 24 |
47921385 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.2107210157 |
|
|
Oct 09 11:30:35 PM UTC 24 |
Oct 09 11:31:33 PM UTC 24 |
1301505211 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4045234695 |
|
|
Oct 09 11:31:28 PM UTC 24 |
Oct 09 11:31:38 PM UTC 24 |
52295588 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.779082543 |
|
|
Oct 09 11:29:35 PM UTC 24 |
Oct 09 11:31:51 PM UTC 24 |
2696065102 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.377030769 |
|
|
Oct 09 11:31:47 PM UTC 24 |
Oct 09 11:32:23 PM UTC 24 |
351424377 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1677620162 |
|
|
Oct 09 11:22:41 PM UTC 24 |
Oct 09 11:32:26 PM UTC 24 |
5725492988 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1314659340 |
|
|
Oct 09 11:31:40 PM UTC 24 |
Oct 09 11:32:41 PM UTC 24 |
1232130585 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2126310802 |
|
|
Oct 09 11:31:33 PM UTC 24 |
Oct 09 11:32:45 PM UTC 24 |
7318393828 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1638706964 |
|
|
Oct 09 11:32:14 PM UTC 24 |
Oct 09 11:32:46 PM UTC 24 |
172146381 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.1669903452 |
|
|
Oct 09 11:32:49 PM UTC 24 |
Oct 09 11:33:03 PM UTC 24 |
78303882 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3735815953 |
|
|
Oct 09 11:17:50 PM UTC 24 |
Oct 09 11:33:12 PM UTC 24 |
10334742685 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3656487738 |
|
|
Oct 09 11:33:04 PM UTC 24 |
Oct 09 11:33:15 PM UTC 24 |
128707011 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.853005059 |
|
|
Oct 09 11:22:45 PM UTC 24 |
Oct 09 11:33:19 PM UTC 24 |
5561231330 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.539101899 |
|
|
Oct 09 11:33:10 PM UTC 24 |
Oct 09 11:33:24 PM UTC 24 |
53595637 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.2912781545 |
|
|
Oct 09 11:18:45 PM UTC 24 |
Oct 09 11:33:32 PM UTC 24 |
94456160839 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.3534791654 |
|
|
Oct 09 11:27:35 PM UTC 24 |
Oct 09 11:33:41 PM UTC 24 |
9289323816 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3807262679 |
|
|
Oct 09 11:33:09 PM UTC 24 |
Oct 09 11:33:42 PM UTC 24 |
228812999 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.773601686 |
|
|
Oct 09 11:31:34 PM UTC 24 |
Oct 09 11:33:55 PM UTC 24 |
6219691565 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1967192105 |
|
|
Oct 09 11:30:46 PM UTC 24 |
Oct 09 11:33:58 PM UTC 24 |
4346407245 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.3123497157 |
|
|
Oct 09 11:25:59 PM UTC 24 |
Oct 09 11:34:15 PM UTC 24 |
51165809975 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.3094306290 |
|
|
Oct 09 11:21:36 PM UTC 24 |
Oct 09 11:34:16 PM UTC 24 |
68780922590 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2644212526 |
|
|
Oct 09 11:34:18 PM UTC 24 |
Oct 09 11:34:28 PM UTC 24 |
51694812 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.841301970 |
|
|
Oct 09 11:34:19 PM UTC 24 |
Oct 09 11:34:34 PM UTC 24 |
228529068 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.4171460822 |
|
|
Oct 09 11:31:10 PM UTC 24 |
Oct 09 11:35:12 PM UTC 24 |
3409214358 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3165662840 |
|
|
Oct 09 11:33:38 PM UTC 24 |
Oct 09 11:35:30 PM UTC 24 |
1326803101 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.732438818 |
|
|
Oct 09 11:29:18 PM UTC 24 |
Oct 09 11:35:30 PM UTC 24 |
35298646671 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.2952107192 |
|
|
Oct 09 11:34:52 PM UTC 24 |
Oct 09 11:35:33 PM UTC 24 |
299891088 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.370219109 |
|
|
Oct 09 11:34:57 PM UTC 24 |
Oct 09 11:35:35 PM UTC 24 |
399267115 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1474173806 |
|
|
Oct 09 11:30:46 PM UTC 24 |
Oct 09 11:35:41 PM UTC 24 |
820198184 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1649930535 |
|
|
Oct 09 11:35:54 PM UTC 24 |
Oct 09 11:36:30 PM UTC 24 |
364667744 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.773253789 |
|
|
Oct 09 11:34:39 PM UTC 24 |
Oct 09 11:36:35 PM UTC 24 |
4700372089 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.4006330791 |
|
|
Oct 09 11:35:59 PM UTC 24 |
Oct 09 11:36:40 PM UTC 24 |
1536879444 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3752365380 |
|
|
Oct 09 11:36:04 PM UTC 24 |
Oct 09 11:36:55 PM UTC 24 |
1033796818 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.3479746715 |
|
|
Oct 09 11:34:38 PM UTC 24 |
Oct 09 11:36:58 PM UTC 24 |
9931813665 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3345065460 |
|
|
Oct 09 11:24:07 PM UTC 24 |
Oct 09 11:37:24 PM UTC 24 |
46955246628 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1408111623 |
|
|
Oct 09 11:33:34 PM UTC 24 |
Oct 09 11:37:24 PM UTC 24 |
421381381 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2313236855 |
|
|
Oct 09 11:36:58 PM UTC 24 |
Oct 09 11:37:29 PM UTC 24 |
173797782 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.3947334431 |
|
|
Oct 09 11:29:32 PM UTC 24 |
Oct 09 11:37:31 PM UTC 24 |
26679586765 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4278245731 |
|
|
Oct 09 11:27:45 PM UTC 24 |
Oct 09 11:37:37 PM UTC 24 |
12241464679 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.4153605040 |
|
|
Oct 09 11:28:22 PM UTC 24 |
Oct 09 11:37:40 PM UTC 24 |
5787311806 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.2713052709 |
|
|
Oct 09 11:36:53 PM UTC 24 |
Oct 09 11:37:45 PM UTC 24 |
1142470065 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.2011568414 |
|
|
Oct 09 11:34:04 PM UTC 24 |
Oct 09 11:37:54 PM UTC 24 |
3489545946 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.86464572 |
|
|
Oct 09 11:38:03 PM UTC 24 |
Oct 09 11:38:14 PM UTC 24 |
51456595 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.390773801 |
|
|
Oct 09 11:38:06 PM UTC 24 |
Oct 09 11:38:17 PM UTC 24 |
48280739 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.991186316 |
|
|
Oct 09 11:30:38 PM UTC 24 |
Oct 09 11:38:18 PM UTC 24 |
4720945527 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.265646749 |
|
|
Oct 09 11:23:49 PM UTC 24 |
Oct 09 11:38:29 PM UTC 24 |
89874987802 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.4181157037 |
|
|
Oct 09 11:03:03 PM UTC 24 |
Oct 09 11:38:31 PM UTC 24 |
16406210460 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3518537483 |
|
|
Oct 09 11:09:28 PM UTC 24 |
Oct 09 11:38:33 PM UTC 24 |
98468093979 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2640977558 |
|
|
Oct 09 11:37:46 PM UTC 24 |
Oct 09 11:38:35 PM UTC 24 |
139222187 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.1785370377 |
|
|
Oct 09 11:33:28 PM UTC 24 |
Oct 09 11:38:37 PM UTC 24 |
3387467773 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.3251141969 |
|
|
Oct 09 11:37:03 PM UTC 24 |
Oct 09 11:38:41 PM UTC 24 |
902101484 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.579253969 |
|
|
Oct 09 11:30:40 PM UTC 24 |
Oct 09 11:38:54 PM UTC 24 |
9917195281 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1032354397 |
|
|
Oct 09 11:27:46 PM UTC 24 |
Oct 09 11:38:59 PM UTC 24 |
6487870828 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3044397418 |
|
|
Oct 09 11:37:18 PM UTC 24 |
Oct 09 11:39:11 PM UTC 24 |
240822020 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.555936241 |
|
|
Oct 09 11:38:40 PM UTC 24 |
Oct 09 11:39:19 PM UTC 24 |
301533730 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4256381456 |
|
|
Oct 09 11:33:40 PM UTC 24 |
Oct 09 11:39:26 PM UTC 24 |
3895484529 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.2868202625 |
|
|
Oct 09 11:38:55 PM UTC 24 |
Oct 09 11:39:27 PM UTC 24 |
357273835 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.275933692 |
|
|
Oct 09 11:39:18 PM UTC 24 |
Oct 09 11:39:31 PM UTC 24 |
94324755 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.1718271535 |
|
|
Oct 09 11:38:59 PM UTC 24 |
Oct 09 11:39:35 PM UTC 24 |
443847676 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3845034450 |
|
|
Oct 09 11:38:38 PM UTC 24 |
Oct 09 11:39:37 PM UTC 24 |
589494192 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3911966141 |
|
|
Oct 09 11:39:22 PM UTC 24 |
Oct 09 11:39:44 PM UTC 24 |
312328688 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.360060475 |
|
|
Oct 09 11:38:16 PM UTC 24 |
Oct 09 11:39:53 PM UTC 24 |
9379684924 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1128448340 |
|
|
Oct 09 11:22:45 PM UTC 24 |
Oct 09 11:39:59 PM UTC 24 |
12221092950 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.1079030232 |
|
|
Oct 09 11:32:01 PM UTC 24 |
Oct 09 11:39:59 PM UTC 24 |
36154221541 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2276145765 |
|
|
Oct 09 11:30:57 PM UTC 24 |
Oct 09 11:40:00 PM UTC 24 |
6017236856 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.29717394 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:40:02 PM UTC 24 |
143683133376 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3425531436 |
|
|
Oct 09 11:38:34 PM UTC 24 |
Oct 09 11:40:05 PM UTC 24 |
5704009723 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1926777467 |
|
|
Oct 09 11:24:52 PM UTC 24 |
Oct 09 11:40:17 PM UTC 24 |
15101451388 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.1396092055 |
|
|
Oct 09 11:39:03 PM UTC 24 |
Oct 09 11:40:20 PM UTC 24 |
1641770851 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.4034017280 |
|
|
Oct 09 11:40:14 PM UTC 24 |
Oct 09 11:40:23 PM UTC 24 |
39110665 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1887879927 |
|
|
Oct 09 11:40:22 PM UTC 24 |
Oct 09 11:40:32 PM UTC 24 |
45107616 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3119267226 |
|
|
Oct 09 11:19:09 PM UTC 24 |
Oct 09 11:40:36 PM UTC 24 |
83567792655 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.2896662265 |
|
|
Oct 09 11:40:26 PM UTC 24 |
Oct 09 11:40:37 PM UTC 24 |
46424183 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.3947781203 |
|
|
Oct 09 11:40:23 PM UTC 24 |
Oct 09 11:40:39 PM UTC 24 |
87358708 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2571043381 |
|
|
Oct 09 11:39:40 PM UTC 24 |
Oct 09 11:40:47 PM UTC 24 |
106589389 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.1234051207 |
|
|
Oct 09 11:26:12 PM UTC 24 |
Oct 09 11:41:17 PM UTC 24 |
57123093603 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.930459764 |
|
|
Oct 09 11:40:59 PM UTC 24 |
Oct 09 11:41:19 PM UTC 24 |
264510150 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1209673123 |
|
|
Oct 09 11:41:10 PM UTC 24 |
Oct 09 11:41:23 PM UTC 24 |
237055962 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.2717932208 |
|
|
Oct 09 11:38:01 PM UTC 24 |
Oct 09 11:41:31 PM UTC 24 |
2870780340 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1473812925 |
|
|
Oct 09 11:35:57 PM UTC 24 |
Oct 09 11:41:35 PM UTC 24 |
20832408420 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.878461655 |
|
|
Oct 09 11:25:18 PM UTC 24 |
Oct 09 11:41:40 PM UTC 24 |
9363215807 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1773086628 |
|
|
Oct 09 11:23:50 PM UTC 24 |
Oct 09 11:41:45 PM UTC 24 |
69564720812 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2026006248 |
|
|
Oct 09 11:40:23 PM UTC 24 |
Oct 09 11:41:45 PM UTC 24 |
3652573075 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.3710837495 |
|
|
Oct 09 11:41:00 PM UTC 24 |
Oct 09 11:41:50 PM UTC 24 |
414849334 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.940796836 |
|
|
Oct 09 11:40:46 PM UTC 24 |
Oct 09 11:42:01 PM UTC 24 |
780495263 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.1304133976 |
|
|
Oct 09 11:40:59 PM UTC 24 |
Oct 09 11:42:05 PM UTC 24 |
1577006972 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.4101055225 |
|
|
Oct 09 11:42:11 PM UTC 24 |
Oct 09 11:42:22 PM UTC 24 |
46979241 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3189189463 |
|
|
Oct 09 11:40:23 PM UTC 24 |
Oct 09 11:42:25 PM UTC 24 |
7828129830 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1358114347 |
|
|
Oct 09 11:42:24 PM UTC 24 |
Oct 09 11:42:34 PM UTC 24 |
45791224 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3717538900 |
|
|
Oct 09 11:31:57 PM UTC 24 |
Oct 09 11:42:41 PM UTC 24 |
65110958269 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3740186533 |
|
|
Oct 09 11:37:46 PM UTC 24 |
Oct 09 11:43:09 PM UTC 24 |
4293164750 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.3763652044 |
|
|
Oct 09 11:35:53 PM UTC 24 |
Oct 09 11:43:20 PM UTC 24 |
31930181828 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3284861881 |
|
|
Oct 09 11:32:46 PM UTC 24 |
Oct 09 11:43:20 PM UTC 24 |
36103286918 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.2799376113 |
|
|
Oct 09 11:30:52 PM UTC 24 |
Oct 09 11:43:32 PM UTC 24 |
5798126955 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.2920960886 |
|
|
Oct 09 11:42:47 PM UTC 24 |
Oct 09 11:43:52 PM UTC 24 |
1487565312 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.2203277510 |
|
|
Oct 09 11:42:56 PM UTC 24 |
Oct 09 11:43:53 PM UTC 24 |
447491179 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.517047745 |
|
|
Oct 09 11:33:45 PM UTC 24 |
Oct 09 11:44:00 PM UTC 24 |
5519089290 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2906649162 |
|
|
Oct 09 11:42:45 PM UTC 24 |
Oct 09 11:44:03 PM UTC 24 |
4710967776 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.1889383638 |
|
|
Oct 09 11:40:08 PM UTC 24 |
Oct 09 11:44:15 PM UTC 24 |
3401443500 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.3151492247 |
|
|
Oct 09 11:43:55 PM UTC 24 |
Oct 09 11:44:17 PM UTC 24 |
476093607 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.2191047629 |
|
|
Oct 09 11:44:16 PM UTC 24 |
Oct 09 11:44:27 PM UTC 24 |
65992876 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.4284414920 |
|
|
Oct 09 11:28:06 PM UTC 24 |
Oct 09 11:44:35 PM UTC 24 |
12578432543 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2649260881 |
|
|
Oct 09 11:27:27 PM UTC 24 |
Oct 09 11:44:35 PM UTC 24 |
6219181042 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3218075918 |
|
|
Oct 09 11:42:28 PM UTC 24 |
Oct 09 11:44:36 PM UTC 24 |
8194316395 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2990837935 |
|
|
Oct 09 11:37:52 PM UTC 24 |
Oct 09 11:44:37 PM UTC 24 |
5178801477 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.2324508500 |
|
|
Oct 09 11:44:16 PM UTC 24 |
Oct 09 11:44:52 PM UTC 24 |
720725340 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.340813403 |
|
|
Oct 09 11:44:39 PM UTC 24 |
Oct 09 11:45:01 PM UTC 24 |
7983108 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3176792557 |
|
|
Oct 09 11:44:26 PM UTC 24 |
Oct 09 11:45:07 PM UTC 24 |
1029072560 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.275334840 |
|
|
Oct 09 11:43:40 PM UTC 24 |
Oct 09 11:45:14 PM UTC 24 |
1051659203 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3004868994 |
|
|
Oct 09 11:41:42 PM UTC 24 |
Oct 09 11:45:19 PM UTC 24 |
386325246 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3594217773 |
|
|
Oct 09 11:44:24 PM UTC 24 |
Oct 09 11:45:21 PM UTC 24 |
1224762339 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1708689090 |
|
|
Oct 09 11:41:54 PM UTC 24 |
Oct 09 11:45:23 PM UTC 24 |
752768758 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2607819532 |
|
|
Oct 09 11:41:38 PM UTC 24 |
Oct 09 11:45:25 PM UTC 24 |
2351813734 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.2184531828 |
|
|
Oct 09 11:45:15 PM UTC 24 |
Oct 09 11:45:29 PM UTC 24 |
213832912 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.75319882 |
|
|
Oct 09 11:45:22 PM UTC 24 |
Oct 09 11:45:33 PM UTC 24 |
48695663 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.314240957 |
|
|
Oct 09 11:39:53 PM UTC 24 |
Oct 09 11:45:47 PM UTC 24 |
4850851480 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.3729628860 |
|
|
Oct 09 11:39:48 PM UTC 24 |
Oct 09 11:45:52 PM UTC 24 |
9389343644 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.697907695 |
|
|
Oct 09 11:40:42 PM UTC 24 |
Oct 09 11:46:01 PM UTC 24 |
16039566196 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.1386328031 |
|
|
Oct 09 11:45:43 PM UTC 24 |
Oct 09 11:46:03 PM UTC 24 |
512088697 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.362356168 |
|
|
Oct 09 11:39:49 PM UTC 24 |
Oct 09 11:46:09 PM UTC 24 |
7862839777 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.2973722464 |
|
|
Oct 09 11:45:43 PM UTC 24 |
Oct 09 11:46:09 PM UTC 24 |
198614110 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.1502759208 |
|
|
Oct 09 11:41:46 PM UTC 24 |
Oct 09 11:46:16 PM UTC 24 |
6601325229 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.3866068632 |
|
|
Oct 09 11:46:07 PM UTC 24 |
Oct 09 11:46:34 PM UTC 24 |
262440482 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.1402777167 |
|
|
Oct 09 11:46:23 PM UTC 24 |
Oct 09 11:46:46 PM UTC 24 |
102560877 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.18223962 |
|
|
Oct 09 11:39:32 PM UTC 24 |
Oct 09 11:46:53 PM UTC 24 |
10983459759 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2951308768 |
|
|
Oct 09 11:46:12 PM UTC 24 |
Oct 09 11:46:54 PM UTC 24 |
958421301 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.1365033618 |
|
|
Oct 09 11:44:40 PM UTC 24 |
Oct 09 11:46:57 PM UTC 24 |
4200006641 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3537606424 |
|
|
Oct 09 11:45:36 PM UTC 24 |
Oct 09 11:47:00 PM UTC 24 |
4911991195 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2087651762 |
|
|
Oct 09 11:46:25 PM UTC 24 |
Oct 09 11:47:01 PM UTC 24 |
212343846 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2739819974 |
|
|
Oct 09 11:42:07 PM UTC 24 |
Oct 09 11:47:17 PM UTC 24 |
4223318893 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.2151362377 |
|
|
Oct 09 11:40:41 PM UTC 24 |
Oct 09 11:47:29 PM UTC 24 |
36718796740 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1630328580 |
|
|
Oct 09 11:45:29 PM UTC 24 |
Oct 09 11:47:30 PM UTC 24 |
7644902078 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2017468498 |
|
|
Oct 09 11:47:21 PM UTC 24 |
Oct 09 11:47:33 PM UTC 24 |
194379705 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2819918793 |
|
|
Oct 09 11:47:25 PM UTC 24 |
Oct 09 11:47:34 PM UTC 24 |
43160948 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.2405037880 |
|
|
Oct 09 11:45:51 PM UTC 24 |
Oct 09 11:47:50 PM UTC 24 |
2430667630 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.2450086759 |
|
|
Oct 09 11:46:31 PM UTC 24 |
Oct 09 11:48:12 PM UTC 24 |
1096923483 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.2021412761 |
|
|
Oct 09 11:47:56 PM UTC 24 |
Oct 09 11:48:31 PM UTC 24 |
300844808 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.2476526404 |
|
|
Oct 09 11:37:22 PM UTC 24 |
Oct 09 11:48:34 PM UTC 24 |
16789615337 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3698212383 |
|
|
Oct 09 11:41:58 PM UTC 24 |
Oct 09 11:48:47 PM UTC 24 |
4248361080 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1669315682 |
|
|
Oct 09 11:48:14 PM UTC 24 |
Oct 09 11:49:00 PM UTC 24 |
1861252539 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3111273473 |
|
|
Oct 09 11:47:53 PM UTC 24 |
Oct 09 11:49:01 PM UTC 24 |
1248137979 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.258028260 |
|
|
Oct 09 11:35:34 PM UTC 24 |
Oct 09 11:49:04 PM UTC 24 |
74353097147 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.1068994895 |
|
|
Oct 09 11:47:41 PM UTC 24 |
Oct 09 11:49:05 PM UTC 24 |
9431498139 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3692270002 |
|
|
Oct 09 11:40:52 PM UTC 24 |
Oct 09 11:49:22 PM UTC 24 |
25528645647 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.2906159399 |
|
|
Oct 09 11:48:34 PM UTC 24 |
Oct 09 11:49:46 PM UTC 24 |
665807641 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2702081367 |
|
|
Oct 09 11:49:22 PM UTC 24 |
Oct 09 11:49:48 PM UTC 24 |
374966915 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.21975105 |
|
|
Oct 09 11:48:56 PM UTC 24 |
Oct 09 11:49:49 PM UTC 24 |
1416933418 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2458529174 |
|
|
Oct 09 11:47:52 PM UTC 24 |
Oct 09 11:49:53 PM UTC 24 |
6364840007 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.237758205 |
|
|
Oct 09 11:49:25 PM UTC 24 |
Oct 09 11:50:06 PM UTC 24 |
268945040 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3495325455 |
|
|
Oct 09 11:50:29 PM UTC 24 |
Oct 09 11:50:39 PM UTC 24 |
44340556 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3703927094 |
|
|
Oct 09 11:46:33 PM UTC 24 |
Oct 09 11:50:45 PM UTC 24 |
635597452 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1719705752 |
|
|
Oct 09 11:39:58 PM UTC 24 |
Oct 09 11:50:56 PM UTC 24 |
8680180476 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.2034084958 |
|
|
Oct 09 11:47:51 PM UTC 24 |
Oct 09 11:50:59 PM UTC 24 |
21354203377 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.1840999629 |
|
|
Oct 09 11:46:39 PM UTC 24 |
Oct 09 11:50:59 PM UTC 24 |
3107655232 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.1760089457 |
|
|
Oct 09 11:49:10 PM UTC 24 |
Oct 09 11:51:01 PM UTC 24 |
2413023543 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.2954962668 |
|
|
Oct 09 11:49:45 PM UTC 24 |
Oct 09 11:51:05 PM UTC 24 |
1874139312 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.709942913 |
|
|
Oct 09 11:51:03 PM UTC 24 |
Oct 09 11:51:10 PM UTC 24 |
40253622 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.527633577 |
|
|
Oct 09 11:51:20 PM UTC 24 |
Oct 09 11:51:38 PM UTC 24 |
279027927 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.3953469505 |
|
|
Oct 09 11:51:20 PM UTC 24 |
Oct 09 11:51:40 PM UTC 24 |
127975158 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2091518414 |
|
|
Oct 09 11:49:26 PM UTC 24 |
Oct 09 11:51:45 PM UTC 24 |
1627046786 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.438875153 |
|
|
Oct 09 11:33:55 PM UTC 24 |
Oct 09 11:52:09 PM UTC 24 |
11414007575 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.4148368056 |
|
|
Oct 09 11:45:01 PM UTC 24 |
Oct 09 11:52:10 PM UTC 24 |
4604140148 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.1257797248 |
|
|
Oct 09 11:51:08 PM UTC 24 |
Oct 09 11:52:17 PM UTC 24 |
6925071170 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1652501933 |
|
|
Oct 09 11:44:51 PM UTC 24 |
Oct 09 11:52:19 PM UTC 24 |
6031370853 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.2145664846 |
|
|
Oct 09 11:47:21 PM UTC 24 |
Oct 09 11:52:22 PM UTC 24 |
4287465880 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1438559131 |
|
|
Oct 09 11:38:50 PM UTC 24 |
Oct 09 11:52:35 PM UTC 24 |
56704459671 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.3511651504 |
|
|
Oct 09 11:51:21 PM UTC 24 |
Oct 09 11:52:43 PM UTC 24 |
5021594698 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3304444441 |
|
|
Oct 09 11:46:57 PM UTC 24 |
Oct 09 11:52:45 PM UTC 24 |
7955501193 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.4137156747 |
|
|
Oct 09 11:52:33 PM UTC 24 |
Oct 09 11:52:51 PM UTC 24 |
357116104 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2203272954 |
|
|
Oct 09 11:51:16 PM UTC 24 |
Oct 09 11:52:53 PM UTC 24 |
4218118551 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2672153535 |
|
|
Oct 09 11:45:54 PM UTC 24 |
Oct 09 11:52:56 PM UTC 24 |
26011984084 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2936694151 |
|
|
Oct 09 11:52:08 PM UTC 24 |
Oct 09 11:53:04 PM UTC 24 |
1437387532 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3110230 |
|
|
Oct 09 11:53:12 PM UTC 24 |
Oct 09 11:53:24 PM UTC 24 |
55582753 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.2278584597 |
|
|
Oct 09 11:53:09 PM UTC 24 |
Oct 09 11:53:24 PM UTC 24 |
221652603 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.318883729 |
|
|
Oct 09 11:51:33 PM UTC 24 |
Oct 09 11:53:30 PM UTC 24 |
1951069842 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.2039667912 |
|
|
Oct 09 11:52:03 PM UTC 24 |
Oct 09 11:53:30 PM UTC 24 |
2655487932 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.539396094 |
|
|
Oct 09 11:52:58 PM UTC 24 |
Oct 09 11:53:38 PM UTC 24 |
64477658 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.3408010277 |
|
|
Oct 09 11:53:27 PM UTC 24 |
Oct 09 11:53:42 PM UTC 24 |
316751029 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.284762315 |
|
|
Oct 09 11:14:40 PM UTC 24 |
Oct 09 11:53:49 PM UTC 24 |
152189108328 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.2384733266 |
|
|
Oct 09 11:52:32 PM UTC 24 |
Oct 09 11:53:53 PM UTC 24 |
1200406505 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2950014219 |
|
|
Oct 09 11:52:43 PM UTC 24 |
Oct 09 11:54:00 PM UTC 24 |
1685681628 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.2878021576 |
|
|
Oct 09 11:53:17 PM UTC 24 |
Oct 09 11:54:12 PM UTC 24 |
5591652567 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4242026046 |
|
|
Oct 09 11:53:45 PM UTC 24 |
Oct 09 11:54:23 PM UTC 24 |
367018052 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.2457761414 |
|
|
Oct 09 11:54:04 PM UTC 24 |
Oct 09 11:54:33 PM UTC 24 |
890943568 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.572182700 |
|
|
Oct 09 11:53:17 PM UTC 24 |
Oct 09 11:55:01 PM UTC 24 |
5589867977 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.4145594360 |
|
|
Oct 09 11:53:52 PM UTC 24 |
Oct 09 11:55:03 PM UTC 24 |
459258924 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.1117443194 |
|
|
Oct 09 11:52:38 PM UTC 24 |
Oct 09 11:55:07 PM UTC 24 |
1441288416 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2725981799 |
|
|
Oct 09 11:54:24 PM UTC 24 |
Oct 09 11:55:18 PM UTC 24 |
1262077038 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.2318473505 |
|
|
Oct 09 11:45:49 PM UTC 24 |
Oct 09 11:55:21 PM UTC 24 |
35947903736 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.4025241509 |
|
|
Oct 09 11:54:15 PM UTC 24 |
Oct 09 11:55:34 PM UTC 24 |
1348499448 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2924301349 |
|
|
Oct 09 11:55:29 PM UTC 24 |
Oct 09 11:55:40 PM UTC 24 |
56450429 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3815634064 |
|
|
Oct 09 11:54:12 PM UTC 24 |
Oct 09 11:55:43 PM UTC 24 |
2156786547 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.901925414 |
|
|
Oct 09 11:47:08 PM UTC 24 |
Oct 09 11:55:46 PM UTC 24 |
5572419809 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2999075190 |
|
|
Oct 09 11:55:41 PM UTC 24 |
Oct 09 11:55:52 PM UTC 24 |
40006125 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.1351405684 |
|
|
Oct 09 11:44:57 PM UTC 24 |
Oct 09 11:56:09 PM UTC 24 |
6204499400 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.689506546 |
|
|
Oct 09 11:56:02 PM UTC 24 |
Oct 09 11:56:12 PM UTC 24 |
30337916 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2831739933 |
|
|
Oct 09 11:43:05 PM UTC 24 |
Oct 09 11:56:13 PM UTC 24 |
67946377564 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1862903915 |
|
|
Oct 09 11:49:28 PM UTC 24 |
Oct 09 11:56:21 PM UTC 24 |
8533358035 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2706989335 |
|
|
Oct 09 11:44:59 PM UTC 24 |
Oct 09 11:56:28 PM UTC 24 |
10751956305 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1928046866 |
|
|
Oct 09 11:53:06 PM UTC 24 |
Oct 09 11:56:36 PM UTC 24 |
2542260450 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2067947670 |
|
|
Oct 09 11:43:32 PM UTC 24 |
Oct 09 11:56:53 PM UTC 24 |
49794053072 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.2741697085 |
|
|
Oct 09 11:56:06 PM UTC 24 |
Oct 09 11:57:00 PM UTC 24 |
585245398 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3823139331 |
|
|
Oct 09 11:55:25 PM UTC 24 |
Oct 09 11:57:00 PM UTC 24 |
356222542 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3856758073 |
|
|
Oct 09 11:54:56 PM UTC 24 |
Oct 09 11:57:08 PM UTC 24 |
1380758336 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.412345408 |
|
|
Oct 09 11:55:57 PM UTC 24 |
Oct 09 11:57:16 PM UTC 24 |
5832777766 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.2015123512 |
|
|
Oct 09 11:56:36 PM UTC 24 |
Oct 09 11:57:17 PM UTC 24 |
959636422 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.1717865867 |
|
|
Oct 09 11:56:45 PM UTC 24 |
Oct 09 11:57:17 PM UTC 24 |
219671427 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1670109654 |
|
|
Oct 09 11:52:46 PM UTC 24 |
Oct 09 11:57:24 PM UTC 24 |
5728951887 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.786641755 |
|
|
Oct 09 11:56:52 PM UTC 24 |
Oct 09 11:57:26 PM UTC 24 |
551192770 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.1590556431 |
|
|
Oct 09 11:55:43 PM UTC 24 |
Oct 09 11:57:28 PM UTC 24 |
8075965902 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3582833750 |
|
|
Oct 09 11:57:00 PM UTC 24 |
Oct 09 11:57:39 PM UTC 24 |
826387107 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.4008219013 |
|
|
Oct 09 11:56:33 PM UTC 24 |
Oct 09 11:57:48 PM UTC 24 |
1825899219 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.3515905531 |
|
|
Oct 09 11:57:41 PM UTC 24 |
Oct 09 11:57:49 PM UTC 24 |
43182125 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3710245382 |
|
|
Oct 09 11:57:40 PM UTC 24 |
Oct 09 11:57:49 PM UTC 24 |
50360914 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.3874146503 |
|
|
Oct 09 11:55:24 PM UTC 24 |
Oct 09 11:57:57 PM UTC 24 |
2537991240 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.956511022 |
|
|
Oct 09 11:47:17 PM UTC 24 |
Oct 09 11:58:06 PM UTC 24 |
5999049984 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.1035650478 |
|
|
Oct 09 11:38:47 PM UTC 24 |
Oct 09 11:58:09 PM UTC 24 |
115669448133 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3919277137 |
|
|
Oct 09 11:50:12 PM UTC 24 |
Oct 09 11:58:29 PM UTC 24 |
6183189784 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.3337849057 |
|
|
Oct 09 11:58:10 PM UTC 24 |
Oct 09 11:58:32 PM UTC 24 |
252951149 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1324375335 |
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|
Oct 09 11:57:50 PM UTC 24 |
Oct 09 11:58:43 PM UTC 24 |
2650879150 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.530599352 |
|
|
Oct 09 11:57:23 PM UTC 24 |
Oct 09 11:58:46 PM UTC 24 |
985700050 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.1650437003 |
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|
Oct 09 11:58:03 PM UTC 24 |
Oct 09 11:58:51 PM UTC 24 |
348768651 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.3336119044 |
|
|
Oct 09 11:57:50 PM UTC 24 |
Oct 09 11:58:52 PM UTC 24 |
504813398 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.1529000038 |
|
|
Oct 09 11:58:34 PM UTC 24 |
Oct 09 11:59:08 PM UTC 24 |
331531742 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.2891764433 |
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|
Oct 09 11:57:47 PM UTC 24 |
Oct 09 11:59:16 PM UTC 24 |
10670132296 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.241209036 |
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|
Oct 09 11:53:53 PM UTC 24 |
Oct 09 11:59:16 PM UTC 24 |
17256509156 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3713458590 |
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|
Oct 09 11:58:56 PM UTC 24 |
Oct 09 11:59:22 PM UTC 24 |
125082800 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.1325189762 |
|
|
Oct 09 11:28:11 PM UTC 24 |
Oct 09 11:59:30 PM UTC 24 |
15065882232 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2341715773 |
|
|
Oct 09 11:22:49 PM UTC 24 |
Oct 09 11:59:43 PM UTC 24 |
15769762829 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.3547176424 |
|
|
Oct 09 11:03:08 PM UTC 24 |
Oct 09 11:59:43 PM UTC 24 |
30222055072 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1128640199 |
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|
Oct 09 11:59:38 PM UTC 24 |
Oct 09 11:59:47 PM UTC 24 |
52015987 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.560562863 |
|
|
Oct 09 11:58:29 PM UTC 24 |
Oct 09 11:59:49 PM UTC 24 |
1871157939 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.183070746 |
|
|
Oct 09 11:59:39 PM UTC 24 |
Oct 09 11:59:50 PM UTC 24 |
50765681 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2366578669 |
|
|
Oct 09 11:58:53 PM UTC 24 |
Oct 09 11:59:54 PM UTC 24 |
334633671 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2161376735 |
|
|
Oct 09 11:31:06 PM UTC 24 |
Oct 09 11:59:55 PM UTC 24 |
15272054671 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1855429388 |
|
|
Oct 09 11:57:24 PM UTC 24 |
Oct 09 11:59:55 PM UTC 24 |
2088735254 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3122802546 |
|
|
Oct 09 11:21:45 PM UTC 24 |
Oct 09 11:59:59 PM UTC 24 |
129715991245 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2311844298 |
|
|
Oct 09 11:26:37 PM UTC 24 |
Oct 10 12:00:04 AM UTC 24 |
119573791525 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.38188062 |
|
|
Oct 09 11:58:20 PM UTC 24 |
Oct 10 12:00:11 AM UTC 24 |
6183911560 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.2950393150 |
|
|
Oct 09 11:50:17 PM UTC 24 |
Oct 10 12:00:36 AM UTC 24 |
5658713899 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2157884862 |
|
|
Oct 10 12:00:19 AM UTC 24 |
Oct 10 12:00:43 AM UTC 24 |
514711615 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2406167718 |
|
|
Oct 09 11:21:03 PM UTC 24 |
Oct 10 12:00:47 AM UTC 24 |
15302566050 ps |