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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.50 94.21 95.38 95.05 97.40 99.53


Total test records in report: 2927
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T2265 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.3338359581 Oct 10 12:56:21 AM UTC 24 Oct 10 12:58:32 AM UTC 24 10925535725 ps
T2266 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.227047506 Oct 10 12:56:36 AM UTC 24 Oct 10 12:58:34 AM UTC 24 5636114751 ps
T2267 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.2722333386 Oct 09 11:42:07 PM UTC 24 Oct 10 12:58:48 AM UTC 24 31046982384 ps
T2268 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.3586392040 Oct 10 12:54:58 AM UTC 24 Oct 10 12:58:49 AM UTC 24 5712192730 ps
T2269 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3554686469 Oct 10 12:56:03 AM UTC 24 Oct 10 12:58:49 AM UTC 24 447373164 ps
T2270 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1736976637 Oct 10 12:58:40 AM UTC 24 Oct 10 12:58:51 AM UTC 24 47249405 ps
T2271 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3756134957 Oct 10 12:58:18 AM UTC 24 Oct 10 12:58:52 AM UTC 24 956504652 ps
T2272 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.4006917676 Oct 10 12:58:38 AM UTC 24 Oct 10 12:58:54 AM UTC 24 241947050 ps
T2273 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2169089244 Oct 10 12:42:55 AM UTC 24 Oct 10 12:58:55 AM UTC 24 8490374616 ps
T2274 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2035257809 Oct 10 12:57:33 AM UTC 24 Oct 10 12:58:57 AM UTC 24 5488301852 ps
T2275 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2304152611 Oct 10 12:58:01 AM UTC 24 Oct 10 12:58:57 AM UTC 24 721783009 ps
T2276 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3834964930 Oct 10 12:34:32 AM UTC 24 Oct 10 12:58:58 AM UTC 24 95520032666 ps
T2277 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.3862331959 Oct 10 12:58:47 AM UTC 24 Oct 10 12:59:08 AM UTC 24 300441929 ps
T2278 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.3221784712 Oct 10 12:44:45 AM UTC 24 Oct 10 12:59:09 AM UTC 24 55890494350 ps
T2279 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.212739381 Oct 10 12:57:33 AM UTC 24 Oct 10 12:59:12 AM UTC 24 10147162147 ps
T2280 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.4100386752 Oct 10 12:58:06 AM UTC 24 Oct 10 12:59:26 AM UTC 24 1993476976 ps
T2281 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.2668398323 Oct 10 12:58:50 AM UTC 24 Oct 10 12:59:27 AM UTC 24 404767969 ps
T2282 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1794959362 Oct 10 12:59:21 AM UTC 24 Oct 10 12:59:29 AM UTC 24 45964594 ps
T2283 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1262692633 Oct 10 12:59:15 AM UTC 24 Oct 10 12:59:30 AM UTC 24 220888078 ps
T2284 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1503230180 Oct 10 12:58:59 AM UTC 24 Oct 10 12:59:41 AM UTC 24 387193853 ps
T2285 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2794925255 Oct 10 12:59:32 AM UTC 24 Oct 10 12:59:44 AM UTC 24 53741193 ps
T2286 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1214835649 Oct 10 12:59:13 AM UTC 24 Oct 10 12:59:49 AM UTC 24 797109002 ps
T2287 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.2564181127 Oct 10 12:58:23 AM UTC 24 Oct 10 12:59:57 AM UTC 24 1158124253 ps
T2288 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.85808292 Oct 10 12:55:36 AM UTC 24 Oct 10 12:59:59 AM UTC 24 20125037201 ps
T2289 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.2526194013 Oct 10 12:59:11 AM UTC 24 Oct 10 01:00:04 AM UTC 24 1065843892 ps
T2290 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.2089902578 Oct 10 12:58:45 AM UTC 24 Oct 10 01:00:04 AM UTC 24 5937332618 ps
T2291 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.1400545392 Oct 10 12:59:50 AM UTC 24 Oct 10 01:00:07 AM UTC 24 101321640 ps
T2292 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.4018033035 Oct 10 12:59:50 AM UTC 24 Oct 10 01:00:24 AM UTC 24 410615903 ps
T2293 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2997150638 Oct 10 12:59:10 AM UTC 24 Oct 10 01:00:34 AM UTC 24 2829142978 ps
T2294 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3060031390 Oct 10 12:59:36 AM UTC 24 Oct 10 01:00:40 AM UTC 24 3578875972 ps
T2295 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3297408787 Oct 10 12:58:45 AM UTC 24 Oct 10 01:00:46 AM UTC 24 5285460986 ps
T2296 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.632688911 Oct 10 12:59:32 AM UTC 24 Oct 10 01:00:52 AM UTC 24 4913138365 ps
T2297 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3814703544 Oct 10 12:50:38 AM UTC 24 Oct 10 01:01:02 AM UTC 24 9873424623 ps
T2298 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.3332629613 Oct 10 12:51:21 AM UTC 24 Oct 10 01:01:05 AM UTC 24 32502378051 ps
T2299 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.424311012 Oct 10 01:00:33 AM UTC 24 Oct 10 01:01:06 AM UTC 24 520302051 ps
T2300 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.3254296966 Oct 10 01:01:02 AM UTC 24 Oct 10 01:01:09 AM UTC 24 46929153 ps
T2301 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.1941156315 Oct 10 12:52:40 AM UTC 24 Oct 10 01:01:14 AM UTC 24 41898417593 ps
T2302 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2389017551 Oct 10 01:01:10 AM UTC 24 Oct 10 01:01:16 AM UTC 24 45713395 ps
T2303 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.1193747225 Oct 10 12:59:17 AM UTC 24 Oct 10 01:01:17 AM UTC 24 1266365983 ps
T2304 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.3813741251 Oct 10 01:00:24 AM UTC 24 Oct 10 01:01:26 AM UTC 24 1089630057 ps
T2305 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.3576672656 Oct 10 12:55:35 AM UTC 24 Oct 10 01:01:29 AM UTC 24 19562690187 ps
T2306 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.1686114256 Oct 10 01:00:22 AM UTC 24 Oct 10 01:01:37 AM UTC 24 1556733498 ps
T2307 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.1034413309 Oct 10 12:58:57 AM UTC 24 Oct 10 01:01:44 AM UTC 24 11841385745 ps
T2308 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.2230818262 Oct 10 12:48:33 AM UTC 24 Oct 10 01:01:45 AM UTC 24 52008157393 ps
T2309 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.741219079 Oct 10 01:01:28 AM UTC 24 Oct 10 01:01:46 AM UTC 24 121519477 ps
T2310 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.4142283768 Oct 10 01:00:12 AM UTC 24 Oct 10 01:01:50 AM UTC 24 2316251510 ps
T2311 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.3485287090 Oct 10 01:00:05 AM UTC 24 Oct 10 01:01:50 AM UTC 24 750726143 ps
T2312 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1325897888 Oct 10 12:57:02 AM UTC 24 Oct 10 01:01:58 AM UTC 24 1323004307 ps
T2313 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.3466062996 Oct 10 12:53:57 AM UTC 24 Oct 10 01:01:59 AM UTC 24 24541248004 ps
T2314 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1616373192 Oct 10 12:48:36 AM UTC 24 Oct 10 01:02:01 AM UTC 24 54202600048 ps
T2315 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.124575912 Oct 10 12:46:15 AM UTC 24 Oct 10 01:02:04 AM UTC 24 61816519379 ps
T2316 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.1078561395 Oct 09 11:44:59 PM UTC 24 Oct 10 01:02:18 AM UTC 24 28081506125 ps
T2317 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.678730011 Oct 10 01:02:04 AM UTC 24 Oct 10 01:02:19 AM UTC 24 78257348 ps
T2318 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.3456221810 Oct 10 12:51:44 AM UTC 24 Oct 10 01:02:22 AM UTC 24 16346804856 ps
T2319 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.240823716 Oct 10 01:04:52 AM UTC 24 Oct 10 01:05:04 AM UTC 24 136597233 ps
T2320 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.1887500211 Oct 10 01:01:16 AM UTC 24 Oct 10 01:02:24 AM UTC 24 6828424063 ps
T2321 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2804078488 Oct 10 12:56:09 AM UTC 24 Oct 10 01:02:32 AM UTC 24 4295217621 ps
T2322 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.4034128359 Oct 10 01:02:24 AM UTC 24 Oct 10 01:02:33 AM UTC 24 38044876 ps
T2323 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.2088192995 Oct 10 01:02:19 AM UTC 24 Oct 10 01:02:34 AM UTC 24 217300924 ps
T2324 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.946372805 Oct 10 01:01:51 AM UTC 24 Oct 10 01:02:36 AM UTC 24 433920350 ps
T2325 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.2649346701 Oct 10 01:01:29 AM UTC 24 Oct 10 01:02:37 AM UTC 24 1661454779 ps
T2326 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.230668561 Oct 10 01:01:56 AM UTC 24 Oct 10 01:02:38 AM UTC 24 250084740 ps
T2327 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2601587375 Oct 10 12:46:17 AM UTC 24 Oct 10 01:02:42 AM UTC 24 65463393196 ps
T2328 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.135218085 Oct 10 01:01:53 AM UTC 24 Oct 10 01:02:56 AM UTC 24 1691811246 ps
T2329 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.2091559143 Oct 10 12:58:14 AM UTC 24 Oct 10 01:03:02 AM UTC 24 7688340978 ps
T2330 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3155335531 Oct 10 01:01:24 AM UTC 24 Oct 10 01:03:09 AM UTC 24 5092638054 ps
T2331 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.599954553 Oct 10 12:30:22 AM UTC 24 Oct 10 01:03:10 AM UTC 24 123653588164 ps
T2332 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3388983577 Oct 10 12:57:53 AM UTC 24 Oct 10 01:03:15 AM UTC 24 23789605290 ps
T2333 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.794724744 Oct 10 12:57:17 AM UTC 24 Oct 10 01:03:23 AM UTC 24 9289772628 ps
T2334 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.1397007963 Oct 10 01:03:01 AM UTC 24 Oct 10 01:03:23 AM UTC 24 122556691 ps
T2335 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.4035981377 Oct 10 01:03:02 AM UTC 24 Oct 10 01:03:23 AM UTC 24 450547740 ps
T2336 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1930446885 Oct 10 12:46:10 AM UTC 24 Oct 10 01:03:29 AM UTC 24 93001562137 ps
T2337 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.13641376 Oct 10 01:02:58 AM UTC 24 Oct 10 01:03:29 AM UTC 24 309839373 ps
T2338 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2348324503 Oct 10 01:02:43 AM UTC 24 Oct 10 01:03:31 AM UTC 24 355016557 ps
T2339 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.2549147800 Oct 10 01:02:56 AM UTC 24 Oct 10 01:03:40 AM UTC 24 770394071 ps
T2340 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.3399704858 Oct 10 01:03:33 AM UTC 24 Oct 10 01:03:43 AM UTC 24 38457403 ps
T2341 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.1651583048 Oct 10 01:02:44 AM UTC 24 Oct 10 01:03:44 AM UTC 24 516330411 ps
T2342 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.4025920375 Oct 10 01:01:39 AM UTC 24 Oct 10 01:03:46 AM UTC 24 2885023523 ps
T2343 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1234133409 Oct 10 01:03:40 AM UTC 24 Oct 10 01:03:49 AM UTC 24 44346786 ps
T2344 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.564592244 Oct 10 12:58:03 AM UTC 24 Oct 10 01:03:50 AM UTC 24 22750859810 ps
T2345 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.774076630 Oct 10 01:02:25 AM UTC 24 Oct 10 01:04:08 AM UTC 24 6469237473 ps
T501 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.249746066 Oct 10 12:47:32 AM UTC 24 Oct 10 01:04:12 AM UTC 24 60669070614 ps
T2346 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3638754833 Oct 10 01:03:54 AM UTC 24 Oct 10 01:04:19 AM UTC 24 155396691 ps
T2347 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1261719571 Oct 10 01:03:01 AM UTC 24 Oct 10 01:04:19 AM UTC 24 1952374516 ps
T2348 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3717580622 Oct 10 01:02:30 AM UTC 24 Oct 10 01:04:27 AM UTC 24 5487065036 ps
T2349 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3259821248 Oct 10 12:59:18 AM UTC 24 Oct 10 01:04:27 AM UTC 24 685657827 ps
T2350 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3494830235 Oct 10 01:04:08 AM UTC 24 Oct 10 01:04:29 AM UTC 24 588551874 ps
T2351 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1351667201 Oct 10 12:55:45 AM UTC 24 Oct 10 01:04:36 AM UTC 24 34564086619 ps
T2352 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.2539453016 Oct 10 01:03:48 AM UTC 24 Oct 10 01:04:48 AM UTC 24 1345137084 ps
T2353 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.503255426 Oct 10 01:04:11 AM UTC 24 Oct 10 01:04:50 AM UTC 24 426330602 ps
T2354 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1946611766 Oct 10 01:04:51 AM UTC 24 Oct 10 01:05:02 AM UTC 24 46439027 ps
T2355 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.4049999708 Oct 10 12:36:34 AM UTC 24 Oct 10 01:05:04 AM UTC 24 119351893357 ps
T2356 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2387179221 Oct 10 01:02:07 AM UTC 24 Oct 10 01:05:11 AM UTC 24 1271413074 ps
T2357 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3833383676 Oct 10 01:00:56 AM UTC 24 Oct 10 01:05:12 AM UTC 24 2330898911 ps
T2358 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.1516421560 Oct 10 01:03:46 AM UTC 24 Oct 10 01:05:15 AM UTC 24 7428070047 ps
T2359 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2473922820 Oct 10 01:04:16 AM UTC 24 Oct 10 01:05:16 AM UTC 24 1338322707 ps
T2360 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.3326981803 Oct 10 01:04:13 AM UTC 24 Oct 10 01:05:19 AM UTC 24 1274316801 ps
T2361 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.4022746396 Oct 10 01:05:15 AM UTC 24 Oct 10 01:05:24 AM UTC 24 32835112 ps
T2362 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.4124375418 Oct 10 01:04:06 AM UTC 24 Oct 10 01:05:34 AM UTC 24 1489092927 ps
T2363 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4212773980 Oct 10 01:03:48 AM UTC 24 Oct 10 01:05:49 AM UTC 24 5984883997 ps
T2364 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.2062795895 Oct 10 01:00:33 AM UTC 24 Oct 10 01:05:59 AM UTC 24 3447023030 ps
T2365 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.781002730 Oct 10 12:58:23 AM UTC 24 Oct 10 01:06:03 AM UTC 24 3148324788 ps
T2366 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2570806679 Oct 10 01:04:37 AM UTC 24 Oct 10 01:06:10 AM UTC 24 375826677 ps
T2367 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2800715261 Oct 10 01:04:42 AM UTC 24 Oct 10 01:06:12 AM UTC 24 128941953 ps
T2368 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.2911051416 Oct 10 01:05:12 AM UTC 24 Oct 10 01:06:12 AM UTC 24 1754738533 ps
T2369 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.3722227295 Oct 10 12:54:00 AM UTC 24 Oct 10 01:06:21 AM UTC 24 72037984001 ps
T2370 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.601297328 Oct 10 01:05:38 AM UTC 24 Oct 10 01:06:23 AM UTC 24 1377506529 ps
T2371 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.490710025 Oct 10 01:04:55 AM UTC 24 Oct 10 01:06:23 AM UTC 24 6656599849 ps
T2372 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.1665106386 Oct 10 12:55:56 AM UTC 24 Oct 10 01:06:24 AM UTC 24 15730423368 ps
T2373 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.396170098 Oct 10 12:49:45 AM UTC 24 Oct 10 01:06:36 AM UTC 24 82971839347 ps
T2374 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.2334212251 Oct 10 01:06:26 AM UTC 24 Oct 10 01:06:40 AM UTC 24 207359036 ps
T2375 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3329880061 Oct 10 01:00:33 AM UTC 24 Oct 10 01:06:42 AM UTC 24 2114468653 ps
T2376 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1394284379 Oct 10 01:06:34 AM UTC 24 Oct 10 01:06:43 AM UTC 24 52209627 ps
T2377 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.4189383737 Oct 10 12:59:21 AM UTC 24 Oct 10 01:06:45 AM UTC 24 13252664048 ps
T2378 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.3800237199 Oct 10 01:00:47 AM UTC 24 Oct 10 01:06:46 AM UTC 24 9709318958 ps
T2379 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3992360781 Oct 10 01:05:44 AM UTC 24 Oct 10 01:06:54 AM UTC 24 1338174522 ps
T2380 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1999542910 Oct 10 01:05:02 AM UTC 24 Oct 10 01:06:56 AM UTC 24 5206079382 ps
T2381 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3046864504 Oct 10 12:48:23 AM UTC 24 Oct 10 01:06:58 AM UTC 24 99656578041 ps
T2382 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.2015133159 Oct 10 01:06:45 AM UTC 24 Oct 10 01:06:59 AM UTC 24 281061582 ps
T2383 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.3202704611 Oct 10 01:05:37 AM UTC 24 Oct 10 01:07:01 AM UTC 24 1312871737 ps
T2384 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2376936959 Oct 10 01:05:28 AM UTC 24 Oct 10 01:07:02 AM UTC 24 1971977066 ps
T2385 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1191485894 Oct 10 12:58:20 AM UTC 24 Oct 10 01:07:03 AM UTC 24 8529952565 ps
T2386 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.1308410691 Oct 10 12:52:43 AM UTC 24 Oct 10 01:07:07 AM UTC 24 54994395562 ps
T2387 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.1523318921 Oct 10 01:05:36 AM UTC 24 Oct 10 01:07:13 AM UTC 24 2232111030 ps
T2388 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.976544689 Oct 10 01:07:05 AM UTC 24 Oct 10 01:07:23 AM UTC 24 172879778 ps
T2389 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.2900216011 Oct 10 01:03:27 AM UTC 24 Oct 10 01:07:29 AM UTC 24 6201928918 ps
T2390 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.2448200759 Oct 10 01:06:45 AM UTC 24 Oct 10 01:07:29 AM UTC 24 507226493 ps
T2391 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3375171091 Oct 10 01:07:25 AM UTC 24 Oct 10 01:07:36 AM UTC 24 50572782 ps
T2392 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.2785987330 Oct 10 01:07:26 AM UTC 24 Oct 10 01:07:37 AM UTC 24 53000912 ps
T2393 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.899788814 Oct 10 01:07:08 AM UTC 24 Oct 10 01:07:45 AM UTC 24 830946618 ps
T2394 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3115739020 Oct 10 01:07:10 AM UTC 24 Oct 10 01:08:00 AM UTC 24 1217864206 ps
T2395 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.3753626688 Oct 10 01:06:34 AM UTC 24 Oct 10 01:08:02 AM UTC 24 8536837931 ps
T2396 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3608847880 Oct 10 01:06:34 AM UTC 24 Oct 10 01:08:03 AM UTC 24 5522006260 ps
T2397 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.3427953233 Oct 10 01:07:07 AM UTC 24 Oct 10 01:08:06 AM UTC 24 1461753537 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.169077412 Oct 10 01:05:58 AM UTC 24 Oct 10 01:08:19 AM UTC 24 220741445 ps
T2398 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.3293365837 Oct 10 01:07:48 AM UTC 24 Oct 10 01:08:20 AM UTC 24 225163557 ps
T2399 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1532965295 Oct 10 01:02:07 AM UTC 24 Oct 10 01:08:21 AM UTC 24 3521509932 ps
T2400 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.3893371601 Oct 10 01:03:07 AM UTC 24 Oct 10 01:08:37 AM UTC 24 9026371348 ps
T2401 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3127869328 Oct 10 01:03:54 AM UTC 24 Oct 10 01:08:39 AM UTC 24 20571906231 ps
T2402 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.161419215 Oct 10 01:03:21 AM UTC 24 Oct 10 01:08:50 AM UTC 24 457079765 ps
T2403 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.3244815008 Oct 10 01:08:27 AM UTC 24 Oct 10 01:08:50 AM UTC 24 113900351 ps
T2404 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.3774167420 Oct 10 01:07:38 AM UTC 24 Oct 10 01:08:55 AM UTC 24 1628688257 ps
T2405 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3978419671 Oct 10 01:02:13 AM UTC 24 Oct 10 01:08:56 AM UTC 24 11130708707 ps
T2406 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3670306345 Oct 10 01:03:32 AM UTC 24 Oct 10 01:09:00 AM UTC 24 5250960473 ps
T2407 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.79421159 Oct 10 01:08:27 AM UTC 24 Oct 10 01:09:00 AM UTC 24 220082210 ps
T2408 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1503888289 Oct 10 01:07:28 AM UTC 24 Oct 10 01:09:04 AM UTC 24 7263139204 ps
T2409 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.3901339338 Oct 10 01:04:33 AM UTC 24 Oct 10 01:09:04 AM UTC 24 2713852298 ps
T2410 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.1066407272 Oct 10 01:07:23 AM UTC 24 Oct 10 01:09:07 AM UTC 24 1467385974 ps
T2411 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.4218663141 Oct 10 01:07:31 AM UTC 24 Oct 10 01:09:11 AM UTC 24 6407968132 ps
T2412 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3112477791 Oct 10 01:09:04 AM UTC 24 Oct 10 01:09:11 AM UTC 24 42487159 ps
T2413 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.794046033 Oct 10 01:08:24 AM UTC 24 Oct 10 01:09:12 AM UTC 24 463381065 ps
T2414 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1857004688 Oct 10 01:09:02 AM UTC 24 Oct 10 01:09:14 AM UTC 24 173431075 ps
T2415 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3762225156 Oct 10 12:56:40 AM UTC 24 Oct 10 01:09:15 AM UTC 24 83544302353 ps
T2416 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.3269913591 Oct 10 01:06:58 AM UTC 24 Oct 10 01:09:30 AM UTC 24 3139628980 ps
T2417 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3429261936 Oct 10 01:02:55 AM UTC 24 Oct 10 01:09:39 AM UTC 24 22111237487 ps
T2418 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.1543678605 Oct 10 01:09:31 AM UTC 24 Oct 10 01:09:39 AM UTC 24 39890817 ps
T2419 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.827491700 Oct 10 01:08:09 AM UTC 24 Oct 10 01:09:44 AM UTC 24 2643106673 ps
T2420 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4094268170 Oct 10 01:07:22 AM UTC 24 Oct 10 01:09:46 AM UTC 24 346207077 ps
T2421 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3803388429 Oct 10 01:09:32 AM UTC 24 Oct 10 01:09:49 AM UTC 24 245792047 ps
T2422 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.4225843644 Oct 10 01:09:35 AM UTC 24 Oct 10 01:09:55 AM UTC 24 104206579 ps
T2423 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1322811445 Oct 10 01:08:00 AM UTC 24 Oct 10 01:10:00 AM UTC 24 2654994720 ps
T2424 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2041211495 Oct 10 12:58:52 AM UTC 24 Oct 10 01:10:06 AM UTC 24 73243323330 ps
T2425 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2269684257 Oct 10 01:09:30 AM UTC 24 Oct 10 01:10:07 AM UTC 24 962764744 ps
T2426 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.37159153 Oct 10 01:10:03 AM UTC 24 Oct 10 01:10:13 AM UTC 24 41177021 ps
T2427 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.46809646 Oct 10 01:09:22 AM UTC 24 Oct 10 01:10:13 AM UTC 24 550315263 ps
T2428 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.260526769 Oct 10 01:09:28 AM UTC 24 Oct 10 01:10:16 AM UTC 24 625924135 ps
T2429 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2938598473 Oct 10 01:10:08 AM UTC 24 Oct 10 01:10:17 AM UTC 24 52765939 ps
T2430 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3098805554 Oct 10 01:09:19 AM UTC 24 Oct 10 01:10:33 AM UTC 24 2144008540 ps
T2431 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.780665532 Oct 10 01:10:19 AM UTC 24 Oct 10 01:10:36 AM UTC 24 143722551 ps
T2432 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3250634110 Oct 10 01:09:14 AM UTC 24 Oct 10 01:10:43 AM UTC 24 5258551252 ps
T2433 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3820252829 Oct 10 01:10:41 AM UTC 24 Oct 10 01:10:48 AM UTC 24 36580400 ps
T2434 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.1054223682 Oct 10 01:02:46 AM UTC 24 Oct 10 01:10:49 AM UTC 24 45418939407 ps
T2435 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2439209359 Oct 10 01:09:25 AM UTC 24 Oct 10 01:10:50 AM UTC 24 8183198686 ps
T2436 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.2555572030 Oct 10 01:09:14 AM UTC 24 Oct 10 01:10:50 AM UTC 24 10289812083 ps
T2437 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.1358411896 Oct 10 01:10:42 AM UTC 24 Oct 10 01:10:53 AM UTC 24 128468121 ps
T2438 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1220996280 Oct 10 01:05:47 AM UTC 24 Oct 10 01:10:54 AM UTC 24 8469699594 ps
T2439 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.1858350120 Oct 10 12:57:52 AM UTC 24 Oct 10 01:10:55 AM UTC 24 80285791735 ps
T2440 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3243799012 Oct 10 01:10:03 AM UTC 24 Oct 10 01:10:57 AM UTC 24 63082815 ps
T2441 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.201295428 Oct 10 01:10:19 AM UTC 24 Oct 10 01:10:58 AM UTC 24 421668581 ps
T2442 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.3336004342 Oct 10 01:09:38 AM UTC 24 Oct 10 01:11:00 AM UTC 24 1381450890 ps
T2443 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.205643351 Oct 10 01:06:24 AM UTC 24 Oct 10 01:11:18 AM UTC 24 6634099296 ps
T2444 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.1782498233 Oct 10 12:51:23 AM UTC 24 Oct 10 01:11:21 AM UTC 24 105558554873 ps
T2445 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.4164489385 Oct 10 01:08:45 AM UTC 24 Oct 10 01:11:23 AM UTC 24 2016097568 ps
T2446 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.3049077180 Oct 10 01:11:13 AM UTC 24 Oct 10 01:11:23 AM UTC 24 213546304 ps
T2447 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.2009290559 Oct 10 01:10:09 AM UTC 24 Oct 10 01:11:24 AM UTC 24 7285659539 ps
T2448 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1450019452 Oct 10 01:11:16 AM UTC 24 Oct 10 01:11:26 AM UTC 24 41908679 ps
T2449 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1042373933 Oct 10 01:02:11 AM UTC 24 Oct 10 01:11:29 AM UTC 24 10403689098 ps
T2450 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.3203762810 Oct 10 01:11:18 AM UTC 24 Oct 10 01:11:31 AM UTC 24 128277225 ps
T2451 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.1197799186 Oct 10 01:08:31 AM UTC 24 Oct 10 01:11:31 AM UTC 24 1613493672 ps
T2452 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.600625638 Oct 10 01:11:01 AM UTC 24 Oct 10 01:11:34 AM UTC 24 688444289 ps
T2453 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.746624282 Oct 10 01:11:10 AM UTC 24 Oct 10 01:11:37 AM UTC 24 116610329 ps
T2454 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2445912375 Oct 10 01:10:57 AM UTC 24 Oct 10 01:11:45 AM UTC 24 1081276766 ps
T2455 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.1041680457 Oct 10 01:04:43 AM UTC 24 Oct 10 01:11:50 AM UTC 24 5419613515 ps
T2456 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2315587922 Oct 10 01:10:11 AM UTC 24 Oct 10 01:11:50 AM UTC 24 5741660316 ps
T2457 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3229029598 Oct 10 12:59:19 AM UTC 24 Oct 10 01:11:55 AM UTC 24 7420369512 ps
T2458 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.1812591571 Oct 10 01:01:34 AM UTC 24 Oct 10 01:11:58 AM UTC 24 42894318935 ps
T2459 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.2328325830 Oct 10 01:11:21 AM UTC 24 Oct 10 01:12:00 AM UTC 24 393189634 ps
T2460 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.2840831887 Oct 10 01:08:44 AM UTC 24 Oct 10 01:12:03 AM UTC 24 1163193445 ps
T2461 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1627573389 Oct 10 01:11:16 AM UTC 24 Oct 10 01:12:09 AM UTC 24 3259836710 ps
T2462 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2196965645 Oct 10 01:00:08 AM UTC 24 Oct 10 01:12:09 AM UTC 24 45811927446 ps
T2463 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2638564852 Oct 10 01:11:54 AM UTC 24 Oct 10 01:12:10 AM UTC 24 144315546 ps
T2464 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3954290294 Oct 10 12:59:52 AM UTC 24 Oct 10 01:12:15 AM UTC 24 64566891356 ps
T2465 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2004856568 Oct 10 01:12:05 AM UTC 24 Oct 10 01:12:16 AM UTC 24 38537438 ps
T2466 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.1328595478 Oct 10 01:06:13 AM UTC 24 Oct 10 01:12:20 AM UTC 24 4490616645 ps
T2467 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.381608468 Oct 10 01:12:12 AM UTC 24 Oct 10 01:12:23 AM UTC 24 46699372 ps
T2468 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.749144853 Oct 10 01:11:48 AM UTC 24 Oct 10 01:12:25 AM UTC 24 980920603 ps
T2469 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.975825947 Oct 10 01:11:14 AM UTC 24 Oct 10 01:12:31 AM UTC 24 7692185226 ps
T2470 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2813521011 Oct 10 01:11:47 AM UTC 24 Oct 10 01:12:32 AM UTC 24 1071578884 ps
T2471 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.3708072722 Oct 10 01:09:55 AM UTC 24 Oct 10 01:12:37 AM UTC 24 4458658976 ps
T2472 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2725124288 Oct 10 12:35:40 AM UTC 24 Oct 10 01:12:42 AM UTC 24 115973846414 ps
T2473 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.2330469362 Oct 10 01:10:37 AM UTC 24 Oct 10 01:12:45 AM UTC 24 2752977023 ps
T2474 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.4189172404 Oct 10 01:11:49 AM UTC 24 Oct 10 01:12:55 AM UTC 24 1390185553 ps
T2475 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.2515378914 Oct 10 01:11:44 AM UTC 24 Oct 10 01:13:04 AM UTC 24 1608271510 ps
T2476 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.773640297 Oct 10 01:12:45 AM UTC 24 Oct 10 01:13:07 AM UTC 24 276330530 ps
T2477 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3944925518 Oct 10 01:12:45 AM UTC 24 Oct 10 01:13:17 AM UTC 24 227767185 ps
T2478 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4162020536 Oct 10 01:13:09 AM UTC 24 Oct 10 01:13:18 AM UTC 24 42363302 ps
T2479 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1412885113 Oct 10 01:13:07 AM UTC 24 Oct 10 01:13:22 AM UTC 24 206706747 ps
T2480 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2418633322 Oct 10 01:12:18 AM UTC 24 Oct 10 01:13:30 AM UTC 24 3668866137 ps
T2481 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.133119641 Oct 10 01:12:25 AM UTC 24 Oct 10 01:13:32 AM UTC 24 532963824 ps
T2482 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.2788960332 Oct 10 01:12:32 AM UTC 24 Oct 10 01:13:33 AM UTC 24 730436706 ps
T2483 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.276083527 Oct 10 01:12:40 AM UTC 24 Oct 10 01:13:47 AM UTC 24 2081280098 ps
T2484 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.504973509 Oct 10 01:12:00 AM UTC 24 Oct 10 01:13:47 AM UTC 24 604512705 ps
T2485 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1706871342 Oct 10 01:11:11 AM UTC 24 Oct 10 01:13:48 AM UTC 24 3276500119 ps
T2486 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.1540619995 Oct 10 01:12:21 AM UTC 24 Oct 10 01:13:52 AM UTC 24 1935959454 ps
T2487 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.2640184007 Oct 10 01:13:31 AM UTC 24 Oct 10 01:14:00 AM UTC 24 619547636 ps
T2488 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.2503746983 Oct 10 01:12:37 AM UTC 24 Oct 10 01:14:05 AM UTC 24 1748766532 ps
T2489 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.3430763085 Oct 10 01:11:06 AM UTC 24 Oct 10 01:14:10 AM UTC 24 2151484203 ps
T2490 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.2742360003 Oct 10 01:13:55 AM UTC 24 Oct 10 01:14:13 AM UTC 24 107675571 ps
T2491 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3923128542 Oct 10 01:13:58 AM UTC 24 Oct 10 01:14:16 AM UTC 24 125399157 ps
T2492 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2423129125 Oct 10 01:14:09 AM UTC 24 Oct 10 01:14:27 AM UTC 24 285092279 ps
T2493 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.793805004 Oct 10 01:07:19 AM UTC 24 Oct 10 01:14:27 AM UTC 24 3932024528 ps
T2494 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.529101837 Oct 10 01:14:10 AM UTC 24 Oct 10 01:14:35 AM UTC 24 209647470 ps
T2495 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.3575978031 Oct 10 01:13:43 AM UTC 24 Oct 10 01:14:36 AM UTC 24 448017842 ps
T2496 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.705339803 Oct 10 01:12:10 AM UTC 24 Oct 10 01:14:36 AM UTC 24 8158750940 ps
T2497 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.694151099 Oct 10 01:14:11 AM UTC 24 Oct 10 01:14:37 AM UTC 24 535637980 ps
T2498 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3939683062 Oct 10 01:01:26 AM UTC 24 Oct 10 01:14:38 AM UTC 24 71507896874 ps
T2499 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.3333003334 Oct 10 01:14:38 AM UTC 24 Oct 10 01:14:51 AM UTC 24 173201338 ps
T2500 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.993398551 Oct 10 01:14:41 AM UTC 24 Oct 10 01:14:51 AM UTC 24 45438602 ps
T2501 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.162048417 Oct 10 01:12:45 AM UTC 24 Oct 10 01:14:52 AM UTC 24 3012079516 ps
T2502 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.3349238949 Oct 10 01:03:55 AM UTC 24 Oct 10 01:14:55 AM UTC 24 47122459731 ps
T2503 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.3412627411 Oct 10 01:11:56 AM UTC 24 Oct 10 01:14:55 AM UTC 24 2468589464 ps
T2504 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.683983187 Oct 10 01:13:21 AM UTC 24 Oct 10 01:15:01 AM UTC 24 8149162795 ps
T2505 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1257635154 Oct 10 01:05:26 AM UTC 24 Oct 10 01:15:09 AM UTC 24 58831614853 ps
T2506 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3892968211 Oct 10 12:47:35 AM UTC 24 Oct 10 01:15:09 AM UTC 24 101025216523 ps
T2507 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1161733708 Oct 10 01:13:24 AM UTC 24 Oct 10 01:15:21 AM UTC 24 6818304664 ps
T2508 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.522244235 Oct 10 01:14:29 AM UTC 24 Oct 10 01:15:22 AM UTC 24 739433520 ps
T2509 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.2277275323 Oct 10 01:11:09 AM UTC 24 Oct 10 01:15:28 AM UTC 24 7888082107 ps
T2510 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.4192890394 Oct 10 01:15:16 AM UTC 24 Oct 10 01:15:31 AM UTC 24 85926266 ps
T2511 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.2188866127 Oct 10 01:02:49 AM UTC 24 Oct 10 01:15:45 AM UTC 24 50959136749 ps
T2512 /workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.1691257858 Oct 10 01:14:58 AM UTC 24 Oct 10 01:15:49 AM UTC 24 555130092 ps
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