| T954 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.898280384 |
|
|
Oct 12 08:48:18 PM UTC 24 |
Oct 12 09:55:14 PM UTC 24 |
15126270292 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1868690721 |
|
|
Oct 12 08:51:50 PM UTC 24 |
Oct 12 09:56:37 PM UTC 24 |
14978384984 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2187516169 |
|
|
Oct 12 08:37:33 PM UTC 24 |
Oct 12 09:56:55 PM UTC 24 |
24422616114 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.3127112278 |
|
|
Oct 12 09:49:17 PM UTC 24 |
Oct 12 09:57:27 PM UTC 24 |
5059177160 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.517776812 |
|
|
Oct 12 08:43:23 PM UTC 24 |
Oct 12 09:58:10 PM UTC 24 |
16071346356 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.83386161 |
|
|
Oct 12 09:52:32 PM UTC 24 |
Oct 12 09:58:14 PM UTC 24 |
2842585072 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.590758998 |
|
|
Oct 12 08:49:07 PM UTC 24 |
Oct 12 09:59:02 PM UTC 24 |
14944892031 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1323279732 |
|
|
Oct 12 09:49:54 PM UTC 24 |
Oct 12 09:59:08 PM UTC 24 |
4110785240 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.3730322212 |
|
|
Oct 12 09:53:15 PM UTC 24 |
Oct 12 09:59:24 PM UTC 24 |
3164310392 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4124743618 |
|
|
Oct 12 08:43:34 PM UTC 24 |
Oct 12 09:59:46 PM UTC 24 |
16369342232 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.996740103 |
|
|
Oct 12 09:42:48 PM UTC 24 |
Oct 12 10:00:11 PM UTC 24 |
6199958880 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.3442207429 |
|
|
Oct 12 09:53:14 PM UTC 24 |
Oct 12 10:00:20 PM UTC 24 |
5949339350 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4271901724 |
|
|
Oct 12 08:48:22 PM UTC 24 |
Oct 12 10:00:33 PM UTC 24 |
14759525704 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1662232647 |
|
|
Oct 12 08:45:48 PM UTC 24 |
Oct 12 10:01:04 PM UTC 24 |
15773901756 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.303422107 |
|
|
Oct 12 08:48:14 PM UTC 24 |
Oct 12 10:01:29 PM UTC 24 |
15072611640 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1521519510 |
|
|
Oct 12 08:43:33 PM UTC 24 |
Oct 12 10:01:36 PM UTC 24 |
15840932988 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.2947952511 |
|
|
Oct 12 09:53:09 PM UTC 24 |
Oct 12 10:01:58 PM UTC 24 |
3855980660 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.798671642 |
|
|
Oct 12 08:44:58 PM UTC 24 |
Oct 12 10:01:59 PM UTC 24 |
14887974996 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2805657456 |
|
|
Oct 12 09:58:04 PM UTC 24 |
Oct 12 10:02:11 PM UTC 24 |
3576237163 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.1185146333 |
|
|
Oct 12 09:58:01 PM UTC 24 |
Oct 12 10:02:26 PM UTC 24 |
2985205320 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.1182644668 |
|
|
Oct 12 09:53:29 PM UTC 24 |
Oct 12 10:02:40 PM UTC 24 |
3961363814 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3264371723 |
|
|
Oct 12 09:57:33 PM UTC 24 |
Oct 12 10:02:45 PM UTC 24 |
3302660526 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.1898034966 |
|
|
Oct 12 09:54:09 PM UTC 24 |
Oct 12 10:02:46 PM UTC 24 |
3811717424 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1042444391 |
|
|
Oct 12 08:43:07 PM UTC 24 |
Oct 12 10:03:03 PM UTC 24 |
15706833640 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.271186964 |
|
|
Oct 12 09:53:29 PM UTC 24 |
Oct 12 10:03:30 PM UTC 24 |
4342995516 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3139827715 |
|
|
Oct 12 09:54:39 PM UTC 24 |
Oct 12 10:03:57 PM UTC 24 |
4411868914 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.272584240 |
|
|
Oct 12 09:53:25 PM UTC 24 |
Oct 12 10:04:05 PM UTC 24 |
4208017558 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2889427087 |
|
|
Oct 12 09:54:38 PM UTC 24 |
Oct 12 10:04:21 PM UTC 24 |
4625853952 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.3261985465 |
|
|
Oct 12 09:59:10 PM UTC 24 |
Oct 12 10:05:12 PM UTC 24 |
3639892551 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1453107106 |
|
|
Oct 12 09:53:16 PM UTC 24 |
Oct 12 10:06:07 PM UTC 24 |
5302139704 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.232821527 |
|
|
Oct 12 09:57:15 PM UTC 24 |
Oct 12 10:06:13 PM UTC 24 |
4458951850 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2610444240 |
|
|
Oct 12 10:03:47 PM UTC 24 |
Oct 12 10:06:39 PM UTC 24 |
2931337591 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3333132829 |
|
|
Oct 12 10:02:16 PM UTC 24 |
Oct 12 10:07:34 PM UTC 24 |
2613053912 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.973550631 |
|
|
Oct 12 10:04:06 PM UTC 24 |
Oct 12 10:07:39 PM UTC 24 |
2261045008 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.932051715 |
|
|
Oct 12 10:00:57 PM UTC 24 |
Oct 12 10:07:56 PM UTC 24 |
3109642492 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.2931742240 |
|
|
Oct 12 09:59:09 PM UTC 24 |
Oct 12 10:08:05 PM UTC 24 |
4321464707 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.3302594199 |
|
|
Oct 12 09:54:39 PM UTC 24 |
Oct 12 10:08:10 PM UTC 24 |
5365193836 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.2591421300 |
|
|
Oct 12 08:55:47 PM UTC 24 |
Oct 12 10:08:11 PM UTC 24 |
15261742024 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4177038717 |
|
|
Oct 12 09:55:49 PM UTC 24 |
Oct 12 10:08:39 PM UTC 24 |
5399335024 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.547878590 |
|
|
Oct 12 10:06:53 PM UTC 24 |
Oct 12 10:08:58 PM UTC 24 |
2329132969 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2078648280 |
|
|
Oct 12 10:06:52 PM UTC 24 |
Oct 12 10:08:59 PM UTC 24 |
2920023022 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1554744216 |
|
|
Oct 12 10:03:45 PM UTC 24 |
Oct 12 10:09:10 PM UTC 24 |
3112739114 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3366683018 |
|
|
Oct 12 10:04:44 PM UTC 24 |
Oct 12 10:09:11 PM UTC 24 |
3746551728 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.939751259 |
|
|
Oct 12 10:00:03 PM UTC 24 |
Oct 12 10:09:20 PM UTC 24 |
4757786031 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.1138052976 |
|
|
Oct 12 10:00:00 PM UTC 24 |
Oct 12 10:09:51 PM UTC 24 |
4030418620 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.2847996609 |
|
|
Oct 12 08:56:13 PM UTC 24 |
Oct 12 10:11:05 PM UTC 24 |
16162779301 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.2754865834 |
|
|
Oct 12 07:48:41 PM UTC 24 |
Oct 12 10:11:17 PM UTC 24 |
31690405476 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.16824208 |
|
|
Oct 12 09:59:59 PM UTC 24 |
Oct 12 10:11:37 PM UTC 24 |
4698906910 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.3547540720 |
|
|
Oct 12 08:54:38 PM UTC 24 |
Oct 12 10:12:45 PM UTC 24 |
15703730572 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.2321515796 |
|
|
Oct 12 10:09:09 PM UTC 24 |
Oct 12 10:12:57 PM UTC 24 |
3011340800 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.1849419126 |
|
|
Oct 12 09:59:06 PM UTC 24 |
Oct 12 10:13:05 PM UTC 24 |
8047095827 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.4006069171 |
|
|
Oct 12 09:11:35 PM UTC 24 |
Oct 12 10:13:46 PM UTC 24 |
41956702099 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2377205666 |
|
|
Oct 12 10:03:04 PM UTC 24 |
Oct 12 10:13:53 PM UTC 24 |
4391805264 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_descrambling.1466797667 |
|
|
Oct 12 10:04:11 PM UTC 24 |
Oct 12 10:14:06 PM UTC 24 |
4551616496 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.1008602149 |
|
|
Oct 12 10:09:01 PM UTC 24 |
Oct 12 10:14:24 PM UTC 24 |
3317870226 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1128941244 |
|
|
Oct 12 09:09:32 PM UTC 24 |
Oct 12 10:14:47 PM UTC 24 |
30012094754 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.4273888956 |
|
|
Oct 12 09:52:25 PM UTC 24 |
Oct 12 10:15:13 PM UTC 24 |
8700104376 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.1147014000 |
|
|
Oct 12 09:13:02 PM UTC 24 |
Oct 12 10:15:14 PM UTC 24 |
44751243431 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.766329825 |
|
|
Oct 12 10:09:32 PM UTC 24 |
Oct 12 10:15:39 PM UTC 24 |
6839316612 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.157226621 |
|
|
Oct 12 10:09:08 PM UTC 24 |
Oct 12 10:16:46 PM UTC 24 |
5317515085 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4114611076 |
|
|
Oct 12 10:13:15 PM UTC 24 |
Oct 12 10:17:30 PM UTC 24 |
2842422440 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.2424992199 |
|
|
Oct 12 10:00:17 PM UTC 24 |
Oct 12 10:17:46 PM UTC 24 |
6060225784 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.1461129112 |
|
|
Oct 12 08:11:10 PM UTC 24 |
Oct 12 10:17:46 PM UTC 24 |
26038158864 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2701383116 |
|
|
Oct 12 10:11:52 PM UTC 24 |
Oct 12 10:17:59 PM UTC 24 |
7478469160 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2042676454 |
|
|
Oct 12 10:00:54 PM UTC 24 |
Oct 12 10:18:38 PM UTC 24 |
6290773893 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1033899784 |
|
|
Oct 12 10:02:16 PM UTC 24 |
Oct 12 10:18:47 PM UTC 24 |
5595553829 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1379091068 |
|
|
Oct 12 09:54:10 PM UTC 24 |
Oct 12 10:19:07 PM UTC 24 |
8505744014 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.122104112 |
|
|
Oct 12 10:13:43 PM UTC 24 |
Oct 12 10:19:35 PM UTC 24 |
3771377720 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4175371970 |
|
|
Oct 12 10:10:38 PM UTC 24 |
Oct 12 10:19:42 PM UTC 24 |
7392004196 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3426716988 |
|
|
Oct 12 10:14:44 PM UTC 24 |
Oct 12 10:19:51 PM UTC 24 |
2753087133 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.600127564 |
|
|
Oct 12 09:00:18 PM UTC 24 |
Oct 12 10:20:19 PM UTC 24 |
14934396110 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1129723433 |
|
|
Oct 12 10:13:43 PM UTC 24 |
Oct 12 10:20:35 PM UTC 24 |
3229031304 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3863153719 |
|
|
Oct 12 10:10:37 PM UTC 24 |
Oct 12 10:21:39 PM UTC 24 |
6404612376 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4119355906 |
|
|
Oct 12 08:45:42 PM UTC 24 |
Oct 12 10:21:40 PM UTC 24 |
18749698568 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.2191438940 |
|
|
Oct 12 10:16:13 PM UTC 24 |
Oct 12 10:21:42 PM UTC 24 |
3568115672 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1423091461 |
|
|
Oct 12 10:16:09 PM UTC 24 |
Oct 12 10:21:51 PM UTC 24 |
3760282488 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.3369325887 |
|
|
Oct 12 10:05:42 PM UTC 24 |
Oct 12 10:21:53 PM UTC 24 |
9967609444 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1464300217 |
|
|
Oct 12 10:04:10 PM UTC 24 |
Oct 12 10:22:08 PM UTC 24 |
8623598618 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.621985755 |
|
|
Oct 12 10:03:25 PM UTC 24 |
Oct 12 10:22:28 PM UTC 24 |
7892922982 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.564372758 |
|
|
Oct 12 10:15:01 PM UTC 24 |
Oct 12 10:22:30 PM UTC 24 |
6448435644 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.247068441 |
|
|
Oct 12 10:09:08 PM UTC 24 |
Oct 12 10:22:32 PM UTC 24 |
5981807240 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.408544428 |
|
|
Oct 12 08:46:35 PM UTC 24 |
Oct 12 10:22:39 PM UTC 24 |
18389477145 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.858155791 |
|
|
Oct 12 10:04:11 PM UTC 24 |
Oct 12 10:22:47 PM UTC 24 |
11887586496 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3087742986 |
|
|
Oct 12 10:03:04 PM UTC 24 |
Oct 12 10:23:07 PM UTC 24 |
7381195096 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2900912357 |
|
|
Oct 12 10:18:08 PM UTC 24 |
Oct 12 10:24:22 PM UTC 24 |
4494433680 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3907236330 |
|
|
Oct 12 10:14:46 PM UTC 24 |
Oct 12 10:24:24 PM UTC 24 |
4154989073 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.448386914 |
|
|
Oct 12 10:20:31 PM UTC 24 |
Oct 12 10:25:08 PM UTC 24 |
2357865928 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1809077069 |
|
|
Oct 12 10:21:12 PM UTC 24 |
Oct 12 10:25:08 PM UTC 24 |
2718392280 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2857986049 |
|
|
Oct 12 09:14:18 PM UTC 24 |
Oct 12 10:25:31 PM UTC 24 |
15269926580 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.374386992 |
|
|
Oct 12 10:16:32 PM UTC 24 |
Oct 12 10:25:49 PM UTC 24 |
6686734644 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.423947312 |
|
|
Oct 12 10:20:55 PM UTC 24 |
Oct 12 10:26:53 PM UTC 24 |
2836407286 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1191157918 |
|
|
Oct 12 10:17:23 PM UTC 24 |
Oct 12 10:27:39 PM UTC 24 |
7450539966 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3627058234 |
|
|
Oct 12 10:18:44 PM UTC 24 |
Oct 12 10:27:44 PM UTC 24 |
18099531510 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2980287701 |
|
|
Oct 12 10:10:16 PM UTC 24 |
Oct 12 10:28:42 PM UTC 24 |
11324235264 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.406674451 |
|
|
Oct 12 10:24:22 PM UTC 24 |
Oct 12 10:28:53 PM UTC 24 |
2962054664 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3474885222 |
|
|
Oct 12 10:10:34 PM UTC 24 |
Oct 12 10:28:47 PM UTC 24 |
6992554281 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.737059553 |
|
|
Oct 12 10:19:43 PM UTC 24 |
Oct 12 10:29:00 PM UTC 24 |
4551545416 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3355650005 |
|
|
Oct 12 10:18:45 PM UTC 24 |
Oct 12 10:29:17 PM UTC 24 |
4787461340 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.4222377321 |
|
|
Oct 12 10:22:41 PM UTC 24 |
Oct 12 10:29:17 PM UTC 24 |
3920013314 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.177554491 |
|
|
Oct 12 10:25:08 PM UTC 24 |
Oct 12 10:29:18 PM UTC 24 |
2251587896 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.2543132484 |
|
|
Oct 12 10:24:17 PM UTC 24 |
Oct 12 10:29:32 PM UTC 24 |
2457446771 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3712860761 |
|
|
Oct 12 10:24:23 PM UTC 24 |
Oct 12 10:30:00 PM UTC 24 |
3327002662 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.873036787 |
|
|
Oct 12 10:23:51 PM UTC 24 |
Oct 12 10:30:25 PM UTC 24 |
4531101810 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.2477732586 |
|
|
Oct 12 10:24:14 PM UTC 24 |
Oct 12 10:30:32 PM UTC 24 |
3419049426 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1949991906 |
|
|
Oct 12 10:28:25 PM UTC 24 |
Oct 12 10:32:55 PM UTC 24 |
2447876936 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2505558062 |
|
|
Oct 12 10:20:35 PM UTC 24 |
Oct 12 10:33:31 PM UTC 24 |
4775277242 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.4039096893 |
|
|
Oct 12 10:25:53 PM UTC 24 |
Oct 12 10:33:52 PM UTC 24 |
2586575230 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.785563583 |
|
|
Oct 12 10:23:57 PM UTC 24 |
Oct 12 10:33:58 PM UTC 24 |
5356595240 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.781073927 |
|
|
Oct 12 10:20:31 PM UTC 24 |
Oct 12 10:34:02 PM UTC 24 |
5125854720 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.364063041 |
|
|
Oct 12 10:30:43 PM UTC 24 |
Oct 12 10:34:03 PM UTC 24 |
3321834428 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.2488866941 |
|
|
Oct 12 10:18:45 PM UTC 24 |
Oct 12 10:34:06 PM UTC 24 |
5896799324 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.722802018 |
|
|
Oct 12 10:30:39 PM UTC 24 |
Oct 12 10:34:28 PM UTC 24 |
2833594696 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1085245989 |
|
|
Oct 12 10:28:25 PM UTC 24 |
Oct 12 10:34:33 PM UTC 24 |
4404362320 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.103378480 |
|
|
Oct 12 10:25:53 PM UTC 24 |
Oct 12 10:34:41 PM UTC 24 |
3537918400 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4242727483 |
|
|
Oct 12 09:19:34 PM UTC 24 |
Oct 12 10:34:55 PM UTC 24 |
15357026372 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2355999216 |
|
|
Oct 12 09:20:06 PM UTC 24 |
Oct 12 10:34:59 PM UTC 24 |
15351043400 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.3364511950 |
|
|
Oct 12 10:01:03 PM UTC 24 |
Oct 12 10:35:27 PM UTC 24 |
18084008760 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.820508258 |
|
|
Oct 12 10:10:38 PM UTC 24 |
Oct 12 10:35:34 PM UTC 24 |
10731095396 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1558350456 |
|
|
Oct 12 10:49:41 PM UTC 24 |
Oct 12 10:55:22 PM UTC 24 |
3508021488 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3066755536 |
|
|
Oct 12 10:10:29 PM UTC 24 |
Oct 12 10:35:38 PM UTC 24 |
17099703187 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.3195702722 |
|
|
Oct 12 10:31:20 PM UTC 24 |
Oct 12 10:36:07 PM UTC 24 |
2303590917 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.2335557531 |
|
|
Oct 12 10:30:42 PM UTC 24 |
Oct 12 10:36:28 PM UTC 24 |
2294323320 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.372692651 |
|
|
Oct 12 09:13:56 PM UTC 24 |
Oct 12 10:36:31 PM UTC 24 |
17111789736 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.3400746746 |
|
|
Oct 12 10:30:41 PM UTC 24 |
Oct 12 10:36:52 PM UTC 24 |
3186578188 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1612705026 |
|
|
Oct 12 10:26:25 PM UTC 24 |
Oct 12 10:38:41 PM UTC 24 |
7521448181 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.493323471 |
|
|
Oct 12 10:35:29 PM UTC 24 |
Oct 12 10:38:48 PM UTC 24 |
2538798960 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.195898797 |
|
|
Oct 12 10:35:43 PM UTC 24 |
Oct 12 10:40:38 PM UTC 24 |
3314689372 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.3371036085 |
|
|
Oct 12 10:36:22 PM UTC 24 |
Oct 12 10:40:42 PM UTC 24 |
3298643370 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3388887608 |
|
|
Oct 12 10:35:33 PM UTC 24 |
Oct 12 10:41:03 PM UTC 24 |
3381429325 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.325212908 |
|
|
Oct 12 10:36:52 PM UTC 24 |
Oct 12 10:41:16 PM UTC 24 |
2547791774 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.881536002 |
|
|
Oct 12 10:37:30 PM UTC 24 |
Oct 12 10:42:07 PM UTC 24 |
2599081115 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2632352906 |
|
|
Oct 12 10:15:21 PM UTC 24 |
Oct 12 10:42:14 PM UTC 24 |
23278610784 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.193707926 |
|
|
Oct 12 10:30:43 PM UTC 24 |
Oct 12 10:43:47 PM UTC 24 |
5801547550 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.962807144 |
|
|
Oct 12 10:37:28 PM UTC 24 |
Oct 12 10:43:58 PM UTC 24 |
5344444320 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.221969559 |
|
|
Oct 12 08:48:50 PM UTC 24 |
Oct 12 10:44:27 PM UTC 24 |
22758304960 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.4261753848 |
|
|
Oct 12 10:09:31 PM UTC 24 |
Oct 12 10:44:55 PM UTC 24 |
14695719322 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.157781711 |
|
|
Oct 12 10:41:27 PM UTC 24 |
Oct 12 10:45:26 PM UTC 24 |
2958394456 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.186455104 |
|
|
Oct 12 10:36:50 PM UTC 24 |
Oct 12 10:45:47 PM UTC 24 |
5278859720 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1837194458 |
|
|
Oct 12 10:30:44 PM UTC 24 |
Oct 12 10:46:31 PM UTC 24 |
5440701238 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.247144573 |
|
|
Oct 12 10:36:55 PM UTC 24 |
Oct 12 10:46:36 PM UTC 24 |
8072534355 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.2445116601 |
|
|
Oct 12 10:24:21 PM UTC 24 |
Oct 12 10:46:40 PM UTC 24 |
8465140748 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3050314634 |
|
|
Oct 12 10:36:46 PM UTC 24 |
Oct 12 10:46:55 PM UTC 24 |
7569358420 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3847690521 |
|
|
Oct 12 10:35:45 PM UTC 24 |
Oct 12 10:46:57 PM UTC 24 |
8784527382 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2968981560 |
|
|
Oct 12 10:24:22 PM UTC 24 |
Oct 12 10:47:43 PM UTC 24 |
13158473508 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.33720144 |
|
|
Oct 12 10:36:22 PM UTC 24 |
Oct 12 10:47:56 PM UTC 24 |
5147287941 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4200276444 |
|
|
Oct 12 08:47:39 PM UTC 24 |
Oct 12 10:48:19 PM UTC 24 |
23423525315 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3595382368 |
|
|
Oct 12 10:10:17 PM UTC 24 |
Oct 12 10:48:19 PM UTC 24 |
21825808497 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.51517737 |
|
|
Oct 12 10:39:31 PM UTC 24 |
Oct 12 10:48:22 PM UTC 24 |
3791915976 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.1904044039 |
|
|
Oct 12 10:25:08 PM UTC 24 |
Oct 12 10:48:51 PM UTC 24 |
5675786188 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3600570611 |
|
|
Oct 12 10:42:54 PM UTC 24 |
Oct 12 10:49:19 PM UTC 24 |
3825342360 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1505593031 |
|
|
Oct 12 10:41:53 PM UTC 24 |
Oct 12 10:50:18 PM UTC 24 |
4459018032 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1042856891 |
|
|
Oct 12 10:37:16 PM UTC 24 |
Oct 12 10:50:19 PM UTC 24 |
6363115368 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3564663779 |
|
|
Oct 12 10:42:54 PM UTC 24 |
Oct 12 10:50:46 PM UTC 24 |
4681629270 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1783151325 |
|
|
Oct 12 10:08:17 PM UTC 24 |
Oct 12 10:50:56 PM UTC 24 |
33364011342 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3073669830 |
|
|
Oct 12 10:36:55 PM UTC 24 |
Oct 12 10:51:01 PM UTC 24 |
6595685350 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.747382680 |
|
|
Oct 12 10:47:52 PM UTC 24 |
Oct 12 10:51:50 PM UTC 24 |
3218979746 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3127205646 |
|
|
Oct 12 08:47:08 PM UTC 24 |
Oct 12 10:52:42 PM UTC 24 |
23368145069 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.539980169 |
|
|
Oct 12 10:24:15 PM UTC 24 |
Oct 12 10:52:48 PM UTC 24 |
7857863464 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.3643041636 |
|
|
Oct 12 10:41:26 PM UTC 24 |
Oct 12 10:54:00 PM UTC 24 |
4619481558 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.207705272 |
|
|
Oct 12 10:23:57 PM UTC 24 |
Oct 12 10:54:03 PM UTC 24 |
8205819064 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.1737396752 |
|
|
Oct 12 10:47:49 PM UTC 24 |
Oct 12 10:54:16 PM UTC 24 |
3625008586 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.751556240 |
|
|
Oct 12 10:44:33 PM UTC 24 |
Oct 12 10:54:20 PM UTC 24 |
4038302440 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2642167546 |
|
|
Oct 12 08:45:37 PM UTC 24 |
Oct 12 10:54:29 PM UTC 24 |
24028940020 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2018500838 |
|
|
Oct 12 10:47:51 PM UTC 24 |
Oct 12 10:55:19 PM UTC 24 |
4079135238 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.1311476738 |
|
|
Oct 12 11:03:55 PM UTC 24 |
Oct 12 11:07:57 PM UTC 24 |
4559267991 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2557979361 |
|
|
Oct 12 10:45:02 PM UTC 24 |
Oct 12 10:55:24 PM UTC 24 |
3438872600 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.192512887 |
|
|
Oct 12 10:46:03 PM UTC 24 |
Oct 12 10:55:24 PM UTC 24 |
3611795560 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1415066741 |
|
|
Oct 12 10:45:32 PM UTC 24 |
Oct 12 10:55:28 PM UTC 24 |
4769702856 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.1179454237 |
|
|
Oct 12 10:53:12 PM UTC 24 |
Oct 12 10:55:43 PM UTC 24 |
3204227196 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1114877570 |
|
|
Oct 12 10:46:23 PM UTC 24 |
Oct 12 10:55:59 PM UTC 24 |
5136166492 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2775293788 |
|
|
Oct 12 08:46:36 PM UTC 24 |
Oct 12 10:56:28 PM UTC 24 |
23821804586 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4076352467 |
|
|
Oct 12 10:44:37 PM UTC 24 |
Oct 12 10:57:08 PM UTC 24 |
13003168076 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2887133969 |
|
|
Oct 12 08:48:02 PM UTC 24 |
Oct 12 10:57:11 PM UTC 24 |
24065049115 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.1418710113 |
|
|
Oct 12 10:54:35 PM UTC 24 |
Oct 12 10:57:21 PM UTC 24 |
2143384240 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.385589899 |
|
|
Oct 12 10:49:09 PM UTC 24 |
Oct 12 10:57:24 PM UTC 24 |
4776586904 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3314276110 |
|
|
Oct 12 10:55:10 PM UTC 24 |
Oct 12 10:57:40 PM UTC 24 |
2039694152 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2200432583 |
|
|
Oct 12 10:48:21 PM UTC 24 |
Oct 12 10:57:45 PM UTC 24 |
4927047740 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.838051422 |
|
|
Oct 12 10:51:07 PM UTC 24 |
Oct 12 10:57:53 PM UTC 24 |
5640348552 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1115222416 |
|
|
Oct 12 10:49:40 PM UTC 24 |
Oct 12 10:58:16 PM UTC 24 |
7440317848 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3206104463 |
|
|
Oct 12 10:39:30 PM UTC 24 |
Oct 12 10:58:21 PM UTC 24 |
6144126450 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.185029513 |
|
|
Oct 12 10:53:18 PM UTC 24 |
Oct 12 10:58:54 PM UTC 24 |
4220109905 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2614801701 |
|
|
Oct 12 10:51:41 PM UTC 24 |
Oct 12 10:58:55 PM UTC 24 |
4923981968 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.643965099 |
|
|
Oct 12 10:47:48 PM UTC 24 |
Oct 12 10:59:12 PM UTC 24 |
5603225424 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1860880409 |
|
|
Oct 12 10:47:49 PM UTC 24 |
Oct 12 10:59:12 PM UTC 24 |
4721904328 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2457721362 |
|
|
Oct 12 10:55:12 PM UTC 24 |
Oct 12 10:59:15 PM UTC 24 |
2705262621 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.112790631 |
|
|
Oct 12 10:51:47 PM UTC 24 |
Oct 12 10:59:16 PM UTC 24 |
6059038446 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2388660226 |
|
|
Oct 12 10:41:49 PM UTC 24 |
Oct 12 10:59:38 PM UTC 24 |
12077416032 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2047145431 |
|
|
Oct 12 08:46:05 PM UTC 24 |
Oct 12 11:00:17 PM UTC 24 |
24613599410 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1717185375 |
|
|
Oct 12 10:55:13 PM UTC 24 |
Oct 12 11:00:22 PM UTC 24 |
3812208270 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2821893025 |
|
|
Oct 12 10:52:27 PM UTC 24 |
Oct 12 11:00:29 PM UTC 24 |
4469005465 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.653822940 |
|
|
Oct 12 10:57:09 PM UTC 24 |
Oct 12 11:00:30 PM UTC 24 |
2572132104 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.634616415 |
|
|
Oct 12 10:51:46 PM UTC 24 |
Oct 12 11:00:30 PM UTC 24 |
4065340546 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2328058089 |
|
|
Oct 12 10:57:09 PM UTC 24 |
Oct 12 11:00:57 PM UTC 24 |
3160380306 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4164997592 |
|
|
Oct 12 10:51:07 PM UTC 24 |
Oct 12 11:01:05 PM UTC 24 |
6076374140 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1432654949 |
|
|
Oct 12 08:45:41 PM UTC 24 |
Oct 12 11:01:23 PM UTC 24 |
24431359280 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1847901428 |
|
|
Oct 12 10:57:10 PM UTC 24 |
Oct 12 11:01:32 PM UTC 24 |
2660526142 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.2588784020 |
|
|
Oct 12 10:56:51 PM UTC 24 |
Oct 12 11:02:31 PM UTC 24 |
3379452620 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.3401875862 |
|
|
Oct 12 10:30:20 PM UTC 24 |
Oct 12 11:02:55 PM UTC 24 |
8343705442 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.35769665 |
|
|
Oct 12 10:58:39 PM UTC 24 |
Oct 12 11:02:57 PM UTC 24 |
2948010037 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.325781340 |
|
|
Oct 12 10:49:09 PM UTC 24 |
Oct 12 11:04:13 PM UTC 24 |
7392351228 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.3299793037 |
|
|
Oct 12 10:59:32 PM UTC 24 |
Oct 12 11:04:23 PM UTC 24 |
4593421550 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.3187031767 |
|
|
Oct 12 10:31:15 PM UTC 24 |
Oct 12 11:04:23 PM UTC 24 |
8003820064 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2145822392 |
|
|
Oct 12 10:34:09 PM UTC 24 |
Oct 12 11:04:35 PM UTC 24 |
9738267720 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.2412002333 |
|
|
Oct 12 10:26:08 PM UTC 24 |
Oct 12 11:04:40 PM UTC 24 |
9430699050 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2147717446 |
|
|
Oct 12 11:03:25 PM UTC 24 |
Oct 12 11:05:20 PM UTC 24 |
2480814764 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_aes.2164682394 |
|
|
Oct 12 10:36:33 PM UTC 24 |
Oct 12 11:06:04 PM UTC 24 |
9481037752 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.4049037129 |
|
|
Oct 12 10:56:36 PM UTC 24 |
Oct 12 11:06:06 PM UTC 24 |
4770925670 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.354340770 |
|
|
Oct 12 11:02:55 PM UTC 24 |
Oct 12 11:06:48 PM UTC 24 |
2949143656 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.2999938758 |
|
|
Oct 12 11:04:06 PM UTC 24 |
Oct 12 11:07:50 PM UTC 24 |
2967317820 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.3857410941 |
|
|
Oct 12 10:54:35 PM UTC 24 |
Oct 12 11:08:03 PM UTC 24 |
7715622600 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2005114055 |
|
|
Oct 12 10:56:50 PM UTC 24 |
Oct 12 11:08:06 PM UTC 24 |
4807458948 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2974001234 |
|
|
Oct 12 10:59:14 PM UTC 24 |
Oct 12 11:08:28 PM UTC 24 |
5214605205 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.2190077893 |
|
|
Oct 12 11:05:02 PM UTC 24 |
Oct 12 11:08:39 PM UTC 24 |
2365763000 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.1202824063 |
|
|
Oct 12 10:59:17 PM UTC 24 |
Oct 12 11:08:56 PM UTC 24 |
4389645564 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.1074825139 |
|
|
Oct 12 10:48:20 PM UTC 24 |
Oct 12 11:09:01 PM UTC 24 |
11433136365 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.1440184819 |
|
|
Oct 12 11:04:06 PM UTC 24 |
Oct 12 11:09:18 PM UTC 24 |
3014409740 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1031623246 |
|
|
Oct 12 11:05:30 PM UTC 24 |
Oct 12 11:09:31 PM UTC 24 |
2998873767 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1012888135 |
|
|
Oct 12 11:05:26 PM UTC 24 |
Oct 12 11:09:51 PM UTC 24 |
2856574758 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.3904013056 |
|
|
Oct 12 10:48:43 PM UTC 24 |
Oct 12 11:10:47 PM UTC 24 |
14194646514 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.4255099575 |
|
|
Oct 12 11:05:56 PM UTC 24 |
Oct 12 11:11:10 PM UTC 24 |
3320574558 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.957953268 |
|
|
Oct 12 11:05:31 PM UTC 24 |
Oct 12 11:11:15 PM UTC 24 |
2826314764 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.1085995838 |
|
|
Oct 12 11:06:52 PM UTC 24 |
Oct 12 11:12:00 PM UTC 24 |
3034549440 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.987972862 |
|
|
Oct 12 11:09:33 PM UTC 24 |
Oct 12 11:12:04 PM UTC 24 |
2314489464 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.1104766276 |
|
|
Oct 12 11:04:05 PM UTC 24 |
Oct 12 11:12:09 PM UTC 24 |
3914176180 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3887039345 |
|
|
Oct 12 11:09:27 PM UTC 24 |
Oct 12 11:12:44 PM UTC 24 |
2541941872 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2236654645 |
|
|
Oct 12 10:49:56 PM UTC 24 |
Oct 12 11:13:03 PM UTC 24 |
21416943456 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2467359703 |
|
|
Oct 12 10:50:37 PM UTC 24 |
Oct 12 11:13:39 PM UTC 24 |
24674201160 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.1719158605 |
|
|
Oct 12 11:09:36 PM UTC 24 |
Oct 12 11:13:43 PM UTC 24 |
2820408078 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.3275402266 |
|
|
Oct 12 11:08:53 PM UTC 24 |
Oct 12 11:13:45 PM UTC 24 |
3127008484 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.1015801609 |
|
|
Oct 12 11:09:32 PM UTC 24 |
Oct 12 11:14:13 PM UTC 24 |
3122921704 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.515895459 |
|
|
Oct 12 11:09:14 PM UTC 24 |
Oct 12 11:14:14 PM UTC 24 |
3119015932 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.3446566529 |
|
|
Oct 12 11:09:51 PM UTC 24 |
Oct 12 11:14:27 PM UTC 24 |
2138505432 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.2207429853 |
|
|
Oct 12 11:09:16 PM UTC 24 |
Oct 12 11:14:29 PM UTC 24 |
2414521304 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2810799054 |
|
|
Oct 12 10:57:06 PM UTC 24 |
Oct 12 11:14:54 PM UTC 24 |
6902861464 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.2918041641 |
|
|
Oct 12 11:10:07 PM UTC 24 |
Oct 12 11:14:54 PM UTC 24 |
3154724440 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2907540449 |
|
|
Oct 12 11:05:29 PM UTC 24 |
Oct 12 11:15:42 PM UTC 24 |
3667090230 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.1195507931 |
|
|
Oct 12 11:10:28 PM UTC 24 |
Oct 12 11:15:44 PM UTC 24 |
3620443400 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3148072190 |
|
|
Oct 12 11:08:52 PM UTC 24 |
Oct 12 11:16:25 PM UTC 24 |
6294153774 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1824867244 |
|
|
Oct 12 11:07:25 PM UTC 24 |
Oct 12 11:16:30 PM UTC 24 |
5592032920 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.476227189 |
|
|
Oct 12 11:13:00 PM UTC 24 |
Oct 12 11:16:40 PM UTC 24 |
2494448000 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1650268815 |
|
|
Oct 12 11:13:00 PM UTC 24 |
Oct 12 11:18:07 PM UTC 24 |
3677114028 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.2279329211 |
|
|
Oct 12 10:27:32 PM UTC 24 |
Oct 12 11:18:22 PM UTC 24 |
12000552156 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2729923703 |
|
|
Oct 12 10:16:10 PM UTC 24 |
Oct 12 11:18:26 PM UTC 24 |
20997058314 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.109817530 |
|
|
Oct 12 11:00:27 PM UTC 24 |
Oct 12 11:18:57 PM UTC 24 |
5703158278 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.752503040 |
|
|
Oct 12 11:13:38 PM UTC 24 |
Oct 12 11:19:07 PM UTC 24 |
2995571092 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.3001943602 |
|
|
Oct 12 11:11:27 PM UTC 24 |
Oct 12 11:22:17 PM UTC 24 |
4518037734 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3452117558 |
|
|
Oct 12 11:16:04 PM UTC 24 |
Oct 12 11:22:19 PM UTC 24 |
3786454367 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.1392020883 |
|
|
Oct 12 11:18:39 PM UTC 24 |
Oct 12 11:22:24 PM UTC 24 |
2700104328 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.131903036 |
|
|
Oct 12 11:17:26 PM UTC 24 |
Oct 12 11:23:49 PM UTC 24 |
2865868425 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3433059410 |
|
|
Oct 12 11:12:00 PM UTC 24 |
Oct 12 11:24:13 PM UTC 24 |
5961675906 ps |