| T2023 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2789739606 |
|
|
Oct 12 06:54:48 PM UTC 24 |
Oct 12 06:57:44 PM UTC 24 |
418733364 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.3427107138 |
|
|
Oct 12 06:48:15 PM UTC 24 |
Oct 12 06:57:50 PM UTC 24 |
57016498392 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.2508838946 |
|
|
Oct 12 06:56:58 PM UTC 24 |
Oct 12 06:57:52 PM UTC 24 |
1185743818 ps |
| T2026 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.222288017 |
|
|
Oct 12 06:57:38 PM UTC 24 |
Oct 12 06:57:53 PM UTC 24 |
306793087 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1166863457 |
|
|
Oct 12 06:57:04 PM UTC 24 |
Oct 12 06:57:59 PM UTC 24 |
595557649 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.196296382 |
|
|
Oct 12 06:57:31 PM UTC 24 |
Oct 12 06:58:04 PM UTC 24 |
227454765 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2404998591 |
|
|
Oct 12 06:55:59 PM UTC 24 |
Oct 12 06:58:05 PM UTC 24 |
7596887843 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.1638608280 |
|
|
Oct 12 06:57:29 PM UTC 24 |
Oct 12 06:58:10 PM UTC 24 |
517462753 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.348151241 |
|
|
Oct 12 06:46:34 PM UTC 24 |
Oct 12 06:58:11 PM UTC 24 |
45110793944 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2900486440 |
|
|
Oct 12 06:58:04 PM UTC 24 |
Oct 12 06:58:13 PM UTC 24 |
47100816 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1213739047 |
|
|
Oct 12 06:57:00 PM UTC 24 |
Oct 12 06:58:16 PM UTC 24 |
4657064652 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2063519560 |
|
|
Oct 12 06:58:07 PM UTC 24 |
Oct 12 06:58:17 PM UTC 24 |
49794010 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3506874558 |
|
|
Oct 12 06:58:16 PM UTC 24 |
Oct 12 06:58:30 PM UTC 24 |
68959272 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2410577079 |
|
|
Oct 12 06:56:58 PM UTC 24 |
Oct 12 06:58:42 PM UTC 24 |
7435547818 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.1090784634 |
|
|
Oct 12 06:57:30 PM UTC 24 |
Oct 12 06:58:48 PM UTC 24 |
2384044037 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2687830402 |
|
|
Oct 12 06:54:38 PM UTC 24 |
Oct 12 06:58:50 PM UTC 24 |
1756750167 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.3165628066 |
|
|
Oct 12 06:58:12 PM UTC 24 |
Oct 12 06:58:51 PM UTC 24 |
479494702 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.653145476 |
|
|
Oct 12 06:57:10 PM UTC 24 |
Oct 12 06:58:57 PM UTC 24 |
2382814931 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.319613640 |
|
|
Oct 12 06:56:18 PM UTC 24 |
Oct 12 06:58:59 PM UTC 24 |
10295320467 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.404827809 |
|
|
Oct 12 06:58:34 PM UTC 24 |
Oct 12 06:59:04 PM UTC 24 |
225759640 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.460081249 |
|
|
Oct 12 06:58:33 PM UTC 24 |
Oct 12 06:59:04 PM UTC 24 |
270145871 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.514813781 |
|
|
Oct 12 06:56:22 PM UTC 24 |
Oct 12 06:59:10 PM UTC 24 |
12989471808 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3571547368 |
|
|
Oct 12 06:47:22 PM UTC 24 |
Oct 12 06:59:15 PM UTC 24 |
47888877577 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1045538978 |
|
|
Oct 12 06:58:40 PM UTC 24 |
Oct 12 06:59:17 PM UTC 24 |
682667970 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2812210651 |
|
|
Oct 12 06:43:55 PM UTC 24 |
Oct 12 06:59:22 PM UTC 24 |
67863265163 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2172052282 |
|
|
Oct 12 06:59:15 PM UTC 24 |
Oct 12 06:59:23 PM UTC 24 |
41155958 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3830150175 |
|
|
Oct 12 06:57:11 PM UTC 24 |
Oct 12 06:59:24 PM UTC 24 |
7247926956 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2145081116 |
|
|
Oct 12 06:56:41 PM UTC 24 |
Oct 12 06:59:24 PM UTC 24 |
1204983168 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.3119604297 |
|
|
Oct 12 06:58:30 PM UTC 24 |
Oct 12 06:59:26 PM UTC 24 |
1979654072 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.938305441 |
|
|
Oct 12 06:59:15 PM UTC 24 |
Oct 12 06:59:26 PM UTC 24 |
142997404 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1813601630 |
|
|
Oct 12 06:58:52 PM UTC 24 |
Oct 12 06:59:32 PM UTC 24 |
146758472 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2953997020 |
|
|
Oct 12 06:58:09 PM UTC 24 |
Oct 12 06:59:36 PM UTC 24 |
3983682084 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.3731625620 |
|
|
Oct 12 06:59:26 PM UTC 24 |
Oct 12 06:59:41 PM UTC 24 |
118305670 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.1390185123 |
|
|
Oct 12 06:53:13 PM UTC 24 |
Oct 12 06:59:51 PM UTC 24 |
35938038970 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.834126865 |
|
|
Oct 12 06:50:46 PM UTC 24 |
Oct 12 06:59:52 PM UTC 24 |
7426730503 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2734268958 |
|
|
Oct 12 06:55:40 PM UTC 24 |
Oct 12 06:59:54 PM UTC 24 |
3123147460 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.4003024285 |
|
|
Oct 12 06:58:07 PM UTC 24 |
Oct 12 06:59:57 PM UTC 24 |
6962334491 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.552315123 |
|
|
Oct 12 06:59:40 PM UTC 24 |
Oct 12 07:00:02 PM UTC 24 |
186338234 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.54302943 |
|
|
Oct 12 06:59:28 PM UTC 24 |
Oct 12 07:00:03 PM UTC 24 |
444645674 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.665056123 |
|
|
Oct 12 06:51:42 PM UTC 24 |
Oct 12 07:00:07 PM UTC 24 |
32080631907 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1169636117 |
|
|
Oct 12 06:59:47 PM UTC 24 |
Oct 12 07:00:08 PM UTC 24 |
299479189 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.735935012 |
|
|
Oct 12 06:56:42 PM UTC 24 |
Oct 12 07:00:12 PM UTC 24 |
6523187421 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3123610819 |
|
|
Oct 12 06:48:58 PM UTC 24 |
Oct 12 07:00:16 PM UTC 24 |
16788088517 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.3179803053 |
|
|
Oct 12 06:59:46 PM UTC 24 |
Oct 12 07:00:17 PM UTC 24 |
303344595 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3210046092 |
|
|
Oct 12 06:59:48 PM UTC 24 |
Oct 12 07:00:18 PM UTC 24 |
387408988 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1697831382 |
|
|
Oct 12 06:51:48 PM UTC 24 |
Oct 12 07:00:20 PM UTC 24 |
34408105669 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1936087319 |
|
|
Oct 12 06:49:40 PM UTC 24 |
Oct 12 07:00:20 PM UTC 24 |
39850709900 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3530559879 |
|
|
Oct 12 06:53:47 PM UTC 24 |
Oct 12 07:00:21 PM UTC 24 |
6913028584 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1591111385 |
|
|
Oct 12 07:00:13 PM UTC 24 |
Oct 12 07:00:22 PM UTC 24 |
47084076 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.1644977545 |
|
|
Oct 12 07:00:14 PM UTC 24 |
Oct 12 07:00:23 PM UTC 24 |
148833270 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3534109633 |
|
|
Oct 12 06:48:39 PM UTC 24 |
Oct 12 07:00:27 PM UTC 24 |
4853720442 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2780750238 |
|
|
Oct 12 06:55:38 PM UTC 24 |
Oct 12 07:00:27 PM UTC 24 |
741889875 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.123148129 |
|
|
Oct 12 06:59:48 PM UTC 24 |
Oct 12 07:00:28 PM UTC 24 |
317855647 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.1023543167 |
|
|
Oct 12 06:54:36 PM UTC 24 |
Oct 12 07:00:30 PM UTC 24 |
3962794509 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.2096605177 |
|
|
Oct 12 06:58:21 PM UTC 24 |
Oct 12 07:00:31 PM UTC 24 |
9019504322 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.2908005298 |
|
|
Oct 12 06:59:47 PM UTC 24 |
Oct 12 07:00:49 PM UTC 24 |
1468752331 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.4105511465 |
|
|
Oct 12 06:58:26 PM UTC 24 |
Oct 12 07:00:52 PM UTC 24 |
3190798397 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2509338957 |
|
|
Oct 12 07:00:50 PM UTC 24 |
Oct 12 07:00:59 PM UTC 24 |
43839127 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2527051646 |
|
|
Oct 12 07:00:47 PM UTC 24 |
Oct 12 07:01:00 PM UTC 24 |
173141445 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3676706245 |
|
|
Oct 12 06:53:13 PM UTC 24 |
Oct 12 07:01:09 PM UTC 24 |
32242646199 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.4093901466 |
|
|
Oct 12 07:00:42 PM UTC 24 |
Oct 12 07:01:11 PM UTC 24 |
511551763 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.890385331 |
|
|
Oct 12 07:00:29 PM UTC 24 |
Oct 12 07:01:15 PM UTC 24 |
551602967 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2600070497 |
|
|
Oct 12 06:59:17 PM UTC 24 |
Oct 12 07:01:16 PM UTC 24 |
8742019606 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.1877624392 |
|
|
Oct 12 06:55:15 PM UTC 24 |
Oct 12 07:01:20 PM UTC 24 |
26473369420 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2909246888 |
|
|
Oct 12 06:59:24 PM UTC 24 |
Oct 12 07:01:21 PM UTC 24 |
6140522309 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.1495324301 |
|
|
Oct 12 07:00:27 PM UTC 24 |
Oct 12 07:01:23 PM UTC 24 |
1512568684 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.1272602599 |
|
|
Oct 12 07:00:43 PM UTC 24 |
Oct 12 07:01:25 PM UTC 24 |
558715573 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.4079280825 |
|
|
Oct 12 07:00:40 PM UTC 24 |
Oct 12 07:01:27 PM UTC 24 |
395402396 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.1234033194 |
|
|
Oct 12 07:00:41 PM UTC 24 |
Oct 12 07:01:28 PM UTC 24 |
1111157807 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.99774135 |
|
|
Oct 12 07:00:30 PM UTC 24 |
Oct 12 07:01:30 PM UTC 24 |
3477760723 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.1114099735 |
|
|
Oct 12 06:52:20 PM UTC 24 |
Oct 12 07:01:30 PM UTC 24 |
14903340110 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.2406619196 |
|
|
Oct 12 07:00:39 PM UTC 24 |
Oct 12 07:01:32 PM UTC 24 |
529365350 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.2282367080 |
|
|
Oct 12 06:56:34 PM UTC 24 |
Oct 12 07:01:38 PM UTC 24 |
3816507468 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.3791262580 |
|
|
Oct 12 07:00:35 PM UTC 24 |
Oct 12 07:01:48 PM UTC 24 |
2014947396 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.3125588721 |
|
|
Oct 12 07:01:12 PM UTC 24 |
Oct 12 07:01:56 PM UTC 24 |
464437037 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.2642970211 |
|
|
Oct 12 07:01:30 PM UTC 24 |
Oct 12 07:02:01 PM UTC 24 |
394882361 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.3435652917 |
|
|
Oct 12 07:01:38 PM UTC 24 |
Oct 12 07:02:02 PM UTC 24 |
177039624 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3068123150 |
|
|
Oct 12 07:00:21 PM UTC 24 |
Oct 12 07:02:04 PM UTC 24 |
4914214453 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.4100865450 |
|
|
Oct 12 07:01:54 PM UTC 24 |
Oct 12 07:02:05 PM UTC 24 |
53098066 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.3906106708 |
|
|
Oct 12 07:01:54 PM UTC 24 |
Oct 12 07:02:07 PM UTC 24 |
215332700 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.3987482865 |
|
|
Oct 12 07:00:18 PM UTC 24 |
Oct 12 07:02:09 PM UTC 24 |
8831271461 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.44636091 |
|
|
Oct 12 06:57:53 PM UTC 24 |
Oct 12 07:02:12 PM UTC 24 |
2207179774 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1475266658 |
|
|
Oct 12 07:01:45 PM UTC 24 |
Oct 12 07:02:15 PM UTC 24 |
504096173 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.1075724458 |
|
|
Oct 12 06:58:41 PM UTC 24 |
Oct 12 07:02:18 PM UTC 24 |
4747842485 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.1532512675 |
|
|
Oct 12 07:01:37 PM UTC 24 |
Oct 12 07:02:21 PM UTC 24 |
537632864 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.2387488622 |
|
|
Oct 12 07:01:42 PM UTC 24 |
Oct 12 07:02:29 PM UTC 24 |
1103429436 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.2232516302 |
|
|
Oct 12 07:01:18 PM UTC 24 |
Oct 12 07:02:30 PM UTC 24 |
6725794490 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.285217650 |
|
|
Oct 12 07:00:53 PM UTC 24 |
Oct 12 07:02:34 PM UTC 24 |
6062365750 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1112916499 |
|
|
Oct 12 06:53:41 PM UTC 24 |
Oct 12 07:02:35 PM UTC 24 |
3745290304 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.42216810 |
|
|
Oct 12 07:01:12 PM UTC 24 |
Oct 12 07:02:43 PM UTC 24 |
2469433521 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.1107610739 |
|
|
Oct 12 07:02:27 PM UTC 24 |
Oct 12 07:02:43 PM UTC 24 |
415861567 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2543760188 |
|
|
Oct 12 07:02:37 PM UTC 24 |
Oct 12 07:02:47 PM UTC 24 |
89185842 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.451405036 |
|
|
Oct 12 06:55:14 PM UTC 24 |
Oct 12 07:02:48 PM UTC 24 |
37612300187 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.1149174422 |
|
|
Oct 12 07:02:21 PM UTC 24 |
Oct 12 07:02:48 PM UTC 24 |
281666963 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2944360841 |
|
|
Oct 12 06:45:42 PM UTC 24 |
Oct 12 07:02:48 PM UTC 24 |
68726113461 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3065732724 |
|
|
Oct 12 07:00:49 PM UTC 24 |
Oct 12 07:02:49 PM UTC 24 |
9269009813 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.864495205 |
|
|
Oct 12 07:02:12 PM UTC 24 |
Oct 12 07:02:59 PM UTC 24 |
1081928251 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.1480368052 |
|
|
Oct 12 07:02:35 PM UTC 24 |
Oct 12 07:02:59 PM UTC 24 |
503981824 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.2611273921 |
|
|
Oct 12 07:02:56 PM UTC 24 |
Oct 12 07:03:03 PM UTC 24 |
43685953 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1828733982 |
|
|
Oct 12 07:02:56 PM UTC 24 |
Oct 12 07:03:04 PM UTC 24 |
42276782 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.3025379652 |
|
|
Oct 12 07:02:31 PM UTC 24 |
Oct 12 07:03:07 PM UTC 24 |
434129127 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2231936320 |
|
|
Oct 12 07:02:44 PM UTC 24 |
Oct 12 07:03:11 PM UTC 24 |
7743908 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2538517655 |
|
|
Oct 12 06:51:09 PM UTC 24 |
Oct 12 07:03:13 PM UTC 24 |
16349116155 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2543986316 |
|
|
Oct 12 06:59:05 PM UTC 24 |
Oct 12 07:03:14 PM UTC 24 |
7947016573 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1871164376 |
|
|
Oct 12 06:56:39 PM UTC 24 |
Oct 12 07:03:18 PM UTC 24 |
754143188 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.987598969 |
|
|
Oct 12 07:01:56 PM UTC 24 |
Oct 12 07:03:21 PM UTC 24 |
7102084612 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1273096591 |
|
|
Oct 12 07:02:33 PM UTC 24 |
Oct 12 07:03:28 PM UTC 24 |
1534646366 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2804394721 |
|
|
Oct 12 07:02:01 PM UTC 24 |
Oct 12 07:03:28 PM UTC 24 |
5316484477 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.3370203813 |
|
|
Oct 12 07:03:24 PM UTC 24 |
Oct 12 07:03:34 PM UTC 24 |
71997261 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.2782373293 |
|
|
Oct 12 07:03:10 PM UTC 24 |
Oct 12 07:03:35 PM UTC 24 |
206471665 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.861550671 |
|
|
Oct 12 06:48:27 PM UTC 24 |
Oct 12 07:03:41 PM UTC 24 |
62508990890 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.313108981 |
|
|
Oct 12 07:00:03 PM UTC 24 |
Oct 12 07:03:43 PM UTC 24 |
467442712 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.2255078572 |
|
|
Oct 12 07:01:49 PM UTC 24 |
Oct 12 07:03:45 PM UTC 24 |
3130572640 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2506544349 |
|
|
Oct 12 07:03:30 PM UTC 24 |
Oct 12 07:03:50 PM UTC 24 |
110319029 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.156863670 |
|
|
Oct 12 06:55:27 PM UTC 24 |
Oct 12 07:03:53 PM UTC 24 |
34635554949 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.3338909652 |
|
|
Oct 12 07:03:45 PM UTC 24 |
Oct 12 07:03:57 PM UTC 24 |
178547567 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.452002573 |
|
|
Oct 12 07:00:48 PM UTC 24 |
Oct 12 07:03:57 PM UTC 24 |
1193676669 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.2838279264 |
|
|
Oct 12 07:00:44 PM UTC 24 |
Oct 12 07:04:01 PM UTC 24 |
5132785890 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2608766916 |
|
|
Oct 12 07:03:52 PM UTC 24 |
Oct 12 07:04:02 PM UTC 24 |
47115042 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.3571980493 |
|
|
Oct 12 07:03:10 PM UTC 24 |
Oct 12 07:04:05 PM UTC 24 |
695963385 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.596886428 |
|
|
Oct 12 07:03:26 PM UTC 24 |
Oct 12 07:04:07 PM UTC 24 |
417080199 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.814343102 |
|
|
Oct 12 07:01:45 PM UTC 24 |
Oct 12 07:04:11 PM UTC 24 |
1554386954 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1231781087 |
|
|
Oct 12 06:52:34 PM UTC 24 |
Oct 12 07:04:11 PM UTC 24 |
16299490146 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.682052375 |
|
|
Oct 12 07:00:40 PM UTC 24 |
Oct 12 07:04:16 PM UTC 24 |
14039310823 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.635659374 |
|
|
Oct 12 06:59:30 PM UTC 24 |
Oct 12 07:04:22 PM UTC 24 |
26669456638 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1335488725 |
|
|
Oct 12 07:04:22 PM UTC 24 |
Oct 12 07:04:31 PM UTC 24 |
156292480 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.674416239 |
|
|
Oct 12 06:54:43 PM UTC 24 |
Oct 12 07:04:33 PM UTC 24 |
14501495474 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.2115007286 |
|
|
Oct 12 07:03:09 PM UTC 24 |
Oct 12 07:04:34 PM UTC 24 |
2290581654 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.445878836 |
|
|
Oct 12 07:03:22 PM UTC 24 |
Oct 12 07:04:36 PM UTC 24 |
2461251387 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1827373790 |
|
|
Oct 12 07:03:06 PM UTC 24 |
Oct 12 07:04:39 PM UTC 24 |
6360873573 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.3431549710 |
|
|
Oct 12 07:04:04 PM UTC 24 |
Oct 12 07:04:41 PM UTC 24 |
289306922 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.3617279689 |
|
|
Oct 12 07:04:21 PM UTC 24 |
Oct 12 07:04:48 PM UTC 24 |
659544554 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.2221805241 |
|
|
Oct 12 07:04:38 PM UTC 24 |
Oct 12 07:04:51 PM UTC 24 |
201556033 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.1231518483 |
|
|
Oct 12 06:59:38 PM UTC 24 |
Oct 12 07:04:55 PM UTC 24 |
20286613007 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3238088137 |
|
|
Oct 12 07:04:44 PM UTC 24 |
Oct 12 07:04:56 PM UTC 24 |
60647620 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3376070996 |
|
|
Oct 12 07:04:13 PM UTC 24 |
Oct 12 07:04:59 PM UTC 24 |
467634522 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.3690760047 |
|
|
Oct 12 06:58:16 PM UTC 24 |
Oct 12 07:05:06 PM UTC 24 |
39346738149 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1745271743 |
|
|
Oct 12 07:03:07 PM UTC 24 |
Oct 12 07:05:12 PM UTC 24 |
8694279330 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.3038403442 |
|
|
Oct 12 06:57:42 PM UTC 24 |
Oct 12 07:05:15 PM UTC 24 |
11878011824 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.1299597735 |
|
|
Oct 12 06:57:09 PM UTC 24 |
Oct 12 07:05:17 PM UTC 24 |
44411433158 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.3532552376 |
|
|
Oct 12 07:03:50 PM UTC 24 |
Oct 12 07:05:18 PM UTC 24 |
9458511299 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.291896024 |
|
|
Oct 12 07:04:17 PM UTC 24 |
Oct 12 07:05:20 PM UTC 24 |
1865223428 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1044302277 |
|
|
Oct 12 07:03:58 PM UTC 24 |
Oct 12 07:05:30 PM UTC 24 |
6418860141 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.2263630247 |
|
|
Oct 12 07:04:58 PM UTC 24 |
Oct 12 07:05:31 PM UTC 24 |
704802584 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3573888313 |
|
|
Oct 12 07:05:12 PM UTC 24 |
Oct 12 07:05:35 PM UTC 24 |
312840649 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.2700176741 |
|
|
Oct 12 07:05:24 PM UTC 24 |
Oct 12 07:05:36 PM UTC 24 |
54007582 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.2710409708 |
|
|
Oct 12 07:04:19 PM UTC 24 |
Oct 12 07:05:39 PM UTC 24 |
2450303689 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1812832655 |
|
|
Oct 12 07:05:20 PM UTC 24 |
Oct 12 07:05:41 PM UTC 24 |
258204030 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.182690736 |
|
|
Oct 12 07:05:00 PM UTC 24 |
Oct 12 07:05:43 PM UTC 24 |
487384131 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.1918684398 |
|
|
Oct 12 07:03:59 PM UTC 24 |
Oct 12 07:05:46 PM UTC 24 |
2370792398 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.3516090951 |
|
|
Oct 12 07:04:34 PM UTC 24 |
Oct 12 07:05:53 PM UTC 24 |
2152782375 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3703161914 |
|
|
Oct 12 07:05:44 PM UTC 24 |
Oct 12 07:05:58 PM UTC 24 |
211704258 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.352310624 |
|
|
Oct 12 07:05:52 PM UTC 24 |
Oct 12 07:06:02 PM UTC 24 |
46576780 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.3882127368 |
|
|
Oct 12 07:04:54 PM UTC 24 |
Oct 12 07:06:08 PM UTC 24 |
7355915478 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.3498811429 |
|
|
Oct 12 07:05:30 PM UTC 24 |
Oct 12 07:06:08 PM UTC 24 |
908692408 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.1000318790 |
|
|
Oct 12 07:02:41 PM UTC 24 |
Oct 12 07:06:09 PM UTC 24 |
2472603991 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.46532059 |
|
|
Oct 12 07:05:19 PM UTC 24 |
Oct 12 07:06:15 PM UTC 24 |
1344605714 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2966899421 |
|
|
Oct 12 06:58:27 PM UTC 24 |
Oct 12 07:06:29 PM UTC 24 |
33453032127 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.1552332 |
|
|
Oct 12 07:06:23 PM UTC 24 |
Oct 12 07:06:34 PM UTC 24 |
98545278 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1346018110 |
|
|
Oct 12 07:06:00 PM UTC 24 |
Oct 12 07:06:34 PM UTC 24 |
732403264 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.953351724 |
|
|
Oct 12 07:02:29 PM UTC 24 |
Oct 12 07:06:35 PM UTC 24 |
14247466773 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3575328549 |
|
|
Oct 12 07:04:56 PM UTC 24 |
Oct 12 07:06:37 PM UTC 24 |
5933083990 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.2668449619 |
|
|
Oct 12 07:06:00 PM UTC 24 |
Oct 12 07:06:37 PM UTC 24 |
331978529 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.2978379560 |
|
|
Oct 12 07:03:38 PM UTC 24 |
Oct 12 07:06:38 PM UTC 24 |
2082897915 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1863008277 |
|
|
Oct 12 07:06:28 PM UTC 24 |
Oct 12 07:06:40 PM UTC 24 |
40425530 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.4133520533 |
|
|
Oct 12 07:03:38 PM UTC 24 |
Oct 12 07:07:01 PM UTC 24 |
3833273119 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.2550719286 |
|
|
Oct 12 07:00:30 PM UTC 24 |
Oct 12 07:07:02 PM UTC 24 |
34238396998 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.4043112084 |
|
|
Oct 12 07:06:31 PM UTC 24 |
Oct 12 07:07:06 PM UTC 24 |
567244308 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.673076616 |
|
|
Oct 12 07:05:02 PM UTC 24 |
Oct 12 07:07:08 PM UTC 24 |
9798868912 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.2415544764 |
|
|
Oct 12 07:06:58 PM UTC 24 |
Oct 12 07:07:09 PM UTC 24 |
43709383 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.852290294 |
|
|
Oct 12 07:06:59 PM UTC 24 |
Oct 12 07:07:09 PM UTC 24 |
40280494 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.944656160 |
|
|
Oct 12 07:07:01 PM UTC 24 |
Oct 12 07:07:11 PM UTC 24 |
42360590 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.2485655427 |
|
|
Oct 12 07:02:50 PM UTC 24 |
Oct 12 07:07:16 PM UTC 24 |
3119817595 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3872206461 |
|
|
Oct 12 07:04:04 PM UTC 24 |
Oct 12 07:07:16 PM UTC 24 |
23080042439 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2447782610 |
|
|
Oct 12 07:05:54 PM UTC 24 |
Oct 12 07:07:18 PM UTC 24 |
6428054990 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.664356232 |
|
|
Oct 12 07:05:40 PM UTC 24 |
Oct 12 07:07:28 PM UTC 24 |
2429316969 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3558497644 |
|
|
Oct 12 07:00:45 PM UTC 24 |
Oct 12 07:07:29 PM UTC 24 |
3266542682 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1489698674 |
|
|
Oct 12 07:10:11 PM UTC 24 |
Oct 12 07:11:39 PM UTC 24 |
4025271411 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3539630790 |
|
|
Oct 12 07:05:36 PM UTC 24 |
Oct 12 07:07:34 PM UTC 24 |
105404183 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2585286218 |
|
|
Oct 12 07:06:00 PM UTC 24 |
Oct 12 07:07:44 PM UTC 24 |
6164989304 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.708706135 |
|
|
Oct 12 07:07:04 PM UTC 24 |
Oct 12 07:07:46 PM UTC 24 |
430927081 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.2504638523 |
|
|
Oct 12 07:06:22 PM UTC 24 |
Oct 12 07:07:48 PM UTC 24 |
2716249734 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.2147620628 |
|
|
Oct 12 07:01:24 PM UTC 24 |
Oct 12 07:07:51 PM UTC 24 |
27214784908 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.752172075 |
|
|
Oct 12 07:06:08 PM UTC 24 |
Oct 12 07:08:01 PM UTC 24 |
2798430943 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.3477070274 |
|
|
Oct 12 07:07:56 PM UTC 24 |
Oct 12 07:08:07 PM UTC 24 |
52360485 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.552448179 |
|
|
Oct 12 07:02:25 PM UTC 24 |
Oct 12 07:08:11 PM UTC 24 |
34429340135 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.2129611766 |
|
|
Oct 12 07:07:32 PM UTC 24 |
Oct 12 07:08:11 PM UTC 24 |
458855684 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.3800614421 |
|
|
Oct 12 07:02:23 PM UTC 24 |
Oct 12 07:08:12 PM UTC 24 |
23747319337 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.679864372 |
|
|
Oct 12 07:07:03 PM UTC 24 |
Oct 12 07:08:12 PM UTC 24 |
4658718068 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.4086017389 |
|
|
Oct 12 07:06:06 PM UTC 24 |
Oct 12 07:08:15 PM UTC 24 |
8836175281 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2376399467 |
|
|
Oct 12 07:08:08 PM UTC 24 |
Oct 12 07:08:19 PM UTC 24 |
50746626 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3461984575 |
|
|
Oct 12 07:07:41 PM UTC 24 |
Oct 12 07:08:19 PM UTC 24 |
313757774 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.1215202654 |
|
|
Oct 12 07:07:32 PM UTC 24 |
Oct 12 07:08:20 PM UTC 24 |
1148947481 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1096727620 |
|
|
Oct 12 07:01:35 PM UTC 24 |
Oct 12 07:08:20 PM UTC 24 |
26816958329 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.2939869379 |
|
|
Oct 12 07:07:32 PM UTC 24 |
Oct 12 07:08:28 PM UTC 24 |
1384286248 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.34532188 |
|
|
Oct 12 06:59:12 PM UTC 24 |
Oct 12 07:08:37 PM UTC 24 |
10096531880 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.4100123235 |
|
|
Oct 12 07:07:28 PM UTC 24 |
Oct 12 07:08:38 PM UTC 24 |
1590537463 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.1482425744 |
|
|
Oct 12 07:08:23 PM UTC 24 |
Oct 12 07:08:41 PM UTC 24 |
181226467 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.2022631403 |
|
|
Oct 12 07:07:01 PM UTC 24 |
Oct 12 07:08:42 PM UTC 24 |
10478060168 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.488617513 |
|
|
Oct 12 07:08:15 PM UTC 24 |
Oct 12 07:08:50 PM UTC 24 |
871557377 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2360713782 |
|
|
Oct 12 07:06:57 PM UTC 24 |
Oct 12 07:08:51 PM UTC 24 |
524221311 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.1639408858 |
|
|
Oct 12 06:59:58 PM UTC 24 |
Oct 12 07:08:53 PM UTC 24 |
15956800019 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.1910439007 |
|
|
Oct 12 07:03:11 PM UTC 24 |
Oct 12 07:08:54 PM UTC 24 |
24910081285 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1722009929 |
|
|
Oct 12 06:59:54 PM UTC 24 |
Oct 12 07:08:56 PM UTC 24 |
3074047400 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1441264247 |
|
|
Oct 12 07:02:52 PM UTC 24 |
Oct 12 07:08:59 PM UTC 24 |
7127744302 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.3412901337 |
|
|
Oct 12 07:08:33 PM UTC 24 |
Oct 12 07:09:00 PM UTC 24 |
238302407 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3937526884 |
|
|
Oct 12 07:08:43 PM UTC 24 |
Oct 12 07:09:05 PM UTC 24 |
121161821 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.1756513960 |
|
|
Oct 12 07:09:00 PM UTC 24 |
Oct 12 07:09:07 PM UTC 24 |
52015094 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.924706153 |
|
|
Oct 12 07:08:40 PM UTC 24 |
Oct 12 07:09:10 PM UTC 24 |
865654810 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1264677805 |
|
|
Oct 12 07:09:06 PM UTC 24 |
Oct 12 07:09:13 PM UTC 24 |
50015632 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.1235147281 |
|
|
Oct 12 07:08:32 PM UTC 24 |
Oct 12 07:09:19 PM UTC 24 |
410182492 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3315861542 |
|
|
Oct 12 06:57:45 PM UTC 24 |
Oct 12 07:09:29 PM UTC 24 |
14956906699 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3895289976 |
|
|
Oct 12 07:08:09 PM UTC 24 |
Oct 12 07:09:31 PM UTC 24 |
4841487557 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.1240761562 |
|
|
Oct 12 07:09:17 PM UTC 24 |
Oct 12 07:09:33 PM UTC 24 |
152134158 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.1253771249 |
|
|
Oct 12 07:08:42 PM UTC 24 |
Oct 12 07:09:35 PM UTC 24 |
1296273736 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.586826501 |
|
|
Oct 12 07:07:52 PM UTC 24 |
Oct 12 07:09:36 PM UTC 24 |
1509889916 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1887877232 |
|
|
Oct 12 07:09:35 PM UTC 24 |
Oct 12 07:09:48 PM UTC 24 |
214923409 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.572204206 |
|
|
Oct 12 07:09:32 PM UTC 24 |
Oct 12 07:09:50 PM UTC 24 |
132218572 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.494868942 |
|
|
Oct 12 07:08:35 PM UTC 24 |
Oct 12 07:09:51 PM UTC 24 |
3296341966 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.2548865708 |
|
|
Oct 12 07:09:13 PM UTC 24 |
Oct 12 07:09:52 PM UTC 24 |
919041865 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.4041647411 |
|
|
Oct 12 07:09:20 PM UTC 24 |
Oct 12 07:09:55 PM UTC 24 |
2616539291 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.4215936349 |
|
|
Oct 12 07:09:29 PM UTC 24 |
Oct 12 07:09:57 PM UTC 24 |
729528564 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.4231146503 |
|
|
Oct 12 07:09:27 PM UTC 24 |
Oct 12 07:09:59 PM UTC 24 |
324387239 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2476097518 |
|
|
Oct 12 06:50:34 PM UTC 24 |
Oct 12 07:10:00 PM UTC 24 |
58631908683 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.784192806 |
|
|
Oct 12 07:04:30 PM UTC 24 |
Oct 12 07:10:00 PM UTC 24 |
603297343 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.178485206 |
|
|
Oct 12 07:07:31 PM UTC 24 |
Oct 12 07:10:03 PM UTC 24 |
9265512417 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.2276331645 |
|
|
Oct 12 07:06:54 PM UTC 24 |
Oct 12 07:10:05 PM UTC 24 |
2703227262 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1296000831 |
|
|
Oct 12 07:03:42 PM UTC 24 |
Oct 12 07:10:05 PM UTC 24 |
5934837862 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.2942165734 |
|
|
Oct 12 06:57:42 PM UTC 24 |
Oct 12 07:10:08 PM UTC 24 |
21437876471 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2300111958 |
|
|
Oct 12 07:09:58 PM UTC 24 |
Oct 12 07:10:09 PM UTC 24 |
187450308 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2706240142 |
|
|
Oct 12 07:10:00 PM UTC 24 |
Oct 12 07:10:10 PM UTC 24 |
46194504 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.1310647525 |
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|
Oct 12 07:08:43 PM UTC 24 |
Oct 12 07:10:12 PM UTC 24 |
136839830 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3137317141 |
|
|
Oct 12 07:08:06 PM UTC 24 |
Oct 12 07:10:14 PM UTC 24 |
8260882322 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.684243124 |
|
|
Oct 12 07:06:32 PM UTC 24 |
Oct 12 07:10:23 PM UTC 24 |
5659254896 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.161239399 |
|
|
Oct 12 07:10:12 PM UTC 24 |
Oct 12 07:10:26 PM UTC 24 |
96464127 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.2015007198 |
|
|
Oct 12 07:10:12 PM UTC 24 |
Oct 12 07:10:33 PM UTC 24 |
296847314 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.59992094 |
|
|
Oct 12 07:09:13 PM UTC 24 |
Oct 12 07:10:33 PM UTC 24 |
4483269889 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.3435733217 |
|
|
Oct 12 07:03:35 PM UTC 24 |
Oct 12 07:10:34 PM UTC 24 |
11085253247 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3293709312 |
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|
Oct 12 07:01:47 PM UTC 24 |
Oct 12 07:10:39 PM UTC 24 |
10097409610 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2897101395 |
|
|
Oct 12 07:10:32 PM UTC 24 |
Oct 12 07:10:45 PM UTC 24 |
185541671 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.27743948 |
|
|
Oct 12 07:10:23 PM UTC 24 |
Oct 12 07:10:45 PM UTC 24 |
192028021 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.855404943 |
|
|
Oct 12 07:10:24 PM UTC 24 |
Oct 12 07:10:50 PM UTC 24 |
645089077 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3745783661 |
|
|
Oct 12 07:10:44 PM UTC 24 |
Oct 12 07:10:53 PM UTC 24 |
41545195 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.65258335 |
|
|
Oct 12 07:10:26 PM UTC 24 |
Oct 12 07:10:59 PM UTC 24 |
306257380 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.2857767608 |
|
|
Oct 12 07:10:15 PM UTC 24 |
Oct 12 07:11:04 PM UTC 24 |
759323767 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.923247769 |
|
|
Oct 12 07:09:04 PM UTC 24 |
Oct 12 07:11:06 PM UTC 24 |
10218981999 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2480059341 |
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|
Oct 12 06:54:18 PM UTC 24 |
Oct 12 07:11:08 PM UTC 24 |
62385846381 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3821418138 |
|
|
Oct 12 07:04:34 PM UTC 24 |
Oct 12 07:11:11 PM UTC 24 |
5862767825 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3744515252 |
|
|
Oct 12 07:10:27 PM UTC 24 |
Oct 12 07:11:19 PM UTC 24 |
1309326932 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.888751221 |
|
|
Oct 12 07:10:17 PM UTC 24 |
Oct 12 07:11:22 PM UTC 24 |
7215549142 ps |