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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.81 95.32 93.12 95.43 93.85 97.57 99.57


Total test records in report: 2913
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T1797 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.3954251114 Oct 12 06:41:14 PM UTC 24 Oct 12 06:42:57 PM UTC 24 1133262820 ps
T1798 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2033783210 Oct 12 06:42:59 PM UTC 24 Oct 12 06:43:23 PM UTC 24 166885354 ps
T1799 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2548071591 Oct 12 06:43:16 PM UTC 24 Oct 12 06:43:27 PM UTC 24 49169126 ps
T1800 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.1802479363 Oct 12 06:42:38 PM UTC 24 Oct 12 06:43:27 PM UTC 24 527916249 ps
T1801 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.3116854381 Oct 12 06:43:13 PM UTC 24 Oct 12 06:43:28 PM UTC 24 256357546 ps
T1802 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.3822684581 Oct 12 06:42:39 PM UTC 24 Oct 12 06:43:28 PM UTC 24 511561422 ps
T1803 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.2183452500 Oct 12 06:43:00 PM UTC 24 Oct 12 06:43:31 PM UTC 24 659832706 ps
T1804 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.672010549 Oct 12 06:42:36 PM UTC 24 Oct 12 06:43:33 PM UTC 24 4224645661 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.3925117943 Oct 12 06:40:04 PM UTC 24 Oct 12 06:43:47 PM UTC 24 6930919098 ps
T1805 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.209433151 Oct 12 06:39:28 PM UTC 24 Oct 12 06:43:51 PM UTC 24 24974054865 ps
T1806 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.2508557414 Oct 12 06:43:46 PM UTC 24 Oct 12 06:43:59 PM UTC 24 111076472 ps
T1807 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.1039905675 Oct 12 06:36:14 PM UTC 24 Oct 12 06:44:03 PM UTC 24 12173623113 ps
T1808 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.594826198 Oct 12 06:42:49 PM UTC 24 Oct 12 06:44:03 PM UTC 24 2397888809 ps
T1809 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.4144824841 Oct 12 06:42:32 PM UTC 24 Oct 12 06:44:05 PM UTC 24 8270365210 ps
T1810 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1219406949 Oct 12 06:43:10 PM UTC 24 Oct 12 06:44:06 PM UTC 24 558920275 ps
T1811 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.52411651 Oct 12 06:43:51 PM UTC 24 Oct 12 06:44:07 PM UTC 24 91633371 ps
T1812 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.1727873319 Oct 12 06:39:02 PM UTC 24 Oct 12 06:44:07 PM UTC 24 8683495977 ps
T1813 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3281944678 Oct 12 06:43:21 PM UTC 24 Oct 12 06:44:11 PM UTC 24 3260588223 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.1993797026 Oct 12 06:42:47 PM UTC 24 Oct 12 06:44:12 PM UTC 24 2480450811 ps
T516 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.4161381096 Oct 12 06:42:59 PM UTC 24 Oct 12 06:44:14 PM UTC 24 1341717372 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1558528011 Oct 12 06:27:44 PM UTC 24 Oct 12 06:44:18 PM UTC 24 62302783065 ps
T1814 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2028521698 Oct 12 06:42:08 PM UTC 24 Oct 12 06:44:19 PM UTC 24 352696932 ps
T1815 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3553815749 Oct 12 06:39:05 PM UTC 24 Oct 12 06:44:26 PM UTC 24 5140618869 ps
T1816 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.1366791994 Oct 12 06:37:36 PM UTC 24 Oct 12 06:44:30 PM UTC 24 28175808825 ps
T1817 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.2530630107 Oct 12 06:44:10 PM UTC 24 Oct 12 06:44:31 PM UTC 24 173071802 ps
T1818 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1538513290 Oct 12 06:44:15 PM UTC 24 Oct 12 06:44:31 PM UTC 24 287734333 ps
T1819 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.2719769708 Oct 12 06:43:19 PM UTC 24 Oct 12 06:44:32 PM UTC 24 6387320628 ps
T1820 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2573664689 Oct 12 06:44:29 PM UTC 24 Oct 12 06:44:38 PM UTC 24 41020559 ps
T1821 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3722472370 Oct 12 06:43:57 PM UTC 24 Oct 12 06:44:39 PM UTC 24 431861257 ps
T1822 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2944046161 Oct 12 06:43:12 PM UTC 24 Oct 12 06:44:40 PM UTC 24 361112233 ps
T1823 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.154197868 Oct 12 06:44:27 PM UTC 24 Oct 12 06:44:41 PM UTC 24 229503468 ps
T1824 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.3135185618 Oct 12 06:44:53 PM UTC 24 Oct 12 06:45:08 PM UTC 24 119544787 ps
T1825 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.3566618939 Oct 12 06:44:35 PM UTC 24 Oct 12 06:44:45 PM UTC 24 123058760 ps
T1826 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.1937670091 Oct 12 06:43:53 PM UTC 24 Oct 12 06:44:50 PM UTC 24 543487931 ps
T1827 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.431297765 Oct 12 06:44:22 PM UTC 24 Oct 12 06:44:56 PM UTC 24 265861768 ps
T1828 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.854558728 Oct 12 06:36:44 PM UTC 24 Oct 12 06:44:56 PM UTC 24 35544446090 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.914367081 Oct 12 06:37:44 PM UTC 24 Oct 12 06:44:58 PM UTC 24 30239612741 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.628063013 Oct 12 06:39:04 PM UTC 24 Oct 12 06:45:03 PM UTC 24 4953142309 ps
T1829 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.1244411055 Oct 12 06:38:59 PM UTC 24 Oct 12 06:45:04 PM UTC 24 10451865511 ps
T1830 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.2819118896 Oct 12 06:36:41 PM UTC 24 Oct 12 06:45:06 PM UTC 24 44405513911 ps
T1831 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.3286072071 Oct 12 06:43:02 PM UTC 24 Oct 12 06:45:09 PM UTC 24 1651062357 ps
T1832 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.914070053 Oct 12 06:33:36 PM UTC 24 Oct 12 06:45:17 PM UTC 24 38135962195 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.2824035303 Oct 12 06:44:41 PM UTC 24 Oct 12 06:45:19 PM UTC 24 420738949 ps
T677 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3532322656 Oct 12 06:42:12 PM UTC 24 Oct 12 06:45:25 PM UTC 24 2554050925 ps
T1833 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3750043235 Oct 12 06:44:34 PM UTC 24 Oct 12 06:45:27 PM UTC 24 4702085297 ps
T1834 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2424467449 Oct 12 06:45:19 PM UTC 24 Oct 12 06:45:27 PM UTC 24 43508955 ps
T1835 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.3202316048 Oct 12 06:45:02 PM UTC 24 Oct 12 06:45:28 PM UTC 24 357634675 ps
T1836 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.3043091694 Oct 12 06:45:20 PM UTC 24 Oct 12 06:45:29 PM UTC 24 140400922 ps
T1837 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.933104673 Oct 12 06:42:45 PM UTC 24 Oct 12 06:45:30 PM UTC 24 7977009059 ps
T1838 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.544152336 Oct 12 06:45:00 PM UTC 24 Oct 12 06:45:43 PM UTC 24 262455444 ps
T1839 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.436961893 Oct 12 06:44:55 PM UTC 24 Oct 12 06:45:43 PM UTC 24 517143355 ps
T1840 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.817191009 Oct 12 06:44:25 PM UTC 24 Oct 12 06:45:43 PM UTC 24 136776257 ps
T1841 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.573814937 Oct 12 06:45:01 PM UTC 24 Oct 12 06:45:46 PM UTC 24 988975722 ps
T1842 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.466570111 Oct 12 06:45:27 PM UTC 24 Oct 12 06:45:49 PM UTC 24 128323086 ps
T1843 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.3537438994 Oct 12 06:09:33 PM UTC 24 Oct 12 06:45:54 PM UTC 24 15274742074 ps
T1844 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2938612425 Oct 12 06:44:26 PM UTC 24 Oct 12 06:45:56 PM UTC 24 200024859 ps
T1845 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.4113690690 Oct 12 06:40:06 PM UTC 24 Oct 12 06:46:03 PM UTC 24 6277689720 ps
T1846 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.113056644 Oct 12 06:44:36 PM UTC 24 Oct 12 06:46:06 PM UTC 24 5547307675 ps
T1847 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.676583700 Oct 12 06:11:11 PM UTC 24 Oct 12 06:46:07 PM UTC 24 15609219001 ps
T1848 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2493475347 Oct 12 06:35:07 PM UTC 24 Oct 12 06:46:07 PM UTC 24 5716054949 ps
T1849 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.2119104521 Oct 12 06:45:53 PM UTC 24 Oct 12 06:46:13 PM UTC 24 175464747 ps
T1850 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.301774667 Oct 12 06:45:27 PM UTC 24 Oct 12 06:46:17 PM UTC 24 904931414 ps
T1851 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1990735988 Oct 12 06:46:08 PM UTC 24 Oct 12 06:46:18 PM UTC 24 50666521 ps
T1852 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.2059802971 Oct 12 06:46:07 PM UTC 24 Oct 12 06:46:19 PM UTC 24 173342120 ps
T1853 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.2709098117 Oct 12 06:45:49 PM UTC 24 Oct 12 06:46:21 PM UTC 24 295534059 ps
T1854 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.373168612 Oct 12 06:45:52 PM UTC 24 Oct 12 06:46:21 PM UTC 24 169296567 ps
T1855 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.3780756197 Oct 12 06:44:56 PM UTC 24 Oct 12 06:46:24 PM UTC 24 2352479681 ps
T1856 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3100311869 Oct 12 06:45:49 PM UTC 24 Oct 12 06:46:29 PM UTC 24 527447985 ps
T1857 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1754610565 Oct 12 06:44:54 PM UTC 24 Oct 12 06:46:34 PM UTC 24 5047482992 ps
T1858 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.1927418813 Oct 12 06:45:52 PM UTC 24 Oct 12 06:46:45 PM UTC 24 1262316775 ps
T1859 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.845913410 Oct 12 06:42:08 PM UTC 24 Oct 12 06:46:46 PM UTC 24 3208817908 ps
T1860 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.2742218969 Oct 12 06:41:44 PM UTC 24 Oct 12 06:46:46 PM UTC 24 20636677271 ps
T526 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.3205814349 Oct 12 06:45:38 PM UTC 24 Oct 12 06:46:47 PM UTC 24 1082527069 ps
T1861 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1712398041 Oct 12 06:45:20 PM UTC 24 Oct 12 06:46:50 PM UTC 24 8778144306 ps
T538 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.3240175846 Oct 12 06:44:25 PM UTC 24 Oct 12 06:46:50 PM UTC 24 1463877250 ps
T1862 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.2394444960 Oct 12 06:46:38 PM UTC 24 Oct 12 06:46:52 PM UTC 24 309078799 ps
T1863 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.4227721201 Oct 12 06:46:43 PM UTC 24 Oct 12 06:46:54 PM UTC 24 47778041 ps
T1864 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3638108822 Oct 12 06:46:45 PM UTC 24 Oct 12 06:46:56 PM UTC 24 51653484 ps
T1865 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.3344982166 Oct 12 06:46:28 PM UTC 24 Oct 12 06:46:59 PM UTC 24 229583909 ps
T1866 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1828987241 Oct 12 06:45:26 PM UTC 24 Oct 12 06:47:04 PM UTC 24 6735863950 ps
T1867 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2916649820 Oct 12 06:46:40 PM UTC 24 Oct 12 06:47:07 PM UTC 24 187381094 ps
T1868 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.709640246 Oct 12 06:47:08 PM UTC 24 Oct 12 06:47:16 PM UTC 24 47738262 ps
T1869 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2293432781 Oct 12 06:46:18 PM UTC 24 Oct 12 06:47:16 PM UTC 24 3639091098 ps
T1870 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.2840546755 Oct 12 06:46:41 PM UTC 24 Oct 12 06:47:17 PM UTC 24 320512522 ps
T1871 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3935275114 Oct 12 06:47:10 PM UTC 24 Oct 12 06:47:19 PM UTC 24 50748612 ps
T1872 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1742267661 Oct 12 06:41:19 PM UTC 24 Oct 12 06:47:19 PM UTC 24 6892586818 ps
T1873 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.2742989313 Oct 12 06:43:51 PM UTC 24 Oct 12 06:47:21 PM UTC 24 21958180624 ps
T1874 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.2102176648 Oct 12 06:46:19 PM UTC 24 Oct 12 06:47:27 PM UTC 24 2061216309 ps
T1875 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1043718874 Oct 12 06:29:15 PM UTC 24 Oct 12 06:47:31 PM UTC 24 60578354261 ps
T1876 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1496778933 Oct 12 06:46:33 PM UTC 24 Oct 12 06:47:36 PM UTC 24 1125237436 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3930249893 Oct 12 06:40:00 PM UTC 24 Oct 12 06:47:41 PM UTC 24 3079557809 ps
T1877 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.279841348 Oct 12 06:47:12 PM UTC 24 Oct 12 06:47:44 PM UTC 24 389382133 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2628591409 Oct 12 06:37:50 PM UTC 24 Oct 12 06:47:46 PM UTC 24 6066604949 ps
T1878 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.3961694103 Oct 12 06:44:24 PM UTC 24 Oct 12 06:47:53 PM UTC 24 5870024726 ps
T1879 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.758326948 Oct 12 06:46:54 PM UTC 24 Oct 12 06:48:00 PM UTC 24 127034499 ps
T1880 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.2939448149 Oct 12 06:47:51 PM UTC 24 Oct 12 06:48:01 PM UTC 24 50510829 ps
T1881 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2327714607 Oct 12 06:47:56 PM UTC 24 Oct 12 06:48:06 PM UTC 24 54739304 ps
T1882 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.1822051466 Oct 12 06:47:26 PM UTC 24 Oct 12 06:48:07 PM UTC 24 1311808817 ps
T1883 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2648022088 Oct 12 06:47:10 PM UTC 24 Oct 12 06:48:09 PM UTC 24 3803815043 ps
T1884 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.4237100296 Oct 12 06:47:07 PM UTC 24 Oct 12 06:48:11 PM UTC 24 5154236955 ps
T1885 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.2759570354 Oct 12 06:47:14 PM UTC 24 Oct 12 06:48:13 PM UTC 24 1297365032 ps
T1886 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.3866132442 Oct 12 06:46:10 PM UTC 24 Oct 12 06:48:13 PM UTC 24 9046604298 ps
T1887 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3701454976 Oct 12 06:47:40 PM UTC 24 Oct 12 06:48:16 PM UTC 24 317620360 ps
T1888 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.2004339675 Oct 12 06:47:18 PM UTC 24 Oct 12 06:48:29 PM UTC 24 882561766 ps
T1889 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.2741952483 Oct 12 06:48:10 PM UTC 24 Oct 12 06:48:33 PM UTC 24 164710962 ps
T1890 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1408004513 Oct 12 06:45:03 PM UTC 24 Oct 12 06:48:35 PM UTC 24 4607805946 ps
T1891 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.1271924855 Oct 12 06:42:43 PM UTC 24 Oct 12 06:48:43 PM UTC 24 34937439575 ps
T1892 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.4028737074 Oct 12 06:47:41 PM UTC 24 Oct 12 06:48:47 PM UTC 24 1275349563 ps
T1893 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1406361419 Oct 12 06:48:30 PM UTC 24 Oct 12 06:48:52 PM UTC 24 280907063 ps
T1894 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.17674908 Oct 12 06:45:28 PM UTC 24 Oct 12 06:48:57 PM UTC 24 21608081775 ps
T1895 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.3856996999 Oct 12 06:48:32 PM UTC 24 Oct 12 06:49:03 PM UTC 24 294520379 ps
T1896 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.774793352 Oct 12 06:48:56 PM UTC 24 Oct 12 06:49:09 PM UTC 24 157031590 ps
T1897 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.4104870120 Oct 12 06:47:30 PM UTC 24 Oct 12 06:49:14 PM UTC 24 2124164276 ps
T1898 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.2599828552 Oct 12 06:48:23 PM UTC 24 Oct 12 06:49:15 PM UTC 24 725677594 ps
T1899 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.732959306 Oct 12 06:49:07 PM UTC 24 Oct 12 06:49:17 PM UTC 24 45129489 ps
T1900 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.729608597 Oct 12 06:48:34 PM UTC 24 Oct 12 06:49:17 PM UTC 24 252419952 ps
T1901 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.1123673110 Oct 12 06:46:28 PM UTC 24 Oct 12 06:49:19 PM UTC 24 18832814275 ps
T1902 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.784873380 Oct 12 06:15:06 PM UTC 24 Oct 12 06:49:25 PM UTC 24 15628064052 ps
T1903 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3857514481 Oct 12 06:48:32 PM UTC 24 Oct 12 06:49:30 PM UTC 24 1068603263 ps
T1904 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.145124705 Oct 12 06:45:32 PM UTC 24 Oct 12 06:49:30 PM UTC 24 13101398898 ps
T1905 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1482942286 Oct 12 06:47:58 PM UTC 24 Oct 12 06:49:33 PM UTC 24 10186052044 ps
T1906 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.258906741 Oct 12 06:49:26 PM UTC 24 Oct 12 06:49:38 PM UTC 24 86312392 ps
T1907 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.3311123323 Oct 12 06:49:20 PM UTC 24 Oct 12 06:49:39 PM UTC 24 105950632 ps
T1908 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.715785883 Oct 12 06:41:37 PM UTC 24 Oct 12 06:49:45 PM UTC 24 46075051285 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.610083528 Oct 12 06:26:32 PM UTC 24 Oct 12 06:49:49 PM UTC 24 81395979238 ps
T1909 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.1284224903 Oct 12 06:49:42 PM UTC 24 Oct 12 06:49:51 PM UTC 24 134372901 ps
T1910 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.2291241345 Oct 12 06:48:21 PM UTC 24 Oct 12 06:49:52 PM UTC 24 5162729519 ps
T1911 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3438149513 Oct 12 06:48:05 PM UTC 24 Oct 12 06:49:52 PM UTC 24 6169504001 ps
T1912 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.1842056271 Oct 12 06:45:08 PM UTC 24 Oct 12 06:49:57 PM UTC 24 8876082787 ps
T1913 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3733015498 Oct 12 06:45:53 PM UTC 24 Oct 12 06:50:07 PM UTC 24 664128498 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.1460969633 Oct 12 06:38:07 PM UTC 24 Oct 12 06:50:08 PM UTC 24 18833426073 ps
T1914 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.4077488713 Oct 12 06:42:44 PM UTC 24 Oct 12 06:50:10 PM UTC 24 27766853117 ps
T1915 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.811125090 Oct 12 06:50:01 PM UTC 24 Oct 12 06:50:10 PM UTC 24 48427960 ps
T1916 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.237975316 Oct 12 06:43:08 PM UTC 24 Oct 12 06:50:18 PM UTC 24 2653257389 ps
T1917 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.69771195 Oct 12 06:50:08 PM UTC 24 Oct 12 06:50:18 PM UTC 24 47732360 ps
T1918 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.4235375108 Oct 12 06:49:48 PM UTC 24 Oct 12 06:50:19 PM UTC 24 223107688 ps
T1919 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.3140070017 Oct 12 06:49:39 PM UTC 24 Oct 12 06:50:20 PM UTC 24 535232547 ps
T1920 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1722081202 Oct 12 06:49:17 PM UTC 24 Oct 12 06:50:22 PM UTC 24 3339384885 ps
T1921 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2077342880 Oct 12 06:49:50 PM UTC 24 Oct 12 06:50:40 PM UTC 24 1285843348 ps
T1922 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2650448547 Oct 12 06:47:43 PM UTC 24 Oct 12 06:50:47 PM UTC 24 4795176574 ps
T1923 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.790481351 Oct 12 06:49:36 PM UTC 24 Oct 12 06:50:48 PM UTC 24 957135650 ps
T1924 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.24733028 Oct 12 06:50:42 PM UTC 24 Oct 12 06:50:52 PM UTC 24 35334434 ps
T1925 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.784516773 Oct 12 06:50:40 PM UTC 24 Oct 12 06:51:11 PM UTC 24 208641269 ps
T1926 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.793012473 Oct 12 06:49:11 PM UTC 24 Oct 12 06:51:14 PM UTC 24 7641111196 ps
T1927 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.2255603444 Oct 12 06:50:32 PM UTC 24 Oct 12 06:51:14 PM UTC 24 809873062 ps
T1928 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.3819968607 Oct 12 06:50:42 PM UTC 24 Oct 12 06:51:15 PM UTC 24 270249595 ps
T1929 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.1716721231 Oct 12 06:50:12 PM UTC 24 Oct 12 06:51:18 PM UTC 24 540448352 ps
T1930 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3703665162 Oct 12 06:44:49 PM UTC 24 Oct 12 06:51:19 PM UTC 24 22426711516 ps
T1931 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1736747509 Oct 12 06:51:09 PM UTC 24 Oct 12 06:51:20 PM UTC 24 252095507 ps
T1932 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3168255058 Oct 12 06:51:13 PM UTC 24 Oct 12 06:51:23 PM UTC 24 37772880 ps
T1933 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.1809630612 Oct 12 06:50:15 PM UTC 24 Oct 12 06:51:28 PM UTC 24 1781852210 ps
T1934 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3182130018 Oct 12 06:49:53 PM UTC 24 Oct 12 06:51:30 PM UTC 24 319858825 ps
T1935 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.4291023566 Oct 12 06:47:42 PM UTC 24 Oct 12 06:51:43 PM UTC 24 711319406 ps
T1936 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.1510936163 Oct 12 06:43:53 PM UTC 24 Oct 12 06:51:50 PM UTC 24 32997167146 ps
T1937 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3561661896 Oct 12 06:50:13 PM UTC 24 Oct 12 06:51:56 PM UTC 24 8588712381 ps
T1938 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.3259373360 Oct 12 06:51:52 PM UTC 24 Oct 12 06:52:10 PM UTC 24 120329638 ps
T1939 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.1481501507 Oct 12 06:51:35 PM UTC 24 Oct 12 06:52:13 PM UTC 24 394089190 ps
T1940 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1858268682 Oct 12 06:50:14 PM UTC 24 Oct 12 06:52:21 PM UTC 24 6162210049 ps
T1941 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.2045518459 Oct 12 06:49:56 PM UTC 24 Oct 12 06:52:22 PM UTC 24 1652411935 ps
T1942 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.2612727915 Oct 12 06:50:33 PM UTC 24 Oct 12 06:52:23 PM UTC 24 2693155919 ps
T1943 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2055880426 Oct 12 06:52:14 PM UTC 24 Oct 12 06:52:24 PM UTC 24 61920014 ps
T1944 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1513799746 Oct 12 06:51:40 PM UTC 24 Oct 12 06:52:27 PM UTC 24 440806122 ps
T1945 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.2732029195 Oct 12 06:52:08 PM UTC 24 Oct 12 06:52:36 PM UTC 24 416426905 ps
T1946 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.3075271535 Oct 12 06:51:53 PM UTC 24 Oct 12 06:52:46 PM UTC 24 1327897669 ps
T1947 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.3529323461 Oct 12 06:51:34 PM UTC 24 Oct 12 06:52:49 PM UTC 24 7207927866 ps
T1948 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.4189740003 Oct 12 06:48:38 PM UTC 24 Oct 12 06:52:50 PM UTC 24 7080436806 ps
T1949 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.2408597064 Oct 12 06:52:46 PM UTC 24 Oct 12 06:52:58 PM UTC 24 138480451 ps
T1950 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3544043579 Oct 12 06:52:48 PM UTC 24 Oct 12 06:52:59 PM UTC 24 39533855 ps
T1951 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2150170137 Oct 12 06:46:08 PM UTC 24 Oct 12 06:52:59 PM UTC 24 6717001519 ps
T1952 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.636673711 Oct 12 06:49:52 PM UTC 24 Oct 12 06:53:01 PM UTC 24 2563138890 ps
T1953 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.2988203925 Oct 12 06:50:20 PM UTC 24 Oct 12 06:53:01 PM UTC 24 16531797146 ps
T1954 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2350985214 Oct 12 06:46:06 PM UTC 24 Oct 12 06:53:02 PM UTC 24 12710037835 ps
T1955 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.2883519143 Oct 12 06:51:44 PM UTC 24 Oct 12 06:53:16 PM UTC 24 2396271517 ps
T1956 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3900718104 Oct 12 06:51:35 PM UTC 24 Oct 12 06:53:18 PM UTC 24 4501178634 ps
T1957 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.3834096248 Oct 12 06:46:30 PM UTC 24 Oct 12 06:53:20 PM UTC 24 28159123892 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1643522672 Oct 12 06:50:00 PM UTC 24 Oct 12 06:53:23 PM UTC 24 3900365738 ps
T1958 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2523198503 Oct 12 05:52:24 PM UTC 24 Oct 12 06:54:32 PM UTC 24 28339170936 ps
T1959 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.3366134377 Oct 12 06:46:52 PM UTC 24 Oct 12 06:53:25 PM UTC 24 5216325773 ps
T1960 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.1764071776 Oct 12 06:47:42 PM UTC 24 Oct 12 06:53:28 PM UTC 24 9473839907 ps
T1961 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.179114967 Oct 12 06:53:00 PM UTC 24 Oct 12 06:53:34 PM UTC 24 265196394 ps
T1962 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2389068569 Oct 12 06:53:24 PM UTC 24 Oct 12 06:53:34 PM UTC 24 117771079 ps
T1963 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.630700645 Oct 12 06:53:24 PM UTC 24 Oct 12 06:53:36 PM UTC 24 48461496 ps
T1964 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.2759185287 Oct 12 06:49:37 PM UTC 24 Oct 12 06:53:37 PM UTC 24 18978079544 ps
T1965 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2015495897 Oct 12 06:53:26 PM UTC 24 Oct 12 06:53:45 PM UTC 24 377604281 ps
T1966 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.856096240 Oct 12 06:49:30 PM UTC 24 Oct 12 06:53:46 PM UTC 24 28238960480 ps
T1967 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3854726073 Oct 12 06:34:19 PM UTC 24 Oct 12 06:53:48 PM UTC 24 30085362971 ps
T1968 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1890290368 Oct 12 06:52:51 PM UTC 24 Oct 12 06:53:55 PM UTC 24 4569951040 ps
T1969 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.898269085 Oct 12 06:53:49 PM UTC 24 Oct 12 06:53:57 PM UTC 24 41667783 ps
T1970 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.3818878740 Oct 12 06:53:10 PM UTC 24 Oct 12 06:53:57 PM UTC 24 460693666 ps
T1971 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3947280799 Oct 12 06:53:51 PM UTC 24 Oct 12 06:54:01 PM UTC 24 52808603 ps
T1972 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.3706321017 Oct 12 06:17:10 PM UTC 24 Oct 12 06:54:03 PM UTC 24 16133759976 ps
T1973 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2077746257 Oct 12 06:41:12 PM UTC 24 Oct 12 06:54:11 PM UTC 24 6388810702 ps
T1974 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.3637944258 Oct 12 06:52:48 PM UTC 24 Oct 12 06:54:14 PM UTC 24 6151770062 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.1077908000 Oct 12 06:53:21 PM UTC 24 Oct 12 06:54:19 PM UTC 24 1480955267 ps
T1975 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.694014813 Oct 12 06:53:22 PM UTC 24 Oct 12 06:54:24 PM UTC 24 1933985253 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2917780504 Oct 12 06:41:49 PM UTC 24 Oct 12 06:54:27 PM UTC 24 47678118214 ps
T1976 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.1681391286 Oct 12 06:53:59 PM UTC 24 Oct 12 06:54:37 PM UTC 24 467556576 ps
T1977 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.597003500 Oct 12 06:54:27 PM UTC 24 Oct 12 06:54:47 PM UTC 24 168790332 ps
T1978 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.775380466 Oct 12 06:53:38 PM UTC 24 Oct 12 06:54:48 PM UTC 24 928462688 ps
T1979 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.2128699778 Oct 12 06:54:00 PM UTC 24 Oct 12 06:54:52 PM UTC 24 393805818 ps
T1980 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.3483915744 Oct 12 06:47:15 PM UTC 24 Oct 12 06:54:54 PM UTC 24 32586422689 ps
T1981 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.543652393 Oct 12 06:54:20 PM UTC 24 Oct 12 06:55:01 PM UTC 24 349148282 ps
T1982 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.439252189 Oct 12 06:54:21 PM UTC 24 Oct 12 06:55:04 PM UTC 24 1605029615 ps
T1983 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.4087666518 Oct 12 06:54:52 PM UTC 24 Oct 12 06:55:04 PM UTC 24 176873227 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2762400981 Oct 12 06:36:48 PM UTC 24 Oct 12 06:55:05 PM UTC 24 74657479282 ps
T1984 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2936625777 Oct 12 06:54:55 PM UTC 24 Oct 12 06:55:06 PM UTC 24 55544288 ps
T1985 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.6006522 Oct 12 06:54:08 PM UTC 24 Oct 12 06:55:07 PM UTC 24 3126217400 ps
T1986 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3944086391 Oct 12 06:53:43 PM UTC 24 Oct 12 06:55:12 PM UTC 24 1155897117 ps
T1987 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3564677880 Oct 12 06:53:58 PM UTC 24 Oct 12 06:55:15 PM UTC 24 4249639451 ps
T1988 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.1127371765 Oct 12 06:53:56 PM UTC 24 Oct 12 06:55:20 PM UTC 24 6365582077 ps
T1989 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.1119571608 Oct 12 06:54:26 PM UTC 24 Oct 12 06:55:20 PM UTC 24 1081500340 ps
T1990 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.2786315633 Oct 12 06:52:37 PM UTC 24 Oct 12 06:55:27 PM UTC 24 4849638732 ps
T1991 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.307942892 Oct 12 06:54:12 PM UTC 24 Oct 12 06:55:30 PM UTC 24 934488388 ps
T1992 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.133725764 Oct 12 06:55:11 PM UTC 24 Oct 12 06:55:39 PM UTC 24 287829084 ps
T1993 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.2083780205 Oct 12 06:55:27 PM UTC 24 Oct 12 06:55:43 PM UTC 24 133048554 ps
T1994 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.952118091 Oct 12 06:45:13 PM UTC 24 Oct 12 06:55:54 PM UTC 24 12771519441 ps
T1995 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.42164578 Oct 12 06:55:29 PM UTC 24 Oct 12 06:55:55 PM UTC 24 166502437 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1846016159 Oct 12 06:46:46 PM UTC 24 Oct 12 06:55:58 PM UTC 24 7351935392 ps
T1996 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.1628921913 Oct 12 06:55:50 PM UTC 24 Oct 12 06:56:00 PM UTC 24 50696307 ps
T1997 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.1415135051 Oct 12 06:55:28 PM UTC 24 Oct 12 06:56:01 PM UTC 24 264535575 ps
T1998 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.629086186 Oct 12 06:55:55 PM UTC 24 Oct 12 06:56:02 PM UTC 24 49668294 ps
T1999 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3896204755 Oct 12 06:54:55 PM UTC 24 Oct 12 06:56:02 PM UTC 24 6354830052 ps
T2000 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.488863551 Oct 12 06:55:28 PM UTC 24 Oct 12 06:56:09 PM UTC 24 392586135 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.3876576262 Oct 12 06:48:53 PM UTC 24 Oct 12 06:56:09 PM UTC 24 11898927608 ps
T2001 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2405173939 Oct 12 06:55:22 PM UTC 24 Oct 12 06:56:13 PM UTC 24 1259765359 ps
T679 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.1893700111 Oct 12 06:51:02 PM UTC 24 Oct 12 06:56:13 PM UTC 24 7756899512 ps
T2002 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2945444877 Oct 12 06:55:42 PM UTC 24 Oct 12 06:56:15 PM UTC 24 95464806 ps
T2003 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1473448618 Oct 12 06:54:58 PM UTC 24 Oct 12 06:56:18 PM UTC 24 3598502251 ps
T2004 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2004787576 Oct 12 06:44:40 PM UTC 24 Oct 12 06:56:19 PM UTC 24 62791860248 ps
T2005 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.688207899 Oct 12 06:54:09 PM UTC 24 Oct 12 06:56:28 PM UTC 24 12945223041 ps
T2006 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.696254220 Oct 12 06:55:09 PM UTC 24 Oct 12 06:56:34 PM UTC 24 2387656067 ps
T2007 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.152092570 Oct 12 06:51:42 PM UTC 24 Oct 12 06:56:34 PM UTC 24 31908715481 ps
T2008 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.3280060778 Oct 12 06:56:17 PM UTC 24 Oct 12 06:56:37 PM UTC 24 170777424 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.3682071753 Oct 12 05:54:27 PM UTC 24 Oct 12 06:56:40 PM UTC 24 30354890728 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3370009261 Oct 12 06:40:45 PM UTC 24 Oct 12 06:56:42 PM UTC 24 66776886868 ps
T2009 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3846810340 Oct 12 06:52:46 PM UTC 24 Oct 12 06:56:44 PM UTC 24 5428997292 ps
T2010 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.2514982807 Oct 12 06:56:30 PM UTC 24 Oct 12 06:56:47 PM UTC 24 162132648 ps
T2011 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3379979185 Oct 12 06:56:34 PM UTC 24 Oct 12 06:56:48 PM UTC 24 70676320 ps
T2012 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.2246195704 Oct 12 06:56:16 PM UTC 24 Oct 12 06:56:53 PM UTC 24 486964710 ps
T2013 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2986489580 Oct 12 06:56:52 PM UTC 24 Oct 12 06:57:05 PM UTC 24 168170509 ps
T2014 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3423936156 Oct 12 06:56:56 PM UTC 24 Oct 12 06:57:06 PM UTC 24 50739855 ps
T2015 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.3784127016 Oct 12 06:56:25 PM UTC 24 Oct 12 06:57:10 PM UTC 24 1585636702 ps
T2016 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.3767614880 Oct 12 06:50:31 PM UTC 24 Oct 12 06:57:18 PM UTC 24 26902190994 ps
T2017 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3425432211 Oct 12 06:47:44 PM UTC 24 Oct 12 06:57:19 PM UTC 24 12464146503 ps
T2018 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.713893752 Oct 12 06:56:32 PM UTC 24 Oct 12 06:57:23 PM UTC 24 1073311116 ps
T2019 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.2689766043 Oct 12 06:56:22 PM UTC 24 Oct 12 06:57:23 PM UTC 24 801964094 ps
T2020 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1926951358 Oct 12 06:56:06 PM UTC 24 Oct 12 06:57:35 PM UTC 24 6505568171 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1503185097 Oct 12 06:53:21 PM UTC 24 Oct 12 06:57:40 PM UTC 24 13581628476 ps
T2021 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.1638986821 Oct 12 06:50:44 PM UTC 24 Oct 12 06:57:42 PM UTC 24 12051008487 ps
T2022 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.3454665163 Oct 12 06:55:30 PM UTC 24 Oct 12 06:57:43 PM UTC 24 3834485485 ps
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