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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.81 95.32 93.12 95.43 93.85 97.57 99.57


Total test records in report: 2913
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T2515 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.1632274232 Oct 12 07:22:23 PM UTC 24 Oct 12 07:23:37 PM UTC 24 7601869489 ps
T2516 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.3901356377 Oct 12 07:22:25 PM UTC 24 Oct 12 07:23:40 PM UTC 24 1967107395 ps
T2517 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.1487746280 Oct 12 07:21:59 PM UTC 24 Oct 12 07:23:42 PM UTC 24 2593492423 ps
T2518 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1613387759 Oct 12 07:23:24 PM UTC 24 Oct 12 07:23:43 PM UTC 24 176730161 ps
T2519 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.4140087719 Oct 12 07:23:05 PM UTC 24 Oct 12 07:23:43 PM UTC 24 602748513 ps
T2520 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2770648166 Oct 12 07:22:56 PM UTC 24 Oct 12 07:23:45 PM UTC 24 866323988 ps
T2521 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.3946908263 Oct 12 07:16:54 PM UTC 24 Oct 12 07:23:45 PM UTC 24 12071078552 ps
T2522 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.2661388063 Oct 12 07:18:39 PM UTC 24 Oct 12 07:23:48 PM UTC 24 8526148310 ps
T2523 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1666479006 Oct 12 07:22:26 PM UTC 24 Oct 12 07:23:52 PM UTC 24 5299403193 ps
T2524 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.3299410477 Oct 12 07:23:39 PM UTC 24 Oct 12 07:23:52 PM UTC 24 67291066 ps
T2525 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.902673993 Oct 12 07:23:42 PM UTC 24 Oct 12 07:23:57 PM UTC 24 70864196 ps
T2526 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.2542190800 Oct 12 07:23:40 PM UTC 24 Oct 12 07:24:11 PM UTC 24 1029282954 ps
T2527 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3828549286 Oct 12 07:23:57 PM UTC 24 Oct 12 07:24:11 PM UTC 24 192524903 ps
T2528 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1613606421 Oct 12 07:19:51 PM UTC 24 Oct 12 07:24:12 PM UTC 24 7177134447 ps
T2529 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2706546266 Oct 12 07:24:03 PM UTC 24 Oct 12 07:24:12 PM UTC 24 48117983 ps
T2530 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.258951324 Oct 12 07:23:11 PM UTC 24 Oct 12 07:24:14 PM UTC 24 6448209854 ps
T2531 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3567351306 Oct 12 07:15:11 PM UTC 24 Oct 12 07:24:16 PM UTC 24 12548975042 ps
T2532 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.2082042922 Oct 12 07:24:06 PM UTC 24 Oct 12 07:24:17 PM UTC 24 39346918 ps
T2533 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.21057218 Oct 12 07:23:43 PM UTC 24 Oct 12 07:24:18 PM UTC 24 222478254 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.415973516 Oct 12 07:18:43 PM UTC 24 Oct 12 07:24:26 PM UTC 24 4582642700 ps
T2534 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.1802276344 Oct 12 07:23:27 PM UTC 24 Oct 12 07:24:33 PM UTC 24 589607902 ps
T2535 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.3607289159 Oct 12 07:24:12 PM UTC 24 Oct 12 07:24:37 PM UTC 24 291253166 ps
T2536 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.3636889348 Oct 12 07:22:39 PM UTC 24 Oct 12 07:24:40 PM UTC 24 7074747616 ps
T2537 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1917014121 Oct 12 07:20:57 PM UTC 24 Oct 12 07:24:46 PM UTC 24 974009717 ps
T2538 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.4049241018 Oct 12 07:24:07 PM UTC 24 Oct 12 07:24:52 PM UTC 24 476221214 ps
T2539 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.4118728777 Oct 12 07:24:50 PM UTC 24 Oct 12 07:24:58 PM UTC 24 48083273 ps
T2540 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.476300329 Oct 12 07:14:54 PM UTC 24 Oct 12 07:24:59 PM UTC 24 15358729917 ps
T2541 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.937042406 Oct 12 07:20:49 PM UTC 24 Oct 12 07:25:01 PM UTC 24 3025921717 ps
T2542 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.349440243 Oct 12 07:26:03 PM UTC 24 Oct 12 07:26:42 PM UTC 24 388922694 ps
T2543 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3426681923 Oct 12 07:24:37 PM UTC 24 Oct 12 07:25:06 PM UTC 24 195971005 ps
T2544 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.1950996785 Oct 12 07:19:33 PM UTC 24 Oct 12 07:25:06 PM UTC 24 9264357585 ps
T2545 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.4040487529 Oct 12 07:24:34 PM UTC 24 Oct 12 07:25:07 PM UTC 24 298412796 ps
T2546 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3934182385 Oct 12 07:24:58 PM UTC 24 Oct 12 07:25:07 PM UTC 24 56407223 ps
T2547 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3623799453 Oct 12 07:19:24 PM UTC 24 Oct 12 07:25:07 PM UTC 24 23936297431 ps
T2548 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1245314725 Oct 12 07:24:03 PM UTC 24 Oct 12 07:25:11 PM UTC 24 5209174295 ps
T2549 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.2261128330 Oct 12 07:24:35 PM UTC 24 Oct 12 07:25:13 PM UTC 24 918842291 ps
T2550 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.530321160 Oct 12 07:13:32 PM UTC 24 Oct 12 07:25:15 PM UTC 24 6827123868 ps
T2551 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2584426429 Oct 12 07:22:14 PM UTC 24 Oct 12 07:25:17 PM UTC 24 567709347 ps
T2552 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.1891208279 Oct 12 07:24:36 PM UTC 24 Oct 12 07:25:18 PM UTC 24 413350712 ps
T2553 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.899526579 Oct 12 07:24:05 PM UTC 24 Oct 12 07:25:22 PM UTC 24 5236474683 ps
T2554 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1770748401 Oct 12 07:23:11 PM UTC 24 Oct 12 07:25:25 PM UTC 24 6541484258 ps
T2555 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.2146017268 Oct 12 07:22:10 PM UTC 24 Oct 12 07:25:35 PM UTC 24 2581973134 ps
T2556 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3293074314 Oct 12 07:18:40 PM UTC 24 Oct 12 07:25:36 PM UTC 24 9005628020 ps
T2557 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.3533825133 Oct 12 07:25:29 PM UTC 24 Oct 12 07:25:38 PM UTC 24 69710199 ps
T2558 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2631385187 Oct 12 07:25:27 PM UTC 24 Oct 12 07:25:42 PM UTC 24 317484236 ps
T2559 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.3365675176 Oct 12 07:25:15 PM UTC 24 Oct 12 07:25:42 PM UTC 24 257868551 ps
T2560 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.529234864 Oct 12 07:25:36 PM UTC 24 Oct 12 07:25:47 PM UTC 24 196213209 ps
T2561 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.3743859520 Oct 12 07:25:23 PM UTC 24 Oct 12 07:25:47 PM UTC 24 555767498 ps
T2562 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1180349253 Oct 12 07:25:41 PM UTC 24 Oct 12 07:25:51 PM UTC 24 46314406 ps
T2563 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3073924686 Oct 12 07:25:45 PM UTC 24 Oct 12 07:25:53 PM UTC 24 54440133 ps
T2564 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.953343969 Oct 12 07:19:51 PM UTC 24 Oct 12 07:26:01 PM UTC 24 3369027133 ps
T2565 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.3958797885 Oct 12 07:25:31 PM UTC 24 Oct 12 07:26:04 PM UTC 24 693012407 ps
T2566 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.3130973947 Oct 12 07:19:21 PM UTC 24 Oct 12 07:26:07 PM UTC 24 23410681286 ps
T2567 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.252950493 Oct 12 07:22:19 PM UTC 24 Oct 12 07:26:10 PM UTC 24 919779482 ps
T2568 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.1789697961 Oct 12 07:22:58 PM UTC 24 Oct 12 07:26:12 PM UTC 24 2000368904 ps
T2569 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2583627372 Oct 12 07:23:40 PM UTC 24 Oct 12 07:26:14 PM UTC 24 3333516011 ps
T2570 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.4258506234 Oct 12 07:25:22 PM UTC 24 Oct 12 07:26:15 PM UTC 24 3586908723 ps
T2571 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.92790430 Oct 12 07:26:15 PM UTC 24 Oct 12 07:26:27 PM UTC 24 138699505 ps
T2572 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.244879360 Oct 12 07:25:06 PM UTC 24 Oct 12 07:26:32 PM UTC 24 2251518098 ps
T2573 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2077523541 Oct 12 07:25:05 PM UTC 24 Oct 12 07:26:34 PM UTC 24 6367740249 ps
T2574 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.623127067 Oct 12 07:25:01 PM UTC 24 Oct 12 07:26:37 PM UTC 24 8922232594 ps
T2575 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.649204022 Oct 12 07:25:28 PM UTC 24 Oct 12 07:26:40 PM UTC 24 2582318292 ps
T2576 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.1373376568 Oct 12 07:26:10 PM UTC 24 Oct 12 07:26:42 PM UTC 24 767164098 ps
T2577 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.2831242293 Oct 12 07:25:33 PM UTC 24 Oct 12 07:26:44 PM UTC 24 1829815800 ps
T2578 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.2309586270 Oct 12 07:26:16 PM UTC 24 Oct 12 07:26:46 PM UTC 24 605535588 ps
T2579 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.3852081759 Oct 12 07:24:08 PM UTC 24 Oct 12 07:26:50 PM UTC 24 13572232956 ps
T2580 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1375013230 Oct 12 07:11:47 PM UTC 24 Oct 12 07:26:51 PM UTC 24 21863385015 ps
T2581 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.1799574588 Oct 12 07:26:40 PM UTC 24 Oct 12 07:26:54 PM UTC 24 231314759 ps
T2582 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.2269191121 Oct 12 07:22:16 PM UTC 24 Oct 12 07:26:54 PM UTC 24 4345165913 ps
T2583 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3855898040 Oct 12 07:26:49 PM UTC 24 Oct 12 07:26:56 PM UTC 24 40021593 ps
T2584 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.2343706844 Oct 12 07:26:25 PM UTC 24 Oct 12 07:27:00 PM UTC 24 822579041 ps
T2585 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.347727904 Oct 12 07:26:27 PM UTC 24 Oct 12 07:27:02 PM UTC 24 923046946 ps
T2586 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3894440262 Oct 12 07:25:57 PM UTC 24 Oct 12 07:27:08 PM UTC 24 4691260568 ps
T2587 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.4018581 Oct 12 07:26:01 PM UTC 24 Oct 12 07:27:11 PM UTC 24 2428936868 ps
T2588 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.3521364572 Oct 12 07:23:35 PM UTC 24 Oct 12 07:27:12 PM UTC 24 19451797023 ps
T2589 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3884982137 Oct 12 07:08:59 PM UTC 24 Oct 12 07:27:12 PM UTC 24 12998859622 ps
T2590 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1070324634 Oct 12 07:27:02 PM UTC 24 Oct 12 07:27:16 PM UTC 24 64054003 ps
T2591 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.2520024248 Oct 12 07:27:04 PM UTC 24 Oct 12 07:27:16 PM UTC 24 246624150 ps
T2592 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.3978663823 Oct 12 07:23:36 PM UTC 24 Oct 12 07:27:21 PM UTC 24 15231979131 ps
T2593 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.3946201448 Oct 12 07:20:47 PM UTC 24 Oct 12 07:27:24 PM UTC 24 11687728731 ps
T2594 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1453696641 Oct 12 07:24:37 PM UTC 24 Oct 12 07:27:33 PM UTC 24 5211173334 ps
T2595 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.1888967765 Oct 12 07:21:07 PM UTC 24 Oct 12 07:27:35 PM UTC 24 25572795316 ps
T2596 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.3041740395 Oct 12 07:27:13 PM UTC 24 Oct 12 07:27:42 PM UTC 24 300558625 ps
T2597 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.3938853999 Oct 12 07:27:34 PM UTC 24 Oct 12 07:27:44 PM UTC 24 53502104 ps
T2598 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.1594592037 Oct 12 07:27:10 PM UTC 24 Oct 12 07:27:49 PM UTC 24 1265433649 ps
T2599 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.3603098282 Oct 12 07:27:33 PM UTC 24 Oct 12 07:27:51 PM UTC 24 261590592 ps
T2600 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.1390817456 Oct 12 07:25:49 PM UTC 24 Oct 12 07:27:51 PM UTC 24 10308368894 ps
T2601 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.2499197998 Oct 12 07:27:33 PM UTC 24 Oct 12 07:27:53 PM UTC 24 510104837 ps
T2602 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3860901895 Oct 12 07:25:35 PM UTC 24 Oct 12 07:27:54 PM UTC 24 1416951354 ps
T2603 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1235792049 Oct 12 07:26:33 PM UTC 24 Oct 12 07:27:56 PM UTC 24 1364665201 ps
T2604 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.4052704613 Oct 12 07:27:14 PM UTC 24 Oct 12 07:27:59 PM UTC 24 1304937452 ps
T2605 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.3068133855 Oct 12 07:21:56 PM UTC 24 Oct 12 07:28:02 PM UTC 24 24128075398 ps
T2606 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.1045493121 Oct 12 07:26:57 PM UTC 24 Oct 12 07:28:06 PM UTC 24 1928814063 ps
T2607 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.922498179 Oct 12 07:26:56 PM UTC 24 Oct 12 07:28:13 PM UTC 24 4649573819 ps
T2608 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.1215545338 Oct 12 07:26:52 PM UTC 24 Oct 12 07:28:17 PM UTC 24 8167026510 ps
T2609 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.3510515005 Oct 12 07:19:17 PM UTC 24 Oct 12 07:28:17 PM UTC 24 44696469856 ps
T2610 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.555237931 Oct 12 07:21:36 PM UTC 24 Oct 12 07:28:19 PM UTC 24 3716682341 ps
T2611 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.2295875753 Oct 12 07:27:17 PM UTC 24 Oct 12 07:28:20 PM UTC 24 1342701735 ps
T2612 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.742615064 Oct 12 07:27:42 PM UTC 24 Oct 12 07:28:26 PM UTC 24 425166369 ps
T2613 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.2538152313 Oct 12 07:24:39 PM UTC 24 Oct 12 07:28:32 PM UTC 24 3430242700 ps
T2614 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2279876632 Oct 12 07:27:06 PM UTC 24 Oct 12 07:28:38 PM UTC 24 5198452263 ps
T2615 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.2458929602 Oct 12 07:28:26 PM UTC 24 Oct 12 07:28:39 PM UTC 24 208513104 ps
T2616 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2188023114 Oct 12 07:28:30 PM UTC 24 Oct 12 07:28:39 PM UTC 24 42972896 ps
T2617 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.3755393274 Oct 12 07:28:15 PM UTC 24 Oct 12 07:28:44 PM UTC 24 626149943 ps
T2618 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2693190532 Oct 12 07:27:13 PM UTC 24 Oct 12 07:28:50 PM UTC 24 959054606 ps
T2619 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.1104370423 Oct 12 07:28:43 PM UTC 24 Oct 12 07:28:55 PM UTC 24 56595727 ps
T2620 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.3634080025 Oct 12 07:28:08 PM UTC 24 Oct 12 07:28:56 PM UTC 24 1408993854 ps
T2621 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.3750948221 Oct 12 07:27:35 PM UTC 24 Oct 12 07:28:56 PM UTC 24 7615072867 ps
T2622 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1723882736 Oct 12 07:27:36 PM UTC 24 Oct 12 07:29:01 PM UTC 24 5357679469 ps
T2623 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3601989581 Oct 12 07:28:14 PM UTC 24 Oct 12 07:29:03 PM UTC 24 1255461938 ps
T2624 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.2828497009 Oct 12 07:26:05 PM UTC 24 Oct 12 07:29:08 PM UTC 24 14033452757 ps
T2625 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.3097954005 Oct 12 07:29:03 PM UTC 24 Oct 12 07:29:12 PM UTC 24 62989725 ps
T2626 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.2936660885 Oct 12 07:29:03 PM UTC 24 Oct 12 07:29:12 PM UTC 24 51045780 ps
T2627 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.3335753068 Oct 12 07:27:02 PM UTC 24 Oct 12 07:29:17 PM UTC 24 7894093748 ps
T2628 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.996868103 Oct 12 07:25:37 PM UTC 24 Oct 12 07:29:18 PM UTC 24 1825104501 ps
T2629 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.1651394828 Oct 12 07:28:13 PM UTC 24 Oct 12 07:29:31 PM UTC 24 1735813801 ps
T2630 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3476045775 Oct 12 07:29:04 PM UTC 24 Oct 12 07:29:38 PM UTC 24 832789759 ps
T2631 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.2439756077 Oct 12 07:28:41 PM UTC 24 Oct 12 07:29:40 PM UTC 24 1713841546 ps
T2632 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1302685866 Oct 12 07:29:32 PM UTC 24 Oct 12 07:29:42 PM UTC 24 42099274 ps
T2633 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.1446553066 Oct 12 07:29:28 PM UTC 24 Oct 12 07:29:43 PM UTC 24 250682257 ps
T2634 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2936616194 Oct 12 07:29:11 PM UTC 24 Oct 12 07:29:46 PM UTC 24 731314900 ps
T2635 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.155104281 Oct 12 07:28:56 PM UTC 24 Oct 12 07:29:47 PM UTC 24 1195940202 ps
T2636 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.4177555844 Oct 12 07:28:37 PM UTC 24 Oct 12 07:29:57 PM UTC 24 7924218486 ps
T2637 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.1864458478 Oct 12 07:29:43 PM UTC 24 Oct 12 07:30:06 PM UTC 24 258922135 ps
T2638 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.3679631601 Oct 12 07:29:40 PM UTC 24 Oct 12 07:30:07 PM UTC 24 261030071 ps
T2639 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.2873312252 Oct 12 07:22:35 PM UTC 24 Oct 12 07:30:14 PM UTC 24 41426088598 ps
T2640 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.574696514 Oct 12 07:27:04 PM UTC 24 Oct 12 07:30:15 PM UTC 24 17980940405 ps
T2641 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.3926878912 Oct 12 07:23:46 PM UTC 24 Oct 12 07:30:18 PM UTC 24 10323849741 ps
T2642 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3270820097 Oct 12 07:30:07 PM UTC 24 Oct 12 07:30:20 PM UTC 24 157724564 ps
T2643 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.32806428 Oct 12 07:27:58 PM UTC 24 Oct 12 07:30:27 PM UTC 24 2915710929 ps
T2644 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.2384809816 Oct 12 07:27:56 PM UTC 24 Oct 12 07:30:28 PM UTC 24 10139362036 ps
T2645 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2441196484 Oct 12 07:24:40 PM UTC 24 Oct 12 07:30:31 PM UTC 24 3162781360 ps
T2646 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.3810491004 Oct 12 07:23:55 PM UTC 24 Oct 12 07:30:37 PM UTC 24 12236292898 ps
T2647 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.3836520202 Oct 12 07:30:12 PM UTC 24 Oct 12 07:30:43 PM UTC 24 743706511 ps
T2648 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.160905317 Oct 12 07:28:40 PM UTC 24 Oct 12 07:30:45 PM UTC 24 5950321885 ps
T2649 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.28499144 Oct 12 07:11:13 PM UTC 24 Oct 12 07:30:46 PM UTC 24 81484102655 ps
T2650 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2035830277 Oct 12 07:29:20 PM UTC 24 Oct 12 07:30:49 PM UTC 24 86650554 ps
T2651 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.3662654291 Oct 12 07:30:08 PM UTC 24 Oct 12 07:30:50 PM UTC 24 460528614 ps
T2652 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.2815971375 Oct 12 07:27:24 PM UTC 24 Oct 12 07:30:50 PM UTC 24 6844502312 ps
T2653 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.4024860628 Oct 12 07:21:56 PM UTC 24 Oct 12 07:30:51 PM UTC 24 42952747228 ps
T2654 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2291439177 Oct 12 07:30:44 PM UTC 24 Oct 12 07:30:53 PM UTC 24 35708013 ps
T2655 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.1217257027 Oct 12 07:25:23 PM UTC 24 Oct 12 07:30:57 PM UTC 24 22544768270 ps
T2656 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.616171012 Oct 12 07:30:43 PM UTC 24 Oct 12 07:30:57 PM UTC 24 222229211 ps
T2657 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.4127375297 Oct 12 07:24:15 PM UTC 24 Oct 12 07:31:03 PM UTC 24 28378695555 ps
T2658 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1776576587 Oct 12 07:24:41 PM UTC 24 Oct 12 07:31:09 PM UTC 24 3738312985 ps
T2659 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.3168029879 Oct 12 07:30:54 PM UTC 24 Oct 12 07:31:10 PM UTC 24 117290621 ps
T2660 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2350861187 Oct 12 07:30:21 PM UTC 24 Oct 12 07:31:11 PM UTC 24 1299247717 ps
T2661 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.1795253835 Oct 12 07:28:49 PM UTC 24 Oct 12 07:31:13 PM UTC 24 8655789338 ps
T2662 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1065740237 Oct 12 07:29:37 PM UTC 24 Oct 12 07:31:14 PM UTC 24 5455264029 ps
T2663 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.2818029047 Oct 12 07:29:35 PM UTC 24 Oct 12 07:31:16 PM UTC 24 7902017733 ps
T2664 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3766807371 Oct 12 07:29:25 PM UTC 24 Oct 12 07:31:16 PM UTC 24 690496352 ps
T2665 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.1176284387 Oct 12 07:31:01 PM UTC 24 Oct 12 07:31:19 PM UTC 24 212356811 ps
T2666 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.1503408009 Oct 12 07:31:14 PM UTC 24 Oct 12 07:31:28 PM UTC 24 53559121 ps
T2667 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2641185956 Oct 12 07:22:57 PM UTC 24 Oct 12 07:31:35 PM UTC 24 12290220223 ps
T2668 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.550889193 Oct 12 07:31:15 PM UTC 24 Oct 12 07:31:36 PM UTC 24 195917140 ps
T2669 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.3392939336 Oct 12 07:31:33 PM UTC 24 Oct 12 07:31:43 PM UTC 24 49664440 ps
T2670 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.2197434899 Oct 12 07:31:32 PM UTC 24 Oct 12 07:31:45 PM UTC 24 202569184 ps
T2671 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2707882606 Oct 12 07:27:22 PM UTC 24 Oct 12 07:31:49 PM UTC 24 603154491 ps
T2672 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1873481861 Oct 12 07:25:28 PM UTC 24 Oct 12 07:31:50 PM UTC 24 25999878496 ps
T2673 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1339807706 Oct 12 07:30:38 PM UTC 24 Oct 12 07:31:53 PM UTC 24 905804643 ps
T2674 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.2428255174 Oct 12 07:31:36 PM UTC 24 Oct 12 07:31:54 PM UTC 24 196563950 ps
T2675 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1801047516 Oct 12 07:18:25 PM UTC 24 Oct 12 07:31:59 PM UTC 24 63670304098 ps
T2676 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.585064759 Oct 12 07:31:32 PM UTC 24 Oct 12 07:32:05 PM UTC 24 121522572 ps
T2677 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.1842152667 Oct 12 07:31:39 PM UTC 24 Oct 12 07:32:06 PM UTC 24 241671900 ps
T2678 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.964716267 Oct 12 07:30:02 PM UTC 24 Oct 12 07:32:12 PM UTC 24 2843420780 ps
T2679 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.679605979 Oct 12 07:23:50 PM UTC 24 Oct 12 07:32:13 PM UTC 24 7061762272 ps
T2680 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.313001425 Oct 12 07:23:07 PM UTC 24 Oct 12 07:32:16 PM UTC 24 9083038494 ps
T2681 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1754251884 Oct 12 07:28:18 PM UTC 24 Oct 12 07:32:25 PM UTC 24 3073502714 ps
T2682 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.2694298581 Oct 12 07:31:13 PM UTC 24 Oct 12 07:32:27 PM UTC 24 2679715486 ps
T2683 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.2843889006 Oct 12 07:29:55 PM UTC 24 Oct 12 07:32:28 PM UTC 24 14381314784 ps
T2684 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1311014718 Oct 12 07:32:13 PM UTC 24 Oct 12 07:32:30 PM UTC 24 115891577 ps
T2685 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.4195367055 Oct 12 07:32:06 PM UTC 24 Oct 12 07:32:30 PM UTC 24 237253324 ps
T2686 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.4130631571 Oct 12 07:30:53 PM UTC 24 Oct 12 07:32:35 PM UTC 24 5303621432 ps
T2687 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.1468189556 Oct 12 07:31:11 PM UTC 24 Oct 12 07:32:38 PM UTC 24 1970778787 ps
T2688 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1843289429 Oct 12 07:32:29 PM UTC 24 Oct 12 07:32:41 PM UTC 24 132754307 ps
T2689 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3834666015 Oct 12 07:31:12 PM UTC 24 Oct 12 07:32:43 PM UTC 24 2168962991 ps
T2690 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2744332369 Oct 12 07:32:33 PM UTC 24 Oct 12 07:32:43 PM UTC 24 47271733 ps
T2691 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3376295522 Oct 12 07:13:59 PM UTC 24 Oct 12 07:32:43 PM UTC 24 67957939936 ps
T676 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.572614260 Oct 12 07:26:38 PM UTC 24 Oct 12 07:32:44 PM UTC 24 6876640445 ps
T2692 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3976714408 Oct 12 07:24:00 PM UTC 24 Oct 12 07:32:45 PM UTC 24 9490906599 ps
T2693 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.1133786093 Oct 12 07:30:52 PM UTC 24 Oct 12 07:32:53 PM UTC 24 9485385459 ps
T2694 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2095991494 Oct 12 07:31:56 PM UTC 24 Oct 12 07:32:55 PM UTC 24 742586146 ps
T2695 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.269963970 Oct 12 07:32:04 PM UTC 24 Oct 12 07:32:55 PM UTC 24 560499747 ps
T2696 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1094969937 Oct 12 07:28:17 PM UTC 24 Oct 12 07:32:57 PM UTC 24 619348001 ps
T2697 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3319989258 Oct 12 07:27:31 PM UTC 24 Oct 12 07:32:58 PM UTC 24 1919893704 ps
T2698 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3227605686 Oct 12 07:31:38 PM UTC 24 Oct 12 07:32:59 PM UTC 24 5377570081 ps
T2699 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2671367186 Oct 12 07:32:14 PM UTC 24 Oct 12 07:33:06 PM UTC 24 1329375171 ps
T2700 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.3996766057 Oct 12 07:26:34 PM UTC 24 Oct 12 07:33:06 PM UTC 24 4962574541 ps
T2701 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.3401601663 Oct 12 07:31:20 PM UTC 24 Oct 12 07:33:10 PM UTC 24 3086093320 ps
T2702 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.1081073075 Oct 12 07:31:35 PM UTC 24 Oct 12 07:33:11 PM UTC 24 8151996736 ps
T2703 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.3082856421 Oct 12 07:26:29 PM UTC 24 Oct 12 07:33:12 PM UTC 24 11990996120 ps
T2704 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3083344384 Oct 12 07:33:05 PM UTC 24 Oct 12 07:33:18 PM UTC 24 82728719 ps
T2705 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.4267630999 Oct 12 07:32:48 PM UTC 24 Oct 12 07:33:25 PM UTC 24 295891254 ps
T2706 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.2519456792 Oct 12 07:33:17 PM UTC 24 Oct 12 07:33:27 PM UTC 24 56854145 ps
T2707 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.887294893 Oct 12 07:33:19 PM UTC 24 Oct 12 07:33:28 PM UTC 24 38030064 ps
T2708 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.914714725 Oct 12 07:29:17 PM UTC 24 Oct 12 07:33:28 PM UTC 24 2679806371 ps
T2709 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.4258959747 Oct 12 07:33:02 PM UTC 24 Oct 12 07:33:29 PM UTC 24 215270316 ps
T2710 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.1111313461 Oct 12 07:32:59 PM UTC 24 Oct 12 07:33:31 PM UTC 24 921138385 ps
T2711 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.19898269 Oct 12 07:32:50 PM UTC 24 Oct 12 07:33:36 PM UTC 24 473468717 ps
T2712 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3324412551 Oct 12 07:33:14 PM UTC 24 Oct 12 07:33:48 PM UTC 24 130328217 ps
T2713 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.2221035379 Oct 12 07:32:53 PM UTC 24 Oct 12 07:33:52 PM UTC 24 1159085532 ps
T2714 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2785265808 Oct 12 07:32:37 PM UTC 24 Oct 12 07:33:52 PM UTC 24 4321079129 ps
T2715 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2306009232 Oct 12 07:33:22 PM UTC 24 Oct 12 07:33:58 PM UTC 24 880849951 ps
T2716 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.2045754889 Oct 12 07:32:58 PM UTC 24 Oct 12 07:34:00 PM UTC 24 2388539262 ps
T2717 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.814430672 Oct 12 07:32:37 PM UTC 24 Oct 12 07:34:06 PM UTC 24 6918238773 ps
T2718 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1261803908 Oct 12 07:22:43 PM UTC 24 Oct 12 07:34:08 PM UTC 24 47877717263 ps
T2719 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.460419439 Oct 12 07:33:27 PM UTC 24 Oct 12 07:34:16 PM UTC 24 509492242 ps
T2720 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.3962097770 Oct 12 07:32:48 PM UTC 24 Oct 12 07:34:17 PM UTC 24 6141063980 ps
T2721 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.1323704558 Oct 12 07:34:12 PM UTC 24 Oct 12 07:34:22 PM UTC 24 41103992 ps
T2722 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3394527045 Oct 12 07:34:15 PM UTC 24 Oct 12 07:34:23 PM UTC 24 50632785 ps
T2723 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.1264848845 Oct 12 07:33:32 PM UTC 24 Oct 12 07:34:24 PM UTC 24 412336617 ps
T2724 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.3512782731 Oct 12 07:31:04 PM UTC 24 Oct 12 07:34:24 PM UTC 24 18581861393 ps
T2725 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.76388410 Oct 12 07:33:18 PM UTC 24 Oct 12 07:34:25 PM UTC 24 3410708459 ps
T2726 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.1176907649 Oct 12 07:32:20 PM UTC 24 Oct 12 07:34:26 PM UTC 24 1963696238 ps
T2727 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.2073532689 Oct 12 07:34:23 PM UTC 24 Oct 12 07:34:32 PM UTC 24 120116457 ps
T2728 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.1756868736 Oct 12 07:33:18 PM UTC 24 Oct 12 07:34:28 PM UTC 24 6731853866 ps
T2729 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1992196963 Oct 12 07:33:48 PM UTC 24 Oct 12 07:34:29 PM UTC 24 284381230 ps
T2730 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.241239876 Oct 12 07:30:37 PM UTC 24 Oct 12 07:34:30 PM UTC 24 4482348498 ps
T2731 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.779169439 Oct 12 07:33:38 PM UTC 24 Oct 12 07:34:40 PM UTC 24 1690223916 ps
T2732 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.2423956149 Oct 12 07:33:50 PM UTC 24 Oct 12 07:34:43 PM UTC 24 836006080 ps
T2733 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1824102672 Oct 12 07:28:21 PM UTC 24 Oct 12 07:34:43 PM UTC 24 3113314646 ps
T2734 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.2360657506 Oct 12 07:34:38 PM UTC 24 Oct 12 07:34:49 PM UTC 24 107692872 ps
T2735 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.866770547 Oct 12 07:34:45 PM UTC 24 Oct 12 07:34:51 PM UTC 24 32175196 ps
T2736 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.1304470087 Oct 12 07:30:29 PM UTC 24 Oct 12 07:34:52 PM UTC 24 6791263028 ps
T2737 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.2746056169 Oct 12 07:34:28 PM UTC 24 Oct 12 07:34:54 PM UTC 24 195728961 ps
T2738 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.1527383905 Oct 12 07:33:51 PM UTC 24 Oct 12 07:34:55 PM UTC 24 702900961 ps
T2739 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.1450188889 Oct 12 07:33:49 PM UTC 24 Oct 12 07:34:59 PM UTC 24 1816196148 ps
T2740 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.99367388 Oct 12 07:33:06 PM UTC 24 Oct 12 07:35:01 PM UTC 24 233805785 ps
T2741 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2711148346 Oct 12 07:34:54 PM UTC 24 Oct 12 07:35:02 PM UTC 24 44548752 ps
T2742 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.4070827796 Oct 12 07:35:03 PM UTC 24 Oct 12 07:35:11 PM UTC 24 49596895 ps
T2743 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.36347233 Oct 12 07:34:46 PM UTC 24 Oct 12 07:35:18 PM UTC 24 318570260 ps
T2744 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.2911247244 Oct 12 07:34:44 PM UTC 24 Oct 12 07:35:23 PM UTC 24 875630264 ps
T2745 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.1268435904 Oct 12 07:34:17 PM UTC 24 Oct 12 07:35:26 PM UTC 24 7491370450 ps
T2746 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1480990292 Oct 12 07:35:11 PM UTC 24 Oct 12 07:35:27 PM UTC 24 142203615 ps
T2747 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1421016908 Oct 12 07:32:17 PM UTC 24 Oct 12 07:35:29 PM UTC 24 5384172384 ps
T2748 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.4245912964 Oct 12 07:33:54 PM UTC 24 Oct 12 07:35:31 PM UTC 24 1262609547 ps
T2749 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.3717011599 Oct 12 07:34:52 PM UTC 24 Oct 12 07:35:36 PM UTC 24 1102660003 ps
T2750 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.1944109758 Oct 12 07:34:43 PM UTC 24 Oct 12 07:35:37 PM UTC 24 1907411549 ps
T2751 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1346188374 Oct 12 05:47:39 PM UTC 24 Oct 12 07:35:40 PM UTC 24 37094795518 ps
T2752 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3274863377 Oct 12 07:30:31 PM UTC 24 Oct 12 07:35:40 PM UTC 24 2237599125 ps
T2753 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.520784496 Oct 12 07:22:02 PM UTC 24 Oct 12 07:35:47 PM UTC 24 57930512096 ps
T2754 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.3188416149 Oct 12 07:35:24 PM UTC 24 Oct 12 07:35:48 PM UTC 24 261634800 ps
T2755 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.1216135310 Oct 12 07:35:12 PM UTC 24 Oct 12 07:35:49 PM UTC 24 807278081 ps
T2756 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.2632460145 Oct 12 07:35:24 PM UTC 24 Oct 12 07:35:52 PM UTC 24 906458039 ps
T2757 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3504807557 Oct 12 07:17:23 PM UTC 24 Oct 12 07:35:57 PM UTC 24 68159850600 ps
T2758 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2345676140 Oct 12 07:35:42 PM UTC 24 Oct 12 07:35:59 PM UTC 24 143270122 ps
T2759 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.3570417794 Oct 12 07:35:17 PM UTC 24 Oct 12 07:36:03 PM UTC 24 433566819 ps
T2760 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.3236994920 Oct 12 07:35:55 PM UTC 24 Oct 12 07:36:04 PM UTC 24 41682906 ps
T2761 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2768237764 Oct 12 07:35:59 PM UTC 24 Oct 12 07:36:08 PM UTC 24 45176612 ps
T2762 /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.1969079417 Oct 12 07:31:51 PM UTC 24 Oct 12 07:36:10 PM UTC 24 19679763330 ps
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