| T581 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.4117997423 |
|
|
Oct 12 06:00:53 PM UTC 24 |
Oct 12 06:06:38 PM UTC 24 |
4384641390 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.1964351844 |
|
|
Oct 12 06:02:56 PM UTC 24 |
Oct 12 06:06:39 PM UTC 24 |
3576868526 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1751716780 |
|
|
Oct 12 06:06:34 PM UTC 24 |
Oct 12 06:06:44 PM UTC 24 |
49102332 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.696270894 |
|
|
Oct 12 06:06:45 PM UTC 24 |
Oct 12 06:06:58 PM UTC 24 |
81784390 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1502236209 |
|
|
Oct 12 06:03:20 PM UTC 24 |
Oct 12 06:07:01 PM UTC 24 |
20372762984 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.2530875724 |
|
|
Oct 12 06:06:46 PM UTC 24 |
Oct 12 06:07:03 PM UTC 24 |
98351117 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.207846221 |
|
|
Oct 12 05:55:34 PM UTC 24 |
Oct 12 06:07:03 PM UTC 24 |
4525406719 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1590366849 |
|
|
Oct 12 06:02:29 PM UTC 24 |
Oct 12 06:07:12 PM UTC 24 |
3505858736 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.1940491334 |
|
|
Oct 12 06:06:58 PM UTC 24 |
Oct 12 06:07:14 PM UTC 24 |
69511794 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.3611500045 |
|
|
Oct 12 06:07:07 PM UTC 24 |
Oct 12 06:07:18 PM UTC 24 |
132143089 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.987971087 |
|
|
Oct 12 06:07:01 PM UTC 24 |
Oct 12 06:07:24 PM UTC 24 |
161695753 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1498585203 |
|
|
Oct 12 06:04:16 PM UTC 24 |
Oct 12 06:07:35 PM UTC 24 |
226838667 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3377253975 |
|
|
Oct 12 05:57:00 PM UTC 24 |
Oct 12 06:07:36 PM UTC 24 |
15185622431 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3916448694 |
|
|
Oct 12 06:06:50 PM UTC 24 |
Oct 12 06:07:48 PM UTC 24 |
3926820248 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1010867465 |
|
|
Oct 12 05:58:45 PM UTC 24 |
Oct 12 06:07:50 PM UTC 24 |
6771624914 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.2125568758 |
|
|
Oct 12 06:07:22 PM UTC 24 |
Oct 12 06:07:57 PM UTC 24 |
335972009 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3188099698 |
|
|
Oct 12 06:07:25 PM UTC 24 |
Oct 12 06:08:04 PM UTC 24 |
664983331 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1492173367 |
|
|
Oct 12 06:00:29 PM UTC 24 |
Oct 12 06:08:14 PM UTC 24 |
7659060126 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.2268382879 |
|
|
Oct 12 06:08:10 PM UTC 24 |
Oct 12 06:08:19 PM UTC 24 |
177108748 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.2655496635 |
|
|
Oct 12 06:06:39 PM UTC 24 |
Oct 12 06:08:21 PM UTC 24 |
8624208610 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2537536006 |
|
|
Oct 12 06:08:12 PM UTC 24 |
Oct 12 06:08:22 PM UTC 24 |
35788109 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3716295980 |
|
|
Oct 12 06:06:10 PM UTC 24 |
Oct 12 06:08:24 PM UTC 24 |
2978007077 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3817243717 |
|
|
Oct 12 06:06:41 PM UTC 24 |
Oct 12 06:08:29 PM UTC 24 |
6295338670 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.508575699 |
|
|
Oct 12 06:05:15 PM UTC 24 |
Oct 12 06:08:33 PM UTC 24 |
16747193412 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3959489953 |
|
|
Oct 12 06:07:00 PM UTC 24 |
Oct 12 06:08:36 PM UTC 24 |
5333336650 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1121207109 |
|
|
Oct 12 06:07:38 PM UTC 24 |
Oct 12 06:08:37 PM UTC 24 |
118531367 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.935267016 |
|
|
Oct 12 06:06:53 PM UTC 24 |
Oct 12 06:08:50 PM UTC 24 |
7929746971 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.4121646381 |
|
|
Oct 12 06:03:23 PM UTC 24 |
Oct 12 06:08:50 PM UTC 24 |
23513001696 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1401200065 |
|
|
Oct 12 06:02:29 PM UTC 24 |
Oct 12 06:08:51 PM UTC 24 |
7919624246 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2487376010 |
|
|
Oct 12 06:08:43 PM UTC 24 |
Oct 12 06:08:59 PM UTC 24 |
122273828 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.3246864015 |
|
|
Oct 12 05:59:32 PM UTC 24 |
Oct 12 06:09:00 PM UTC 24 |
29118256527 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2980716835 |
|
|
Oct 12 05:55:58 PM UTC 24 |
Oct 12 06:09:02 PM UTC 24 |
9331634532 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.3558309038 |
|
|
Oct 12 06:08:37 PM UTC 24 |
Oct 12 06:09:05 PM UTC 24 |
636488906 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.3913753225 |
|
|
Oct 12 06:08:47 PM UTC 24 |
Oct 12 06:09:11 PM UTC 24 |
462538141 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.820826606 |
|
|
Oct 12 06:08:56 PM UTC 24 |
Oct 12 06:09:12 PM UTC 24 |
313540986 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2300869007 |
|
|
Oct 12 05:56:55 PM UTC 24 |
Oct 12 06:09:19 PM UTC 24 |
18234194487 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2037865350 |
|
|
Oct 12 06:07:27 PM UTC 24 |
Oct 12 06:09:29 PM UTC 24 |
360438789 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.2878828983 |
|
|
Oct 12 06:01:27 PM UTC 24 |
Oct 12 06:09:29 PM UTC 24 |
34963494044 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.3654025054 |
|
|
Oct 12 06:08:21 PM UTC 24 |
Oct 12 06:09:41 PM UTC 24 |
6321477481 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1676107650 |
|
|
Oct 12 06:06:22 PM UTC 24 |
Oct 12 06:09:42 PM UTC 24 |
3224281164 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1603116240 |
|
|
Oct 12 06:09:13 PM UTC 24 |
Oct 12 06:09:50 PM UTC 24 |
242094500 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3409172634 |
|
|
Oct 12 06:09:42 PM UTC 24 |
Oct 12 06:09:52 PM UTC 24 |
45760522 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.2166474258 |
|
|
Oct 12 06:08:44 PM UTC 24 |
Oct 12 06:09:57 PM UTC 24 |
5253765248 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1041470636 |
|
|
Oct 12 06:09:00 PM UTC 24 |
Oct 12 06:09:58 PM UTC 24 |
874938868 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2343798082 |
|
|
Oct 12 06:05:50 PM UTC 24 |
Oct 12 06:10:01 PM UTC 24 |
2669116808 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.278037492 |
|
|
Oct 12 06:09:51 PM UTC 24 |
Oct 12 06:10:01 PM UTC 24 |
49409901 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2900883440 |
|
|
Oct 12 06:08:27 PM UTC 24 |
Oct 12 06:10:02 PM UTC 24 |
5126526533 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.72621274 |
|
|
Oct 12 06:04:28 PM UTC 24 |
Oct 12 06:10:02 PM UTC 24 |
3728861726 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.3607432455 |
|
|
Oct 12 06:07:37 PM UTC 24 |
Oct 12 06:10:18 PM UTC 24 |
4208134577 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.1376576154 |
|
|
Oct 12 06:10:12 PM UTC 24 |
Oct 12 06:10:26 PM UTC 24 |
93199455 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.5022627 |
|
|
Oct 12 06:08:59 PM UTC 24 |
Oct 12 06:10:30 PM UTC 24 |
2382399885 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.2946294750 |
|
|
Oct 12 06:10:04 PM UTC 24 |
Oct 12 06:10:32 PM UTC 24 |
701121469 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1514049151 |
|
|
Oct 12 05:54:17 PM UTC 24 |
Oct 12 06:10:41 PM UTC 24 |
10111081740 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3368858246 |
|
|
Oct 12 06:10:26 PM UTC 24 |
Oct 12 06:10:43 PM UTC 24 |
69210960 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.3900890489 |
|
|
Oct 12 06:10:25 PM UTC 24 |
Oct 12 06:10:44 PM UTC 24 |
424263678 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.3315258376 |
|
|
Oct 12 06:09:52 PM UTC 24 |
Oct 12 06:10:49 PM UTC 24 |
6014942350 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2759154251 |
|
|
Oct 12 05:59:33 PM UTC 24 |
Oct 12 06:11:02 PM UTC 24 |
41931429053 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1865129517 |
|
|
Oct 12 06:09:15 PM UTC 24 |
Oct 12 06:11:13 PM UTC 24 |
247241336 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2696835835 |
|
|
Oct 12 06:10:42 PM UTC 24 |
Oct 12 06:11:15 PM UTC 24 |
210213861 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.3548733063 |
|
|
Oct 12 06:07:59 PM UTC 24 |
Oct 12 06:11:19 PM UTC 24 |
3037710965 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2930546905 |
|
|
Oct 12 06:10:51 PM UTC 24 |
Oct 12 06:11:24 PM UTC 24 |
50934826 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2523421663 |
|
|
Oct 12 06:10:24 PM UTC 24 |
Oct 12 06:11:37 PM UTC 24 |
1679861303 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.2623317089 |
|
|
Oct 12 06:10:21 PM UTC 24 |
Oct 12 06:11:39 PM UTC 24 |
1971355455 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1453992341 |
|
|
Oct 12 06:11:39 PM UTC 24 |
Oct 12 06:11:47 PM UTC 24 |
35430041 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.2600267479 |
|
|
Oct 12 06:11:37 PM UTC 24 |
Oct 12 06:11:47 PM UTC 24 |
48176774 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3281396681 |
|
|
Oct 12 06:10:04 PM UTC 24 |
Oct 12 06:11:52 PM UTC 24 |
4608843234 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2428753544 |
|
|
Oct 12 06:09:23 PM UTC 24 |
Oct 12 06:11:53 PM UTC 24 |
561814470 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1117738152 |
|
|
Oct 12 06:11:04 PM UTC 24 |
Oct 12 06:12:13 PM UTC 24 |
448211784 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.365000717 |
|
|
Oct 12 06:09:21 PM UTC 24 |
Oct 12 06:12:15 PM UTC 24 |
1711233035 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.2069744483 |
|
|
Oct 12 06:05:56 PM UTC 24 |
Oct 12 06:12:20 PM UTC 24 |
11023556251 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.2074732762 |
|
|
Oct 12 06:12:00 PM UTC 24 |
Oct 12 06:12:50 PM UTC 24 |
481610920 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.1985099197 |
|
|
Oct 12 06:12:03 PM UTC 24 |
Oct 12 06:12:16 PM UTC 24 |
65525956 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.551747015 |
|
|
Oct 12 06:01:30 PM UTC 24 |
Oct 12 06:12:41 PM UTC 24 |
49561521374 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1545516376 |
|
|
Oct 12 06:11:48 PM UTC 24 |
Oct 12 06:12:43 PM UTC 24 |
3091587896 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1512254198 |
|
|
Oct 12 06:10:23 PM UTC 24 |
Oct 12 06:12:48 PM UTC 24 |
10167585013 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.3284353534 |
|
|
Oct 12 06:12:37 PM UTC 24 |
Oct 12 06:12:55 PM UTC 24 |
227815332 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.2254579372 |
|
|
Oct 12 06:10:56 PM UTC 24 |
Oct 12 06:12:56 PM UTC 24 |
1395539155 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.167313167 |
|
|
Oct 12 06:03:31 PM UTC 24 |
Oct 12 06:12:57 PM UTC 24 |
35188459728 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.2177220694 |
|
|
Oct 12 06:12:35 PM UTC 24 |
Oct 12 06:12:58 PM UTC 24 |
152605588 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.973257248 |
|
|
Oct 12 06:12:37 PM UTC 24 |
Oct 12 06:13:08 PM UTC 24 |
264256412 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.856166380 |
|
|
Oct 12 06:05:19 PM UTC 24 |
Oct 12 06:13:12 PM UTC 24 |
23966882167 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.342772782 |
|
|
Oct 12 06:12:17 PM UTC 24 |
Oct 12 06:13:13 PM UTC 24 |
2802468237 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1810752683 |
|
|
Oct 12 06:12:42 PM UTC 24 |
Oct 12 06:13:14 PM UTC 24 |
233218449 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.2570943217 |
|
|
Oct 12 06:13:03 PM UTC 24 |
Oct 12 06:13:20 PM UTC 24 |
108375212 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.293280978 |
|
|
Oct 12 06:02:35 PM UTC 24 |
Oct 12 06:13:22 PM UTC 24 |
5064518510 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.2416047124 |
|
|
Oct 12 06:04:21 PM UTC 24 |
Oct 12 06:13:32 PM UTC 24 |
5403617864 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2302486819 |
|
|
Oct 12 06:02:43 PM UTC 24 |
Oct 12 06:13:33 PM UTC 24 |
6390443660 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2962995779 |
|
|
Oct 12 06:13:32 PM UTC 24 |
Oct 12 06:13:42 PM UTC 24 |
34062467 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2838240564 |
|
|
Oct 12 06:13:35 PM UTC 24 |
Oct 12 06:13:46 PM UTC 24 |
52011247 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.3966146433 |
|
|
Oct 12 06:09:25 PM UTC 24 |
Oct 12 06:14:06 PM UTC 24 |
3967236110 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.4169438822 |
|
|
Oct 12 06:13:44 PM UTC 24 |
Oct 12 06:14:08 PM UTC 24 |
392097232 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.203545477 |
|
|
Oct 12 06:07:25 PM UTC 24 |
Oct 12 06:14:08 PM UTC 24 |
11840371020 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2628964733 |
|
|
Oct 12 06:05:23 PM UTC 24 |
Oct 12 06:14:08 PM UTC 24 |
35951318158 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2191723264 |
|
|
Oct 12 06:06:14 PM UTC 24 |
Oct 12 06:14:10 PM UTC 24 |
7301316552 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.1289224839 |
|
|
Oct 12 06:12:15 PM UTC 24 |
Oct 12 06:14:13 PM UTC 24 |
2644965107 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.819336884 |
|
|
Oct 12 06:11:44 PM UTC 24 |
Oct 12 06:14:15 PM UTC 24 |
10264104825 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3955981432 |
|
|
Oct 12 05:57:03 PM UTC 24 |
Oct 12 06:14:18 PM UTC 24 |
9062571823 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.2844452424 |
|
|
Oct 12 06:14:04 PM UTC 24 |
Oct 12 06:14:25 PM UTC 24 |
412930333 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.962833144 |
|
|
Oct 12 06:09:14 PM UTC 24 |
Oct 12 06:14:34 PM UTC 24 |
3687426383 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.4126648445 |
|
|
Oct 12 06:14:30 PM UTC 24 |
Oct 12 06:14:43 PM UTC 24 |
74053081 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.3234935408 |
|
|
Oct 12 06:13:46 PM UTC 24 |
Oct 12 06:14:47 PM UTC 24 |
539614741 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.4061530742 |
|
|
Oct 12 06:13:09 PM UTC 24 |
Oct 12 06:14:52 PM UTC 24 |
3036703150 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.2710293274 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 06:14:56 PM UTC 24 |
16054860602 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1964213090 |
|
|
Oct 12 06:05:52 PM UTC 24 |
Oct 12 06:15:03 PM UTC 24 |
2402934567 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3103919887 |
|
|
Oct 12 06:13:38 PM UTC 24 |
Oct 12 06:15:03 PM UTC 24 |
4557339379 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.2389429329 |
|
|
Oct 12 06:14:29 PM UTC 24 |
Oct 12 06:15:10 PM UTC 24 |
510240171 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.2180296123 |
|
|
Oct 12 06:11:25 PM UTC 24 |
Oct 12 06:15:14 PM UTC 24 |
3626759860 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.3141328835 |
|
|
Oct 12 06:13:37 PM UTC 24 |
Oct 12 06:15:14 PM UTC 24 |
9966396263 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2026150342 |
|
|
Oct 12 06:14:31 PM UTC 24 |
Oct 12 06:15:15 PM UTC 24 |
965272543 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.160709026 |
|
|
Oct 12 06:09:35 PM UTC 24 |
Oct 12 06:15:23 PM UTC 24 |
5290629256 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.1402567591 |
|
|
Oct 12 06:15:15 PM UTC 24 |
Oct 12 06:15:24 PM UTC 24 |
46060372 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2420897597 |
|
|
Oct 12 06:15:16 PM UTC 24 |
Oct 12 06:15:26 PM UTC 24 |
51079311 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2861478644 |
|
|
Oct 12 06:10:50 PM UTC 24 |
Oct 12 06:15:36 PM UTC 24 |
5992449726 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.881632747 |
|
|
Oct 12 06:10:15 PM UTC 24 |
Oct 12 06:15:43 PM UTC 24 |
30289994014 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.609145573 |
|
|
Oct 12 06:06:12 PM UTC 24 |
Oct 12 06:15:50 PM UTC 24 |
6100793352 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.3015795555 |
|
|
Oct 12 05:46:22 PM UTC 24 |
Oct 12 06:16:02 PM UTC 24 |
16704706477 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2666022073 |
|
|
Oct 12 05:47:34 PM UTC 24 |
Oct 12 06:16:03 PM UTC 24 |
13902499208 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.700964936 |
|
|
Oct 12 06:14:31 PM UTC 24 |
Oct 12 06:16:14 PM UTC 24 |
2618935717 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.2397580097 |
|
|
Oct 12 06:15:34 PM UTC 24 |
Oct 12 06:16:21 PM UTC 24 |
1013916210 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2409191914 |
|
|
Oct 12 06:00:43 PM UTC 24 |
Oct 12 06:16:25 PM UTC 24 |
8212211714 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.4127964597 |
|
|
Oct 12 06:15:26 PM UTC 24 |
Oct 12 06:16:39 PM UTC 24 |
4746822289 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.672761576 |
|
|
Oct 12 06:15:27 PM UTC 24 |
Oct 12 06:16:46 PM UTC 24 |
5666133746 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.422244408 |
|
|
Oct 12 06:16:14 PM UTC 24 |
Oct 12 06:16:47 PM UTC 24 |
234102308 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.27002685 |
|
|
Oct 12 06:15:33 PM UTC 24 |
Oct 12 06:16:48 PM UTC 24 |
601256715 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.1018827298 |
|
|
Oct 12 06:15:49 PM UTC 24 |
Oct 12 06:16:55 PM UTC 24 |
2342008252 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.3846458129 |
|
|
Oct 12 06:16:07 PM UTC 24 |
Oct 12 06:17:00 PM UTC 24 |
836472230 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3165629641 |
|
|
Oct 12 06:09:28 PM UTC 24 |
Oct 12 06:17:06 PM UTC 24 |
6412115308 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3128207459 |
|
|
Oct 12 06:15:46 PM UTC 24 |
Oct 12 06:17:17 PM UTC 24 |
1609404990 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.2734644786 |
|
|
Oct 12 06:15:59 PM UTC 24 |
Oct 12 06:17:18 PM UTC 24 |
1907866270 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.2764178373 |
|
|
Oct 12 06:17:12 PM UTC 24 |
Oct 12 06:17:23 PM UTC 24 |
48735584 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3088747782 |
|
|
Oct 12 06:16:38 PM UTC 24 |
Oct 12 06:17:26 PM UTC 24 |
1406538939 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2039349551 |
|
|
Oct 12 06:17:19 PM UTC 24 |
Oct 12 06:17:30 PM UTC 24 |
53285523 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.2532179920 |
|
|
Oct 12 06:17:40 PM UTC 24 |
Oct 12 06:18:11 PM UTC 24 |
216041856 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3190612760 |
|
|
Oct 12 06:07:48 PM UTC 24 |
Oct 12 06:18:12 PM UTC 24 |
7482362344 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.1685232308 |
|
|
Oct 12 06:17:41 PM UTC 24 |
Oct 12 06:18:27 PM UTC 24 |
916848015 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3913955552 |
|
|
Oct 12 06:07:42 PM UTC 24 |
Oct 12 06:18:32 PM UTC 24 |
5699663623 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1924507644 |
|
|
Oct 12 06:16:27 PM UTC 24 |
Oct 12 06:18:35 PM UTC 24 |
145078319 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.29310426 |
|
|
Oct 12 06:17:30 PM UTC 24 |
Oct 12 06:18:36 PM UTC 24 |
2778149659 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3701970268 |
|
|
Oct 12 06:16:45 PM UTC 24 |
Oct 12 06:18:41 PM UTC 24 |
242521000 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.544875103 |
|
|
Oct 12 06:12:09 PM UTC 24 |
Oct 12 06:18:54 PM UTC 24 |
27075515223 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.3708308367 |
|
|
Oct 12 06:18:36 PM UTC 24 |
Oct 12 06:18:56 PM UTC 24 |
142805654 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.4030402899 |
|
|
Oct 12 06:08:44 PM UTC 24 |
Oct 12 06:19:03 PM UTC 24 |
35279901754 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.2227191340 |
|
|
Oct 12 06:18:59 PM UTC 24 |
Oct 12 06:19:15 PM UTC 24 |
276117161 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.3415668066 |
|
|
Oct 12 06:10:20 PM UTC 24 |
Oct 12 06:19:18 PM UTC 24 |
28606722867 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.2901895692 |
|
|
Oct 12 06:13:56 PM UTC 24 |
Oct 12 06:19:25 PM UTC 24 |
21624838478 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.183400090 |
|
|
Oct 12 06:17:22 PM UTC 24 |
Oct 12 06:19:30 PM UTC 24 |
9778433824 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2170482510 |
|
|
Oct 12 06:18:55 PM UTC 24 |
Oct 12 06:19:44 PM UTC 24 |
940738334 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.3168013673 |
|
|
Oct 12 06:13:22 PM UTC 24 |
Oct 12 06:19:48 PM UTC 24 |
4800730912 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2250422806 |
|
|
Oct 12 06:18:58 PM UTC 24 |
Oct 12 06:19:52 PM UTC 24 |
928105452 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.586335864 |
|
|
Oct 12 06:18:51 PM UTC 24 |
Oct 12 06:19:54 PM UTC 24 |
1814169442 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.3679735679 |
|
|
Oct 12 06:19:48 PM UTC 24 |
Oct 12 06:19:58 PM UTC 24 |
49391480 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.275683310 |
|
|
Oct 12 06:12:12 PM UTC 24 |
Oct 12 06:19:59 PM UTC 24 |
49288946135 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.3717040280 |
|
|
Oct 12 06:17:54 PM UTC 24 |
Oct 12 06:20:01 PM UTC 24 |
2323162909 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.1095264910 |
|
|
Oct 12 06:14:46 PM UTC 24 |
Oct 12 06:20:01 PM UTC 24 |
3594746183 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1696203383 |
|
|
Oct 12 06:19:54 PM UTC 24 |
Oct 12 06:20:05 PM UTC 24 |
55115802 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1200618321 |
|
|
Oct 12 06:13:11 PM UTC 24 |
Oct 12 06:20:14 PM UTC 24 |
9876291666 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.2916220136 |
|
|
Oct 12 06:13:56 PM UTC 24 |
Oct 12 06:20:21 PM UTC 24 |
29896281558 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.2347645561 |
|
|
Oct 12 06:20:15 PM UTC 24 |
Oct 12 06:20:31 PM UTC 24 |
86869940 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.457060890 |
|
|
Oct 12 06:20:14 PM UTC 24 |
Oct 12 06:20:48 PM UTC 24 |
325102796 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1301137072 |
|
|
Oct 12 06:20:22 PM UTC 24 |
Oct 12 06:21:12 PM UTC 24 |
3032986070 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.4280961573 |
|
|
Oct 12 06:20:45 PM UTC 24 |
Oct 12 06:21:14 PM UTC 24 |
159171707 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.2945282672 |
|
|
Oct 12 06:14:37 PM UTC 24 |
Oct 12 06:21:15 PM UTC 24 |
10711557821 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.810892362 |
|
|
Oct 12 06:11:04 PM UTC 24 |
Oct 12 06:21:17 PM UTC 24 |
5721396388 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.2075795545 |
|
|
Oct 12 06:16:25 PM UTC 24 |
Oct 12 06:21:20 PM UTC 24 |
3155548786 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.3017140159 |
|
|
Oct 12 06:20:22 PM UTC 24 |
Oct 12 06:21:25 PM UTC 24 |
489412426 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2329390136 |
|
|
Oct 12 06:20:55 PM UTC 24 |
Oct 12 06:21:31 PM UTC 24 |
542906387 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3716882391 |
|
|
Oct 12 06:20:11 PM UTC 24 |
Oct 12 06:21:41 PM UTC 24 |
5582937976 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.2121400337 |
|
|
Oct 12 06:20:38 PM UTC 24 |
Oct 12 06:21:46 PM UTC 24 |
1396932992 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.2447873628 |
|
|
Oct 12 06:15:38 PM UTC 24 |
Oct 12 06:21:46 PM UTC 24 |
22896276263 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.4154228868 |
|
|
Oct 12 06:20:04 PM UTC 24 |
Oct 12 06:21:48 PM UTC 24 |
8854967063 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.909559926 |
|
|
Oct 12 06:20:24 PM UTC 24 |
Oct 12 06:21:49 PM UTC 24 |
5543766002 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.684494536 |
|
|
Oct 12 06:04:22 PM UTC 24 |
Oct 12 06:21:49 PM UTC 24 |
12487334053 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.1244820889 |
|
|
Oct 12 05:47:41 PM UTC 24 |
Oct 12 06:21:52 PM UTC 24 |
15020381334 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.8489307 |
|
|
Oct 12 06:21:44 PM UTC 24 |
Oct 12 06:21:54 PM UTC 24 |
40752703 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3374463284 |
|
|
Oct 12 06:21:47 PM UTC 24 |
Oct 12 06:21:58 PM UTC 24 |
50758869 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.4121783449 |
|
|
Oct 12 06:20:26 PM UTC 24 |
Oct 12 06:22:05 PM UTC 24 |
2639454065 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3144356715 |
|
|
Oct 12 06:13:05 PM UTC 24 |
Oct 12 06:22:24 PM UTC 24 |
7597395800 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1862205626 |
|
|
Oct 12 06:15:48 PM UTC 24 |
Oct 12 06:22:25 PM UTC 24 |
17025062464 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3379841894 |
|
|
Oct 12 06:14:42 PM UTC 24 |
Oct 12 06:22:29 PM UTC 24 |
7954275663 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.3656906570 |
|
|
Oct 12 06:21:12 PM UTC 24 |
Oct 12 06:22:37 PM UTC 24 |
892560275 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.267832353 |
|
|
Oct 12 06:15:09 PM UTC 24 |
Oct 12 06:22:43 PM UTC 24 |
4691175668 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.836236263 |
|
|
Oct 12 06:22:10 PM UTC 24 |
Oct 12 06:22:47 PM UTC 24 |
256862413 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.781027503 |
|
|
Oct 12 06:22:18 PM UTC 24 |
Oct 12 06:22:48 PM UTC 24 |
717675354 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3814087317 |
|
|
Oct 12 06:14:36 PM UTC 24 |
Oct 12 06:22:50 PM UTC 24 |
5996445677 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.674244923 |
|
|
Oct 12 06:22:27 PM UTC 24 |
Oct 12 06:22:50 PM UTC 24 |
109755147 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.1583779031 |
|
|
Oct 12 06:17:51 PM UTC 24 |
Oct 12 06:22:57 PM UTC 24 |
14501490718 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.304000526 |
|
|
Oct 12 06:22:04 PM UTC 24 |
Oct 12 06:22:59 PM UTC 24 |
3351762929 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.3905648026 |
|
|
Oct 12 06:23:00 PM UTC 24 |
Oct 12 06:23:06 PM UTC 24 |
6508227 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2770904244 |
|
|
Oct 12 06:22:48 PM UTC 24 |
Oct 12 06:23:11 PM UTC 24 |
346072603 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2889757705 |
|
|
Oct 12 06:23:07 PM UTC 24 |
Oct 12 06:23:17 PM UTC 24 |
43608444 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1461391628 |
|
|
Oct 12 06:23:11 PM UTC 24 |
Oct 12 06:23:20 PM UTC 24 |
45106121 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1764941463 |
|
|
Oct 12 06:21:40 PM UTC 24 |
Oct 12 06:23:25 PM UTC 24 |
2501349950 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.3724515915 |
|
|
Oct 12 06:22:21 PM UTC 24 |
Oct 12 06:23:26 PM UTC 24 |
1678447322 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.4179381533 |
|
|
Oct 12 06:22:08 PM UTC 24 |
Oct 12 06:23:31 PM UTC 24 |
1653044506 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3955673654 |
|
|
Oct 12 06:20:23 PM UTC 24 |
Oct 12 06:23:33 PM UTC 24 |
7730970702 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2356588414 |
|
|
Oct 12 06:08:52 PM UTC 24 |
Oct 12 06:23:36 PM UTC 24 |
63814758409 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1343050337 |
|
|
Oct 12 06:21:54 PM UTC 24 |
Oct 12 06:23:40 PM UTC 24 |
9858238260 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.2017556150 |
|
|
Oct 12 06:15:36 PM UTC 24 |
Oct 12 06:23:52 PM UTC 24 |
46546001877 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.125543265 |
|
|
Oct 12 06:22:09 PM UTC 24 |
Oct 12 06:24:03 PM UTC 24 |
2143439561 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.3186840156 |
|
|
Oct 12 06:23:28 PM UTC 24 |
Oct 12 06:24:06 PM UTC 24 |
386686907 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3059496260 |
|
|
Oct 12 06:13:19 PM UTC 24 |
Oct 12 06:24:08 PM UTC 24 |
5346892880 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.176666996 |
|
|
Oct 12 06:23:22 PM UTC 24 |
Oct 12 06:24:21 PM UTC 24 |
507459729 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.3156304389 |
|
|
Oct 12 06:17:46 PM UTC 24 |
Oct 12 06:24:23 PM UTC 24 |
30071357542 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.747879001 |
|
|
Oct 12 06:14:31 PM UTC 24 |
Oct 12 06:24:24 PM UTC 24 |
15399645181 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2179976512 |
|
|
Oct 12 06:14:10 PM UTC 24 |
Oct 12 06:24:26 PM UTC 24 |
42362470395 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3942401248 |
|
|
Oct 12 06:14:56 PM UTC 24 |
Oct 12 06:24:31 PM UTC 24 |
6697171717 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.39836282 |
|
|
Oct 12 06:24:00 PM UTC 24 |
Oct 12 06:24:34 PM UTC 24 |
256612467 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.640090018 |
|
|
Oct 12 06:23:53 PM UTC 24 |
Oct 12 06:24:40 PM UTC 24 |
519265932 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3152995744 |
|
|
Oct 12 06:23:06 PM UTC 24 |
Oct 12 06:24:44 PM UTC 24 |
179835068 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1450411447 |
|
|
Oct 12 06:16:49 PM UTC 24 |
Oct 12 06:24:49 PM UTC 24 |
3721449676 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2714562055 |
|
|
Oct 12 06:21:39 PM UTC 24 |
Oct 12 06:24:49 PM UTC 24 |
1560314376 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.2223329016 |
|
|
Oct 12 06:23:44 PM UTC 24 |
Oct 12 06:24:54 PM UTC 24 |
798272740 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.4242961603 |
|
|
Oct 12 06:24:45 PM UTC 24 |
Oct 12 06:24:55 PM UTC 24 |
46924091 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.216500586 |
|
|
Oct 12 06:23:13 PM UTC 24 |
Oct 12 06:24:55 PM UTC 24 |
7538114869 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3356725056 |
|
|
Oct 12 06:23:56 PM UTC 24 |
Oct 12 06:24:56 PM UTC 24 |
1329776180 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.49064715 |
|
|
Oct 12 06:24:46 PM UTC 24 |
Oct 12 06:24:57 PM UTC 24 |
53211330 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1183071690 |
|
|
Oct 12 06:23:50 PM UTC 24 |
Oct 12 06:25:03 PM UTC 24 |
1928045094 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1383521445 |
|
|
Oct 12 06:23:19 PM UTC 24 |
Oct 12 06:25:11 PM UTC 24 |
4850590840 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.191434806 |
|
|
Oct 12 06:19:42 PM UTC 24 |
Oct 12 06:25:23 PM UTC 24 |
3980344526 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.2558404389 |
|
|
Oct 12 06:25:19 PM UTC 24 |
Oct 12 06:25:28 PM UTC 24 |
80164255 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.231360508 |
|
|
Oct 12 06:22:48 PM UTC 24 |
Oct 12 06:25:34 PM UTC 24 |
3933717070 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3575752782 |
|
|
Oct 12 06:11:06 PM UTC 24 |
Oct 12 06:25:38 PM UTC 24 |
12508889693 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.4130208104 |
|
|
Oct 12 06:24:25 PM UTC 24 |
Oct 12 06:25:43 PM UTC 24 |
2025422000 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1233927223 |
|
|
Oct 12 06:24:27 PM UTC 24 |
Oct 12 06:25:48 PM UTC 24 |
290795127 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.1219705716 |
|
|
Oct 12 06:22:12 PM UTC 24 |
Oct 12 06:25:49 PM UTC 24 |
9367078860 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4095825781 |
|
|
Oct 12 06:25:17 PM UTC 24 |
Oct 12 06:25:53 PM UTC 24 |
278473632 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.1007378413 |
|
|
Oct 12 06:25:12 PM UTC 24 |
Oct 12 06:25:54 PM UTC 24 |
428094069 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.911803439 |
|
|
Oct 12 06:25:17 PM UTC 24 |
Oct 12 06:26:01 PM UTC 24 |
1396968367 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.2083664007 |
|
|
Oct 12 06:17:11 PM UTC 24 |
Oct 12 06:26:08 PM UTC 24 |
5127342393 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.3339954922 |
|
|
Oct 12 06:25:19 PM UTC 24 |
Oct 12 06:26:09 PM UTC 24 |
462647261 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.3101883974 |
|
|
Oct 12 06:25:57 PM UTC 24 |
Oct 12 06:26:10 PM UTC 24 |
221351927 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.2514187599 |
|
|
Oct 12 06:24:58 PM UTC 24 |
Oct 12 06:26:11 PM UTC 24 |
572945743 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2176784447 |
|
|
Oct 12 06:26:02 PM UTC 24 |
Oct 12 06:26:12 PM UTC 24 |
41688805 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.1860629252 |
|
|
Oct 12 06:23:41 PM UTC 24 |
Oct 12 06:26:25 PM UTC 24 |
9679921600 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.4268277525 |
|
|
Oct 12 06:26:12 PM UTC 24 |
Oct 12 06:26:31 PM UTC 24 |
119543489 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.216239514 |
|
|
Oct 12 06:24:49 PM UTC 24 |
Oct 12 06:26:40 PM UTC 24 |
9608425048 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1211575168 |
|
|
Oct 12 06:24:54 PM UTC 24 |
Oct 12 06:26:41 PM UTC 24 |
2187619814 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.3281257650 |
|
|
Oct 12 06:24:04 PM UTC 24 |
Oct 12 06:26:42 PM UTC 24 |
2055437776 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.3920850182 |
|
|
Oct 12 06:04:23 PM UTC 24 |
Oct 12 06:26:44 PM UTC 24 |
14832446070 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.579288608 |
|
|
Oct 12 06:26:32 PM UTC 24 |
Oct 12 06:26:58 PM UTC 24 |
843467693 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.810978745 |
|
|
Oct 12 06:26:25 PM UTC 24 |
Oct 12 06:26:58 PM UTC 24 |
1966687425 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.774601941 |
|
|
Oct 12 06:25:26 PM UTC 24 |
Oct 12 06:26:59 PM UTC 24 |
276761513 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.649841129 |
|
|
Oct 12 06:26:34 PM UTC 24 |
Oct 12 06:27:03 PM UTC 24 |
596450373 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.879297600 |
|
|
Oct 12 06:26:15 PM UTC 24 |
Oct 12 06:27:05 PM UTC 24 |
581271157 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1995118590 |
|
|
Oct 12 06:26:13 PM UTC 24 |
Oct 12 06:27:13 PM UTC 24 |
4003591064 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.2782709275 |
|
|
Oct 12 06:26:30 PM UTC 24 |
Oct 12 06:27:14 PM UTC 24 |
741791936 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3267542685 |
|
|
Oct 12 06:26:46 PM UTC 24 |
Oct 12 06:27:14 PM UTC 24 |
203726945 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.2799035653 |
|
|
Oct 12 06:26:33 PM UTC 24 |
Oct 12 06:27:18 PM UTC 24 |
1118264898 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1045220340 |
|
|
Oct 12 06:13:19 PM UTC 24 |
Oct 12 06:27:21 PM UTC 24 |
10923288070 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3731866205 |
|
|
Oct 12 06:24:50 PM UTC 24 |
Oct 12 06:27:25 PM UTC 24 |
6854571313 ps |