| T91 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1952700749 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:46:38 PM UTC 24 |
50887067 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.314582231 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:46:39 PM UTC 24 |
271512601 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.3564239081 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:46:44 PM UTC 24 |
43936535 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1676184677 |
|
|
Oct 12 05:46:22 PM UTC 24 |
Oct 12 05:46:44 PM UTC 24 |
283135544 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2481866788 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:46:51 PM UTC 24 |
968044874 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4114044338 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:46:53 PM UTC 24 |
218859263 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3763352871 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:46:53 PM UTC 24 |
400435640 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2279014248 |
|
|
Oct 12 05:46:48 PM UTC 24 |
Oct 12 05:46:56 PM UTC 24 |
55185316 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.1978056987 |
|
|
Oct 12 05:46:26 PM UTC 24 |
Oct 12 05:46:59 PM UTC 24 |
386923785 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3625447535 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:47:00 PM UTC 24 |
386586253 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.434866498 |
|
|
Oct 12 05:46:48 PM UTC 24 |
Oct 12 05:47:01 PM UTC 24 |
176160288 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.4207068843 |
|
|
Oct 12 05:46:22 PM UTC 24 |
Oct 12 05:47:03 PM UTC 24 |
1407269113 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.582137426 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:47:06 PM UTC 24 |
919615695 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.776959532 |
|
|
Oct 12 05:46:58 PM UTC 24 |
Oct 12 05:47:10 PM UTC 24 |
66488796 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1268565103 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:47:11 PM UTC 24 |
1013627511 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3501716583 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:47:15 PM UTC 24 |
1570914596 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.3597132820 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:47:15 PM UTC 24 |
5954973187 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.4163486078 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:47:18 PM UTC 24 |
452520603 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.1819319608 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:47:21 PM UTC 24 |
6295709714 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.647868197 |
|
|
Oct 12 05:46:26 PM UTC 24 |
Oct 12 05:47:23 PM UTC 24 |
1279994200 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2733142776 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:47:24 PM UTC 24 |
4666273530 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.964945850 |
|
|
Oct 12 05:46:54 PM UTC 24 |
Oct 12 05:47:42 PM UTC 24 |
483574340 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.2320829879 |
|
|
Oct 12 05:47:14 PM UTC 24 |
Oct 12 05:47:43 PM UTC 24 |
391665345 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.1912281734 |
|
|
Oct 12 05:47:04 PM UTC 24 |
Oct 12 05:47:51 PM UTC 24 |
642868908 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.1782378971 |
|
|
Oct 12 05:47:42 PM UTC 24 |
Oct 12 05:47:52 PM UTC 24 |
47885928 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3662310101 |
|
|
Oct 12 05:47:22 PM UTC 24 |
Oct 12 05:47:56 PM UTC 24 |
213876828 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.40117640 |
|
|
Oct 12 05:47:15 PM UTC 24 |
Oct 12 05:48:01 PM UTC 24 |
1399570563 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.2149244971 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:48:01 PM UTC 24 |
8138956080 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.962800246 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:48:02 PM UTC 24 |
149134863 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1703288288 |
|
|
Oct 12 05:47:53 PM UTC 24 |
Oct 12 05:48:03 PM UTC 24 |
47257111 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3785304082 |
|
|
Oct 12 05:47:23 PM UTC 24 |
Oct 12 05:48:16 PM UTC 24 |
75681114 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1359227084 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:48:16 PM UTC 24 |
6106542279 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.304789597 |
|
|
Oct 12 05:47:20 PM UTC 24 |
Oct 12 05:48:25 PM UTC 24 |
1464908499 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.2189155380 |
|
|
Oct 12 05:48:16 PM UTC 24 |
Oct 12 05:48:29 PM UTC 24 |
64514410 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3072467058 |
|
|
Oct 12 05:46:30 PM UTC 24 |
Oct 12 05:48:33 PM UTC 24 |
381873129 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.808956160 |
|
|
Oct 12 05:46:50 PM UTC 24 |
Oct 12 05:48:43 PM UTC 24 |
8027203374 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.2007301702 |
|
|
Oct 12 05:48:27 PM UTC 24 |
Oct 12 05:48:50 PM UTC 24 |
164128888 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.4204380795 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:48:50 PM UTC 24 |
3321071352 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3898493874 |
|
|
Oct 12 05:46:53 PM UTC 24 |
Oct 12 05:48:53 PM UTC 24 |
7213481385 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.29730427 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:53:30 PM UTC 24 |
5886001011 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3421920281 |
|
|
Oct 12 05:48:38 PM UTC 24 |
Oct 12 05:48:56 PM UTC 24 |
279362898 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.4275024144 |
|
|
Oct 12 05:48:38 PM UTC 24 |
Oct 12 05:49:02 PM UTC 24 |
169323857 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.1797609687 |
|
|
Oct 12 05:48:16 PM UTC 24 |
Oct 12 05:49:10 PM UTC 24 |
582291361 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1686762642 |
|
|
Oct 12 05:48:48 PM UTC 24 |
Oct 12 05:49:12 PM UTC 24 |
348805030 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.4001661476 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 05:49:23 PM UTC 24 |
3450506952 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1238366215 |
|
|
Oct 12 05:48:08 PM UTC 24 |
Oct 12 05:49:28 PM UTC 24 |
4533394253 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2192127460 |
|
|
Oct 12 05:48:25 PM UTC 24 |
Oct 12 05:49:33 PM UTC 24 |
1515982309 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.3553180906 |
|
|
Oct 12 05:46:39 PM UTC 24 |
Oct 12 05:49:49 PM UTC 24 |
3382544450 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3162164105 |
|
|
Oct 12 05:49:51 PM UTC 24 |
Oct 12 05:50:01 PM UTC 24 |
35271214 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2101722620 |
|
|
Oct 12 05:49:50 PM UTC 24 |
Oct 12 05:50:02 PM UTC 24 |
207235192 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.3259241597 |
|
|
Oct 12 05:48:06 PM UTC 24 |
Oct 12 05:50:08 PM UTC 24 |
10429348960 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.3911668545 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:50:12 PM UTC 24 |
4456204616 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.621412511 |
|
|
Oct 12 05:48:57 PM UTC 24 |
Oct 12 05:50:29 PM UTC 24 |
184001429 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.1292374686 |
|
|
Oct 12 05:50:26 PM UTC 24 |
Oct 12 05:51:03 PM UTC 24 |
296171078 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.3101448094 |
|
|
Oct 12 05:46:31 PM UTC 24 |
Oct 12 05:51:04 PM UTC 24 |
4963407345 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.733539209 |
|
|
Oct 12 05:46:27 PM UTC 24 |
Oct 12 05:51:08 PM UTC 24 |
3605252947 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.1504643548 |
|
|
Oct 12 05:47:31 PM UTC 24 |
Oct 12 05:51:18 PM UTC 24 |
4623057490 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.2096095814 |
|
|
Oct 12 05:49:57 PM UTC 24 |
Oct 12 05:51:19 PM UTC 24 |
6700946033 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.4206042868 |
|
|
Oct 12 05:50:25 PM UTC 24 |
Oct 12 05:51:23 PM UTC 24 |
1022037003 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.718217598 |
|
|
Oct 12 05:47:01 PM UTC 24 |
Oct 12 05:51:31 PM UTC 24 |
26361219496 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.4234279787 |
|
|
Oct 12 05:46:31 PM UTC 24 |
Oct 12 05:51:32 PM UTC 24 |
3538742690 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2800588655 |
|
|
Oct 12 05:46:31 PM UTC 24 |
Oct 12 05:51:36 PM UTC 24 |
4786674175 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.1741182483 |
|
|
Oct 12 05:51:36 PM UTC 24 |
Oct 12 05:51:43 PM UTC 24 |
44598986 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.205952895 |
|
|
Oct 12 05:51:27 PM UTC 24 |
Oct 12 05:51:44 PM UTC 24 |
143522733 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2485104722 |
|
|
Oct 12 05:51:43 PM UTC 24 |
Oct 12 05:51:59 PM UTC 24 |
80371249 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.3725803089 |
|
|
Oct 12 05:48:20 PM UTC 24 |
Oct 12 05:51:59 PM UTC 24 |
22982704460 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1050213512 |
|
|
Oct 12 05:49:46 PM UTC 24 |
Oct 12 05:52:08 PM UTC 24 |
2689402579 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3960255779 |
|
|
Oct 12 05:50:12 PM UTC 24 |
Oct 12 05:52:11 PM UTC 24 |
5396550658 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.862387277 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 05:52:14 PM UTC 24 |
3840799594 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.2917671597 |
|
|
Oct 12 05:48:24 PM UTC 24 |
Oct 12 05:52:19 PM UTC 24 |
14383620949 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.2456181524 |
|
|
Oct 12 05:51:33 PM UTC 24 |
Oct 12 05:52:22 PM UTC 24 |
577382265 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3049037474 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:52:22 PM UTC 24 |
39464592512 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.23443452 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:52:27 PM UTC 24 |
6637167784 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3217860305 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:52:33 PM UTC 24 |
7905122307 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3182737092 |
|
|
Oct 12 05:52:36 PM UTC 24 |
Oct 12 05:52:44 PM UTC 24 |
42942078 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2500474880 |
|
|
Oct 12 05:52:35 PM UTC 24 |
Oct 12 05:52:45 PM UTC 24 |
48788134 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.111093529 |
|
|
Oct 12 05:50:53 PM UTC 24 |
Oct 12 05:52:45 PM UTC 24 |
2770228654 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3600271373 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:53:07 PM UTC 24 |
28023085309 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2280425719 |
|
|
Oct 12 05:51:58 PM UTC 24 |
Oct 12 05:53:18 PM UTC 24 |
449176876 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2098182069 |
|
|
Oct 12 05:46:30 PM UTC 24 |
Oct 12 05:53:22 PM UTC 24 |
976374621 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.4145023718 |
|
|
Oct 12 05:46:25 PM UTC 24 |
Oct 12 05:53:33 PM UTC 24 |
21558574208 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.636579521 |
|
|
Oct 12 05:47:46 PM UTC 24 |
Oct 12 05:53:38 PM UTC 24 |
3844297752 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.2433200830 |
|
|
Oct 12 05:51:55 PM UTC 24 |
Oct 12 05:53:42 PM UTC 24 |
1244514812 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.897851142 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 05:53:46 PM UTC 24 |
13030045795 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1947786586 |
|
|
Oct 12 05:52:50 PM UTC 24 |
Oct 12 05:53:51 PM UTC 24 |
493781494 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1775170308 |
|
|
Oct 12 05:46:22 PM UTC 24 |
Oct 12 05:53:54 PM UTC 24 |
29779720865 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.1272048093 |
|
|
Oct 12 05:53:10 PM UTC 24 |
Oct 12 05:54:04 PM UTC 24 |
521691139 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3646786650 |
|
|
Oct 12 05:53:54 PM UTC 24 |
Oct 12 05:54:09 PM UTC 24 |
176343578 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.1523908285 |
|
|
Oct 12 05:52:39 PM UTC 24 |
Oct 12 05:54:10 PM UTC 24 |
6020654647 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1925659176 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:54:12 PM UTC 24 |
34293000225 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.954931679 |
|
|
Oct 12 05:52:46 PM UTC 24 |
Oct 12 05:54:12 PM UTC 24 |
5276786561 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.3483661092 |
|
|
Oct 12 05:52:45 PM UTC 24 |
Oct 12 05:54:19 PM UTC 24 |
1799728368 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1485287399 |
|
|
Oct 12 05:46:32 PM UTC 24 |
Oct 12 05:54:19 PM UTC 24 |
7206448478 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3490692191 |
|
|
Oct 12 05:47:24 PM UTC 24 |
Oct 12 05:54:21 PM UTC 24 |
11476003623 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.426300912 |
|
|
Oct 12 05:53:46 PM UTC 24 |
Oct 12 05:54:28 PM UTC 24 |
314530013 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.1542267254 |
|
|
Oct 12 05:53:42 PM UTC 24 |
Oct 12 05:54:29 PM UTC 24 |
531240336 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.3895607310 |
|
|
Oct 12 05:53:31 PM UTC 24 |
Oct 12 05:54:31 PM UTC 24 |
1394599096 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2470372802 |
|
|
Oct 12 05:46:47 PM UTC 24 |
Oct 12 05:54:40 PM UTC 24 |
10088862899 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.2821400597 |
|
|
Oct 12 05:54:33 PM UTC 24 |
Oct 12 05:54:41 PM UTC 24 |
48626053 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2008589988 |
|
|
Oct 12 05:54:33 PM UTC 24 |
Oct 12 05:54:43 PM UTC 24 |
55664958 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1375194006 |
|
|
Oct 12 05:49:15 PM UTC 24 |
Oct 12 05:54:45 PM UTC 24 |
5170546856 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.117640048 |
|
|
Oct 12 05:49:26 PM UTC 24 |
Oct 12 05:54:53 PM UTC 24 |
3585625912 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3408943422 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 05:55:00 PM UTC 24 |
5460131929 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2384748338 |
|
|
Oct 12 05:47:24 PM UTC 24 |
Oct 12 05:55:09 PM UTC 24 |
10681588742 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1026805635 |
|
|
Oct 12 05:46:35 PM UTC 24 |
Oct 12 05:55:21 PM UTC 24 |
5064265889 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.462355301 |
|
|
Oct 12 05:54:44 PM UTC 24 |
Oct 12 05:55:25 PM UTC 24 |
313284940 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.2227580972 |
|
|
Oct 12 05:47:03 PM UTC 24 |
Oct 12 05:55:28 PM UTC 24 |
36198424844 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.1564619412 |
|
|
Oct 12 05:54:41 PM UTC 24 |
Oct 12 05:55:33 PM UTC 24 |
492284776 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.2344940584 |
|
|
Oct 12 05:55:08 PM UTC 24 |
Oct 12 05:55:37 PM UTC 24 |
447353235 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.221504066 |
|
|
Oct 12 05:49:07 PM UTC 24 |
Oct 12 05:55:42 PM UTC 24 |
4705777846 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.3796609472 |
|
|
Oct 12 05:50:32 PM UTC 24 |
Oct 12 05:55:47 PM UTC 24 |
28156774179 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1695550766 |
|
|
Oct 12 05:55:47 PM UTC 24 |
Oct 12 05:55:54 PM UTC 24 |
7209289 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.4023563852 |
|
|
Oct 12 05:55:16 PM UTC 24 |
Oct 12 05:55:54 PM UTC 24 |
255975910 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.3773433523 |
|
|
Oct 12 05:55:08 PM UTC 24 |
Oct 12 05:55:56 PM UTC 24 |
1364626783 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.758202117 |
|
|
Oct 12 05:46:48 PM UTC 24 |
Oct 12 05:55:58 PM UTC 24 |
13187464842 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.2856654630 |
|
|
Oct 12 05:55:03 PM UTC 24 |
Oct 12 05:55:59 PM UTC 24 |
1559501736 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.3457932471 |
|
|
Oct 12 05:54:35 PM UTC 24 |
Oct 12 05:56:00 PM UTC 24 |
8513520213 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.3016354406 |
|
|
Oct 12 05:48:51 PM UTC 24 |
Oct 12 05:56:15 PM UTC 24 |
10687073632 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2746230202 |
|
|
Oct 12 05:54:41 PM UTC 24 |
Oct 12 05:56:23 PM UTC 24 |
5690807382 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2338396608 |
|
|
Oct 12 05:54:02 PM UTC 24 |
Oct 12 05:56:23 PM UTC 24 |
314374019 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.1786800213 |
|
|
Oct 12 05:56:10 PM UTC 24 |
Oct 12 05:56:24 PM UTC 24 |
197833703 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.4229005522 |
|
|
Oct 12 05:58:58 PM UTC 24 |
Oct 12 05:59:09 PM UTC 24 |
44735632 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2805358133 |
|
|
Oct 12 05:56:17 PM UTC 24 |
Oct 12 05:56:25 PM UTC 24 |
47028819 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.2467978679 |
|
|
Oct 12 05:54:53 PM UTC 24 |
Oct 12 05:56:27 PM UTC 24 |
1490323177 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2240995679 |
|
|
Oct 12 05:51:51 PM UTC 24 |
Oct 12 05:56:31 PM UTC 24 |
721666469 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.4129779960 |
|
|
Oct 12 05:49:18 PM UTC 24 |
Oct 12 05:56:32 PM UTC 24 |
3691841611 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2732291427 |
|
|
Oct 12 05:47:29 PM UTC 24 |
Oct 12 05:56:36 PM UTC 24 |
10220676237 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.2077639118 |
|
|
Oct 12 05:53:09 PM UTC 24 |
Oct 12 05:56:37 PM UTC 24 |
10887458383 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2142944219 |
|
|
Oct 12 05:52:31 PM UTC 24 |
Oct 12 05:56:39 PM UTC 24 |
3121340568 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.1984151433 |
|
|
Oct 12 05:55:45 PM UTC 24 |
Oct 12 05:56:39 PM UTC 24 |
1785850230 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.2906256594 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 05:56:48 PM UTC 24 |
5577060683 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.694214284 |
|
|
Oct 12 05:56:21 PM UTC 24 |
Oct 12 05:56:48 PM UTC 24 |
592877404 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.3745002690 |
|
|
Oct 12 05:54:48 PM UTC 24 |
Oct 12 05:56:49 PM UTC 24 |
13488786826 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.20422046 |
|
|
Oct 12 05:56:48 PM UTC 24 |
Oct 12 05:57:15 PM UTC 24 |
285414736 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.1213709360 |
|
|
Oct 12 05:50:36 PM UTC 24 |
Oct 12 05:57:17 PM UTC 24 |
27634513576 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.3638024049 |
|
|
Oct 12 05:55:24 PM UTC 24 |
Oct 12 05:57:21 PM UTC 24 |
1562835694 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.2562272777 |
|
|
Oct 12 05:56:20 PM UTC 24 |
Oct 12 05:57:22 PM UTC 24 |
596264141 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.1174741920 |
|
|
Oct 12 05:57:13 PM UTC 24 |
Oct 12 05:57:22 PM UTC 24 |
46754771 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.107349158 |
|
|
Oct 12 05:56:51 PM UTC 24 |
Oct 12 05:57:26 PM UTC 24 |
839935279 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2784415704 |
|
|
Oct 12 05:56:17 PM UTC 24 |
Oct 12 05:57:41 PM UTC 24 |
5677234682 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.941475225 |
|
|
Oct 12 05:56:46 PM UTC 24 |
Oct 12 05:57:44 PM UTC 24 |
486094301 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.2779367850 |
|
|
Oct 12 05:56:48 PM UTC 24 |
Oct 12 05:57:46 PM UTC 24 |
1755308854 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.4088706937 |
|
|
Oct 12 05:54:30 PM UTC 24 |
Oct 12 05:57:48 PM UTC 24 |
3363040920 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.1779954564 |
|
|
Oct 12 05:56:49 PM UTC 24 |
Oct 12 05:57:48 PM UTC 24 |
1039900409 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.4030663660 |
|
|
Oct 12 05:57:39 PM UTC 24 |
Oct 12 05:57:50 PM UTC 24 |
54869745 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.611295509 |
|
|
Oct 12 05:49:20 PM UTC 24 |
Oct 12 05:57:53 PM UTC 24 |
5791703153 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1253926492 |
|
|
Oct 12 05:56:56 PM UTC 24 |
Oct 12 05:57:57 PM UTC 24 |
78405203 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.92736402 |
|
|
Oct 12 05:56:18 PM UTC 24 |
Oct 12 05:58:01 PM UTC 24 |
10437140687 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.1347009468 |
|
|
Oct 12 05:54:04 PM UTC 24 |
Oct 12 05:58:02 PM UTC 24 |
3027131006 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.390367429 |
|
|
Oct 12 05:47:32 PM UTC 24 |
Oct 12 05:58:07 PM UTC 24 |
6128598638 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.1251953175 |
|
|
Oct 12 05:57:42 PM UTC 24 |
Oct 12 05:58:15 PM UTC 24 |
366456432 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.568153340 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:58:22 PM UTC 24 |
16562182268 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.852918893 |
|
|
Oct 12 05:57:44 PM UTC 24 |
Oct 12 05:58:28 PM UTC 24 |
880159932 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.521165615 |
|
|
Oct 12 05:58:11 PM UTC 24 |
Oct 12 05:58:33 PM UTC 24 |
386984097 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.294446662 |
|
|
Oct 12 05:58:12 PM UTC 24 |
Oct 12 05:58:36 PM UTC 24 |
188524131 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.903006297 |
|
|
Oct 12 05:57:45 PM UTC 24 |
Oct 12 05:58:37 PM UTC 24 |
3182885963 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1975576109 |
|
|
Oct 12 05:49:12 PM UTC 24 |
Oct 12 05:58:38 PM UTC 24 |
3518387999 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3463188307 |
|
|
Oct 12 05:54:10 PM UTC 24 |
Oct 12 05:58:42 PM UTC 24 |
4627319463 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.2002405308 |
|
|
Oct 12 05:58:12 PM UTC 24 |
Oct 12 05:58:47 PM UTC 24 |
334925141 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.269020905 |
|
|
Oct 12 05:51:47 PM UTC 24 |
Oct 12 05:58:50 PM UTC 24 |
11926884571 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1880680356 |
|
|
Oct 12 05:58:17 PM UTC 24 |
Oct 12 05:58:50 PM UTC 24 |
215371855 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1395476422 |
|
|
Oct 12 05:58:22 PM UTC 24 |
Oct 12 05:59:08 PM UTC 24 |
174850219 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1926787194 |
|
|
Oct 12 05:59:01 PM UTC 24 |
Oct 12 05:59:10 PM UTC 24 |
43731101 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.885581807 |
|
|
Oct 12 05:57:40 PM UTC 24 |
Oct 12 05:59:19 PM UTC 24 |
9235888999 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1477117805 |
|
|
Oct 12 05:59:12 PM UTC 24 |
Oct 12 05:59:33 PM UTC 24 |
541429985 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.882617599 |
|
|
Oct 12 05:59:12 PM UTC 24 |
Oct 12 05:59:38 PM UTC 24 |
175883114 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.1953191202 |
|
|
Oct 12 05:56:36 PM UTC 24 |
Oct 12 05:59:45 PM UTC 24 |
10786944390 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.3996000883 |
|
|
Oct 12 05:54:15 PM UTC 24 |
Oct 12 05:59:58 PM UTC 24 |
4462688055 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2938087802 |
|
|
Oct 12 05:56:47 PM UTC 24 |
Oct 12 06:00:04 PM UTC 24 |
13671867189 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4139143364 |
|
|
Oct 12 05:47:13 PM UTC 24 |
Oct 12 06:00:15 PM UTC 24 |
59104069969 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1176263810 |
|
|
Oct 12 05:55:00 PM UTC 24 |
Oct 12 06:00:18 PM UTC 24 |
22724711378 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1083791018 |
|
|
Oct 12 05:52:21 PM UTC 24 |
Oct 12 06:00:19 PM UTC 24 |
4846391636 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.3518787868 |
|
|
Oct 12 05:57:46 PM UTC 24 |
Oct 12 06:00:19 PM UTC 24 |
10714489616 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.2541939830 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 06:00:24 PM UTC 24 |
7757946708 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.538630832 |
|
|
Oct 12 05:58:05 PM UTC 24 |
Oct 12 06:00:29 PM UTC 24 |
3464629364 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2522788920 |
|
|
Oct 12 06:00:09 PM UTC 24 |
Oct 12 06:00:30 PM UTC 24 |
119885944 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.3744515916 |
|
|
Oct 12 05:59:31 PM UTC 24 |
Oct 12 06:00:34 PM UTC 24 |
402607579 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1205725447 |
|
|
Oct 12 05:48:23 PM UTC 24 |
Oct 12 06:00:45 PM UTC 24 |
46091970282 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3649995367 |
|
|
Oct 12 05:46:23 PM UTC 24 |
Oct 12 06:00:50 PM UTC 24 |
15256343689 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.1945104780 |
|
|
Oct 12 05:59:42 PM UTC 24 |
Oct 12 06:00:52 PM UTC 24 |
2078125958 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.2981862071 |
|
|
Oct 12 06:00:00 PM UTC 24 |
Oct 12 06:00:56 PM UTC 24 |
953090023 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2443125436 |
|
|
Oct 12 05:59:03 PM UTC 24 |
Oct 12 06:00:57 PM UTC 24 |
7256954577 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.429769557 |
|
|
Oct 12 05:59:05 PM UTC 24 |
Oct 12 06:01:04 PM UTC 24 |
5375428638 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.206199739 |
|
|
Oct 12 06:00:54 PM UTC 24 |
Oct 12 06:01:09 PM UTC 24 |
229579469 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2642152984 |
|
|
Oct 12 06:00:58 PM UTC 24 |
Oct 12 06:01:10 PM UTC 24 |
57513726 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.2481005608 |
|
|
Oct 12 05:59:57 PM UTC 24 |
Oct 12 06:01:19 PM UTC 24 |
2749553281 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.77944670 |
|
|
Oct 12 05:53:57 PM UTC 24 |
Oct 12 06:01:31 PM UTC 24 |
4539973442 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.2345462208 |
|
|
Oct 12 06:01:33 PM UTC 24 |
Oct 12 06:01:43 PM UTC 24 |
19336213 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1465371240 |
|
|
Oct 12 06:01:20 PM UTC 24 |
Oct 12 06:01:53 PM UTC 24 |
227412486 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.3984490432 |
|
|
Oct 12 05:46:24 PM UTC 24 |
Oct 12 06:01:57 PM UTC 24 |
9127489624 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.340837351 |
|
|
Oct 12 06:01:40 PM UTC 24 |
Oct 12 06:01:58 PM UTC 24 |
127087002 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.230429888 |
|
|
Oct 12 05:52:55 PM UTC 24 |
Oct 12 06:02:06 PM UTC 24 |
46856987722 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.2138543012 |
|
|
Oct 12 06:01:55 PM UTC 24 |
Oct 12 06:02:06 PM UTC 24 |
52080419 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.1901667794 |
|
|
Oct 12 05:58:26 PM UTC 24 |
Oct 12 06:02:11 PM UTC 24 |
6765596715 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.1714604429 |
|
|
Oct 12 06:01:20 PM UTC 24 |
Oct 12 06:02:20 PM UTC 24 |
4408228991 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2154221850 |
|
|
Oct 12 06:00:21 PM UTC 24 |
Oct 12 06:02:22 PM UTC 24 |
1301400699 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.191349382 |
|
|
Oct 12 05:55:52 PM UTC 24 |
Oct 12 06:02:33 PM UTC 24 |
4578384628 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.904022417 |
|
|
Oct 12 05:58:04 PM UTC 24 |
Oct 12 06:02:34 PM UTC 24 |
15603385420 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2389164635 |
|
|
Oct 12 05:47:36 PM UTC 24 |
Oct 12 06:02:36 PM UTC 24 |
9366647051 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1486532181 |
|
|
Oct 12 06:00:40 PM UTC 24 |
Oct 12 06:02:41 PM UTC 24 |
264691049 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2111228644 |
|
|
Oct 12 06:01:15 PM UTC 24 |
Oct 12 06:02:48 PM UTC 24 |
2391677238 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2205662304 |
|
|
Oct 12 06:02:05 PM UTC 24 |
Oct 12 06:02:49 PM UTC 24 |
1176863389 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.1248507850 |
|
|
Oct 12 05:56:05 PM UTC 24 |
Oct 12 06:02:49 PM UTC 24 |
4587844779 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.797544010 |
|
|
Oct 12 06:01:13 PM UTC 24 |
Oct 12 06:02:59 PM UTC 24 |
5251907768 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.2500394170 |
|
|
Oct 12 05:54:51 PM UTC 24 |
Oct 12 06:03:01 PM UTC 24 |
31714945572 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1760825332 |
|
|
Oct 12 06:02:17 PM UTC 24 |
Oct 12 06:03:06 PM UTC 24 |
893479035 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2711942796 |
|
|
Oct 12 06:02:59 PM UTC 24 |
Oct 12 06:03:07 PM UTC 24 |
43666059 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.3471105597 |
|
|
Oct 12 06:01:08 PM UTC 24 |
Oct 12 06:03:10 PM UTC 24 |
8856424642 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.703794507 |
|
|
Oct 12 06:02:57 PM UTC 24 |
Oct 12 06:03:11 PM UTC 24 |
225552118 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.2978936710 |
|
|
Oct 12 05:52:06 PM UTC 24 |
Oct 12 06:03:15 PM UTC 24 |
5895996992 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.873025423 |
|
|
Oct 12 05:58:20 PM UTC 24 |
Oct 12 06:03:19 PM UTC 24 |
7430755740 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.1293387232 |
|
|
Oct 12 05:57:02 PM UTC 24 |
Oct 12 06:03:29 PM UTC 24 |
4022723610 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.902771168 |
|
|
Oct 12 06:03:11 PM UTC 24 |
Oct 12 06:03:34 PM UTC 24 |
186916726 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.1861108128 |
|
|
Oct 12 06:03:12 PM UTC 24 |
Oct 12 06:03:50 PM UTC 24 |
926136030 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.4154619337 |
|
|
Oct 12 05:56:25 PM UTC 24 |
Oct 12 06:03:52 PM UTC 24 |
50096437862 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.67787506 |
|
|
Oct 12 06:03:35 PM UTC 24 |
Oct 12 06:03:57 PM UTC 24 |
559288066 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1357332740 |
|
|
Oct 12 06:03:42 PM UTC 24 |
Oct 12 06:03:59 PM UTC 24 |
236368987 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3695765212 |
|
|
Oct 12 05:58:57 PM UTC 24 |
Oct 12 06:04:02 PM UTC 24 |
3462305588 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.745255274 |
|
|
Oct 12 06:03:32 PM UTC 24 |
Oct 12 06:04:06 PM UTC 24 |
759631497 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2960675817 |
|
|
Oct 12 05:51:26 PM UTC 24 |
Oct 12 06:04:08 PM UTC 24 |
47356149393 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.2001336603 |
|
|
Oct 12 05:57:02 PM UTC 24 |
Oct 12 06:04:19 PM UTC 24 |
12219886011 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.1372887103 |
|
|
Oct 12 06:03:39 PM UTC 24 |
Oct 12 06:04:28 PM UTC 24 |
1129813557 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.1714496435 |
|
|
Oct 12 06:03:02 PM UTC 24 |
Oct 12 06:04:29 PM UTC 24 |
8559266688 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.2838739753 |
|
|
Oct 12 06:04:13 PM UTC 24 |
Oct 12 06:04:30 PM UTC 24 |
168148366 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.128494441 |
|
|
Oct 12 06:04:30 PM UTC 24 |
Oct 12 06:04:39 PM UTC 24 |
55331108 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1547168244 |
|
|
Oct 12 06:04:42 PM UTC 24 |
Oct 12 06:04:53 PM UTC 24 |
44649878 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2066443222 |
|
|
Oct 12 05:53:09 PM UTC 24 |
Oct 12 06:04:57 PM UTC 24 |
47224893687 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3726291325 |
|
|
Oct 12 06:03:11 PM UTC 24 |
Oct 12 06:04:58 PM UTC 24 |
6621714425 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.3609559182 |
|
|
Oct 12 05:57:11 PM UTC 24 |
Oct 12 06:05:03 PM UTC 24 |
4848813964 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.621661438 |
|
|
Oct 12 05:59:14 PM UTC 24 |
Oct 12 06:05:03 PM UTC 24 |
37076003042 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.914224432 |
|
|
Oct 12 06:00:38 PM UTC 24 |
Oct 12 06:05:06 PM UTC 24 |
9037283121 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.943877251 |
|
|
Oct 12 06:03:28 PM UTC 24 |
Oct 12 06:05:12 PM UTC 24 |
2204731501 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.4046762531 |
|
|
Oct 12 06:05:02 PM UTC 24 |
Oct 12 06:05:27 PM UTC 24 |
175773233 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.913313460 |
|
|
Oct 12 06:03:56 PM UTC 24 |
Oct 12 06:05:27 PM UTC 24 |
107756152 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1161113212 |
|
|
Oct 12 06:04:50 PM UTC 24 |
Oct 12 06:05:28 PM UTC 24 |
469211634 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.3339000336 |
|
|
Oct 12 05:58:38 PM UTC 24 |
Oct 12 06:05:31 PM UTC 24 |
4664002902 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.194188745 |
|
|
Oct 12 06:03:54 PM UTC 24 |
Oct 12 06:05:47 PM UTC 24 |
1059368698 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4186482659 |
|
|
Oct 12 06:02:21 PM UTC 24 |
Oct 12 06:05:49 PM UTC 24 |
1393309406 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3430367443 |
|
|
Oct 12 05:58:02 PM UTC 24 |
Oct 12 06:05:49 PM UTC 24 |
31705480445 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.490035253 |
|
|
Oct 12 06:00:42 PM UTC 24 |
Oct 12 06:05:52 PM UTC 24 |
4162739416 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1434249796 |
|
|
Oct 12 05:58:29 PM UTC 24 |
Oct 12 06:05:59 PM UTC 24 |
7289900781 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.4224011953 |
|
|
Oct 12 06:04:50 PM UTC 24 |
Oct 12 06:06:02 PM UTC 24 |
8369011436 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.473038945 |
|
|
Oct 12 06:02:20 PM UTC 24 |
Oct 12 06:06:12 PM UTC 24 |
2890148979 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.1901884125 |
|
|
Oct 12 06:05:27 PM UTC 24 |
Oct 12 06:06:15 PM UTC 24 |
1281927769 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.742336619 |
|
|
Oct 12 06:05:36 PM UTC 24 |
Oct 12 06:06:17 PM UTC 24 |
240496016 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1070597935 |
|
|
Oct 12 06:04:53 PM UTC 24 |
Oct 12 06:06:22 PM UTC 24 |
5732791842 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.3837275219 |
|
|
Oct 12 06:05:19 PM UTC 24 |
Oct 12 06:06:23 PM UTC 24 |
1332199171 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.469081701 |
|
|
Oct 12 06:05:50 PM UTC 24 |
Oct 12 06:06:26 PM UTC 24 |
716166446 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1194768389 |
|
|
Oct 12 06:05:25 PM UTC 24 |
Oct 12 06:06:30 PM UTC 24 |
2190835628 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.3749009947 |
|
|
Oct 12 06:06:25 PM UTC 24 |
Oct 12 06:06:36 PM UTC 24 |
50576621 ps |