| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1421806889 |
|
|
Oct 12 06:27:19 PM UTC 24 |
Oct 12 06:27:30 PM UTC 24 |
54684464 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1043568175 |
|
|
Oct 12 06:27:20 PM UTC 24 |
Oct 12 06:27:32 PM UTC 24 |
147329150 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.283400037 |
|
|
Oct 12 06:27:29 PM UTC 24 |
Oct 12 06:27:42 PM UTC 24 |
69628164 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.3621617634 |
|
|
Oct 12 06:21:39 PM UTC 24 |
Oct 12 06:27:46 PM UTC 24 |
9716786483 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2927446938 |
|
|
Oct 12 06:26:06 PM UTC 24 |
Oct 12 06:27:50 PM UTC 24 |
7980428786 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.540967808 |
|
|
Oct 12 06:25:04 PM UTC 24 |
Oct 12 06:28:11 PM UTC 24 |
17435998633 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.4184889885 |
|
|
Oct 12 05:56:00 PM UTC 24 |
Oct 12 06:28:22 PM UTC 24 |
15542440277 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.4034661851 |
|
|
Oct 12 06:28:05 PM UTC 24 |
Oct 12 06:28:22 PM UTC 24 |
241712639 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.3733000698 |
|
|
Oct 12 06:27:35 PM UTC 24 |
Oct 12 06:28:24 PM UTC 24 |
593370373 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.4230756828 |
|
|
Oct 12 06:25:18 PM UTC 24 |
Oct 12 06:28:25 PM UTC 24 |
3921667041 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.33187803 |
|
|
Oct 12 06:27:49 PM UTC 24 |
Oct 12 06:28:26 PM UTC 24 |
325491515 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.743058489 |
|
|
Oct 12 06:23:09 PM UTC 24 |
Oct 12 06:28:26 PM UTC 24 |
3940894745 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.66957675 |
|
|
Oct 12 06:27:41 PM UTC 24 |
Oct 12 06:28:27 PM UTC 24 |
370961151 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.3471751694 |
|
|
Oct 12 06:22:11 PM UTC 24 |
Oct 12 06:28:34 PM UTC 24 |
38315005591 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.3980973974 |
|
|
Oct 12 06:27:54 PM UTC 24 |
Oct 12 06:28:36 PM UTC 24 |
759318197 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3688212525 |
|
|
Oct 12 06:27:26 PM UTC 24 |
Oct 12 06:28:42 PM UTC 24 |
5398322242 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.1404831395 |
|
|
Oct 12 06:23:35 PM UTC 24 |
Oct 12 06:28:51 PM UTC 24 |
31260896512 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.3515556311 |
|
|
Oct 12 06:27:54 PM UTC 24 |
Oct 12 06:28:51 PM UTC 24 |
1746427764 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.2090392546 |
|
|
Oct 12 06:27:36 PM UTC 24 |
Oct 12 06:28:54 PM UTC 24 |
5230306979 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1873852382 |
|
|
Oct 12 06:28:46 PM UTC 24 |
Oct 12 06:28:56 PM UTC 24 |
39396203 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2257993206 |
|
|
Oct 12 06:28:45 PM UTC 24 |
Oct 12 06:29:00 PM UTC 24 |
231133884 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.4128895862 |
|
|
Oct 12 06:27:22 PM UTC 24 |
Oct 12 06:29:00 PM UTC 24 |
9740800928 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.2430890922 |
|
|
Oct 12 06:25:08 PM UTC 24 |
Oct 12 06:29:01 PM UTC 24 |
13164996665 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.2286734418 |
|
|
Oct 12 06:29:12 PM UTC 24 |
Oct 12 06:29:32 PM UTC 24 |
462215213 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.2818511775 |
|
|
Oct 12 06:24:31 PM UTC 24 |
Oct 12 06:29:34 PM UTC 24 |
3750479412 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3476041611 |
|
|
Oct 12 06:29:17 PM UTC 24 |
Oct 12 06:29:47 PM UTC 24 |
963182219 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.2290364121 |
|
|
Oct 12 06:28:49 PM UTC 24 |
Oct 12 06:29:51 PM UTC 24 |
6745616176 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.4256188179 |
|
|
Oct 12 06:28:57 PM UTC 24 |
Oct 12 06:29:56 PM UTC 24 |
560031831 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.774513280 |
|
|
Oct 12 06:27:05 PM UTC 24 |
Oct 12 06:29:57 PM UTC 24 |
1017562542 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.475015404 |
|
|
Oct 12 06:29:19 PM UTC 24 |
Oct 12 06:30:09 PM UTC 24 |
1037806532 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.3351728703 |
|
|
Oct 12 06:29:22 PM UTC 24 |
Oct 12 06:30:09 PM UTC 24 |
883466135 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.2436430799 |
|
|
Oct 12 06:19:27 PM UTC 24 |
Oct 12 06:30:12 PM UTC 24 |
6366297750 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1127894288 |
|
|
Oct 12 06:19:18 PM UTC 24 |
Oct 12 06:30:13 PM UTC 24 |
5493147758 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.1627318824 |
|
|
Oct 12 06:28:50 PM UTC 24 |
Oct 12 06:30:21 PM UTC 24 |
2092025030 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2081904882 |
|
|
Oct 12 06:29:23 PM UTC 24 |
Oct 12 06:30:22 PM UTC 24 |
1050275308 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.656976538 |
|
|
Oct 12 06:28:58 PM UTC 24 |
Oct 12 06:30:23 PM UTC 24 |
5266436411 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3493262801 |
|
|
Oct 12 06:30:19 PM UTC 24 |
Oct 12 06:30:29 PM UTC 24 |
53393526 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3171922934 |
|
|
Oct 12 06:28:48 PM UTC 24 |
Oct 12 06:30:31 PM UTC 24 |
4443567924 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.322858547 |
|
|
Oct 12 06:30:18 PM UTC 24 |
Oct 12 06:30:31 PM UTC 24 |
219761347 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.1767393005 |
|
|
Oct 12 06:28:32 PM UTC 24 |
Oct 12 06:30:37 PM UTC 24 |
3340426237 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2850034241 |
|
|
Oct 12 06:23:47 PM UTC 24 |
Oct 12 06:30:58 PM UTC 24 |
33012825368 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.3956110480 |
|
|
Oct 12 06:25:34 PM UTC 24 |
Oct 12 06:31:11 PM UTC 24 |
9918424512 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.2711992816 |
|
|
Oct 12 05:57:09 PM UTC 24 |
Oct 12 06:31:12 PM UTC 24 |
16938797742 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.725285159 |
|
|
Oct 12 06:30:45 PM UTC 24 |
Oct 12 06:31:15 PM UTC 24 |
252794773 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1954736509 |
|
|
Oct 12 06:17:02 PM UTC 24 |
Oct 12 06:31:17 PM UTC 24 |
10283384488 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3205107357 |
|
|
Oct 12 06:30:08 PM UTC 24 |
Oct 12 06:31:20 PM UTC 24 |
267158212 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4285583180 |
|
|
Oct 12 06:18:34 PM UTC 24 |
Oct 12 06:31:23 PM UTC 24 |
50350205994 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.2501947037 |
|
|
Oct 12 06:00:48 PM UTC 24 |
Oct 12 06:31:31 PM UTC 24 |
15134342035 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.3500605565 |
|
|
Oct 12 06:30:54 PM UTC 24 |
Oct 12 06:31:31 PM UTC 24 |
346811958 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.2578598815 |
|
|
Oct 12 06:30:37 PM UTC 24 |
Oct 12 06:31:32 PM UTC 24 |
437759668 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1684225350 |
|
|
Oct 12 06:31:22 PM UTC 24 |
Oct 12 06:31:34 PM UTC 24 |
37995693 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.2158858607 |
|
|
Oct 12 06:30:34 PM UTC 24 |
Oct 12 06:31:35 PM UTC 24 |
1686925401 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.3021225694 |
|
|
Oct 12 06:29:03 PM UTC 24 |
Oct 12 06:31:35 PM UTC 24 |
10025742444 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.170553651 |
|
|
Oct 12 06:30:33 PM UTC 24 |
Oct 12 06:31:41 PM UTC 24 |
6356980716 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.1888566646 |
|
|
Oct 12 06:30:55 PM UTC 24 |
Oct 12 06:31:41 PM UTC 24 |
522303459 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.3486114106 |
|
|
Oct 12 06:30:44 PM UTC 24 |
Oct 12 06:31:42 PM UTC 24 |
4998476385 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.4059865427 |
|
|
Oct 12 06:25:51 PM UTC 24 |
Oct 12 06:31:54 PM UTC 24 |
4774518856 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.111970399 |
|
|
Oct 12 06:31:45 PM UTC 24 |
Oct 12 06:31:54 PM UTC 24 |
42534296 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1158971825 |
|
|
Oct 12 06:30:59 PM UTC 24 |
Oct 12 06:31:58 PM UTC 24 |
1374650589 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2705968364 |
|
|
Oct 12 06:21:35 PM UTC 24 |
Oct 12 06:31:58 PM UTC 24 |
4338245140 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2682666307 |
|
|
Oct 12 06:31:51 PM UTC 24 |
Oct 12 06:32:01 PM UTC 24 |
45298087 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2835432814 |
|
|
Oct 12 06:27:04 PM UTC 24 |
Oct 12 06:32:05 PM UTC 24 |
2992827896 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.304047760 |
|
|
Oct 12 06:30:30 PM UTC 24 |
Oct 12 06:32:16 PM UTC 24 |
6714114962 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1390043763 |
|
|
Oct 12 06:31:57 PM UTC 24 |
Oct 12 06:32:23 PM UTC 24 |
272577930 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.3041721273 |
|
|
Oct 12 05:49:36 PM UTC 24 |
Oct 12 06:32:32 PM UTC 24 |
17778242330 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2933936390 |
|
|
Oct 12 06:32:20 PM UTC 24 |
Oct 12 06:32:35 PM UTC 24 |
84973223 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1022652896 |
|
|
Oct 12 06:27:03 PM UTC 24 |
Oct 12 06:32:35 PM UTC 24 |
10217747076 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.2105031688 |
|
|
Oct 12 06:31:55 PM UTC 24 |
Oct 12 06:32:45 PM UTC 24 |
484061236 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.1349340842 |
|
|
Oct 12 06:32:14 PM UTC 24 |
Oct 12 06:32:52 PM UTC 24 |
467283742 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.3624137699 |
|
|
Oct 12 06:32:19 PM UTC 24 |
Oct 12 06:32:55 PM UTC 24 |
195839930 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2079387867 |
|
|
Oct 12 06:32:22 PM UTC 24 |
Oct 12 06:32:57 PM UTC 24 |
128787216 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.3696781462 |
|
|
Oct 12 06:32:00 PM UTC 24 |
Oct 12 06:32:58 PM UTC 24 |
5728530033 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.1205965871 |
|
|
Oct 12 06:27:38 PM UTC 24 |
Oct 12 06:33:02 PM UTC 24 |
14682097479 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.4142891122 |
|
|
Oct 12 06:32:59 PM UTC 24 |
Oct 12 06:33:08 PM UTC 24 |
43121845 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.504805258 |
|
|
Oct 12 06:32:14 PM UTC 24 |
Oct 12 06:33:12 PM UTC 24 |
1538043294 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.1559954203 |
|
|
Oct 12 06:32:57 PM UTC 24 |
Oct 12 06:33:12 PM UTC 24 |
222844004 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3749299254 |
|
|
Oct 12 06:31:55 PM UTC 24 |
Oct 12 06:33:13 PM UTC 24 |
4938605751 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.3639639822 |
|
|
Oct 12 06:30:52 PM UTC 24 |
Oct 12 06:33:17 PM UTC 24 |
9832219371 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.1367345782 |
|
|
Oct 12 06:32:02 PM UTC 24 |
Oct 12 06:33:24 PM UTC 24 |
762761408 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.3900192008 |
|
|
Oct 12 06:31:42 PM UTC 24 |
Oct 12 06:33:32 PM UTC 24 |
2397218674 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.154461125 |
|
|
Oct 12 06:33:17 PM UTC 24 |
Oct 12 06:33:35 PM UTC 24 |
285148900 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.4054166784 |
|
|
Oct 12 06:33:36 PM UTC 24 |
Oct 12 06:33:49 PM UTC 24 |
118399225 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.297201753 |
|
|
Oct 12 06:33:35 PM UTC 24 |
Oct 12 06:33:58 PM UTC 24 |
421082553 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2830959227 |
|
|
Oct 12 06:31:40 PM UTC 24 |
Oct 12 06:33:59 PM UTC 24 |
482379978 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.2724364213 |
|
|
Oct 12 06:31:52 PM UTC 24 |
Oct 12 06:34:01 PM UTC 24 |
8890163833 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2867249259 |
|
|
Oct 12 06:28:42 PM UTC 24 |
Oct 12 06:34:06 PM UTC 24 |
4266608262 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.297938188 |
|
|
Oct 12 06:19:40 PM UTC 24 |
Oct 12 06:34:07 PM UTC 24 |
11948156662 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.1739602332 |
|
|
Oct 12 06:33:40 PM UTC 24 |
Oct 12 06:34:07 PM UTC 24 |
150031576 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.2291704783 |
|
|
Oct 12 06:33:20 PM UTC 24 |
Oct 12 06:34:09 PM UTC 24 |
402702871 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3049421682 |
|
|
Oct 12 06:22:52 PM UTC 24 |
Oct 12 06:34:11 PM UTC 24 |
9235894171 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.2320232914 |
|
|
Oct 12 05:58:51 PM UTC 24 |
Oct 12 06:34:18 PM UTC 24 |
16603118931 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.3946184920 |
|
|
Oct 12 06:19:17 PM UTC 24 |
Oct 12 06:34:21 PM UTC 24 |
22312706791 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.932022349 |
|
|
Oct 12 06:33:15 PM UTC 24 |
Oct 12 06:34:31 PM UTC 24 |
5339475941 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3606141295 |
|
|
Oct 12 06:33:48 PM UTC 24 |
Oct 12 06:34:31 PM UTC 24 |
1084512638 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1016546717 |
|
|
Oct 12 06:34:23 PM UTC 24 |
Oct 12 06:34:34 PM UTC 24 |
57481186 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.2517808040 |
|
|
Oct 12 06:30:14 PM UTC 24 |
Oct 12 06:34:37 PM UTC 24 |
2991665516 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2153340091 |
|
|
Oct 12 06:32:06 PM UTC 24 |
Oct 12 06:34:38 PM UTC 24 |
10533223625 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.942968364 |
|
|
Oct 12 06:34:24 PM UTC 24 |
Oct 12 06:34:39 PM UTC 24 |
227049330 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.2907333398 |
|
|
Oct 12 06:33:08 PM UTC 24 |
Oct 12 06:34:45 PM UTC 24 |
8192098743 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.2638784533 |
|
|
Oct 12 06:02:45 PM UTC 24 |
Oct 12 06:34:51 PM UTC 24 |
14790122444 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.629426521 |
|
|
Oct 12 06:33:58 PM UTC 24 |
Oct 12 06:34:53 PM UTC 24 |
151344247 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2619919812 |
|
|
Oct 12 06:22:16 PM UTC 24 |
Oct 12 06:34:56 PM UTC 24 |
53383419969 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.2276674984 |
|
|
Oct 12 06:34:29 PM UTC 24 |
Oct 12 06:35:01 PM UTC 24 |
305534386 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.746238514 |
|
|
Oct 12 06:29:58 PM UTC 24 |
Oct 12 06:35:02 PM UTC 24 |
3261061302 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.2511785550 |
|
|
Oct 12 06:32:23 PM UTC 24 |
Oct 12 06:35:09 PM UTC 24 |
4614963014 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.1882872947 |
|
|
Oct 12 06:27:08 PM UTC 24 |
Oct 12 06:35:10 PM UTC 24 |
3832086035 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.4060403605 |
|
|
Oct 12 06:26:53 PM UTC 24 |
Oct 12 06:35:12 PM UTC 24 |
12724893534 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.3600265249 |
|
|
Oct 12 06:33:32 PM UTC 24 |
Oct 12 06:35:22 PM UTC 24 |
2471143950 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.30825850 |
|
|
Oct 12 06:35:14 PM UTC 24 |
Oct 12 06:35:22 PM UTC 24 |
47351473 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.3523586864 |
|
|
Oct 12 06:34:33 PM UTC 24 |
Oct 12 06:35:25 PM UTC 24 |
579967776 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2963591149 |
|
|
Oct 12 06:34:57 PM UTC 24 |
Oct 12 06:35:26 PM UTC 24 |
952243202 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.181389907 |
|
|
Oct 12 06:35:23 PM UTC 24 |
Oct 12 06:35:34 PM UTC 24 |
57106177 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.584693251 |
|
|
Oct 12 06:29:54 PM UTC 24 |
Oct 12 06:35:34 PM UTC 24 |
1314269009 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.3424850329 |
|
|
Oct 12 06:35:29 PM UTC 24 |
Oct 12 06:35:40 PM UTC 24 |
153499872 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1326152739 |
|
|
Oct 12 06:35:01 PM UTC 24 |
Oct 12 06:35:46 PM UTC 24 |
1158147877 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.2397142088 |
|
|
Oct 12 06:33:56 PM UTC 24 |
Oct 12 06:35:52 PM UTC 24 |
1286380820 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.3786928147 |
|
|
Oct 12 06:28:11 PM UTC 24 |
Oct 12 06:35:52 PM UTC 24 |
11567387281 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2007120283 |
|
|
Oct 12 06:34:30 PM UTC 24 |
Oct 12 06:35:52 PM UTC 24 |
5677751622 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.1096989800 |
|
|
Oct 12 06:34:27 PM UTC 24 |
Oct 12 06:35:54 PM UTC 24 |
7599143111 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.3937221494 |
|
|
Oct 12 06:34:43 PM UTC 24 |
Oct 12 06:35:55 PM UTC 24 |
695168820 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.736831768 |
|
|
Oct 12 06:34:56 PM UTC 24 |
Oct 12 06:35:58 PM UTC 24 |
1180362610 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.3476050377 |
|
|
Oct 12 06:32:02 PM UTC 24 |
Oct 12 06:36:01 PM UTC 24 |
15531266621 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.3585920617 |
|
|
Oct 12 06:26:18 PM UTC 24 |
Oct 12 06:36:05 PM UTC 24 |
46465320953 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.4145477688 |
|
|
Oct 12 06:35:34 PM UTC 24 |
Oct 12 06:36:10 PM UTC 24 |
358203714 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2636529033 |
|
|
Oct 12 06:34:52 PM UTC 24 |
Oct 12 06:36:14 PM UTC 24 |
2584190190 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.2779580043 |
|
|
Oct 12 06:35:56 PM UTC 24 |
Oct 12 06:36:19 PM UTC 24 |
184697680 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.48131266 |
|
|
Oct 12 06:35:47 PM UTC 24 |
Oct 12 06:36:23 PM UTC 24 |
298506816 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.2324118017 |
|
|
Oct 12 06:32:54 PM UTC 24 |
Oct 12 06:36:24 PM UTC 24 |
3526321044 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1469428548 |
|
|
Oct 12 06:36:18 PM UTC 24 |
Oct 12 06:36:26 PM UTC 24 |
44181164 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.1654419112 |
|
|
Oct 12 06:36:15 PM UTC 24 |
Oct 12 06:36:27 PM UTC 24 |
147207627 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.2817908382 |
|
|
Oct 12 06:35:55 PM UTC 24 |
Oct 12 06:36:28 PM UTC 24 |
638404478 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2941959897 |
|
|
Oct 12 06:34:57 PM UTC 24 |
Oct 12 06:36:29 PM UTC 24 |
2553821517 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1038254888 |
|
|
Oct 12 06:35:43 PM UTC 24 |
Oct 12 06:36:36 PM UTC 24 |
2688309370 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.140696477 |
|
|
Oct 12 06:36:14 PM UTC 24 |
Oct 12 06:36:38 PM UTC 24 |
100566322 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1477497551 |
|
|
Oct 12 06:32:47 PM UTC 24 |
Oct 12 06:36:38 PM UTC 24 |
2052095820 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.3148252838 |
|
|
Oct 12 06:28:43 PM UTC 24 |
Oct 12 06:36:43 PM UTC 24 |
4533926404 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.2479177809 |
|
|
Oct 12 06:35:09 PM UTC 24 |
Oct 12 06:36:46 PM UTC 24 |
2278293268 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.2863185175 |
|
|
Oct 12 06:33:25 PM UTC 24 |
Oct 12 06:36:49 PM UTC 24 |
13854678015 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.2749873246 |
|
|
Oct 12 06:36:31 PM UTC 24 |
Oct 12 06:36:52 PM UTC 24 |
357871384 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2842752076 |
|
|
Oct 12 06:35:25 PM UTC 24 |
Oct 12 06:37:03 PM UTC 24 |
8356038721 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1025694075 |
|
|
Oct 12 06:35:30 PM UTC 24 |
Oct 12 06:37:07 PM UTC 24 |
6339756218 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2895852877 |
|
|
Oct 12 06:38:40 PM UTC 24 |
Oct 12 06:41:00 PM UTC 24 |
7907128369 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3611443768 |
|
|
Oct 12 06:36:56 PM UTC 24 |
Oct 12 06:37:12 PM UTC 24 |
79481909 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1337974743 |
|
|
Oct 12 06:35:57 PM UTC 24 |
Oct 12 06:37:13 PM UTC 24 |
2209197268 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3959660559 |
|
|
Oct 12 06:36:07 PM UTC 24 |
Oct 12 06:37:14 PM UTC 24 |
1236206762 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1986821387 |
|
|
Oct 12 06:19:05 PM UTC 24 |
Oct 12 06:37:16 PM UTC 24 |
10618121659 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3888892115 |
|
|
Oct 12 06:34:53 PM UTC 24 |
Oct 12 06:37:22 PM UTC 24 |
10325163110 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1309023700 |
|
|
Oct 12 06:37:14 PM UTC 24 |
Oct 12 06:37:23 PM UTC 24 |
39895650 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1234076960 |
|
|
Oct 12 06:25:46 PM UTC 24 |
Oct 12 06:37:24 PM UTC 24 |
17289923969 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.661900817 |
|
|
Oct 12 06:37:01 PM UTC 24 |
Oct 12 06:37:25 PM UTC 24 |
78212275 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.782306426 |
|
|
Oct 12 06:36:38 PM UTC 24 |
Oct 12 06:37:26 PM UTC 24 |
535414528 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.2859079663 |
|
|
Oct 12 06:37:07 PM UTC 24 |
Oct 12 06:37:27 PM UTC 24 |
187820397 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.2981031151 |
|
|
Oct 12 06:37:14 PM UTC 24 |
Oct 12 06:37:29 PM UTC 24 |
215185278 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.4281227366 |
|
|
Oct 12 06:36:50 PM UTC 24 |
Oct 12 06:37:29 PM UTC 24 |
975074550 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.3849059293 |
|
|
Oct 12 06:35:44 PM UTC 24 |
Oct 12 06:37:44 PM UTC 24 |
8577108057 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.945990848 |
|
|
Oct 12 06:32:37 PM UTC 24 |
Oct 12 06:37:44 PM UTC 24 |
8545228599 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.4177680511 |
|
|
Oct 12 06:31:38 PM UTC 24 |
Oct 12 06:37:47 PM UTC 24 |
3859287530 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2868155491 |
|
|
Oct 12 06:35:14 PM UTC 24 |
Oct 12 06:37:47 PM UTC 24 |
245502675 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1680997550 |
|
|
Oct 12 06:36:27 PM UTC 24 |
Oct 12 06:37:51 PM UTC 24 |
5635913275 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.945573926 |
|
|
Oct 12 06:36:49 PM UTC 24 |
Oct 12 06:37:53 PM UTC 24 |
1398150621 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.4220000239 |
|
|
Oct 12 05:46:37 PM UTC 24 |
Oct 12 06:37:57 PM UTC 24 |
30467472989 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.1709092596 |
|
|
Oct 12 06:37:32 PM UTC 24 |
Oct 12 06:38:04 PM UTC 24 |
377535706 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.920551464 |
|
|
Oct 12 06:38:05 PM UTC 24 |
Oct 12 06:38:15 PM UTC 24 |
47631601 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.446720818 |
|
|
Oct 12 06:36:49 PM UTC 24 |
Oct 12 06:38:17 PM UTC 24 |
2313978177 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.36735570 |
|
|
Oct 12 06:37:45 PM UTC 24 |
Oct 12 06:38:20 PM UTC 24 |
400787999 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.4282671555 |
|
|
Oct 12 06:37:47 PM UTC 24 |
Oct 12 06:38:21 PM UTC 24 |
473871903 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3145580050 |
|
|
Oct 12 06:38:11 PM UTC 24 |
Oct 12 06:38:21 PM UTC 24 |
50440119 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.1696816642 |
|
|
Oct 12 06:35:45 PM UTC 24 |
Oct 12 06:38:24 PM UTC 24 |
15396348717 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.2963994124 |
|
|
Oct 12 06:29:21 PM UTC 24 |
Oct 12 06:38:34 PM UTC 24 |
14789625812 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.944383540 |
|
|
Oct 12 06:37:44 PM UTC 24 |
Oct 12 06:38:35 PM UTC 24 |
1100047097 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.3404870014 |
|
|
Oct 12 06:36:20 PM UTC 24 |
Oct 12 06:38:37 PM UTC 24 |
8786341199 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.3467222214 |
|
|
Oct 12 06:37:42 PM UTC 24 |
Oct 12 06:38:39 PM UTC 24 |
1179093766 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1090807354 |
|
|
Oct 12 06:38:27 PM UTC 24 |
Oct 12 06:38:40 PM UTC 24 |
75959581 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.414727382 |
|
|
Oct 12 06:30:47 PM UTC 24 |
Oct 12 06:38:42 PM UTC 24 |
32648036828 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.2514228897 |
|
|
Oct 12 06:37:44 PM UTC 24 |
Oct 12 06:38:42 PM UTC 24 |
2075564169 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.3687338277 |
|
|
Oct 12 06:38:22 PM UTC 24 |
Oct 12 06:38:50 PM UTC 24 |
727693442 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.3556261759 |
|
|
Oct 12 06:37:34 PM UTC 24 |
Oct 12 06:38:51 PM UTC 24 |
2165530279 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.1602204369 |
|
|
Oct 12 06:37:35 PM UTC 24 |
Oct 12 06:38:52 PM UTC 24 |
7886190794 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.2314107312 |
|
|
Oct 12 06:38:44 PM UTC 24 |
Oct 12 06:38:56 PM UTC 24 |
221136156 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.564854749 |
|
|
Oct 12 06:37:31 PM UTC 24 |
Oct 12 06:39:06 PM UTC 24 |
6406288451 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.3068885800 |
|
|
Oct 12 06:36:46 PM UTC 24 |
Oct 12 06:39:08 PM UTC 24 |
3063510071 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.2573049049 |
|
|
Oct 12 06:38:44 PM UTC 24 |
Oct 12 06:39:15 PM UTC 24 |
397397678 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.2583447016 |
|
|
Oct 12 06:37:25 PM UTC 24 |
Oct 12 06:39:19 PM UTC 24 |
9994878189 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2706833783 |
|
|
Oct 12 06:38:08 PM UTC 24 |
Oct 12 06:39:20 PM UTC 24 |
89330722 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.1312124435 |
|
|
Oct 12 06:39:06 PM UTC 24 |
Oct 12 06:39:20 PM UTC 24 |
192915091 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3888884100 |
|
|
Oct 12 06:39:12 PM UTC 24 |
Oct 12 06:39:22 PM UTC 24 |
44804939 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.654453928 |
|
|
Oct 12 06:24:15 PM UTC 24 |
Oct 12 06:39:27 PM UTC 24 |
16658059037 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2694056638 |
|
|
Oct 12 06:38:59 PM UTC 24 |
Oct 12 06:39:27 PM UTC 24 |
165961071 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.2218094087 |
|
|
Oct 12 06:38:13 PM UTC 24 |
Oct 12 06:39:34 PM UTC 24 |
7917114877 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.830934219 |
|
|
Oct 12 06:31:35 PM UTC 24 |
Oct 12 06:39:35 PM UTC 24 |
4240335337 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.505003285 |
|
|
Oct 12 06:38:38 PM UTC 24 |
Oct 12 06:39:41 PM UTC 24 |
5592682812 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.2796691014 |
|
|
Oct 12 06:39:19 PM UTC 24 |
Oct 12 06:39:43 PM UTC 24 |
401697290 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.4566307 |
|
|
Oct 12 06:47:13 PM UTC 24 |
Oct 12 06:54:33 PM UTC 24 |
42096163361 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2131358412 |
|
|
Oct 12 06:38:14 PM UTC 24 |
Oct 12 06:39:45 PM UTC 24 |
5450452693 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.1728496381 |
|
|
Oct 12 06:38:58 PM UTC 24 |
Oct 12 06:39:49 PM UTC 24 |
1075924558 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.1422166533 |
|
|
Oct 12 06:38:48 PM UTC 24 |
Oct 12 06:39:52 PM UTC 24 |
2227788651 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.2723643689 |
|
|
Oct 12 06:39:30 PM UTC 24 |
Oct 12 06:39:55 PM UTC 24 |
218036783 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.2224438303 |
|
|
Oct 12 06:39:44 PM UTC 24 |
Oct 12 06:40:09 PM UTC 24 |
253115634 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.3322168776 |
|
|
Oct 12 06:39:44 PM UTC 24 |
Oct 12 06:40:17 PM UTC 24 |
456181559 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.100060899 |
|
|
Oct 12 06:40:08 PM UTC 24 |
Oct 12 06:40:18 PM UTC 24 |
207190842 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3163068528 |
|
|
Oct 12 06:36:12 PM UTC 24 |
Oct 12 06:40:19 PM UTC 24 |
670967458 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.660269658 |
|
|
Oct 12 06:40:10 PM UTC 24 |
Oct 12 06:40:21 PM UTC 24 |
50406018 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3175254670 |
|
|
Oct 12 06:37:10 PM UTC 24 |
Oct 12 06:40:21 PM UTC 24 |
751750919 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.561967055 |
|
|
Oct 12 06:39:15 PM UTC 24 |
Oct 12 06:40:25 PM UTC 24 |
4540093007 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.1588933931 |
|
|
Oct 12 06:39:16 PM UTC 24 |
Oct 12 06:40:33 PM UTC 24 |
6813806213 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.2943615874 |
|
|
Oct 12 06:39:50 PM UTC 24 |
Oct 12 06:40:35 PM UTC 24 |
986211500 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2167876694 |
|
|
Oct 12 06:28:13 PM UTC 24 |
Oct 12 06:40:35 PM UTC 24 |
6561159947 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.1120635038 |
|
|
Oct 12 06:37:50 PM UTC 24 |
Oct 12 06:40:46 PM UTC 24 |
4733366372 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.1131233081 |
|
|
Oct 12 06:06:15 PM UTC 24 |
Oct 12 06:40:49 PM UTC 24 |
17354146450 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.1702135040 |
|
|
Oct 12 06:40:40 PM UTC 24 |
Oct 12 06:40:50 PM UTC 24 |
15370790 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2977487286 |
|
|
Oct 12 06:39:51 PM UTC 24 |
Oct 12 06:40:56 PM UTC 24 |
1156289651 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2287966038 |
|
|
Oct 12 06:40:31 PM UTC 24 |
Oct 12 06:40:57 PM UTC 24 |
292486673 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.501369613 |
|
|
Oct 12 06:48:05 PM UTC 24 |
Oct 12 06:49:27 PM UTC 24 |
2353815186 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.3566403418 |
|
|
Oct 12 06:40:39 PM UTC 24 |
Oct 12 06:41:03 PM UTC 24 |
200335188 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.3407957490 |
|
|
Oct 12 06:39:41 PM UTC 24 |
Oct 12 06:41:04 PM UTC 24 |
1867745149 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.4266092845 |
|
|
Oct 12 06:40:45 PM UTC 24 |
Oct 12 06:41:06 PM UTC 24 |
413750992 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2466802602 |
|
|
Oct 12 06:25:12 PM UTC 24 |
Oct 12 06:41:10 PM UTC 24 |
67679280142 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.386539967 |
|
|
Oct 12 06:40:59 PM UTC 24 |
Oct 12 06:41:13 PM UTC 24 |
109370493 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.254911131 |
|
|
Oct 12 06:33:18 PM UTC 24 |
Oct 12 06:41:21 PM UTC 24 |
40150347413 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.648337957 |
|
|
Oct 12 06:40:20 PM UTC 24 |
Oct 12 06:41:23 PM UTC 24 |
4357888117 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3274370241 |
|
|
Oct 12 06:40:58 PM UTC 24 |
Oct 12 06:41:25 PM UTC 24 |
225528473 ps |
| T1770 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.4009292130 |
|
|
Oct 12 06:41:24 PM UTC 24 |
Oct 12 06:41:31 PM UTC 24 |
36837321 ps |
| T1771 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.535378821 |
|
|
Oct 12 06:41:21 PM UTC 24 |
Oct 12 06:41:36 PM UTC 24 |
220066388 ps |
| T1772 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.221403749 |
|
|
Oct 12 06:40:16 PM UTC 24 |
Oct 12 06:41:37 PM UTC 24 |
6838886625 ps |
| T1773 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.3675537575 |
|
|
Oct 12 06:34:12 PM UTC 24 |
Oct 12 06:41:39 PM UTC 24 |
12586673735 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1999154300 |
|
|
Oct 12 06:38:45 PM UTC 24 |
Oct 12 06:41:43 PM UTC 24 |
8321775285 ps |
| T1774 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2507612028 |
|
|
Oct 12 06:41:30 PM UTC 24 |
Oct 12 06:41:44 PM UTC 24 |
171711531 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.3081179038 |
|
|
Oct 12 06:31:35 PM UTC 24 |
Oct 12 06:41:48 PM UTC 24 |
14660381251 ps |
| T1775 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.2274779026 |
|
|
Oct 12 06:41:09 PM UTC 24 |
Oct 12 06:41:50 PM UTC 24 |
1204418461 ps |
| T1776 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.2868053726 |
|
|
Oct 12 06:37:01 PM UTC 24 |
Oct 12 06:41:52 PM UTC 24 |
7760803313 ps |
| T1777 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.22730551 |
|
|
Oct 12 06:40:57 PM UTC 24 |
Oct 12 06:42:05 PM UTC 24 |
1655250616 ps |
| T1778 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.1311272671 |
|
|
Oct 12 06:40:40 PM UTC 24 |
Oct 12 06:42:10 PM UTC 24 |
4681843238 ps |
| T1779 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3521794984 |
|
|
Oct 12 06:39:43 PM UTC 24 |
Oct 12 06:42:14 PM UTC 24 |
10139129838 ps |
| T1780 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.2931588704 |
|
|
Oct 12 06:36:12 PM UTC 24 |
Oct 12 06:42:15 PM UTC 24 |
9823484089 ps |
| T1781 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2712542823 |
|
|
Oct 12 06:41:55 PM UTC 24 |
Oct 12 06:42:17 PM UTC 24 |
220570711 ps |
| T1782 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.3625772681 |
|
|
Oct 12 06:34:32 PM UTC 24 |
Oct 12 06:42:21 PM UTC 24 |
47731130268 ps |
| T1783 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.949157754 |
|
|
Oct 12 06:34:42 PM UTC 24 |
Oct 12 06:42:23 PM UTC 24 |
29519973649 ps |
| T1784 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.2212490730 |
|
|
Oct 12 06:42:00 PM UTC 24 |
Oct 12 06:42:24 PM UTC 24 |
191458875 ps |
| T1785 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3004850849 |
|
|
Oct 12 06:41:35 PM UTC 24 |
Oct 12 06:42:24 PM UTC 24 |
368187534 ps |
| T1786 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.2916032364 |
|
|
Oct 12 06:42:16 PM UTC 24 |
Oct 12 06:42:26 PM UTC 24 |
49353311 ps |
| T1787 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.1154837730 |
|
|
Oct 12 06:39:55 PM UTC 24 |
Oct 12 06:42:37 PM UTC 24 |
4965005950 ps |
| T1788 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1981447299 |
|
|
Oct 12 06:42:27 PM UTC 24 |
Oct 12 06:42:37 PM UTC 24 |
41015353 ps |
| T1789 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.255396943 |
|
|
Oct 12 06:41:47 PM UTC 24 |
Oct 12 06:42:39 PM UTC 24 |
1336439795 ps |
| T1790 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.297538346 |
|
|
Oct 12 06:41:29 PM UTC 24 |
Oct 12 06:42:40 PM UTC 24 |
4674493049 ps |
| T1791 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.3337775790 |
|
|
Oct 12 06:41:26 PM UTC 24 |
Oct 12 06:42:45 PM UTC 24 |
6650940393 ps |
| T1792 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.715301716 |
|
|
Oct 12 06:42:02 PM UTC 24 |
Oct 12 06:42:48 PM UTC 24 |
1110851553 ps |
| T1793 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.1589756006 |
|
|
Oct 12 06:39:40 PM UTC 24 |
Oct 12 06:42:49 PM UTC 24 |
12392149231 ps |
| T1794 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.1771478325 |
|
|
Oct 12 06:42:00 PM UTC 24 |
Oct 12 06:42:50 PM UTC 24 |
491896556 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2474049969 |
|
|
Oct 12 06:42:14 PM UTC 24 |
Oct 12 06:42:53 PM UTC 24 |
197988981 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.1260091664 |
|
|
Oct 12 06:40:42 PM UTC 24 |
Oct 12 06:42:55 PM UTC 24 |
12192912981 ps |