| T2267 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.2656048688 |
|
|
Oct 12 07:05:37 PM UTC 24 |
Oct 12 07:11:29 PM UTC 24 |
9643349036 ps |
| T2268 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.2470726025 |
|
|
Oct 12 07:11:17 PM UTC 24 |
Oct 12 07:11:30 PM UTC 24 |
144858346 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.2229152158 |
|
|
Oct 12 07:06:05 PM UTC 24 |
Oct 12 07:11:30 PM UTC 24 |
32905454280 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.2559804006 |
|
|
Oct 12 07:04:27 PM UTC 24 |
Oct 12 07:11:37 PM UTC 24 |
13397769519 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.2670986268 |
|
|
Oct 12 07:10:57 PM UTC 24 |
Oct 12 07:11:37 PM UTC 24 |
347726673 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.3708144967 |
|
|
Oct 12 07:10:10 PM UTC 24 |
Oct 12 07:11:42 PM UTC 24 |
9049959372 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.4010592771 |
|
|
Oct 12 07:10:56 PM UTC 24 |
Oct 12 07:11:44 PM UTC 24 |
441391647 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3713374516 |
|
|
Oct 12 07:09:20 PM UTC 24 |
Oct 12 07:11:47 PM UTC 24 |
7404105985 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.1160464248 |
|
|
Oct 12 07:11:10 PM UTC 24 |
Oct 12 07:11:53 PM UTC 24 |
444914815 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3031258659 |
|
|
Oct 12 07:11:31 PM UTC 24 |
Oct 12 07:11:57 PM UTC 24 |
681761982 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.13248835 |
|
|
Oct 12 07:11:50 PM UTC 24 |
Oct 12 07:11:58 PM UTC 24 |
42119618 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.436276002 |
|
|
Oct 12 07:11:53 PM UTC 24 |
Oct 12 07:12:03 PM UTC 24 |
39550936 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1162936905 |
|
|
Oct 12 07:09:49 PM UTC 24 |
Oct 12 07:12:04 PM UTC 24 |
392989205 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.1598342477 |
|
|
Oct 12 07:11:21 PM UTC 24 |
Oct 12 07:12:07 PM UTC 24 |
1536917412 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.4274671956 |
|
|
Oct 12 06:07:58 PM UTC 24 |
Oct 12 07:12:07 PM UTC 24 |
28825737348 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2792196529 |
|
|
Oct 12 07:05:40 PM UTC 24 |
Oct 12 07:12:10 PM UTC 24 |
5883212191 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.568842926 |
|
|
Oct 12 07:01:50 PM UTC 24 |
Oct 12 07:12:14 PM UTC 24 |
11488721664 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.2047873315 |
|
|
Oct 12 07:07:23 PM UTC 24 |
Oct 12 07:12:14 PM UTC 24 |
18515927308 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.3586958197 |
|
|
Oct 12 07:09:20 PM UTC 24 |
Oct 12 07:12:16 PM UTC 24 |
3700460286 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.4287540022 |
|
|
Oct 12 07:12:02 PM UTC 24 |
Oct 12 07:12:24 PM UTC 24 |
200800905 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3476131155 |
|
|
Oct 12 07:10:56 PM UTC 24 |
Oct 12 07:12:24 PM UTC 24 |
5987521023 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4130419500 |
|
|
Oct 12 06:56:24 PM UTC 24 |
Oct 12 07:12:26 PM UTC 24 |
56392912310 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.292932353 |
|
|
Oct 12 07:10:50 PM UTC 24 |
Oct 12 07:12:29 PM UTC 24 |
9778347983 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.1766885012 |
|
|
Oct 12 07:11:27 PM UTC 24 |
Oct 12 07:12:32 PM UTC 24 |
1563158814 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.49865868 |
|
|
Oct 12 07:05:04 PM UTC 24 |
Oct 12 07:12:35 PM UTC 24 |
26665366092 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.100725304 |
|
|
Oct 12 06:13:21 PM UTC 24 |
Oct 12 07:12:35 PM UTC 24 |
30573799471 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.628046812 |
|
|
Oct 12 07:10:30 PM UTC 24 |
Oct 12 07:12:40 PM UTC 24 |
279988289 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.4093854502 |
|
|
Oct 12 07:12:22 PM UTC 24 |
Oct 12 07:12:45 PM UTC 24 |
409216622 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.312546125 |
|
|
Oct 12 07:12:12 PM UTC 24 |
Oct 12 07:12:46 PM UTC 24 |
309008627 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1959210936 |
|
|
Oct 12 07:12:38 PM UTC 24 |
Oct 12 07:12:46 PM UTC 24 |
47242944 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.1987107110 |
|
|
Oct 12 07:12:19 PM UTC 24 |
Oct 12 07:12:49 PM UTC 24 |
361725409 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.3905335233 |
|
|
Oct 12 07:12:36 PM UTC 24 |
Oct 12 07:12:49 PM UTC 24 |
266872161 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.3863443944 |
|
|
Oct 12 07:11:57 PM UTC 24 |
Oct 12 07:13:02 PM UTC 24 |
1498609517 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.603885141 |
|
|
Oct 12 07:04:07 PM UTC 24 |
Oct 12 07:13:05 PM UTC 24 |
32304794211 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.4096605127 |
|
|
Oct 12 07:10:21 PM UTC 24 |
Oct 12 07:13:10 PM UTC 24 |
9762884456 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.2231152956 |
|
|
Oct 12 07:11:52 PM UTC 24 |
Oct 12 07:13:10 PM UTC 24 |
7617017686 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2450325670 |
|
|
Oct 12 07:12:22 PM UTC 24 |
Oct 12 07:13:22 PM UTC 24 |
564644202 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2177079826 |
|
|
Oct 12 07:12:27 PM UTC 24 |
Oct 12 07:13:25 PM UTC 24 |
1443196092 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2237262094 |
|
|
Oct 12 07:03:23 PM UTC 24 |
Oct 12 07:13:26 PM UTC 24 |
41115585027 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.3889666721 |
|
|
Oct 12 07:03:11 PM UTC 24 |
Oct 12 07:13:28 PM UTC 24 |
49549129199 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.1786474708 |
|
|
Oct 12 07:12:49 PM UTC 24 |
Oct 12 07:13:28 PM UTC 24 |
349367036 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3915062502 |
|
|
Oct 12 07:13:11 PM UTC 24 |
Oct 12 07:13:28 PM UTC 24 |
383606913 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.2130626837 |
|
|
Oct 12 07:13:08 PM UTC 24 |
Oct 12 07:13:36 PM UTC 24 |
276566415 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.1032781103 |
|
|
Oct 12 07:07:40 PM UTC 24 |
Oct 12 07:13:36 PM UTC 24 |
10846433148 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.2811547083 |
|
|
Oct 12 07:08:51 PM UTC 24 |
Oct 12 07:13:37 PM UTC 24 |
7232677029 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.45277936 |
|
|
Oct 12 07:11:59 PM UTC 24 |
Oct 12 07:13:38 PM UTC 24 |
5947623747 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.3934465263 |
|
|
Oct 12 07:13:29 PM UTC 24 |
Oct 12 07:13:38 PM UTC 24 |
37106787 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.4053638552 |
|
|
Oct 12 07:13:09 PM UTC 24 |
Oct 12 07:13:39 PM UTC 24 |
325457645 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.269620900 |
|
|
Oct 12 07:04:14 PM UTC 24 |
Oct 12 07:13:42 PM UTC 24 |
38106337376 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.3242487783 |
|
|
Oct 12 07:12:48 PM UTC 24 |
Oct 12 07:13:50 PM UTC 24 |
509781850 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2022653597 |
|
|
Oct 12 07:13:45 PM UTC 24 |
Oct 12 07:13:54 PM UTC 24 |
46500457 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.1501307334 |
|
|
Oct 12 07:13:06 PM UTC 24 |
Oct 12 07:13:56 PM UTC 24 |
1101541190 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2838689059 |
|
|
Oct 12 07:12:47 PM UTC 24 |
Oct 12 07:14:02 PM UTC 24 |
5593267026 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.1313682237 |
|
|
Oct 12 07:13:49 PM UTC 24 |
Oct 12 07:14:02 PM UTC 24 |
99519020 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.1599183863 |
|
|
Oct 12 07:13:49 PM UTC 24 |
Oct 12 07:14:05 PM UTC 24 |
133421069 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.1286414940 |
|
|
Oct 12 07:07:25 PM UTC 24 |
Oct 12 07:14:06 PM UTC 24 |
43412866567 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.1362011422 |
|
|
Oct 12 07:14:02 PM UTC 24 |
Oct 12 07:14:09 PM UTC 24 |
37146344 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.3396466884 |
|
|
Oct 12 07:13:59 PM UTC 24 |
Oct 12 07:14:12 PM UTC 24 |
204764526 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.333336261 |
|
|
Oct 12 07:12:56 PM UTC 24 |
Oct 12 07:14:12 PM UTC 24 |
1652099332 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.3521271550 |
|
|
Oct 12 07:09:54 PM UTC 24 |
Oct 12 07:14:13 PM UTC 24 |
7167687630 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.1358082883 |
|
|
Oct 12 07:13:59 PM UTC 24 |
Oct 12 07:14:13 PM UTC 24 |
57686182 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.4155482208 |
|
|
Oct 12 07:12:46 PM UTC 24 |
Oct 12 07:14:21 PM UTC 24 |
7492808387 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2818508088 |
|
|
Oct 12 07:13:26 PM UTC 24 |
Oct 12 07:14:22 PM UTC 24 |
102786704 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2789690950 |
|
|
Oct 12 07:14:03 PM UTC 24 |
Oct 12 07:14:26 PM UTC 24 |
200904752 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.2519998091 |
|
|
Oct 12 07:11:04 PM UTC 24 |
Oct 12 07:14:29 PM UTC 24 |
20062297418 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.762557091 |
|
|
Oct 12 07:14:23 PM UTC 24 |
Oct 12 07:14:33 PM UTC 24 |
46392890 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1247468732 |
|
|
Oct 12 07:14:27 PM UTC 24 |
Oct 12 07:14:34 PM UTC 24 |
47516667 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1039139859 |
|
|
Oct 12 07:14:21 PM UTC 24 |
Oct 12 07:14:35 PM UTC 24 |
65491399 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2976473849 |
|
|
Oct 12 07:09:57 PM UTC 24 |
Oct 12 07:14:42 PM UTC 24 |
1677814460 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4178888445 |
|
|
Oct 12 07:12:14 PM UTC 24 |
Oct 12 07:14:46 PM UTC 24 |
9445582535 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3080316236 |
|
|
Oct 12 07:06:37 PM UTC 24 |
Oct 12 07:14:50 PM UTC 24 |
6383850536 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2216133537 |
|
|
Oct 12 07:13:48 PM UTC 24 |
Oct 12 07:14:56 PM UTC 24 |
4916416138 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.2248196722 |
|
|
Oct 12 07:08:41 PM UTC 24 |
Oct 12 07:14:58 PM UTC 24 |
10685207351 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.3928600000 |
|
|
Oct 12 07:14:33 PM UTC 24 |
Oct 12 07:14:58 PM UTC 24 |
278035993 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.627056079 |
|
|
Oct 12 07:14:56 PM UTC 24 |
Oct 12 07:15:04 PM UTC 24 |
85924105 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.817741131 |
|
|
Oct 12 07:07:55 PM UTC 24 |
Oct 12 07:15:05 PM UTC 24 |
4200733228 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3931865560 |
|
|
Oct 12 07:09:16 PM UTC 24 |
Oct 12 07:15:11 PM UTC 24 |
34731110277 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3467078421 |
|
|
Oct 12 07:14:34 PM UTC 24 |
Oct 12 07:15:11 PM UTC 24 |
287063848 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.4292199811 |
|
|
Oct 12 07:06:15 PM UTC 24 |
Oct 12 07:15:19 PM UTC 24 |
34268586792 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3405774992 |
|
|
Oct 12 07:14:47 PM UTC 24 |
Oct 12 07:15:21 PM UTC 24 |
1064401193 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.112841729 |
|
|
Oct 12 07:11:40 PM UTC 24 |
Oct 12 07:15:28 PM UTC 24 |
6613458713 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.420483101 |
|
|
Oct 12 07:15:21 PM UTC 24 |
Oct 12 07:15:29 PM UTC 24 |
48441301 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.1198096171 |
|
|
Oct 12 07:10:33 PM UTC 24 |
Oct 12 07:15:30 PM UTC 24 |
9515341093 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.1601402769 |
|
|
Oct 12 07:15:19 PM UTC 24 |
Oct 12 07:15:30 PM UTC 24 |
186815343 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.1726130964 |
|
|
Oct 12 07:10:26 PM UTC 24 |
Oct 12 07:15:32 PM UTC 24 |
3696157827 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.128698457 |
|
|
Oct 12 07:13:59 PM UTC 24 |
Oct 12 07:15:35 PM UTC 24 |
1972261647 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.882615674 |
|
|
Oct 12 07:07:40 PM UTC 24 |
Oct 12 07:15:48 PM UTC 24 |
4900931959 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.3557497450 |
|
|
Oct 12 07:13:47 PM UTC 24 |
Oct 12 07:15:48 PM UTC 24 |
8474327360 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1316630446 |
|
|
Oct 12 07:10:32 PM UTC 24 |
Oct 12 07:15:49 PM UTC 24 |
5099063510 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.2102368339 |
|
|
Oct 12 07:14:56 PM UTC 24 |
Oct 12 07:15:49 PM UTC 24 |
1462724484 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.3065365389 |
|
|
Oct 12 07:09:43 PM UTC 24 |
Oct 12 07:15:51 PM UTC 24 |
9755398859 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2271206636 |
|
|
Oct 12 06:57:18 PM UTC 24 |
Oct 12 07:16:00 PM UTC 24 |
71513891543 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.1176590512 |
|
|
Oct 12 07:15:34 PM UTC 24 |
Oct 12 07:16:03 PM UTC 24 |
269798614 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.3309659106 |
|
|
Oct 12 07:12:05 PM UTC 24 |
Oct 12 07:16:07 PM UTC 24 |
17525157698 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3225764863 |
|
|
Oct 12 07:14:42 PM UTC 24 |
Oct 12 07:16:13 PM UTC 24 |
2715568745 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.1832533414 |
|
|
Oct 12 07:15:28 PM UTC 24 |
Oct 12 07:16:14 PM UTC 24 |
558952288 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2435915648 |
|
|
Oct 12 07:14:30 PM UTC 24 |
Oct 12 07:16:15 PM UTC 24 |
5717332370 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1614658175 |
|
|
Oct 12 06:59:46 PM UTC 24 |
Oct 12 07:16:18 PM UTC 24 |
52069444452 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2162717698 |
|
|
Oct 12 07:11:36 PM UTC 24 |
Oct 12 07:16:19 PM UTC 24 |
443766089 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3560461594 |
|
|
Oct 12 07:16:13 PM UTC 24 |
Oct 12 07:16:23 PM UTC 24 |
50001624 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.928655656 |
|
|
Oct 12 07:16:11 PM UTC 24 |
Oct 12 07:16:25 PM UTC 24 |
201209618 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1300217746 |
|
|
Oct 12 07:15:54 PM UTC 24 |
Oct 12 07:16:25 PM UTC 24 |
654824270 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.2806154266 |
|
|
Oct 12 07:15:52 PM UTC 24 |
Oct 12 07:16:31 PM UTC 24 |
967524224 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.3218777548 |
|
|
Oct 12 07:14:16 PM UTC 24 |
Oct 12 07:16:31 PM UTC 24 |
1682751523 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.3154552686 |
|
|
Oct 12 07:15:23 PM UTC 24 |
Oct 12 07:16:34 PM UTC 24 |
7632296987 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.602508765 |
|
|
Oct 12 07:16:29 PM UTC 24 |
Oct 12 07:16:37 PM UTC 24 |
88093210 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.416598762 |
|
|
Oct 12 07:15:50 PM UTC 24 |
Oct 12 07:16:38 PM UTC 24 |
1661294976 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.2263796475 |
|
|
Oct 12 07:14:27 PM UTC 24 |
Oct 12 07:16:39 PM UTC 24 |
8540060426 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.270021850 |
|
|
Oct 12 07:14:48 PM UTC 24 |
Oct 12 07:16:39 PM UTC 24 |
2232217407 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1433888663 |
|
|
Oct 12 07:15:28 PM UTC 24 |
Oct 12 07:16:42 PM UTC 24 |
4811815577 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.638224681 |
|
|
Oct 12 07:16:10 PM UTC 24 |
Oct 12 07:16:48 PM UTC 24 |
78718060 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.2845708829 |
|
|
Oct 12 07:15:51 PM UTC 24 |
Oct 12 07:16:51 PM UTC 24 |
1097467151 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.2066190039 |
|
|
Oct 12 07:08:31 PM UTC 24 |
Oct 12 07:16:53 PM UTC 24 |
50114680186 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3571424077 |
|
|
Oct 12 07:16:34 PM UTC 24 |
Oct 12 07:16:54 PM UTC 24 |
168544728 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.615022098 |
|
|
Oct 12 07:16:47 PM UTC 24 |
Oct 12 07:16:57 PM UTC 24 |
131735237 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.1448551787 |
|
|
Oct 12 07:15:45 PM UTC 24 |
Oct 12 07:16:57 PM UTC 24 |
1479398534 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3656039459 |
|
|
Oct 12 07:12:28 PM UTC 24 |
Oct 12 07:16:59 PM UTC 24 |
1035792603 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.1941021695 |
|
|
Oct 12 07:16:59 PM UTC 24 |
Oct 12 07:17:09 PM UTC 24 |
43617728 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3082821583 |
|
|
Oct 12 07:16:53 PM UTC 24 |
Oct 12 07:17:09 PM UTC 24 |
142182225 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2555934543 |
|
|
Oct 12 07:17:03 PM UTC 24 |
Oct 12 07:17:14 PM UTC 24 |
56741818 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.1899817776 |
|
|
Oct 12 07:16:48 PM UTC 24 |
Oct 12 07:17:19 PM UTC 24 |
361052597 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3169767383 |
|
|
Oct 12 07:12:04 PM UTC 24 |
Oct 12 07:17:22 PM UTC 24 |
34390172825 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.4045897908 |
|
|
Oct 12 07:16:40 PM UTC 24 |
Oct 12 07:17:23 PM UTC 24 |
858817639 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.908953416 |
|
|
Oct 12 07:17:15 PM UTC 24 |
Oct 12 07:17:24 PM UTC 24 |
37382566 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.4140722851 |
|
|
Oct 12 07:13:12 PM UTC 24 |
Oct 12 07:17:29 PM UTC 24 |
3296428435 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1930363686 |
|
|
Oct 12 07:14:16 PM UTC 24 |
Oct 12 07:17:32 PM UTC 24 |
445314464 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.2383954696 |
|
|
Oct 12 07:17:17 PM UTC 24 |
Oct 12 07:17:34 PM UTC 24 |
144539015 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.533023283 |
|
|
Oct 12 07:16:49 PM UTC 24 |
Oct 12 07:17:38 PM UTC 24 |
1444571294 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.469326106 |
|
|
Oct 12 07:16:27 PM UTC 24 |
Oct 12 07:17:43 PM UTC 24 |
4310572421 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3379565282 |
|
|
Oct 12 07:16:57 PM UTC 24 |
Oct 12 07:17:45 PM UTC 24 |
110332224 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1697651014 |
|
|
Oct 12 07:15:54 PM UTC 24 |
Oct 12 07:17:47 PM UTC 24 |
1363913898 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.573631872 |
|
|
Oct 12 07:13:50 PM UTC 24 |
Oct 12 07:17:51 PM UTC 24 |
22452360252 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.3237357628 |
|
|
Oct 12 07:13:27 PM UTC 24 |
Oct 12 07:17:52 PM UTC 24 |
7263814490 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.1795768180 |
|
|
Oct 12 07:17:22 PM UTC 24 |
Oct 12 07:17:54 PM UTC 24 |
460381487 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.813622323 |
|
|
Oct 12 07:17:31 PM UTC 24 |
Oct 12 07:18:01 PM UTC 24 |
945828884 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.1791427055 |
|
|
Oct 12 07:16:21 PM UTC 24 |
Oct 12 07:18:05 PM UTC 24 |
7928802523 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3218241375 |
|
|
Oct 12 07:17:57 PM UTC 24 |
Oct 12 07:18:06 PM UTC 24 |
49787660 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.1861596270 |
|
|
Oct 12 07:17:57 PM UTC 24 |
Oct 12 07:18:06 PM UTC 24 |
37667623 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2944735526 |
|
|
Oct 12 07:17:33 PM UTC 24 |
Oct 12 07:18:11 PM UTC 24 |
553302612 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.28009538 |
|
|
Oct 12 07:17:42 PM UTC 24 |
Oct 12 07:18:14 PM UTC 24 |
310524592 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.413839580 |
|
|
Oct 12 07:17:38 PM UTC 24 |
Oct 12 07:18:16 PM UTC 24 |
317982503 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.2726016552 |
|
|
Oct 12 07:12:55 PM UTC 24 |
Oct 12 07:18:16 PM UTC 24 |
32346783618 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.1316746697 |
|
|
Oct 12 07:18:11 PM UTC 24 |
Oct 12 07:18:21 PM UTC 24 |
57998285 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.720542335 |
|
|
Oct 12 07:17:09 PM UTC 24 |
Oct 12 07:18:23 PM UTC 24 |
5501588775 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.477670466 |
|
|
Oct 12 07:17:21 PM UTC 24 |
Oct 12 07:18:25 PM UTC 24 |
4526638891 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1418628459 |
|
|
Oct 12 07:16:10 PM UTC 24 |
Oct 12 07:18:48 PM UTC 24 |
350257354 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1523702827 |
|
|
Oct 12 07:05:15 PM UTC 24 |
Oct 12 07:18:48 PM UTC 24 |
51738149363 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.706913934 |
|
|
Oct 12 07:10:20 PM UTC 24 |
Oct 12 07:18:49 PM UTC 24 |
30645615865 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.3157872535 |
|
|
Oct 12 07:18:07 PM UTC 24 |
Oct 12 07:18:55 PM UTC 24 |
1599297479 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.189369308 |
|
|
Oct 12 07:18:31 PM UTC 24 |
Oct 12 07:18:57 PM UTC 24 |
139751627 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.2271201494 |
|
|
Oct 12 07:18:47 PM UTC 24 |
Oct 12 07:18:58 PM UTC 24 |
203499352 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1652718590 |
|
|
Oct 12 07:17:01 PM UTC 24 |
Oct 12 07:18:58 PM UTC 24 |
7231339934 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1493392007 |
|
|
Oct 12 07:18:49 PM UTC 24 |
Oct 12 07:18:59 PM UTC 24 |
53685806 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2608428402 |
|
|
Oct 12 07:18:29 PM UTC 24 |
Oct 12 07:19:00 PM UTC 24 |
636849933 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.1606252892 |
|
|
Oct 12 07:18:19 PM UTC 24 |
Oct 12 07:19:02 PM UTC 24 |
1192190989 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3107856233 |
|
|
Oct 12 07:18:35 PM UTC 24 |
Oct 12 07:19:02 PM UTC 24 |
211465070 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1198766634 |
|
|
Oct 12 07:12:38 PM UTC 24 |
Oct 12 07:19:06 PM UTC 24 |
7541392982 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3854614935 |
|
|
Oct 12 07:08:35 PM UTC 24 |
Oct 12 07:19:10 PM UTC 24 |
37116624622 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3940718768 |
|
|
Oct 12 07:15:06 PM UTC 24 |
Oct 12 07:19:12 PM UTC 24 |
6539086484 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.4257245833 |
|
|
Oct 12 07:14:35 PM UTC 24 |
Oct 12 07:19:27 PM UTC 24 |
20080537581 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.2914162967 |
|
|
Oct 12 07:12:58 PM UTC 24 |
Oct 12 07:19:30 PM UTC 24 |
25256372584 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.323207942 |
|
|
Oct 12 07:21:03 PM UTC 24 |
Oct 12 07:22:48 PM UTC 24 |
8625451626 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3213898687 |
|
|
Oct 12 07:15:02 PM UTC 24 |
Oct 12 07:19:31 PM UTC 24 |
2957284130 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.1525981700 |
|
|
Oct 12 07:19:21 PM UTC 24 |
Oct 12 07:19:31 PM UTC 24 |
88425907 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.2432076758 |
|
|
Oct 12 07:19:24 PM UTC 24 |
Oct 12 07:19:37 PM UTC 24 |
206033779 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.537630390 |
|
|
Oct 12 07:19:21 PM UTC 24 |
Oct 12 07:19:38 PM UTC 24 |
131716201 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2787559148 |
|
|
Oct 12 07:18:14 PM UTC 24 |
Oct 12 07:19:41 PM UTC 24 |
7194422146 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.1628350804 |
|
|
Oct 12 07:18:29 PM UTC 24 |
Oct 12 07:19:42 PM UTC 24 |
2374203701 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3214282600 |
|
|
Oct 12 07:19:27 PM UTC 24 |
Oct 12 07:19:44 PM UTC 24 |
195970557 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.3672156525 |
|
|
Oct 12 07:19:12 PM UTC 24 |
Oct 12 07:19:46 PM UTC 24 |
378852108 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.2717177993 |
|
|
Oct 12 07:11:08 PM UTC 24 |
Oct 12 07:19:48 PM UTC 24 |
33178943510 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.1881148798 |
|
|
Oct 12 07:17:18 PM UTC 24 |
Oct 12 07:19:52 PM UTC 24 |
14260870603 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3607721624 |
|
|
Oct 12 07:19:17 PM UTC 24 |
Oct 12 07:20:03 PM UTC 24 |
372148035 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1848584680 |
|
|
Oct 12 07:19:51 PM UTC 24 |
Oct 12 07:20:04 PM UTC 24 |
249670407 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.315013795 |
|
|
Oct 12 07:19:56 PM UTC 24 |
Oct 12 07:20:05 PM UTC 24 |
39801074 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2953192199 |
|
|
Oct 12 07:19:11 PM UTC 24 |
Oct 12 07:20:22 PM UTC 24 |
4626529641 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.1520381855 |
|
|
Oct 12 07:18:03 PM UTC 24 |
Oct 12 07:20:23 PM UTC 24 |
10273370070 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1039991148 |
|
|
Oct 12 07:18:04 PM UTC 24 |
Oct 12 07:20:25 PM UTC 24 |
7153695165 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.3985313890 |
|
|
Oct 12 07:20:12 PM UTC 24 |
Oct 12 07:20:28 PM UTC 24 |
122287733 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.1452080713 |
|
|
Oct 12 07:19:11 PM UTC 24 |
Oct 12 07:20:33 PM UTC 24 |
6499985817 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.1227574742 |
|
|
Oct 12 07:19:27 PM UTC 24 |
Oct 12 07:20:35 PM UTC 24 |
1437402617 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.1582515615 |
|
|
Oct 12 07:12:27 PM UTC 24 |
Oct 12 07:20:39 PM UTC 24 |
5005642462 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.3792417316 |
|
|
Oct 12 07:16:09 PM UTC 24 |
Oct 12 07:20:40 PM UTC 24 |
7567489203 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.3857564285 |
|
|
Oct 12 07:20:02 PM UTC 24 |
Oct 12 07:20:41 PM UTC 24 |
503721269 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.3992945750 |
|
|
Oct 12 07:14:14 PM UTC 24 |
Oct 12 07:20:43 PM UTC 24 |
10366667975 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.631304296 |
|
|
Oct 12 07:16:37 PM UTC 24 |
Oct 12 07:20:43 PM UTC 24 |
17233332537 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.1050621386 |
|
|
Oct 12 07:20:26 PM UTC 24 |
Oct 12 07:20:43 PM UTC 24 |
181966657 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.3166154421 |
|
|
Oct 12 07:20:06 PM UTC 24 |
Oct 12 07:20:44 PM UTC 24 |
315790571 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.521322708 |
|
|
Oct 12 07:17:45 PM UTC 24 |
Oct 12 07:20:54 PM UTC 24 |
5056633114 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.3599779605 |
|
|
Oct 12 07:20:24 PM UTC 24 |
Oct 12 07:20:55 PM UTC 24 |
918028907 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.866098307 |
|
|
Oct 12 07:17:00 PM UTC 24 |
Oct 12 07:20:59 PM UTC 24 |
842173210 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.2104859457 |
|
|
Oct 12 07:20:27 PM UTC 24 |
Oct 12 07:21:00 PM UTC 24 |
200055812 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.2304137705 |
|
|
Oct 12 07:11:29 PM UTC 24 |
Oct 12 07:21:02 PM UTC 24 |
14656773709 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.1082202159 |
|
|
Oct 12 07:20:56 PM UTC 24 |
Oct 12 07:21:04 PM UTC 24 |
40416992 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.970142528 |
|
|
Oct 12 07:20:59 PM UTC 24 |
Oct 12 07:21:09 PM UTC 24 |
50100516 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.1133583733 |
|
|
Oct 12 07:15:35 PM UTC 24 |
Oct 12 07:21:10 PM UTC 24 |
32499058791 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.384973089 |
|
|
Oct 12 07:17:46 PM UTC 24 |
Oct 12 07:21:11 PM UTC 24 |
2730576212 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.1627341370 |
|
|
Oct 12 07:20:07 PM UTC 24 |
Oct 12 07:21:15 PM UTC 24 |
5707350343 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.3273038612 |
|
|
Oct 12 07:15:39 PM UTC 24 |
Oct 12 07:21:19 PM UTC 24 |
22813425585 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.313915595 |
|
|
Oct 12 07:16:35 PM UTC 24 |
Oct 12 07:21:19 PM UTC 24 |
28739229164 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.4173523540 |
|
|
Oct 12 07:17:47 PM UTC 24 |
Oct 12 07:21:24 PM UTC 24 |
4277999867 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1197023287 |
|
|
Oct 12 07:17:48 PM UTC 24 |
Oct 12 07:21:28 PM UTC 24 |
420090426 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.151941146 |
|
|
Oct 12 07:12:34 PM UTC 24 |
Oct 12 07:21:29 PM UTC 24 |
13114701935 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.1777851794 |
|
|
Oct 12 07:20:44 PM UTC 24 |
Oct 12 07:21:32 PM UTC 24 |
1216254991 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.3930436809 |
|
|
Oct 12 07:13:58 PM UTC 24 |
Oct 12 07:21:34 PM UTC 24 |
30886635031 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1352590052 |
|
|
Oct 12 07:21:26 PM UTC 24 |
Oct 12 07:21:36 PM UTC 24 |
57392992 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.804495110 |
|
|
Oct 12 07:16:58 PM UTC 24 |
Oct 12 07:21:39 PM UTC 24 |
4396038888 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.168327436 |
|
|
Oct 12 07:21:05 PM UTC 24 |
Oct 12 07:21:39 PM UTC 24 |
310077196 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.1673021361 |
|
|
Oct 12 07:20:00 PM UTC 24 |
Oct 12 07:21:41 PM UTC 24 |
8994473763 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1477417232 |
|
|
Oct 12 07:18:15 PM UTC 24 |
Oct 12 07:21:42 PM UTC 24 |
13585803604 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.863749495 |
|
|
Oct 12 07:21:22 PM UTC 24 |
Oct 12 07:21:45 PM UTC 24 |
378576522 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.154619545 |
|
|
Oct 12 07:21:38 PM UTC 24 |
Oct 12 07:21:46 PM UTC 24 |
36779403 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.4004104794 |
|
|
Oct 12 07:20:52 PM UTC 24 |
Oct 12 07:21:48 PM UTC 24 |
636931309 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.736538609 |
|
|
Oct 12 07:21:25 PM UTC 24 |
Oct 12 07:21:53 PM UTC 24 |
159094734 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.1919934844 |
|
|
Oct 12 07:21:29 PM UTC 24 |
Oct 12 07:21:54 PM UTC 24 |
272182434 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.1026359268 |
|
|
Oct 12 07:21:44 PM UTC 24 |
Oct 12 07:21:57 PM UTC 24 |
178841265 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.800801339 |
|
|
Oct 12 07:21:07 PM UTC 24 |
Oct 12 07:21:57 PM UTC 24 |
4485558003 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.2042852388 |
|
|
Oct 12 07:21:05 PM UTC 24 |
Oct 12 07:22:00 PM UTC 24 |
1496112863 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.1849440015 |
|
|
Oct 12 07:14:35 PM UTC 24 |
Oct 12 07:22:00 PM UTC 24 |
47943875767 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.805329718 |
|
|
Oct 12 07:21:52 PM UTC 24 |
Oct 12 07:22:04 PM UTC 24 |
120094404 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.760482957 |
|
|
Oct 12 07:21:34 PM UTC 24 |
Oct 12 07:22:05 PM UTC 24 |
436141188 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.1721936311 |
|
|
Oct 12 07:18:40 PM UTC 24 |
Oct 12 07:22:06 PM UTC 24 |
3012334377 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2541055625 |
|
|
Oct 12 07:20:03 PM UTC 24 |
Oct 12 07:22:13 PM UTC 24 |
6290132448 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.867085331 |
|
|
Oct 12 07:22:05 PM UTC 24 |
Oct 12 07:22:18 PM UTC 24 |
156643776 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1768858557 |
|
|
Oct 12 07:21:33 PM UTC 24 |
Oct 12 07:22:21 PM UTC 24 |
168905509 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2020716439 |
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|
Oct 12 07:21:54 PM UTC 24 |
Oct 12 07:22:23 PM UTC 24 |
214884681 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.3495925502 |
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|
Oct 12 07:20:10 PM UTC 24 |
Oct 12 07:22:30 PM UTC 24 |
7302659152 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.3722282347 |
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|
Oct 12 07:22:21 PM UTC 24 |
Oct 12 07:22:31 PM UTC 24 |
45054907 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2626053078 |
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|
Oct 12 07:22:21 PM UTC 24 |
Oct 12 07:22:31 PM UTC 24 |
47564814 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.736015835 |
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|
Oct 12 07:21:04 PM UTC 24 |
Oct 12 07:22:32 PM UTC 24 |
5585591479 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.1292293916 |
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|
Oct 12 07:21:15 PM UTC 24 |
Oct 12 07:22:33 PM UTC 24 |
1015678677 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.1396167334 |
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|
Oct 12 07:21:22 PM UTC 24 |
Oct 12 07:22:36 PM UTC 24 |
2685578722 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.2480767368 |
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|
Oct 12 07:22:06 PM UTC 24 |
Oct 12 07:22:43 PM UTC 24 |
776956372 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2683566198 |
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|
Oct 12 07:14:42 PM UTC 24 |
Oct 12 07:22:43 PM UTC 24 |
34688853717 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1771906601 |
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|
Oct 12 07:21:52 PM UTC 24 |
Oct 12 07:22:45 PM UTC 24 |
3931144014 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1265189610 |
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|
Oct 12 07:15:49 PM UTC 24 |
Oct 12 07:22:47 PM UTC 24 |
26414285238 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1178999747 |
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|
Oct 12 07:13:04 PM UTC 24 |
Oct 12 07:22:48 PM UTC 24 |
33472600077 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.2440540073 |
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|
Oct 12 07:22:03 PM UTC 24 |
Oct 12 07:23:02 PM UTC 24 |
606545372 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.147832712 |
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|
Oct 12 07:21:44 PM UTC 24 |
Oct 12 07:23:06 PM UTC 24 |
7456578564 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.335968159 |
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|
Oct 12 07:20:16 PM UTC 24 |
Oct 12 07:23:11 PM UTC 24 |
11035113659 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2769333946 |
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|
Oct 12 07:16:41 PM UTC 24 |
Oct 12 07:23:14 PM UTC 24 |
24169648804 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.2536395891 |
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|
Oct 12 07:23:07 PM UTC 24 |
Oct 12 07:23:17 PM UTC 24 |
41016498 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.132365991 |
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|
Oct 12 07:23:09 PM UTC 24 |
Oct 12 07:23:19 PM UTC 24 |
47650215 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.858988944 |
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|
Oct 12 07:22:01 PM UTC 24 |
Oct 12 07:23:19 PM UTC 24 |
2021469890 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.3956829634 |
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|
Oct 12 07:22:54 PM UTC 24 |
Oct 12 07:23:19 PM UTC 24 |
553109854 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.3181059217 |
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|
Oct 12 07:22:29 PM UTC 24 |
Oct 12 07:23:20 PM UTC 24 |
478997632 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.432201683 |
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|
Oct 12 07:22:53 PM UTC 24 |
Oct 12 07:23:22 PM UTC 24 |
245666475 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2740399797 |
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|
Oct 12 07:19:33 PM UTC 24 |
Oct 12 07:23:23 PM UTC 24 |
5261491962 ps |
| T2513 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2671161860 |
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|
Oct 12 07:22:41 PM UTC 24 |
Oct 12 07:23:30 PM UTC 24 |
1712965609 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.1487805477 |
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|
Oct 12 07:22:54 PM UTC 24 |
Oct 12 07:23:35 PM UTC 24 |
1276065922 ps |