| T162 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.3913726513 |
|
|
Oct 13 12:52:38 AM UTC 24 |
Oct 13 01:03:05 AM UTC 24 |
5724232152 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.3068771704 |
|
|
Oct 13 12:52:38 AM UTC 24 |
Oct 13 01:03:47 AM UTC 24 |
6910864929 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3661325894 |
|
|
Oct 13 12:58:09 AM UTC 24 |
Oct 13 01:04:13 AM UTC 24 |
3583735960 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.1201895126 |
|
|
Oct 13 12:27:31 AM UTC 24 |
Oct 13 01:05:03 AM UTC 24 |
20773930727 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.2812958576 |
|
|
Oct 13 12:56:39 AM UTC 24 |
Oct 13 01:05:12 AM UTC 24 |
3407367704 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.468562795 |
|
|
Oct 13 01:00:39 AM UTC 24 |
Oct 13 01:07:14 AM UTC 24 |
3593020262 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.880058264 |
|
|
Oct 13 12:55:58 AM UTC 24 |
Oct 13 01:07:40 AM UTC 24 |
6521767470 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.2462647580 |
|
|
Oct 13 12:04:52 AM UTC 24 |
Oct 13 01:07:51 AM UTC 24 |
13832915144 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.263343917 |
|
|
Oct 13 12:55:58 AM UTC 24 |
Oct 13 01:08:08 AM UTC 24 |
5651580400 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3410042366 |
|
|
Oct 13 01:02:33 AM UTC 24 |
Oct 13 01:08:28 AM UTC 24 |
3681939668 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.3339611803 |
|
|
Oct 13 12:35:48 AM UTC 24 |
Oct 13 01:08:36 AM UTC 24 |
9424010400 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.3834526001 |
|
|
Oct 13 12:59:20 AM UTC 24 |
Oct 13 01:08:52 AM UTC 24 |
5375660536 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1236377779 |
|
|
Oct 12 07:48:57 PM UTC 24 |
Oct 13 01:09:10 AM UTC 24 |
81957637490 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.3722119543 |
|
|
Oct 13 12:51:56 AM UTC 24 |
Oct 13 01:10:36 AM UTC 24 |
12206663031 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.1915007551 |
|
|
Oct 13 01:01:59 AM UTC 24 |
Oct 13 01:11:11 AM UTC 24 |
3355797928 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2180873000 |
|
|
Oct 13 01:04:23 AM UTC 24 |
Oct 13 01:11:12 AM UTC 24 |
3582537192 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.3081336050 |
|
|
Oct 12 11:32:19 PM UTC 24 |
Oct 13 01:11:23 AM UTC 24 |
46855452959 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.2823519467 |
|
|
Oct 13 12:41:35 AM UTC 24 |
Oct 13 01:11:54 AM UTC 24 |
8280788016 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.2775837008 |
|
|
Oct 13 01:02:29 AM UTC 24 |
Oct 13 01:12:07 AM UTC 24 |
7646139924 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.3180489877 |
|
|
Oct 13 01:01:26 AM UTC 24 |
Oct 13 01:12:37 AM UTC 24 |
5499986120 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.1722571825 |
|
|
Oct 13 12:55:23 AM UTC 24 |
Oct 13 01:12:51 AM UTC 24 |
10150948179 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1907046770 |
|
|
Oct 13 01:05:53 AM UTC 24 |
Oct 13 01:13:43 AM UTC 24 |
5851360378 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.325968065 |
|
|
Oct 13 01:04:08 AM UTC 24 |
Oct 13 01:14:32 AM UTC 24 |
5793583872 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.894858268 |
|
|
Oct 13 01:04:46 AM UTC 24 |
Oct 13 01:14:49 AM UTC 24 |
5716319960 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2403788745 |
|
|
Oct 13 01:09:16 AM UTC 24 |
Oct 13 01:15:09 AM UTC 24 |
2885153596 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.3990176250 |
|
|
Oct 13 12:43:16 AM UTC 24 |
Oct 13 01:15:30 AM UTC 24 |
15337987409 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.3452118698 |
|
|
Oct 13 12:48:30 AM UTC 24 |
Oct 13 01:16:00 AM UTC 24 |
8132747668 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.2231256075 |
|
|
Oct 12 11:32:05 PM UTC 24 |
Oct 13 01:16:08 AM UTC 24 |
47955775876 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.367226719 |
|
|
Oct 13 01:07:54 AM UTC 24 |
Oct 13 01:16:10 AM UTC 24 |
4354970560 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.2319160672 |
|
|
Oct 12 11:24:48 PM UTC 24 |
Oct 13 01:16:14 AM UTC 24 |
44476232138 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.565209052 |
|
|
Oct 13 01:11:15 AM UTC 24 |
Oct 13 01:17:14 AM UTC 24 |
3584086572 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.2273964749 |
|
|
Oct 13 01:09:15 AM UTC 24 |
Oct 13 01:17:47 AM UTC 24 |
5543910371 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.1945311822 |
|
|
Oct 13 01:08:48 AM UTC 24 |
Oct 13 01:17:56 AM UTC 24 |
4637575956 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.374153275 |
|
|
Oct 13 01:08:44 AM UTC 24 |
Oct 13 01:18:15 AM UTC 24 |
4228947352 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.3030416200 |
|
|
Oct 13 01:09:31 AM UTC 24 |
Oct 13 01:18:45 AM UTC 24 |
4068198928 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.3035518248 |
|
|
Oct 13 01:05:52 AM UTC 24 |
Oct 13 01:18:46 AM UTC 24 |
5072226556 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.855072615 |
|
|
Oct 12 11:31:27 PM UTC 24 |
Oct 13 01:18:53 AM UTC 24 |
52546964425 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1577070060 |
|
|
Oct 13 12:57:55 AM UTC 24 |
Oct 13 01:19:30 AM UTC 24 |
10599807113 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.2876098279 |
|
|
Oct 13 01:00:40 AM UTC 24 |
Oct 13 01:20:07 AM UTC 24 |
9670564665 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.974314788 |
|
|
Oct 13 01:09:55 AM UTC 24 |
Oct 13 01:20:27 AM UTC 24 |
7283601871 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1338282511 |
|
|
Oct 13 01:12:44 AM UTC 24 |
Oct 13 01:20:27 AM UTC 24 |
3738993528 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3158753013 |
|
|
Oct 13 01:14:21 AM UTC 24 |
Oct 13 01:21:19 AM UTC 24 |
3356145960 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.2685979075 |
|
|
Oct 13 01:13:28 AM UTC 24 |
Oct 13 01:21:37 AM UTC 24 |
6852358572 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1722891384 |
|
|
Oct 13 01:16:09 AM UTC 24 |
Oct 13 01:22:54 AM UTC 24 |
4422781280 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4219660186 |
|
|
Oct 13 01:13:13 AM UTC 24 |
Oct 13 01:22:59 AM UTC 24 |
4170333088 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.4294273375 |
|
|
Oct 13 01:12:47 AM UTC 24 |
Oct 13 01:24:04 AM UTC 24 |
5221643598 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.29548054 |
|
|
Oct 13 01:17:14 AM UTC 24 |
Oct 13 01:24:50 AM UTC 24 |
4218508038 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.3824290606 |
|
|
Oct 13 01:15:13 AM UTC 24 |
Oct 13 01:24:52 AM UTC 24 |
4442268736 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.4245944216 |
|
|
Oct 13 01:15:28 AM UTC 24 |
Oct 13 01:25:01 AM UTC 24 |
3936044572 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.2611170408 |
|
|
Oct 13 01:04:16 AM UTC 24 |
Oct 13 01:25:13 AM UTC 24 |
12328749194 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029870119 |
|
|
Oct 13 01:18:04 AM UTC 24 |
Oct 13 01:25:30 AM UTC 24 |
3696683160 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.2797005464 |
|
|
Oct 13 01:17:11 AM UTC 24 |
Oct 13 01:25:41 AM UTC 24 |
3541603720 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2761095514 |
|
|
Oct 13 01:19:47 AM UTC 24 |
Oct 13 01:25:42 AM UTC 24 |
3719217744 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2095671338 |
|
|
Oct 13 12:31:20 AM UTC 24 |
Oct 13 01:26:23 AM UTC 24 |
10867331562 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3508390358 |
|
|
Oct 13 12:59:38 AM UTC 24 |
Oct 13 01:26:35 AM UTC 24 |
8248769350 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2228133699 |
|
|
Oct 13 01:12:14 AM UTC 24 |
Oct 13 01:26:36 AM UTC 24 |
6184940466 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2768570597 |
|
|
Oct 13 01:18:54 AM UTC 24 |
Oct 13 01:27:30 AM UTC 24 |
3998842882 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.3991216966 |
|
|
Oct 13 01:18:37 AM UTC 24 |
Oct 13 01:27:47 AM UTC 24 |
5285174888 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.565644106 |
|
|
Oct 13 01:18:04 AM UTC 24 |
Oct 13 01:28:00 AM UTC 24 |
4431256112 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3530776231 |
|
|
Oct 13 01:21:18 AM UTC 24 |
Oct 13 01:28:21 AM UTC 24 |
3758176200 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.1621946542 |
|
|
Oct 13 01:17:15 AM UTC 24 |
Oct 13 01:28:30 AM UTC 24 |
6282250958 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.2324030441 |
|
|
Oct 13 01:17:13 AM UTC 24 |
Oct 13 01:28:31 AM UTC 24 |
5927873404 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3953574514 |
|
|
Oct 13 01:21:58 AM UTC 24 |
Oct 13 01:28:59 AM UTC 24 |
3610233172 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.3079522667 |
|
|
Oct 13 01:15:47 AM UTC 24 |
Oct 13 01:31:03 AM UTC 24 |
10859558015 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1841183006 |
|
|
Oct 13 01:23:43 AM UTC 24 |
Oct 13 01:31:09 AM UTC 24 |
4114403098 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.1113129478 |
|
|
Oct 13 01:21:18 AM UTC 24 |
Oct 13 01:31:27 AM UTC 24 |
5612861630 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.817727338 |
|
|
Oct 13 01:19:45 AM UTC 24 |
Oct 13 01:31:29 AM UTC 24 |
5523179656 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.868429561 |
|
|
Oct 13 01:20:09 AM UTC 24 |
Oct 13 01:32:11 AM UTC 24 |
4543134024 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1204100528 |
|
|
Oct 13 01:26:35 AM UTC 24 |
Oct 13 01:32:27 AM UTC 24 |
3762161628 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3570145217 |
|
|
Oct 13 01:24:44 AM UTC 24 |
Oct 13 01:32:43 AM UTC 24 |
3559533072 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.531860994 |
|
|
Oct 13 01:12:11 AM UTC 24 |
Oct 13 01:32:55 AM UTC 24 |
12189180536 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.632016391 |
|
|
Oct 13 01:22:16 AM UTC 24 |
Oct 13 01:33:01 AM UTC 24 |
4409153850 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834420333 |
|
|
Oct 13 01:26:35 AM UTC 24 |
Oct 13 01:33:29 AM UTC 24 |
4083662160 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263133118 |
|
|
Oct 13 01:27:10 AM UTC 24 |
Oct 13 01:33:43 AM UTC 24 |
3321456524 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.9063064 |
|
|
Oct 13 01:27:26 AM UTC 24 |
Oct 13 01:34:20 AM UTC 24 |
3675050704 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.231015130 |
|
|
Oct 13 01:26:39 AM UTC 24 |
Oct 13 01:34:36 AM UTC 24 |
4450485566 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1543314076 |
|
|
Oct 13 01:26:44 AM UTC 24 |
Oct 13 01:34:45 AM UTC 24 |
4441410690 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.2361270772 |
|
|
Oct 13 01:23:43 AM UTC 24 |
Oct 13 01:35:00 AM UTC 24 |
5674676858 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4172218543 |
|
|
Oct 13 01:29:21 AM UTC 24 |
Oct 13 01:35:42 AM UTC 24 |
3949453384 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.449727640 |
|
|
Oct 13 01:28:37 AM UTC 24 |
Oct 13 01:36:07 AM UTC 24 |
3452278040 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.344846864 |
|
|
Oct 13 01:26:45 AM UTC 24 |
Oct 13 01:36:13 AM UTC 24 |
5059869120 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.3940953241 |
|
|
Oct 13 01:26:36 AM UTC 24 |
Oct 13 01:36:23 AM UTC 24 |
4968667394 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.3506769596 |
|
|
Oct 13 01:26:45 AM UTC 24 |
Oct 13 01:36:39 AM UTC 24 |
5649962350 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3283705179 |
|
|
Oct 13 01:09:55 AM UTC 24 |
Oct 13 01:36:42 AM UTC 24 |
9040165260 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325568491 |
|
|
Oct 13 01:29:35 AM UTC 24 |
Oct 13 01:36:54 AM UTC 24 |
3697030028 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.3410139713 |
|
|
Oct 13 12:31:11 AM UTC 24 |
Oct 13 01:36:54 AM UTC 24 |
29358039876 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3386587198 |
|
|
Oct 13 01:28:41 AM UTC 24 |
Oct 13 01:37:25 AM UTC 24 |
4239953480 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.1001945385 |
|
|
Oct 13 01:12:12 AM UTC 24 |
Oct 13 01:37:33 AM UTC 24 |
7705177640 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2172676476 |
|
|
Oct 13 01:27:27 AM UTC 24 |
Oct 13 01:38:45 AM UTC 24 |
6140450320 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2085343735 |
|
|
Oct 13 01:33:56 AM UTC 24 |
Oct 13 01:39:00 AM UTC 24 |
3216424298 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.58207034 |
|
|
Oct 13 01:32:19 AM UTC 24 |
Oct 13 01:39:00 AM UTC 24 |
3641102100 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.1232555464 |
|
|
Oct 13 12:32:13 AM UTC 24 |
Oct 13 01:39:16 AM UTC 24 |
14564490500 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.489113150 |
|
|
Oct 13 12:30:44 AM UTC 24 |
Oct 13 01:39:20 AM UTC 24 |
15385795848 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.275582509 |
|
|
Oct 13 01:33:47 AM UTC 24 |
Oct 13 01:39:45 AM UTC 24 |
3425795024 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.3673156339 |
|
|
Oct 13 01:28:10 AM UTC 24 |
Oct 13 01:39:48 AM UTC 24 |
6529113864 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2605716143 |
|
|
Oct 13 01:32:19 AM UTC 24 |
Oct 13 01:39:58 AM UTC 24 |
4387300032 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2252359275 |
|
|
Oct 13 01:29:37 AM UTC 24 |
Oct 13 01:40:03 AM UTC 24 |
5915467804 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687156068 |
|
|
Oct 13 01:34:24 AM UTC 24 |
Oct 13 01:40:14 AM UTC 24 |
3081392160 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.786603161 |
|
|
Oct 13 01:33:55 AM UTC 24 |
Oct 13 01:40:55 AM UTC 24 |
3101936000 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.697877633 |
|
|
Oct 13 12:51:23 AM UTC 24 |
Oct 13 01:41:16 AM UTC 24 |
12917857019 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1095345931 |
|
|
Oct 13 01:29:40 AM UTC 24 |
Oct 13 01:41:23 AM UTC 24 |
6179990040 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3044039263 |
|
|
Oct 13 01:35:08 AM UTC 24 |
Oct 13 01:41:57 AM UTC 24 |
3284543400 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.2861565618 |
|
|
Oct 13 01:32:18 AM UTC 24 |
Oct 13 01:42:19 AM UTC 24 |
4727813384 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844637770 |
|
|
Oct 13 01:36:21 AM UTC 24 |
Oct 13 01:42:28 AM UTC 24 |
3164793048 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3192326152 |
|
|
Oct 13 01:35:34 AM UTC 24 |
Oct 13 01:42:39 AM UTC 24 |
4161188072 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.290988044 |
|
|
Oct 13 01:33:23 AM UTC 24 |
Oct 13 01:42:41 AM UTC 24 |
5427240100 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.2111140847 |
|
|
Oct 13 01:33:47 AM UTC 24 |
Oct 13 01:42:44 AM UTC 24 |
4583788168 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.691125518 |
|
|
Oct 12 11:57:56 PM UTC 24 |
Oct 13 01:42:55 AM UTC 24 |
22246984080 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3317517045 |
|
|
Oct 13 01:32:23 AM UTC 24 |
Oct 13 01:43:04 AM UTC 24 |
4355013260 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.4074471185 |
|
|
Oct 13 01:18:37 AM UTC 24 |
Oct 13 01:43:22 AM UTC 24 |
7804598532 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.2491263895 |
|
|
Oct 13 01:34:25 AM UTC 24 |
Oct 13 01:43:30 AM UTC 24 |
5077006098 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2219385208 |
|
|
Oct 13 12:27:18 AM UTC 24 |
Oct 13 01:44:16 AM UTC 24 |
25005685067 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1539432956 |
|
|
Oct 13 01:38:27 AM UTC 24 |
Oct 13 01:44:18 AM UTC 24 |
3683740000 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.691686185 |
|
|
Oct 13 12:33:59 AM UTC 24 |
Oct 13 01:44:24 AM UTC 24 |
14817952824 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.699173452 |
|
|
Oct 13 12:32:51 AM UTC 24 |
Oct 13 01:44:28 AM UTC 24 |
15300035576 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2152074192 |
|
|
Oct 13 01:38:29 AM UTC 24 |
Oct 13 01:44:33 AM UTC 24 |
4223099880 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1024017892 |
|
|
Oct 13 12:33:52 AM UTC 24 |
Oct 13 01:44:47 AM UTC 24 |
15264969436 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.2427420910 |
|
|
Oct 13 01:35:38 AM UTC 24 |
Oct 13 01:45:02 AM UTC 24 |
5904240098 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3118735252 |
|
|
Oct 13 01:38:14 AM UTC 24 |
Oct 13 01:45:27 AM UTC 24 |
3938971060 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.371845890 |
|
|
Oct 13 01:33:52 AM UTC 24 |
Oct 13 01:45:31 AM UTC 24 |
5712210900 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.4106619192 |
|
|
Oct 13 01:35:24 AM UTC 24 |
Oct 13 01:46:02 AM UTC 24 |
5681310344 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.423380591 |
|
|
Oct 13 01:39:23 AM UTC 24 |
Oct 13 01:46:12 AM UTC 24 |
3378340720 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3151239283 |
|
|
Oct 13 01:41:02 AM UTC 24 |
Oct 13 01:46:19 AM UTC 24 |
3158843990 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1375000948 |
|
|
Oct 13 01:38:35 AM UTC 24 |
Oct 13 01:46:33 AM UTC 24 |
4594011770 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2422521157 |
|
|
Oct 13 12:27:47 AM UTC 24 |
Oct 13 01:47:00 AM UTC 24 |
22941167676 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1112910713 |
|
|
Oct 13 01:04:22 AM UTC 24 |
Oct 13 01:47:22 AM UTC 24 |
12654353168 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293238430 |
|
|
Oct 13 01:41:19 AM UTC 24 |
Oct 13 01:47:26 AM UTC 24 |
4259808868 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.2436705738 |
|
|
Oct 13 01:38:29 AM UTC 24 |
Oct 13 01:47:31 AM UTC 24 |
4940587700 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.901344514 |
|
|
Oct 13 01:20:47 AM UTC 24 |
Oct 13 01:47:35 AM UTC 24 |
8690940834 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.3934543543 |
|
|
Oct 13 12:32:48 AM UTC 24 |
Oct 13 01:47:41 AM UTC 24 |
15112497746 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.780718373 |
|
|
Oct 13 01:38:36 AM UTC 24 |
Oct 13 01:47:42 AM UTC 24 |
4256922888 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4053265487 |
|
|
Oct 13 01:41:40 AM UTC 24 |
Oct 13 01:47:45 AM UTC 24 |
4351539640 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.740113831 |
|
|
Oct 13 01:08:32 AM UTC 24 |
Oct 13 01:47:58 AM UTC 24 |
8840171612 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264798983 |
|
|
Oct 13 01:42:08 AM UTC 24 |
Oct 13 01:48:08 AM UTC 24 |
3554710284 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.2282767344 |
|
|
Oct 13 12:33:08 AM UTC 24 |
Oct 13 01:48:29 AM UTC 24 |
15773390082 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540655641 |
|
|
Oct 13 01:42:14 AM UTC 24 |
Oct 13 01:48:37 AM UTC 24 |
4335803680 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.855584598 |
|
|
Oct 13 01:40:30 AM UTC 24 |
Oct 13 01:48:45 AM UTC 24 |
4290427748 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.1234676685 |
|
|
Oct 13 01:41:20 AM UTC 24 |
Oct 13 01:49:34 AM UTC 24 |
5519213988 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.675814531 |
|
|
Oct 13 12:34:11 AM UTC 24 |
Oct 13 01:49:48 AM UTC 24 |
15108684082 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1407311498 |
|
|
Oct 13 01:38:15 AM UTC 24 |
Oct 13 01:49:54 AM UTC 24 |
6011971580 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.448897737 |
|
|
Oct 13 01:44:35 AM UTC 24 |
Oct 13 01:49:56 AM UTC 24 |
4109852604 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937997673 |
|
|
Oct 13 01:42:37 AM UTC 24 |
Oct 13 01:49:59 AM UTC 24 |
3215008008 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.3979593720 |
|
|
Oct 13 01:38:32 AM UTC 24 |
Oct 13 01:50:02 AM UTC 24 |
4856924878 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.2021446962 |
|
|
Oct 13 12:32:50 AM UTC 24 |
Oct 13 01:50:07 AM UTC 24 |
15844571977 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.2389013946 |
|
|
Oct 13 01:41:03 AM UTC 24 |
Oct 13 01:50:19 AM UTC 24 |
5409719894 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529979264 |
|
|
Oct 13 01:44:32 AM UTC 24 |
Oct 13 01:50:30 AM UTC 24 |
4107393728 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.2092649022 |
|
|
Oct 13 01:42:14 AM UTC 24 |
Oct 13 01:50:33 AM UTC 24 |
5855716476 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3630180634 |
|
|
Oct 13 01:44:39 AM UTC 24 |
Oct 13 01:51:00 AM UTC 24 |
3855003600 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.759827147 |
|
|
Oct 13 01:44:44 AM UTC 24 |
Oct 13 01:51:13 AM UTC 24 |
4334920856 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420778478 |
|
|
Oct 13 01:46:05 AM UTC 24 |
Oct 13 01:51:33 AM UTC 24 |
3305652854 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.741625531 |
|
|
Oct 13 01:41:52 AM UTC 24 |
Oct 13 01:51:36 AM UTC 24 |
5686037840 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.3234101048 |
|
|
Oct 13 01:41:53 AM UTC 24 |
Oct 13 01:52:18 AM UTC 24 |
5843420380 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2500199209 |
|
|
Oct 13 01:46:26 AM UTC 24 |
Oct 13 01:52:20 AM UTC 24 |
3960982228 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.2008820234 |
|
|
Oct 13 01:41:28 AM UTC 24 |
Oct 13 01:52:32 AM UTC 24 |
4863699048 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.466921492 |
|
|
Oct 13 01:42:09 AM UTC 24 |
Oct 13 01:52:38 AM UTC 24 |
5255896248 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.966547814 |
|
|
Oct 13 01:44:27 AM UTC 24 |
Oct 13 01:52:39 AM UTC 24 |
4120014244 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.700614704 |
|
|
Oct 13 01:44:45 AM UTC 24 |
Oct 13 01:52:40 AM UTC 24 |
4116167300 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3980494819 |
|
|
Oct 13 01:46:30 AM UTC 24 |
Oct 13 01:53:04 AM UTC 24 |
3695095400 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.322612068 |
|
|
Oct 13 01:47:56 AM UTC 24 |
Oct 13 01:53:15 AM UTC 24 |
3891258720 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943922566 |
|
|
Oct 13 01:47:42 AM UTC 24 |
Oct 13 01:53:27 AM UTC 24 |
3747435140 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2193520477 |
|
|
Oct 13 01:43:47 AM UTC 24 |
Oct 13 01:53:38 AM UTC 24 |
5361266296 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3009196441 |
|
|
Oct 13 01:47:26 AM UTC 24 |
Oct 13 01:53:43 AM UTC 24 |
4749597384 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1632616685 |
|
|
Oct 13 01:47:22 AM UTC 24 |
Oct 13 01:53:45 AM UTC 24 |
3806896584 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.2759698972 |
|
|
Oct 13 01:44:37 AM UTC 24 |
Oct 13 01:54:09 AM UTC 24 |
4749328460 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.3654041870 |
|
|
Oct 13 01:44:41 AM UTC 24 |
Oct 13 01:54:11 AM UTC 24 |
4362284750 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.2694776293 |
|
|
Oct 13 01:46:44 AM UTC 24 |
Oct 13 01:54:19 AM UTC 24 |
4802707516 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1242969429 |
|
|
Oct 13 01:49:32 AM UTC 24 |
Oct 13 01:54:52 AM UTC 24 |
3587662152 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.287108539 |
|
|
Oct 13 01:49:27 AM UTC 24 |
Oct 13 01:54:55 AM UTC 24 |
4128719232 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.421553666 |
|
|
Oct 13 01:46:42 AM UTC 24 |
Oct 13 01:55:01 AM UTC 24 |
5478772712 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2479021917 |
|
|
Oct 13 01:49:57 AM UTC 24 |
Oct 13 01:55:20 AM UTC 24 |
4048927720 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1528506902 |
|
|
Oct 13 01:50:08 AM UTC 24 |
Oct 13 01:55:51 AM UTC 24 |
3548143376 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3342169950 |
|
|
Oct 13 01:46:13 AM UTC 24 |
Oct 13 01:55:52 AM UTC 24 |
5143807672 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1874695247 |
|
|
Oct 13 01:46:26 AM UTC 24 |
Oct 13 01:56:13 AM UTC 24 |
5822876078 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_all_escalation_resets.3554505280 |
|
|
Oct 13 01:47:44 AM UTC 24 |
Oct 13 01:56:58 AM UTC 24 |
4978479844 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3607379451 |
|
|
Oct 13 12:34:10 AM UTC 24 |
Oct 13 01:57:14 AM UTC 24 |
17020570400 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3060872974 |
|
|
Oct 13 01:51:46 AM UTC 24 |
Oct 13 01:57:34 AM UTC 24 |
3485458488 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339833122 |
|
|
Oct 13 01:51:29 AM UTC 24 |
Oct 13 01:57:40 AM UTC 24 |
3700916708 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.2675253892 |
|
|
Oct 13 01:48:52 AM UTC 24 |
Oct 13 01:58:05 AM UTC 24 |
5435882660 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.2447193653 |
|
|
Oct 13 01:47:41 AM UTC 24 |
Oct 13 01:58:12 AM UTC 24 |
5207329486 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027255114 |
|
|
Oct 13 01:51:48 AM UTC 24 |
Oct 13 01:58:12 AM UTC 24 |
4288458894 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1610979592 |
|
|
Oct 13 01:53:00 AM UTC 24 |
Oct 13 01:58:16 AM UTC 24 |
4263723960 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.527263456 |
|
|
Oct 13 01:51:46 AM UTC 24 |
Oct 13 01:58:20 AM UTC 24 |
3882267400 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3527228533 |
|
|
Oct 13 01:52:41 AM UTC 24 |
Oct 13 01:58:35 AM UTC 24 |
4033107720 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.4066404412 |
|
|
Oct 13 01:47:29 AM UTC 24 |
Oct 13 01:58:54 AM UTC 24 |
5904427000 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3153217075 |
|
|
Oct 13 01:52:53 AM UTC 24 |
Oct 13 01:59:05 AM UTC 24 |
3500024440 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.911072324 |
|
|
Oct 13 01:53:13 AM UTC 24 |
Oct 13 01:59:36 AM UTC 24 |
3180840808 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3746081746 |
|
|
Oct 13 01:52:39 AM UTC 24 |
Oct 13 01:59:37 AM UTC 24 |
4112172884 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.3476810008 |
|
|
Oct 13 01:51:51 AM UTC 24 |
Oct 13 02:00:02 AM UTC 24 |
5011934940 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.2995631842 |
|
|
Oct 13 01:51:06 AM UTC 24 |
Oct 13 02:00:07 AM UTC 24 |
5115308512 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.847641767 |
|
|
Oct 13 01:51:36 AM UTC 24 |
Oct 13 02:00:47 AM UTC 24 |
4480946712 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.357641109 |
|
|
Oct 13 01:55:05 AM UTC 24 |
Oct 13 02:00:54 AM UTC 24 |
3556729864 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.3144585695 |
|
|
Oct 13 01:51:44 AM UTC 24 |
Oct 13 02:00:56 AM UTC 24 |
5197852672 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.87085017 |
|
|
Oct 13 01:55:31 AM UTC 24 |
Oct 13 02:01:02 AM UTC 24 |
3504881232 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2775284322 |
|
|
Oct 13 01:52:21 AM UTC 24 |
Oct 13 02:01:04 AM UTC 24 |
5010034790 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3746602972 |
|
|
Oct 13 01:55:05 AM UTC 24 |
Oct 13 02:01:08 AM UTC 24 |
4444724304 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.217745293 |
|
|
Oct 13 01:55:18 AM UTC 24 |
Oct 13 02:01:15 AM UTC 24 |
4135499360 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.4004592018 |
|
|
Oct 13 01:53:01 AM UTC 24 |
Oct 13 02:01:27 AM UTC 24 |
5184807560 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.3355296956 |
|
|
Oct 13 01:51:35 AM UTC 24 |
Oct 13 02:01:51 AM UTC 24 |
5748013898 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.3089648211 |
|
|
Oct 13 01:53:01 AM UTC 24 |
Oct 13 02:01:51 AM UTC 24 |
4168016840 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.3226607390 |
|
|
Oct 13 01:51:35 AM UTC 24 |
Oct 13 02:02:03 AM UTC 24 |
5988942168 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3474016118 |
|
|
Oct 13 01:55:31 AM UTC 24 |
Oct 13 02:02:07 AM UTC 24 |
4254260860 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.444839751 |
|
|
Oct 13 01:53:25 AM UTC 24 |
Oct 13 02:02:52 AM UTC 24 |
4456813720 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1555198455 |
|
|
Oct 13 01:57:11 AM UTC 24 |
Oct 13 02:02:52 AM UTC 24 |
3447835866 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1958341978 |
|
|
Oct 13 01:57:02 AM UTC 24 |
Oct 13 02:03:00 AM UTC 24 |
4120345840 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.845076608 |
|
|
Oct 13 01:56:05 AM UTC 24 |
Oct 13 02:03:19 AM UTC 24 |
3526644912 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.1824339161 |
|
|
Oct 13 01:52:38 AM UTC 24 |
Oct 13 02:03:24 AM UTC 24 |
5610294664 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.3542606382 |
|
|
Oct 13 01:54:15 AM UTC 24 |
Oct 13 02:03:26 AM UTC 24 |
5055838576 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.610979716 |
|
|
Oct 13 01:53:25 AM UTC 24 |
Oct 13 02:03:30 AM UTC 24 |
5881793290 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3058077953 |
|
|
Oct 13 01:57:02 AM UTC 24 |
Oct 13 02:03:33 AM UTC 24 |
3643443004 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.3216173985 |
|
|
Oct 13 01:56:03 AM UTC 24 |
Oct 13 02:03:45 AM UTC 24 |
5843682648 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3067017909 |
|
|
Oct 13 01:56:57 AM UTC 24 |
Oct 13 02:03:47 AM UTC 24 |
3184026736 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348592805 |
|
|
Oct 13 01:57:52 AM UTC 24 |
Oct 13 02:04:03 AM UTC 24 |
3116090120 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1950401530 |
|
|
Oct 13 01:55:01 AM UTC 24 |
Oct 13 02:04:20 AM UTC 24 |
5084769474 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2979935398 |
|
|
Oct 13 01:57:11 AM UTC 24 |
Oct 13 02:05:30 AM UTC 24 |
4584041520 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3628936683 |
|
|
Oct 13 01:58:24 AM UTC 24 |
Oct 13 02:05:36 AM UTC 24 |
3755684232 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.2260694897 |
|
|
Oct 13 01:56:02 AM UTC 24 |
Oct 13 02:05:38 AM UTC 24 |
4821237114 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.1999764678 |
|
|
Oct 13 01:56:11 AM UTC 24 |
Oct 13 02:05:39 AM UTC 24 |
5600309628 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.1246723001 |
|
|
Oct 13 01:56:38 AM UTC 24 |
Oct 13 02:05:48 AM UTC 24 |
5522018296 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.1718985277 |
|
|
Oct 13 12:58:37 AM UTC 24 |
Oct 13 02:06:04 AM UTC 24 |
15870584670 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1153969273 |
|
|
Oct 13 01:19:47 AM UTC 24 |
Oct 13 02:06:05 AM UTC 24 |
13773869330 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.3320861582 |
|
|
Oct 13 01:56:10 AM UTC 24 |
Oct 13 02:06:18 AM UTC 24 |
5448343640 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.3884348030 |
|
|
Oct 13 01:56:04 AM UTC 24 |
Oct 13 02:06:19 AM UTC 24 |
6115745068 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.119546219 |
|
|
Oct 13 01:57:34 AM UTC 24 |
Oct 13 02:06:50 AM UTC 24 |
4655299600 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.2577154371 |
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|
Oct 13 01:57:09 AM UTC 24 |
Oct 13 02:07:06 AM UTC 24 |
6502103848 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3691083718 |
|
|
Oct 13 01:58:23 AM UTC 24 |
Oct 13 02:07:29 AM UTC 24 |
4677525984 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2565081639 |
|
|
Oct 13 02:00:17 AM UTC 24 |
Oct 13 02:07:42 AM UTC 24 |
5442026540 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.4224469243 |
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|
Oct 13 02:00:40 AM UTC 24 |
Oct 13 02:08:07 AM UTC 24 |
4531758984 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.3735242423 |
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|
Oct 13 12:52:40 AM UTC 24 |
Oct 13 02:08:09 AM UTC 24 |
17294131550 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.4214375856 |
|
|
Oct 13 02:00:41 AM UTC 24 |
Oct 13 02:08:25 AM UTC 24 |
4642425288 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.7038422 |
|
|
Oct 13 02:00:36 AM UTC 24 |
Oct 13 02:08:32 AM UTC 24 |
5315985456 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.987426693 |
|
|
Oct 13 02:00:30 AM UTC 24 |
Oct 13 02:08:36 AM UTC 24 |
5858755832 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2489977437 |
|
|
Oct 13 02:00:34 AM UTC 24 |
Oct 13 02:08:47 AM UTC 24 |
4687179868 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.1693604875 |
|
|
Oct 13 02:00:02 AM UTC 24 |
Oct 13 02:08:51 AM UTC 24 |
5813170384 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.1516548363 |
|
|
Oct 13 02:00:26 AM UTC 24 |
Oct 13 02:08:54 AM UTC 24 |
6212025854 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.2413204850 |
|
|
Oct 13 02:00:37 AM UTC 24 |
Oct 13 02:09:42 AM UTC 24 |
4522194946 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2367744208 |
|
|
Oct 13 02:00:41 AM UTC 24 |
Oct 13 02:11:24 AM UTC 24 |
5674229860 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_inject_scramble_seed.393249659 |
|
|
Oct 12 09:53:26 PM UTC 24 |
Oct 13 02:13:12 AM UTC 24 |
66745841620 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.745573642 |
|
|
Oct 13 01:00:44 AM UTC 24 |
Oct 13 02:26:58 AM UTC 24 |
22454100184 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.3842659782 |
|
|
Oct 13 01:03:21 AM UTC 24 |
Oct 13 02:27:19 AM UTC 24 |
19182914120 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.3547777934 |
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|
Oct 13 01:04:23 AM UTC 24 |
Oct 13 02:29:44 AM UTC 24 |
21616720880 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.2750064673 |
|
|
Oct 13 12:34:08 AM UTC 24 |
Oct 13 02:30:23 AM UTC 24 |
26407346476 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.464637856 |
|
|
Oct 13 12:43:00 AM UTC 24 |
Oct 13 02:30:51 AM UTC 24 |
25682701902 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1608366672 |
|
|
Oct 12 11:16:03 PM UTC 24 |
Oct 13 02:42:20 AM UTC 24 |
63090092848 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.290723369 |
|
|
Oct 12 09:53:21 PM UTC 24 |
Oct 13 02:46:37 AM UTC 24 |
80690694776 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.3903865355 |
|
|
Oct 12 11:16:09 PM UTC 24 |
Oct 13 03:02:29 AM UTC 24 |
69079973636 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2929062881 |
|
|
Oct 12 11:52:46 PM UTC 24 |
Oct 13 03:19:17 AM UTC 24 |
255028459880 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.241679668 |
|
|
Oct 12 11:16:01 PM UTC 24 |
Oct 13 03:31:13 AM UTC 24 |
81974013900 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3732981089 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:46:29 PM UTC 24 |
43748664 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.3644941423 |
|
|
Oct 12 05:46:22 PM UTC 24 |
Oct 12 05:46:32 PM UTC 24 |
198768783 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.720999571 |
|
|
Oct 12 05:46:21 PM UTC 24 |
Oct 12 05:46:35 PM UTC 24 |
278966373 ps |