| T62 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1245124694 |
|
|
Aug 25 07:25:06 PM UTC 24 |
Aug 25 07:44:25 PM UTC 24 |
4602682856 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1696059005 |
|
|
Aug 25 07:36:38 PM UTC 24 |
Aug 25 07:45:37 PM UTC 24 |
3712422954 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2163393914 |
|
|
Aug 25 07:03:53 PM UTC 24 |
Aug 25 07:45:45 PM UTC 24 |
11653629378 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.772722278 |
|
|
Aug 25 06:09:07 PM UTC 24 |
Aug 25 07:46:38 PM UTC 24 |
18564819720 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1763329380 |
|
|
Aug 25 07:35:15 PM UTC 24 |
Aug 25 07:46:46 PM UTC 24 |
5339938232 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.1890577701 |
|
|
Aug 25 07:39:59 PM UTC 24 |
Aug 25 07:47:09 PM UTC 24 |
2516029136 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2426103254 |
|
|
Aug 25 07:30:33 PM UTC 24 |
Aug 25 07:48:47 PM UTC 24 |
6636475786 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.864605862 |
|
|
Aug 25 07:43:00 PM UTC 24 |
Aug 25 07:49:03 PM UTC 24 |
2540873777 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1017195687 |
|
|
Aug 25 07:41:37 PM UTC 24 |
Aug 25 07:49:25 PM UTC 24 |
3069273900 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.4259112610 |
|
|
Aug 25 07:33:40 PM UTC 24 |
Aug 25 07:49:38 PM UTC 24 |
3884697632 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.754485126 |
|
|
Aug 25 07:47:50 PM UTC 24 |
Aug 25 07:50:46 PM UTC 24 |
2466234535 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2984915877 |
|
|
Aug 25 07:43:35 PM UTC 24 |
Aug 25 07:51:20 PM UTC 24 |
3251128481 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2372469606 |
|
|
Aug 25 07:49:27 PM UTC 24 |
Aug 25 07:52:09 PM UTC 24 |
2246492231 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3186684522 |
|
|
Aug 25 07:18:10 PM UTC 24 |
Aug 25 07:52:24 PM UTC 24 |
8934722760 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.712210756 |
|
|
Aug 25 07:35:14 PM UTC 24 |
Aug 25 07:53:33 PM UTC 24 |
4282463052 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3430451874 |
|
|
Aug 25 07:46:29 PM UTC 24 |
Aug 25 07:54:20 PM UTC 24 |
2950553738 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3377310767 |
|
|
Aug 25 06:17:31 PM UTC 24 |
Aug 25 07:56:17 PM UTC 24 |
17044256440 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1778220530 |
|
|
Aug 25 07:42:14 PM UTC 24 |
Aug 25 07:57:10 PM UTC 24 |
4964078728 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.3196653809 |
|
|
Aug 25 06:56:28 PM UTC 24 |
Aug 25 07:57:28 PM UTC 24 |
18591353400 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.4292342229 |
|
|
Aug 25 07:36:09 PM UTC 24 |
Aug 25 07:57:40 PM UTC 24 |
5810384592 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.1876657887 |
|
|
Aug 25 07:51:27 PM UTC 24 |
Aug 25 07:57:43 PM UTC 24 |
2994313602 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2574458388 |
|
|
Aug 25 07:50:22 PM UTC 24 |
Aug 25 07:59:42 PM UTC 24 |
3375616332 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1685561768 |
|
|
Aug 25 06:58:20 PM UTC 24 |
Aug 25 07:59:57 PM UTC 24 |
10843562281 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2401736949 |
|
|
Aug 25 07:36:10 PM UTC 24 |
Aug 25 08:01:54 PM UTC 24 |
5642251194 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.871850269 |
|
|
Aug 25 07:38:55 PM UTC 24 |
Aug 25 08:02:31 PM UTC 24 |
6009180902 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1532814917 |
|
|
Aug 25 07:22:44 PM UTC 24 |
Aug 25 08:03:51 PM UTC 24 |
8983944599 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.3358669961 |
|
|
Aug 25 07:21:05 PM UTC 24 |
Aug 25 08:03:58 PM UTC 24 |
8711861080 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2577150999 |
|
|
Aug 25 06:17:32 PM UTC 24 |
Aug 25 08:04:03 PM UTC 24 |
18895990179 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3541676032 |
|
|
Aug 25 07:53:09 PM UTC 24 |
Aug 25 08:04:58 PM UTC 24 |
8930823056 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1989871570 |
|
|
Aug 25 07:54:16 PM UTC 24 |
Aug 25 08:05:59 PM UTC 24 |
4036705616 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.465198833 |
|
|
Aug 25 07:53:03 PM UTC 24 |
Aug 25 08:09:58 PM UTC 24 |
5950062136 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3171831456 |
|
|
Aug 25 07:42:14 PM UTC 24 |
Aug 25 08:06:59 PM UTC 24 |
7236913864 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2902749544 |
|
|
Aug 25 07:45:07 PM UTC 24 |
Aug 25 08:07:14 PM UTC 24 |
12562689113 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.3076191782 |
|
|
Aug 25 06:06:53 PM UTC 24 |
Aug 25 08:08:11 PM UTC 24 |
44424376732 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3151049090 |
|
|
Aug 25 08:03:51 PM UTC 24 |
Aug 25 08:09:49 PM UTC 24 |
3006664428 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1719434594 |
|
|
Aug 25 08:04:58 PM UTC 24 |
Aug 25 08:11:16 PM UTC 24 |
3430754180 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1388390870 |
|
|
Aug 25 06:57:31 PM UTC 24 |
Aug 25 08:11:53 PM UTC 24 |
11216364116 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1726324457 |
|
|
Aug 25 07:47:33 PM UTC 24 |
Aug 25 08:12:06 PM UTC 24 |
9616599272 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1991075271 |
|
|
Aug 25 08:00:34 PM UTC 24 |
Aug 25 08:13:33 PM UTC 24 |
6031853408 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2385962421 |
|
|
Aug 25 07:06:30 PM UTC 24 |
Aug 25 08:13:40 PM UTC 24 |
10971501874 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1139881888 |
|
|
Aug 25 07:58:41 PM UTC 24 |
Aug 25 08:13:50 PM UTC 24 |
6882223814 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2517819727 |
|
|
Aug 25 08:05:39 PM UTC 24 |
Aug 25 08:14:22 PM UTC 24 |
3022687117 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2640387453 |
|
|
Aug 25 07:42:56 PM UTC 24 |
Aug 25 08:15:00 PM UTC 24 |
9137782688 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2334382166 |
|
|
Aug 25 06:32:29 PM UTC 24 |
Aug 25 08:15:26 PM UTC 24 |
14451762682 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3682304512 |
|
|
Aug 25 07:42:54 PM UTC 24 |
Aug 25 08:16:22 PM UTC 24 |
9682116450 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1003237871 |
|
|
Aug 25 08:02:35 PM UTC 24 |
Aug 25 08:16:28 PM UTC 24 |
6855094908 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2309200696 |
|
|
Aug 25 08:05:01 PM UTC 24 |
Aug 25 08:17:08 PM UTC 24 |
4984332110 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1531365190 |
|
|
Aug 25 07:01:37 PM UTC 24 |
Aug 25 08:18:48 PM UTC 24 |
11858837470 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1634856239 |
|
|
Aug 25 07:55:02 PM UTC 24 |
Aug 25 08:19:36 PM UTC 24 |
7850239066 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1844050945 |
|
|
Aug 25 08:08:53 PM UTC 24 |
Aug 25 08:19:38 PM UTC 24 |
4164449160 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.19791930 |
|
|
Aug 25 08:07:51 PM UTC 24 |
Aug 25 08:19:51 PM UTC 24 |
5710275040 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4162190865 |
|
|
Aug 25 07:05:08 PM UTC 24 |
Aug 25 08:21:26 PM UTC 24 |
12042641268 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3043698452 |
|
|
Aug 25 08:10:41 PM UTC 24 |
Aug 25 08:22:03 PM UTC 24 |
3816708776 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1417462021 |
|
|
Aug 25 08:06:38 PM UTC 24 |
Aug 25 08:22:33 PM UTC 24 |
4591955720 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.1752834867 |
|
|
Aug 25 07:36:33 PM UTC 24 |
Aug 25 08:23:07 PM UTC 24 |
22382015921 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3818666068 |
|
|
Aug 25 08:10:42 PM UTC 24 |
Aug 25 08:23:09 PM UTC 24 |
8149420646 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.436675862 |
|
|
Aug 25 08:17:48 PM UTC 24 |
Aug 25 08:23:25 PM UTC 24 |
2716613080 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.217899647 |
|
|
Aug 25 08:13:01 PM UTC 24 |
Aug 25 08:23:38 PM UTC 24 |
5188855884 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.942787514 |
|
|
Aug 25 08:17:14 PM UTC 24 |
Aug 25 08:23:50 PM UTC 24 |
2467456958 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1351123742 |
|
|
Aug 25 08:17:14 PM UTC 24 |
Aug 25 08:24:06 PM UTC 24 |
2351021700 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3042865217 |
|
|
Aug 25 08:13:05 PM UTC 24 |
Aug 25 08:24:36 PM UTC 24 |
19999975380 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.38343078 |
|
|
Aug 25 06:56:32 PM UTC 24 |
Aug 25 08:25:08 PM UTC 24 |
15017067448 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3793539700 |
|
|
Aug 25 07:52:01 PM UTC 24 |
Aug 25 08:26:38 PM UTC 24 |
10682681292 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.3070382226 |
|
|
Aug 25 06:55:22 PM UTC 24 |
Aug 25 08:27:23 PM UTC 24 |
15315301328 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.635678309 |
|
|
Aug 25 08:19:29 PM UTC 24 |
Aug 25 08:27:23 PM UTC 24 |
3348108064 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.140469562 |
|
|
Aug 25 07:57:00 PM UTC 24 |
Aug 25 08:27:32 PM UTC 24 |
9713934180 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3799006437 |
|
|
Aug 25 07:00:36 PM UTC 24 |
Aug 25 08:27:44 PM UTC 24 |
14680859640 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2392421660 |
|
|
Aug 25 08:13:07 PM UTC 24 |
Aug 25 08:27:55 PM UTC 24 |
5233692876 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.4192164526 |
|
|
Aug 25 08:15:04 PM UTC 24 |
Aug 25 08:28:30 PM UTC 24 |
3939318748 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2605611843 |
|
|
Aug 25 06:58:09 PM UTC 24 |
Aug 25 08:28:41 PM UTC 24 |
14076879542 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4257663334 |
|
|
Aug 25 07:00:37 PM UTC 24 |
Aug 25 08:28:58 PM UTC 24 |
14399401130 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.1308798866 |
|
|
Aug 25 06:57:34 PM UTC 24 |
Aug 25 08:30:23 PM UTC 24 |
15209123360 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1208281802 |
|
|
Aug 25 08:20:46 PM UTC 24 |
Aug 25 08:30:36 PM UTC 24 |
3574109162 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.893013700 |
|
|
Aug 25 08:24:54 PM UTC 24 |
Aug 25 08:31:12 PM UTC 24 |
2942595940 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.2665637697 |
|
|
Aug 25 08:20:45 PM UTC 24 |
Aug 25 08:31:33 PM UTC 24 |
4500429888 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2094789571 |
|
|
Aug 25 07:05:15 PM UTC 24 |
Aug 25 08:31:52 PM UTC 24 |
14449826684 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1192821979 |
|
|
Aug 25 08:25:13 PM UTC 24 |
Aug 25 08:32:11 PM UTC 24 |
2613593706 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.771614213 |
|
|
Aug 25 08:11:58 PM UTC 24 |
Aug 25 08:32:13 PM UTC 24 |
8338763004 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3625501879 |
|
|
Aug 25 06:59:03 PM UTC 24 |
Aug 25 08:32:36 PM UTC 24 |
42088539350 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1296536672 |
|
|
Aug 25 06:53:56 PM UTC 24 |
Aug 25 08:32:42 PM UTC 24 |
29334104360 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2835505555 |
|
|
Aug 25 07:58:36 PM UTC 24 |
Aug 25 08:33:04 PM UTC 24 |
11377610269 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960322058 |
|
|
Aug 25 08:23:15 PM UTC 24 |
Aug 25 08:33:14 PM UTC 24 |
3665066768 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3293780290 |
|
|
Aug 25 06:11:29 PM UTC 24 |
Aug 25 08:33:24 PM UTC 24 |
46340134551 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3668274839 |
|
|
Aug 25 08:25:14 PM UTC 24 |
Aug 25 08:33:36 PM UTC 24 |
3644322411 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3644587672 |
|
|
Aug 25 07:07:30 PM UTC 24 |
Aug 25 08:33:50 PM UTC 24 |
14761484278 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.964908704 |
|
|
Aug 25 07:02:05 PM UTC 24 |
Aug 25 08:33:53 PM UTC 24 |
15024373080 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2931146698 |
|
|
Aug 25 06:27:48 PM UTC 24 |
Aug 25 08:33:54 PM UTC 24 |
20477109220 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.3446254900 |
|
|
Aug 25 08:20:40 PM UTC 24 |
Aug 25 08:34:03 PM UTC 24 |
5412911110 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2199670769 |
|
|
Aug 25 07:03:17 PM UTC 24 |
Aug 25 08:34:20 PM UTC 24 |
15570530452 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2257977263 |
|
|
Aug 25 08:29:43 PM UTC 24 |
Aug 25 08:35:21 PM UTC 24 |
2136175990 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2699888402 |
|
|
Aug 25 06:58:49 PM UTC 24 |
Aug 25 08:35:43 PM UTC 24 |
14561437889 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.536429898 |
|
|
Aug 25 07:00:52 PM UTC 24 |
Aug 25 08:36:02 PM UTC 24 |
15253187000 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4229927279 |
|
|
Aug 25 07:01:02 PM UTC 24 |
Aug 25 08:36:03 PM UTC 24 |
15124804190 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1293355097 |
|
|
Aug 25 08:28:50 PM UTC 24 |
Aug 25 08:36:07 PM UTC 24 |
2750607440 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4107198542 |
|
|
Aug 25 06:59:47 PM UTC 24 |
Aug 25 08:36:51 PM UTC 24 |
34829888270 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.1850137980 |
|
|
Aug 25 07:05:24 PM UTC 24 |
Aug 25 08:37:02 PM UTC 24 |
15456910524 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1523193147 |
|
|
Aug 25 07:58:37 PM UTC 24 |
Aug 25 08:37:34 PM UTC 24 |
14202249949 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.3659009596 |
|
|
Aug 25 08:31:24 PM UTC 24 |
Aug 25 08:37:44 PM UTC 24 |
3261893156 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1726948974 |
|
|
Aug 25 08:16:07 PM UTC 24 |
Aug 25 08:38:40 PM UTC 24 |
5182736232 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.1159359176 |
|
|
Aug 25 08:14:44 PM UTC 24 |
Aug 25 08:38:50 PM UTC 24 |
6000436200 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.1109578348 |
|
|
Aug 25 08:31:55 PM UTC 24 |
Aug 25 08:38:50 PM UTC 24 |
3728566847 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.1601571986 |
|
|
Aug 25 08:25:48 PM UTC 24 |
Aug 25 08:38:55 PM UTC 24 |
3270209800 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2336623397 |
|
|
Aug 25 06:47:26 PM UTC 24 |
Aug 25 08:38:56 PM UTC 24 |
24893175572 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1094522729 |
|
|
Aug 25 06:59:05 PM UTC 24 |
Aug 25 08:39:39 PM UTC 24 |
15067108016 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.597256479 |
|
|
Aug 25 08:32:15 PM UTC 24 |
Aug 25 08:40:07 PM UTC 24 |
3619513000 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3550209138 |
|
|
Aug 25 08:32:34 PM UTC 24 |
Aug 25 08:40:20 PM UTC 24 |
3424548194 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2791179149 |
|
|
Aug 25 07:03:21 PM UTC 24 |
Aug 25 08:40:21 PM UTC 24 |
15006718079 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3275610572 |
|
|
Aug 25 07:03:20 PM UTC 24 |
Aug 25 08:41:00 PM UTC 24 |
15122983380 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3441052823 |
|
|
Aug 25 08:15:41 PM UTC 24 |
Aug 25 08:41:09 PM UTC 24 |
5404668696 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.4183181686 |
|
|
Aug 25 08:27:19 PM UTC 24 |
Aug 25 08:41:43 PM UTC 24 |
3371013248 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.614696986 |
|
|
Aug 25 08:36:36 PM UTC 24 |
Aug 25 08:42:39 PM UTC 24 |
2486655164 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.451081388 |
|
|
Aug 25 08:36:06 PM UTC 24 |
Aug 25 08:43:00 PM UTC 24 |
3140301900 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2232429641 |
|
|
Aug 25 08:36:23 PM UTC 24 |
Aug 25 08:43:06 PM UTC 24 |
3004801544 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.723200948 |
|
|
Aug 25 07:03:22 PM UTC 24 |
Aug 25 08:43:06 PM UTC 24 |
14776451508 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.4024053539 |
|
|
Aug 25 08:35:43 PM UTC 24 |
Aug 25 08:43:14 PM UTC 24 |
3000827204 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1668077876 |
|
|
Aug 25 07:00:34 PM UTC 24 |
Aug 25 08:43:39 PM UTC 24 |
14482610552 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3353480906 |
|
|
Aug 25 08:29:49 PM UTC 24 |
Aug 25 08:43:53 PM UTC 24 |
4453846072 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3294347904 |
|
|
Aug 25 08:37:41 PM UTC 24 |
Aug 25 08:44:03 PM UTC 24 |
2997925681 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1667456201 |
|
|
Aug 25 08:29:46 PM UTC 24 |
Aug 25 08:44:43 PM UTC 24 |
6544847147 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.4061295957 |
|
|
Aug 25 08:35:57 PM UTC 24 |
Aug 25 08:45:20 PM UTC 24 |
2716789500 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3513160419 |
|
|
Aug 25 07:07:26 PM UTC 24 |
Aug 25 08:45:30 PM UTC 24 |
15282959250 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.1627887176 |
|
|
Aug 25 06:09:51 PM UTC 24 |
Aug 25 08:45:40 PM UTC 24 |
48769461658 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.4174014414 |
|
|
Aug 25 06:59:33 PM UTC 24 |
Aug 25 08:45:54 PM UTC 24 |
33094155366 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3540991268 |
|
|
Aug 25 07:04:42 PM UTC 24 |
Aug 25 08:46:02 PM UTC 24 |
15199680088 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.569242766 |
|
|
Aug 25 08:40:27 PM UTC 24 |
Aug 25 08:46:28 PM UTC 24 |
2689360340 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2175038548 |
|
|
Aug 25 07:06:17 PM UTC 24 |
Aug 25 08:46:45 PM UTC 24 |
15109298694 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2363626715 |
|
|
Aug 25 08:07:58 PM UTC 24 |
Aug 25 08:46:45 PM UTC 24 |
25463333182 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1253797061 |
|
|
Aug 25 08:37:45 PM UTC 24 |
Aug 25 08:47:10 PM UTC 24 |
4774427000 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3894846327 |
|
|
Aug 25 08:36:37 PM UTC 24 |
Aug 25 08:47:24 PM UTC 24 |
4047925867 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3510130536 |
|
|
Aug 25 08:36:05 PM UTC 24 |
Aug 25 08:47:38 PM UTC 24 |
9712903996 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3756605565 |
|
|
Aug 25 08:37:08 PM UTC 24 |
Aug 25 08:48:07 PM UTC 24 |
6962410440 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.2097861259 |
|
|
Aug 25 06:59:31 PM UTC 24 |
Aug 25 08:49:01 PM UTC 24 |
15023148315 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.127819077 |
|
|
Aug 25 08:37:13 PM UTC 24 |
Aug 25 08:49:13 PM UTC 24 |
7192697262 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2499457804 |
|
|
Aug 25 08:36:18 PM UTC 24 |
Aug 25 08:50:00 PM UTC 24 |
4696570168 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2697410161 |
|
|
Aug 25 07:00:26 PM UTC 24 |
Aug 25 08:50:16 PM UTC 24 |
15540644000 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.2595573140 |
|
|
Aug 25 08:29:55 PM UTC 24 |
Aug 25 08:50:35 PM UTC 24 |
5484809482 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2682094821 |
|
|
Aug 25 07:07:37 PM UTC 24 |
Aug 25 08:51:01 PM UTC 24 |
14975246860 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.803312666 |
|
|
Aug 25 08:25:19 PM UTC 24 |
Aug 25 08:51:14 PM UTC 24 |
4120443570 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2445880791 |
|
|
Aug 25 08:44:55 PM UTC 24 |
Aug 25 08:51:18 PM UTC 24 |
2841474318 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1707201429 |
|
|
Aug 25 08:37:14 PM UTC 24 |
Aug 25 08:51:25 PM UTC 24 |
5012470250 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4140818840 |
|
|
Aug 25 08:41:20 PM UTC 24 |
Aug 25 08:51:47 PM UTC 24 |
4220926952 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2863697475 |
|
|
Aug 25 08:40:31 PM UTC 24 |
Aug 25 08:52:14 PM UTC 24 |
4294496580 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3372000982 |
|
|
Aug 25 08:44:42 PM UTC 24 |
Aug 25 08:52:40 PM UTC 24 |
3119633196 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1603197164 |
|
|
Aug 25 08:41:04 PM UTC 24 |
Aug 25 08:52:45 PM UTC 24 |
4022073648 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3417851865 |
|
|
Aug 25 08:22:07 PM UTC 24 |
Aug 25 08:53:04 PM UTC 24 |
7764429692 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2328554639 |
|
|
Aug 25 08:41:18 PM UTC 24 |
Aug 25 08:53:41 PM UTC 24 |
6825963496 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2743236411 |
|
|
Aug 25 08:24:25 PM UTC 24 |
Aug 25 08:54:04 PM UTC 24 |
7167372866 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.4079292997 |
|
|
Aug 25 08:50:31 PM UTC 24 |
Aug 25 08:54:26 PM UTC 24 |
2358713014 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1373134574 |
|
|
Aug 25 08:41:05 PM UTC 24 |
Aug 25 08:54:42 PM UTC 24 |
4353997360 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.444045953 |
|
|
Aug 25 08:41:19 PM UTC 24 |
Aug 25 08:54:51 PM UTC 24 |
4711703610 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1556670014 |
|
|
Aug 25 08:44:57 PM UTC 24 |
Aug 25 08:55:01 PM UTC 24 |
4140013916 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4160082828 |
|
|
Aug 25 08:47:21 PM UTC 24 |
Aug 25 08:55:29 PM UTC 24 |
7574049170 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2310633117 |
|
|
Aug 25 08:47:22 PM UTC 24 |
Aug 25 08:58:33 PM UTC 24 |
4728087370 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2644658435 |
|
|
Aug 25 08:24:30 PM UTC 24 |
Aug 25 08:55:35 PM UTC 24 |
7109621164 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2604697805 |
|
|
Aug 25 08:42:24 PM UTC 24 |
Aug 25 08:56:06 PM UTC 24 |
4037184220 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1972700545 |
|
|
Aug 25 08:43:23 PM UTC 24 |
Aug 25 08:56:14 PM UTC 24 |
4046709160 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2191877810 |
|
|
Aug 25 08:41:53 PM UTC 24 |
Aug 25 08:56:40 PM UTC 24 |
4703990796 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1842159947 |
|
|
Aug 25 08:24:52 PM UTC 24 |
Aug 25 08:57:14 PM UTC 24 |
12843092410 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4253069283 |
|
|
Aug 25 08:50:56 PM UTC 24 |
Aug 25 08:57:32 PM UTC 24 |
3296837034 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3973135112 |
|
|
Aug 25 08:44:55 PM UTC 24 |
Aug 25 08:57:45 PM UTC 24 |
3833075098 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.784207042 |
|
|
Aug 25 08:44:44 PM UTC 24 |
Aug 25 08:57:56 PM UTC 24 |
5037156600 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1486829472 |
|
|
Aug 25 08:44:58 PM UTC 24 |
Aug 25 08:58:13 PM UTC 24 |
4249443288 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.801019700 |
|
|
Aug 25 08:41:52 PM UTC 24 |
Aug 25 08:58:26 PM UTC 24 |
4101357968 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2251656150 |
|
|
Aug 25 09:03:28 PM UTC 24 |
Aug 25 09:10:12 PM UTC 24 |
6570016861 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.217187687 |
|
|
Aug 25 08:48:48 PM UTC 24 |
Aug 25 08:58:45 PM UTC 24 |
5174201410 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1484381546 |
|
|
Aug 25 08:53:51 PM UTC 24 |
Aug 25 08:58:51 PM UTC 24 |
2629641493 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2463138216 |
|
|
Aug 25 08:48:27 PM UTC 24 |
Aug 25 08:58:52 PM UTC 24 |
4640919408 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1556538087 |
|
|
Aug 25 08:52:56 PM UTC 24 |
Aug 25 08:58:53 PM UTC 24 |
2911454503 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1732596405 |
|
|
Aug 25 08:52:12 PM UTC 24 |
Aug 25 08:58:57 PM UTC 24 |
3287270879 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2422915352 |
|
|
Aug 25 08:48:44 PM UTC 24 |
Aug 25 08:59:05 PM UTC 24 |
5434226810 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1756069114 |
|
|
Aug 25 08:48:25 PM UTC 24 |
Aug 25 08:59:18 PM UTC 24 |
4830068120 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.5525749 |
|
|
Aug 25 07:57:51 PM UTC 24 |
Aug 25 08:59:43 PM UTC 24 |
23144563094 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.100333636 |
|
|
Aug 25 08:53:44 PM UTC 24 |
Aug 25 08:59:45 PM UTC 24 |
2486705285 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.2425493820 |
|
|
Aug 25 08:37:05 PM UTC 24 |
Aug 25 08:59:55 PM UTC 24 |
9166197063 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.427203555 |
|
|
Aug 25 08:48:24 PM UTC 24 |
Aug 25 09:00:19 PM UTC 24 |
4272186998 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.4280597018 |
|
|
Aug 25 08:40:24 PM UTC 24 |
Aug 25 09:00:19 PM UTC 24 |
4295085364 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3615764634 |
|
|
Aug 25 08:31:22 PM UTC 24 |
Aug 25 09:00:30 PM UTC 24 |
6628762423 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.2865868777 |
|
|
Aug 25 08:52:54 PM UTC 24 |
Aug 25 09:01:01 PM UTC 24 |
3159262542 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2751310623 |
|
|
Aug 25 08:48:30 PM UTC 24 |
Aug 25 09:01:02 PM UTC 24 |
5228648632 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1247501112 |
|
|
Aug 25 08:48:20 PM UTC 24 |
Aug 25 09:01:24 PM UTC 24 |
6235019084 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1637729538 |
|
|
Aug 25 08:49:58 PM UTC 24 |
Aug 25 09:02:28 PM UTC 24 |
7128457406 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.2466010443 |
|
|
Aug 25 08:49:44 PM UTC 24 |
Aug 25 09:02:52 PM UTC 24 |
5539783965 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1990750946 |
|
|
Aug 25 08:54:46 PM UTC 24 |
Aug 25 09:02:56 PM UTC 24 |
3475778959 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2220142045 |
|
|
Aug 25 08:59:20 PM UTC 24 |
Aug 25 09:03:08 PM UTC 24 |
2787162552 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.106843537 |
|
|
Aug 25 07:05:47 PM UTC 24 |
Aug 25 09:03:51 PM UTC 24 |
18240837710 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.783324572 |
|
|
Aug 25 08:49:32 PM UTC 24 |
Aug 25 09:04:25 PM UTC 24 |
6242741128 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2192330057 |
|
|
Aug 25 08:40:22 PM UTC 24 |
Aug 25 09:04:26 PM UTC 24 |
9250188900 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.886473814 |
|
|
Aug 25 08:29:05 PM UTC 24 |
Aug 25 09:04:45 PM UTC 24 |
6421390760 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.3764972146 |
|
|
Aug 25 07:04:43 PM UTC 24 |
Aug 25 09:04:47 PM UTC 24 |
16661637446 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.421345633 |
|
|
Aug 25 08:29:51 PM UTC 24 |
Aug 25 09:06:11 PM UTC 24 |
8107071244 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.182087328 |
|
|
Aug 25 08:57:39 PM UTC 24 |
Aug 25 09:06:36 PM UTC 24 |
4767978054 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1710519173 |
|
|
Aug 25 08:52:51 PM UTC 24 |
Aug 25 09:06:56 PM UTC 24 |
5134519255 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.506456381 |
|
|
Aug 25 08:38:31 PM UTC 24 |
Aug 25 09:07:04 PM UTC 24 |
6142542360 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.1579497943 |
|
|
Aug 25 06:09:09 PM UTC 24 |
Aug 25 09:07:20 PM UTC 24 |
50553403473 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.2894683162 |
|
|
Aug 25 08:52:51 PM UTC 24 |
Aug 25 09:07:54 PM UTC 24 |
5807824142 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3297168239 |
|
|
Aug 25 08:55:06 PM UTC 24 |
Aug 25 09:08:33 PM UTC 24 |
4278641541 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.2813181073 |
|
|
Aug 25 08:44:26 PM UTC 24 |
Aug 25 09:08:37 PM UTC 24 |
9576572445 ps |
| T1041 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2666204078 |
|
|
Aug 25 09:06:19 PM UTC 24 |
Aug 25 09:09:13 PM UTC 24 |
2176349737 ps |
| T1042 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1072728187 |
|
|
Aug 25 09:05:23 PM UTC 24 |
Aug 25 09:09:48 PM UTC 24 |
2129965880 ps |
| T1043 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2471035209 |
|
|
Aug 25 08:55:51 PM UTC 24 |
Aug 25 09:10:03 PM UTC 24 |
4566179700 ps |
| T1044 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2516804789 |
|
|
Aug 25 07:07:05 PM UTC 24 |
Aug 25 09:10:09 PM UTC 24 |
17333301208 ps |
| T1045 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3736459351 |
|
|
Aug 25 09:06:25 PM UTC 24 |
Aug 25 09:10:23 PM UTC 24 |
2417521318 ps |
| T1046 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2223252925 |
|
|
Aug 25 08:35:44 PM UTC 24 |
Aug 25 09:10:24 PM UTC 24 |
9366625760 ps |
| T1047 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1072030582 |
|
|
Aug 25 09:04:04 PM UTC 24 |
Aug 25 09:10:26 PM UTC 24 |
3090556119 ps |
| T1048 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.351097415 |
|
|
Aug 25 09:06:14 PM UTC 24 |
Aug 25 09:10:38 PM UTC 24 |
2573990600 ps |
| T1049 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.478164562 |
|
|
Aug 25 09:04:21 PM UTC 24 |
Aug 25 09:10:56 PM UTC 24 |
2797288088 ps |
| T1050 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.223512751 |
|
|
Aug 25 09:07:08 PM UTC 24 |
Aug 25 09:10:56 PM UTC 24 |
2432217866 ps |
| T1051 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.3096635319 |
|
|
Aug 25 09:04:01 PM UTC 24 |
Aug 25 09:11:03 PM UTC 24 |
3550369560 ps |
| T1052 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3552694582 |
|
|
Aug 25 09:06:24 PM UTC 24 |
Aug 25 09:11:33 PM UTC 24 |
2684494760 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3859444682 |
|
|
Aug 25 09:04:44 PM UTC 24 |
Aug 25 09:11:34 PM UTC 24 |
3208069160 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.3129083209 |
|
|
Aug 25 09:06:23 PM UTC 24 |
Aug 25 09:11:45 PM UTC 24 |
2600063478 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3367500890 |
|
|
Aug 25 08:46:49 PM UTC 24 |
Aug 25 09:12:04 PM UTC 24 |
7743582568 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3950434033 |
|
|
Aug 25 09:06:26 PM UTC 24 |
Aug 25 09:12:46 PM UTC 24 |
2578209170 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.1088354165 |
|
|
Aug 25 09:08:00 PM UTC 24 |
Aug 25 09:12:58 PM UTC 24 |
2831969400 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.4096672528 |
|
|
Aug 25 09:08:01 PM UTC 24 |
Aug 25 09:13:09 PM UTC 24 |
2375758142 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1354333994 |
|
|
Aug 25 09:05:55 PM UTC 24 |
Aug 25 09:13:24 PM UTC 24 |
3190722112 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3722124896 |
|
|
Aug 25 09:06:51 PM UTC 24 |
Aug 25 09:14:05 PM UTC 24 |
3209750512 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.2869548539 |
|
|
Aug 25 06:01:30 PM UTC 24 |
Aug 25 09:14:16 PM UTC 24 |
31391668234 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.2063841466 |
|
|
Aug 25 09:03:26 PM UTC 24 |
Aug 25 09:14:23 PM UTC 24 |
4302404330 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2200486950 |
|
|
Aug 25 09:06:04 PM UTC 24 |
Aug 25 09:14:24 PM UTC 24 |
3541162108 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2139249578 |
|
|
Aug 25 09:05:52 PM UTC 24 |
Aug 25 09:14:45 PM UTC 24 |
3238441684 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.440437517 |
|
|
Aug 25 09:04:14 PM UTC 24 |
Aug 25 09:14:50 PM UTC 24 |
6457216380 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.866192057 |
|
|
Aug 25 09:08:08 PM UTC 24 |
Aug 25 09:15:18 PM UTC 24 |
3117499784 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.895855215 |
|
|
Aug 25 08:33:28 PM UTC 24 |
Aug 25 09:15:43 PM UTC 24 |
10713278608 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2806263884 |
|
|
Aug 25 09:06:16 PM UTC 24 |
Aug 25 09:15:46 PM UTC 24 |
2909140144 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1538983563 |
|
|
Aug 25 09:05:25 PM UTC 24 |
Aug 25 09:15:49 PM UTC 24 |
5567131920 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1820143695 |
|
|
Aug 25 08:35:05 PM UTC 24 |
Aug 25 09:17:39 PM UTC 24 |
10895168505 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2969178764 |
|
|
Aug 25 08:53:00 PM UTC 24 |
Aug 25 09:17:45 PM UTC 24 |
7367692387 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3606189542 |
|
|
Aug 25 09:09:54 PM UTC 24 |
Aug 25 09:17:54 PM UTC 24 |
3643551800 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2361155529 |
|
|
Aug 25 08:33:42 PM UTC 24 |
Aug 25 09:19:00 PM UTC 24 |
7879214200 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2978761620 |
|
|
Aug 25 09:12:50 PM UTC 24 |
Aug 25 09:19:29 PM UTC 24 |
2970679122 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.951369076 |
|
|
Aug 25 08:34:32 PM UTC 24 |
Aug 25 09:20:32 PM UTC 24 |
11011366452 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.549506101 |
|
|
Aug 25 09:11:31 PM UTC 24 |
Aug 25 09:21:59 PM UTC 24 |
7101720490 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.94825479 |
|
|
Aug 25 09:16:53 PM UTC 24 |
Aug 25 09:22:24 PM UTC 24 |
2564391916 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1125259109 |
|
|
Aug 25 09:13:52 PM UTC 24 |
Aug 25 09:22:43 PM UTC 24 |
3473896462 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3429208483 |
|
|
Aug 25 09:17:19 PM UTC 24 |
Aug 25 09:23:33 PM UTC 24 |
3299351341 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3781196179 |
|
|
Aug 25 09:17:08 PM UTC 24 |
Aug 25 09:23:37 PM UTC 24 |
2779731580 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.960849647 |
|
|
Aug 25 08:58:49 PM UTC 24 |
Aug 25 09:23:40 PM UTC 24 |
6146989618 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2910714652 |
|
|
Aug 25 09:09:32 PM UTC 24 |
Aug 25 09:25:03 PM UTC 24 |
4923650666 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3008709370 |
|
|
Aug 25 09:13:17 PM UTC 24 |
Aug 25 09:25:06 PM UTC 24 |
4377433707 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1535464744 |
|
|
Aug 25 09:08:36 PM UTC 24 |
Aug 25 09:25:20 PM UTC 24 |
4531335240 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.4023042180 |
|
|
Aug 25 09:20:10 PM UTC 24 |
Aug 25 09:26:31 PM UTC 24 |
3326798686 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2614965543 |
|
|
Aug 25 09:15:00 PM UTC 24 |
Aug 25 09:26:44 PM UTC 24 |
3751802256 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1898276160 |
|
|
Aug 25 09:14:17 PM UTC 24 |
Aug 25 09:26:47 PM UTC 24 |
3985659600 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.2363359065 |
|
|
Aug 25 09:13:18 PM UTC 24 |
Aug 25 09:27:00 PM UTC 24 |
4441674056 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.861780448 |
|
|
Aug 25 09:13:55 PM UTC 24 |
Aug 25 09:27:04 PM UTC 24 |
4533066984 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.416247101 |
|
|
Aug 25 08:45:05 PM UTC 24 |
Aug 25 09:27:24 PM UTC 24 |
14348402380 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1317879527 |
|
|
Aug 25 09:24:44 PM UTC 24 |
Aug 25 09:27:28 PM UTC 24 |
1907929599 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3839009033 |
|
|
Aug 25 09:18:37 PM UTC 24 |
Aug 25 09:28:28 PM UTC 24 |
3628115128 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1958627673 |
|
|
Aug 25 09:21:12 PM UTC 24 |
Aug 25 09:29:06 PM UTC 24 |
2828096216 ps |