| T2268 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3034576948 |
|
|
Aug 25 05:20:12 PM UTC 24 |
Aug 25 05:20:22 PM UTC 24 |
47453337 ps |
| T2269 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2250455215 |
|
|
Aug 25 04:56:14 PM UTC 24 |
Aug 25 05:20:37 PM UTC 24 |
57491366972 ps |
| T2270 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.4282573277 |
|
|
Aug 25 05:17:02 PM UTC 24 |
Aug 25 05:20:41 PM UTC 24 |
2116009797 ps |
| T2271 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.2263292934 |
|
|
Aug 25 05:19:08 PM UTC 24 |
Aug 25 05:20:47 PM UTC 24 |
1711385994 ps |
| T2272 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.4190471423 |
|
|
Aug 25 04:34:35 PM UTC 24 |
Aug 25 05:20:52 PM UTC 24 |
125246005764 ps |
| T2273 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.304083611 |
|
|
Aug 25 05:20:24 PM UTC 24 |
Aug 25 05:20:53 PM UTC 24 |
510728095 ps |
| T2274 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1363094321 |
|
|
Aug 25 04:30:54 PM UTC 24 |
Aug 25 05:20:59 PM UTC 24 |
117566233807 ps |
| T2275 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.881238942 |
|
|
Aug 25 05:19:01 PM UTC 24 |
Aug 25 05:21:00 PM UTC 24 |
4572190377 ps |
| T2276 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2675624031 |
|
|
Aug 25 05:19:48 PM UTC 24 |
Aug 25 05:21:02 PM UTC 24 |
1062498444 ps |
| T2277 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2957565741 |
|
|
Aug 25 05:19:39 PM UTC 24 |
Aug 25 05:21:06 PM UTC 24 |
1452380725 ps |
| T2278 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.2782059232 |
|
|
Aug 25 05:20:31 PM UTC 24 |
Aug 25 05:21:08 PM UTC 24 |
240201805 ps |
| T2279 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.1898363728 |
|
|
Aug 25 05:18:55 PM UTC 24 |
Aug 25 05:21:13 PM UTC 24 |
7546048187 ps |
| T2280 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.513618042 |
|
|
Aug 25 05:20:45 PM UTC 24 |
Aug 25 05:21:14 PM UTC 24 |
156997323 ps |
| T2281 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.2793215418 |
|
|
Aug 25 05:14:56 PM UTC 24 |
Aug 25 05:21:29 PM UTC 24 |
8580231439 ps |
| T2282 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.717239345 |
|
|
Aug 25 05:21:13 PM UTC 24 |
Aug 25 05:21:30 PM UTC 24 |
92277332 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.2525476662 |
|
|
Aug 25 05:05:17 PM UTC 24 |
Aug 25 05:21:31 PM UTC 24 |
18599998386 ps |
| T2283 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.3398513272 |
|
|
Aug 25 05:21:14 PM UTC 24 |
Aug 25 05:21:34 PM UTC 24 |
78022670 ps |
| T2284 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.4212412343 |
|
|
Aug 25 05:16:57 PM UTC 24 |
Aug 25 05:21:39 PM UTC 24 |
2362900919 ps |
| T2285 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.841648461 |
|
|
Aug 25 05:21:32 PM UTC 24 |
Aug 25 05:21:45 PM UTC 24 |
187119210 ps |
| T2286 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.17876151 |
|
|
Aug 25 05:21:38 PM UTC 24 |
Aug 25 05:21:48 PM UTC 24 |
39191256 ps |
| T2287 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1130455870 |
|
|
Aug 25 05:08:43 PM UTC 24 |
Aug 25 05:21:49 PM UTC 24 |
29838107682 ps |
| T2288 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1020412748 |
|
|
Aug 25 05:21:23 PM UTC 24 |
Aug 25 05:21:50 PM UTC 24 |
122254293 ps |
| T2289 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2456749457 |
|
|
Aug 25 05:21:16 PM UTC 24 |
Aug 25 05:21:59 PM UTC 24 |
293514084 ps |
| T2290 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2376559572 |
|
|
Aug 25 05:09:59 PM UTC 24 |
Aug 25 05:22:02 PM UTC 24 |
13695200996 ps |
| T2291 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3282590718 |
|
|
Aug 25 05:20:15 PM UTC 24 |
Aug 25 05:22:02 PM UTC 24 |
6615029999 ps |
| T2292 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1618012870 |
|
|
Aug 25 04:58:44 PM UTC 24 |
Aug 25 05:22:09 PM UTC 24 |
55215145520 ps |
| T2293 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.924191106 |
|
|
Aug 25 05:21:56 PM UTC 24 |
Aug 25 05:22:11 PM UTC 24 |
65695053 ps |
| T2294 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2601066369 |
|
|
Aug 25 05:21:05 PM UTC 24 |
Aug 25 05:22:16 PM UTC 24 |
1445966106 ps |
| T2295 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2740180233 |
|
|
Aug 25 03:36:22 PM UTC 24 |
Aug 25 05:22:20 PM UTC 24 |
28381608436 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.261702130 |
|
|
Aug 25 05:20:04 PM UTC 24 |
Aug 25 05:22:22 PM UTC 24 |
228900925 ps |
| T2296 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.3337573737 |
|
|
Aug 25 05:12:28 PM UTC 24 |
Aug 25 05:22:26 PM UTC 24 |
12345045113 ps |
| T2297 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2477835559 |
|
|
Aug 25 05:21:54 PM UTC 24 |
Aug 25 05:22:27 PM UTC 24 |
283396242 ps |
| T2298 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.709414378 |
|
|
Aug 25 05:09:30 PM UTC 24 |
Aug 25 05:22:29 PM UTC 24 |
47617875870 ps |
| T2299 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.777729710 |
|
|
Aug 25 05:20:23 PM UTC 24 |
Aug 25 05:22:30 PM UTC 24 |
5417101386 ps |
| T2300 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.4048594382 |
|
|
Aug 25 05:22:08 PM UTC 24 |
Aug 25 05:22:33 PM UTC 24 |
441189115 ps |
| T2301 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3094717296 |
|
|
Aug 25 05:22:27 PM UTC 24 |
Aug 25 05:22:49 PM UTC 24 |
164062336 ps |
| T2302 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1051393223 |
|
|
Aug 25 05:22:45 PM UTC 24 |
Aug 25 05:22:53 PM UTC 24 |
44907497 ps |
| T2303 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.1995441033 |
|
|
Aug 25 03:44:50 PM UTC 24 |
Aug 25 05:22:53 PM UTC 24 |
29248621137 ps |
| T2304 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.4172757752 |
|
|
Aug 25 05:22:12 PM UTC 24 |
Aug 25 05:22:54 PM UTC 24 |
798256807 ps |
| T2305 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.932942157 |
|
|
Aug 25 05:22:42 PM UTC 24 |
Aug 25 05:22:56 PM UTC 24 |
235660078 ps |
| T2306 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2070694260 |
|
|
Aug 25 05:22:32 PM UTC 24 |
Aug 25 05:23:01 PM UTC 24 |
58154824 ps |
| T2307 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.4268325085 |
|
|
Aug 25 04:40:17 PM UTC 24 |
Aug 25 05:23:01 PM UTC 24 |
104857318629 ps |
| T2308 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3607507533 |
|
|
Aug 25 04:29:39 PM UTC 24 |
Aug 25 05:23:03 PM UTC 24 |
145921484144 ps |
| T2309 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.580342143 |
|
|
Aug 25 05:19:59 PM UTC 24 |
Aug 25 05:23:06 PM UTC 24 |
3177108020 ps |
| T2310 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.718520172 |
|
|
Aug 25 05:22:23 PM UTC 24 |
Aug 25 05:23:07 PM UTC 24 |
229747097 ps |
| T2311 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.3303804631 |
|
|
Aug 25 05:22:13 PM UTC 24 |
Aug 25 05:23:13 PM UTC 24 |
626792141 ps |
| T2312 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.465895363 |
|
|
Aug 25 05:18:39 PM UTC 24 |
Aug 25 05:23:16 PM UTC 24 |
2893810804 ps |
| T2313 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3934294203 |
|
|
Aug 25 05:21:52 PM UTC 24 |
Aug 25 05:23:25 PM UTC 24 |
3979949184 ps |
| T2314 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.620463245 |
|
|
Aug 25 05:11:05 PM UTC 24 |
Aug 25 05:23:25 PM UTC 24 |
13128044805 ps |
| T2315 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3840127135 |
|
|
Aug 25 05:22:54 PM UTC 24 |
Aug 25 05:23:27 PM UTC 24 |
275381243 ps |
| T2316 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3440509104 |
|
|
Aug 25 05:23:18 PM UTC 24 |
Aug 25 05:23:31 PM UTC 24 |
87049679 ps |
| T2317 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1469438791 |
|
|
Aug 25 05:05:59 PM UTC 24 |
Aug 25 05:23:35 PM UTC 24 |
63398615095 ps |
| T2318 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.575935396 |
|
|
Aug 25 05:14:49 PM UTC 24 |
Aug 25 05:23:39 PM UTC 24 |
3461877591 ps |
| T2319 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3880006894 |
|
|
Aug 25 05:14:00 PM UTC 24 |
Aug 25 05:23:47 PM UTC 24 |
22623028169 ps |
| T2320 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.48679216 |
|
|
Aug 25 05:21:40 PM UTC 24 |
Aug 25 05:23:49 PM UTC 24 |
8519364876 ps |
| T2321 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2558674303 |
|
|
Aug 25 05:23:39 PM UTC 24 |
Aug 25 05:23:50 PM UTC 24 |
41427162 ps |
| T2322 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.819105761 |
|
|
Aug 25 05:23:27 PM UTC 24 |
Aug 25 05:23:53 PM UTC 24 |
393164583 ps |
| T2323 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2133432517 |
|
|
Aug 25 05:22:39 PM UTC 24 |
Aug 25 05:23:54 PM UTC 24 |
83667873 ps |
| T2324 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1736107200 |
|
|
Aug 25 05:23:49 PM UTC 24 |
Aug 25 05:23:59 PM UTC 24 |
54595600 ps |
| T2325 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.109271756 |
|
|
Aug 25 05:22:27 PM UTC 24 |
Aug 25 05:24:06 PM UTC 24 |
1986390125 ps |
| T2326 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.231297416 |
|
|
Aug 25 05:23:20 PM UTC 24 |
Aug 25 05:24:09 PM UTC 24 |
507389613 ps |
| T2327 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.1131724633 |
|
|
Aug 25 05:23:25 PM UTC 24 |
Aug 25 05:24:10 PM UTC 24 |
254341101 ps |
| T2328 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1712211062 |
|
|
Aug 25 05:23:27 PM UTC 24 |
Aug 25 05:24:14 PM UTC 24 |
801965860 ps |
| T2329 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.805322965 |
|
|
Aug 25 05:22:52 PM UTC 24 |
Aug 25 05:24:28 PM UTC 24 |
1846599230 ps |
| T2330 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3860595680 |
|
|
Aug 25 05:07:23 PM UTC 24 |
Aug 25 05:24:30 PM UTC 24 |
48939360271 ps |
| T2331 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.20898341 |
|
|
Aug 25 05:23:54 PM UTC 24 |
Aug 25 05:24:30 PM UTC 24 |
533918716 ps |
| T2332 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.1030060623 |
|
|
Aug 25 05:24:19 PM UTC 24 |
Aug 25 05:24:34 PM UTC 24 |
107093241 ps |
| T2333 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1304568107 |
|
|
Aug 25 05:11:10 PM UTC 24 |
Aug 25 05:24:41 PM UTC 24 |
9512238188 ps |
| T2334 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.407521031 |
|
|
Aug 25 05:06:08 PM UTC 24 |
Aug 25 05:24:44 PM UTC 24 |
49842158132 ps |
| T2335 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4204739531 |
|
|
Aug 25 05:12:17 PM UTC 24 |
Aug 25 05:24:46 PM UTC 24 |
28960730894 ps |
| T2336 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.4152063615 |
|
|
Aug 25 05:24:23 PM UTC 24 |
Aug 25 05:24:51 PM UTC 24 |
165415195 ps |
| T2337 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.880966909 |
|
|
Aug 25 05:24:17 PM UTC 24 |
Aug 25 05:24:53 PM UTC 24 |
334731471 ps |
| T2338 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1757772010 |
|
|
Aug 25 05:09:15 PM UTC 24 |
Aug 25 05:24:55 PM UTC 24 |
10471258018 ps |
| T2339 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3470477994 |
|
|
Aug 25 05:22:50 PM UTC 24 |
Aug 25 05:24:59 PM UTC 24 |
7837425073 ps |
| T2340 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.2117053567 |
|
|
Aug 25 05:23:59 PM UTC 24 |
Aug 25 05:25:00 PM UTC 24 |
393847879 ps |
| T2341 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3068747037 |
|
|
Aug 25 05:24:53 PM UTC 24 |
Aug 25 05:25:03 PM UTC 24 |
34904613 ps |
| T2342 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.1707489304 |
|
|
Aug 25 05:24:54 PM UTC 24 |
Aug 25 05:25:06 PM UTC 24 |
161500516 ps |
| T2343 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.278436117 |
|
|
Aug 25 05:24:38 PM UTC 24 |
Aug 25 05:25:09 PM UTC 24 |
218849177 ps |
| T2344 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2272054719 |
|
|
Aug 25 05:22:51 PM UTC 24 |
Aug 25 05:25:11 PM UTC 24 |
5478772666 ps |
| T2345 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3682484766 |
|
|
Aug 25 05:18:42 PM UTC 24 |
Aug 25 05:25:16 PM UTC 24 |
2080889484 ps |
| T2346 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.712398130 |
|
|
Aug 25 05:18:03 PM UTC 24 |
Aug 25 05:25:22 PM UTC 24 |
17059659194 ps |
| T2347 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3859797280 |
|
|
Aug 25 05:23:16 PM UTC 24 |
Aug 25 05:25:25 PM UTC 24 |
959160465 ps |
| T2348 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3696246045 |
|
|
Aug 25 05:15:48 PM UTC 24 |
Aug 25 05:25:38 PM UTC 24 |
24728683581 ps |
| T2349 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.138822191 |
|
|
Aug 25 05:25:23 PM UTC 24 |
Aug 25 05:25:41 PM UTC 24 |
115171115 ps |
| T2350 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.2043759220 |
|
|
Aug 25 05:24:10 PM UTC 24 |
Aug 25 05:25:41 PM UTC 24 |
4231534475 ps |
| T2351 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.925213821 |
|
|
Aug 25 05:10:46 PM UTC 24 |
Aug 25 05:25:43 PM UTC 24 |
57864974583 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.393354786 |
|
|
Aug 25 05:16:58 PM UTC 24 |
Aug 25 05:25:46 PM UTC 24 |
5400321638 ps |
| T2352 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3491294757 |
|
|
Aug 25 05:25:11 PM UTC 24 |
Aug 25 05:25:47 PM UTC 24 |
227564119 ps |
| T2353 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3121093224 |
|
|
Aug 25 05:24:29 PM UTC 24 |
Aug 25 05:25:53 PM UTC 24 |
1305748094 ps |
| T2354 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.962237392 |
|
|
Aug 25 05:01:24 PM UTC 24 |
Aug 25 05:25:57 PM UTC 24 |
71499471604 ps |
| T2355 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.930776380 |
|
|
Aug 25 05:25:08 PM UTC 24 |
Aug 25 05:25:57 PM UTC 24 |
469541933 ps |
| T2356 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2564615393 |
|
|
Aug 25 05:23:49 PM UTC 24 |
Aug 25 05:26:09 PM UTC 24 |
9334544446 ps |
| T2357 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.545279579 |
|
|
Aug 25 05:22:34 PM UTC 24 |
Aug 25 05:26:09 PM UTC 24 |
1629869660 ps |
| T2358 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1195845893 |
|
|
Aug 25 05:23:51 PM UTC 24 |
Aug 25 05:26:09 PM UTC 24 |
5073364164 ps |
| T2359 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.2151337972 |
|
|
Aug 25 05:25:20 PM UTC 24 |
Aug 25 05:26:13 PM UTC 24 |
899379289 ps |
| T2360 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2927286328 |
|
|
Aug 25 05:26:02 PM UTC 24 |
Aug 25 05:26:14 PM UTC 24 |
47992826 ps |
| T2361 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.685741404 |
|
|
Aug 25 05:26:01 PM UTC 24 |
Aug 25 05:26:18 PM UTC 24 |
246211537 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3927728838 |
|
|
Aug 25 05:21:31 PM UTC 24 |
Aug 25 05:26:21 PM UTC 24 |
1131017836 ps |
| T2362 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.194072049 |
|
|
Aug 25 05:25:31 PM UTC 24 |
Aug 25 05:26:23 PM UTC 24 |
1062468806 ps |
| T2363 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4232570415 |
|
|
Aug 25 05:24:34 PM UTC 24 |
Aug 25 05:26:33 PM UTC 24 |
2196944480 ps |
| T2364 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.619879886 |
|
|
Aug 25 05:24:57 PM UTC 24 |
Aug 25 05:26:34 PM UTC 24 |
5337637608 ps |
| T2365 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.2252154157 |
|
|
Aug 25 05:25:24 PM UTC 24 |
Aug 25 05:26:36 PM UTC 24 |
1353994647 ps |
| T2366 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.1920579803 |
|
|
Aug 25 05:26:10 PM UTC 24 |
Aug 25 05:26:42 PM UTC 24 |
246627591 ps |
| T2367 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3650702408 |
|
|
Aug 25 05:10:03 PM UTC 24 |
Aug 25 05:26:44 PM UTC 24 |
17183311977 ps |
| T2368 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1814991338 |
|
|
Aug 25 05:12:03 PM UTC 24 |
Aug 25 05:26:44 PM UTC 24 |
34759367585 ps |
| T2369 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.1641193618 |
|
|
Aug 25 05:26:09 PM UTC 24 |
Aug 25 05:26:45 PM UTC 24 |
218965510 ps |
| T2370 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3093371151 |
|
|
Aug 25 05:25:30 PM UTC 24 |
Aug 25 05:26:48 PM UTC 24 |
1379759830 ps |
| T2371 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.43123404 |
|
|
Aug 25 05:26:17 PM UTC 24 |
Aug 25 05:27:01 PM UTC 24 |
713109307 ps |
| T2372 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.38255531 |
|
|
Aug 25 05:21:58 PM UTC 24 |
Aug 25 05:27:03 PM UTC 24 |
18131231316 ps |
| T2373 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1835012360 |
|
|
Aug 25 05:26:33 PM UTC 24 |
Aug 25 05:27:04 PM UTC 24 |
600805158 ps |
| T2374 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.947362754 |
|
|
Aug 25 05:25:05 PM UTC 24 |
Aug 25 05:27:06 PM UTC 24 |
4222984109 ps |
| T2375 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3609577353 |
|
|
Aug 25 05:27:00 PM UTC 24 |
Aug 25 05:27:11 PM UTC 24 |
45504593 ps |
| T2376 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.323236945 |
|
|
Aug 25 05:29:39 PM UTC 24 |
Aug 25 05:30:38 PM UTC 24 |
853196152 ps |
| T2377 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.506499219 |
|
|
Aug 25 05:26:59 PM UTC 24 |
Aug 25 05:27:15 PM UTC 24 |
181498216 ps |
| T2378 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1794841851 |
|
|
Aug 25 05:26:04 PM UTC 24 |
Aug 25 05:27:15 PM UTC 24 |
4475191045 ps |
| T2379 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.2744821092 |
|
|
Aug 25 05:04:18 PM UTC 24 |
Aug 25 05:27:17 PM UTC 24 |
63165322287 ps |
| T2380 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1861421128 |
|
|
Aug 25 05:24:33 PM UTC 24 |
Aug 25 05:27:21 PM UTC 24 |
3647092583 ps |
| T2381 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3204280112 |
|
|
Aug 25 05:14:59 PM UTC 24 |
Aug 25 05:27:22 PM UTC 24 |
8534332887 ps |
| T2382 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1161740543 |
|
|
Aug 25 05:25:38 PM UTC 24 |
Aug 25 05:27:26 PM UTC 24 |
316129164 ps |
| T2383 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1195399386 |
|
|
Aug 25 05:26:19 PM UTC 24 |
Aug 25 05:27:28 PM UTC 24 |
2984204215 ps |
| T2384 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2858615847 |
|
|
Aug 25 05:26:33 PM UTC 24 |
Aug 25 05:27:32 PM UTC 24 |
476737174 ps |
| T2385 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1857013942 |
|
|
Aug 25 05:26:37 PM UTC 24 |
Aug 25 05:27:33 PM UTC 24 |
844588739 ps |
| T2386 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2389507621 |
|
|
Aug 25 05:23:13 PM UTC 24 |
Aug 25 05:30:31 PM UTC 24 |
17768206224 ps |
| T2387 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.2271678143 |
|
|
Aug 25 05:26:34 PM UTC 24 |
Aug 25 05:27:34 PM UTC 24 |
317031741 ps |
| T2388 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2693177968 |
|
|
Aug 25 05:27:09 PM UTC 24 |
Aug 25 05:27:44 PM UTC 24 |
285047705 ps |
| T2389 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3826675866 |
|
|
Aug 25 05:26:56 PM UTC 24 |
Aug 25 05:27:45 PM UTC 24 |
183809863 ps |
| T2390 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.2454360660 |
|
|
Aug 25 05:27:39 PM UTC 24 |
Aug 25 05:27:49 PM UTC 24 |
62586837 ps |
| T2391 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2377800568 |
|
|
Aug 25 05:08:32 PM UTC 24 |
Aug 25 05:27:54 PM UTC 24 |
78000550404 ps |
| T2392 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1733096615 |
|
|
Aug 25 05:27:51 PM UTC 24 |
Aug 25 05:28:05 PM UTC 24 |
222621058 ps |
| T2393 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.13860373 |
|
|
Aug 25 05:26:07 PM UTC 24 |
Aug 25 05:28:07 PM UTC 24 |
5024862394 ps |
| T2394 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4016699489 |
|
|
Aug 25 05:27:56 PM UTC 24 |
Aug 25 05:28:08 PM UTC 24 |
53732387 ps |
| T2395 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1751885404 |
|
|
Aug 25 05:27:40 PM UTC 24 |
Aug 25 05:28:12 PM UTC 24 |
168101007 ps |
| T2396 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2582688826 |
|
|
Aug 25 05:24:13 PM UTC 24 |
Aug 25 05:28:13 PM UTC 24 |
3854479289 ps |
| T2397 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3933947932 |
|
|
Aug 25 05:23:32 PM UTC 24 |
Aug 25 05:28:14 PM UTC 24 |
6624000693 ps |
| T2398 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2020875087 |
|
|
Aug 25 05:08:59 PM UTC 24 |
Aug 25 05:28:16 PM UTC 24 |
18483366266 ps |
| T2399 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.4250405622 |
|
|
Aug 25 05:24:52 PM UTC 24 |
Aug 25 05:28:27 PM UTC 24 |
2407343845 ps |
| T2400 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.3538285697 |
|
|
Aug 25 05:27:26 PM UTC 24 |
Aug 25 05:28:28 PM UTC 24 |
487567365 ps |
| T2401 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.636334851 |
|
|
Aug 25 05:01:21 PM UTC 24 |
Aug 25 05:28:32 PM UTC 24 |
102545964441 ps |
| T2402 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.2063132966 |
|
|
Aug 25 05:27:46 PM UTC 24 |
Aug 25 05:28:42 PM UTC 24 |
561912744 ps |
| T2403 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3691394355 |
|
|
Aug 25 05:28:09 PM UTC 24 |
Aug 25 05:28:44 PM UTC 24 |
314923616 ps |
| T2404 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3573565249 |
|
|
Aug 25 05:28:29 PM UTC 24 |
Aug 25 05:28:49 PM UTC 24 |
34437239 ps |
| T2405 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3131867227 |
|
|
Aug 25 05:23:38 PM UTC 24 |
Aug 25 05:28:51 PM UTC 24 |
712599472 ps |
| T2406 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2197720811 |
|
|
Aug 25 05:28:36 PM UTC 24 |
Aug 25 05:28:53 PM UTC 24 |
72763729 ps |
| T2407 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.809333931 |
|
|
Aug 25 04:44:36 PM UTC 24 |
Aug 25 05:29:00 PM UTC 24 |
102891321265 ps |
| T2408 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.61896819 |
|
|
Aug 25 05:27:08 PM UTC 24 |
Aug 25 05:29:00 PM UTC 24 |
2101726779 ps |
| T2409 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3496206532 |
|
|
Aug 25 05:27:09 PM UTC 24 |
Aug 25 05:29:06 PM UTC 24 |
4464495820 ps |
| T2410 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.198784956 |
|
|
Aug 25 05:27:57 PM UTC 24 |
Aug 25 05:29:09 PM UTC 24 |
4823638330 ps |
| T2411 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2325779777 |
|
|
Aug 25 05:27:34 PM UTC 24 |
Aug 25 05:29:10 PM UTC 24 |
1898589391 ps |
| T2412 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.3734998036 |
|
|
Aug 25 03:40:51 PM UTC 24 |
Aug 25 05:29:11 PM UTC 24 |
30089393475 ps |
| T2413 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2925742170 |
|
|
Aug 25 05:27:31 PM UTC 24 |
Aug 25 05:29:14 PM UTC 24 |
2158099595 ps |
| T2414 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2677206596 |
|
|
Aug 25 05:28:37 PM UTC 24 |
Aug 25 05:29:16 PM UTC 24 |
260906977 ps |
| T2415 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2680441787 |
|
|
Aug 25 05:29:06 PM UTC 24 |
Aug 25 05:29:17 PM UTC 24 |
43211071 ps |
| T2416 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.980773143 |
|
|
Aug 25 05:22:03 PM UTC 24 |
Aug 25 05:29:19 PM UTC 24 |
16647020156 ps |
| T2417 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1632613344 |
|
|
Aug 25 05:29:07 PM UTC 24 |
Aug 25 05:29:21 PM UTC 24 |
196663523 ps |
| T2418 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.1240635011 |
|
|
Aug 25 05:27:06 PM UTC 24 |
Aug 25 05:29:23 PM UTC 24 |
8088978549 ps |
| T2419 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.387482174 |
|
|
Aug 25 05:28:05 PM UTC 24 |
Aug 25 05:29:23 PM UTC 24 |
1499429318 ps |
| T2420 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.1387429506 |
|
|
Aug 25 05:29:23 PM UTC 24 |
Aug 25 05:29:47 PM UTC 24 |
191832082 ps |
| T2421 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3073206338 |
|
|
Aug 25 05:28:32 PM UTC 24 |
Aug 25 05:29:52 PM UTC 24 |
2219891431 ps |
| T2422 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.2517497411 |
|
|
Aug 25 05:29:38 PM UTC 24 |
Aug 25 05:29:54 PM UTC 24 |
91302419 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2529265923 |
|
|
Aug 25 05:17:17 PM UTC 24 |
Aug 25 05:30:02 PM UTC 24 |
8946760355 ps |
| T2423 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.957343498 |
|
|
Aug 25 05:18:35 PM UTC 24 |
Aug 25 05:30:12 PM UTC 24 |
7073607231 ps |
| T2424 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1496103795 |
|
|
Aug 25 05:27:25 PM UTC 24 |
Aug 25 05:30:23 PM UTC 24 |
6584298391 ps |
| T2425 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1176468954 |
|
|
Aug 25 05:30:17 PM UTC 24 |
Aug 25 05:30:26 PM UTC 24 |
51171655 ps |
| T2426 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2717846599 |
|
|
Aug 25 05:30:09 PM UTC 24 |
Aug 25 05:30:28 PM UTC 24 |
257647133 ps |
| T2427 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.4072249969 |
|
|
Aug 25 05:28:34 PM UTC 24 |
Aug 25 05:30:28 PM UTC 24 |
2604968338 ps |
| T2428 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.2027053600 |
|
|
Aug 25 05:29:16 PM UTC 24 |
Aug 25 05:30:28 PM UTC 24 |
1240845104 ps |
| T2429 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2693283076 |
|
|
Aug 25 05:29:40 PM UTC 24 |
Aug 25 05:30:29 PM UTC 24 |
867632668 ps |
| T2430 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2864885728 |
|
|
Aug 25 05:27:57 PM UTC 24 |
Aug 25 05:30:29 PM UTC 24 |
7009649052 ps |
| T2431 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3044999810 |
|
|
Aug 25 04:46:47 PM UTC 24 |
Aug 25 05:30:31 PM UTC 24 |
107429623409 ps |
| T2432 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1872210009 |
|
|
Aug 25 05:28:50 PM UTC 24 |
Aug 25 05:30:43 PM UTC 24 |
1290334044 ps |
| T2433 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2807809979 |
|
|
Aug 25 05:29:33 PM UTC 24 |
Aug 25 05:30:46 PM UTC 24 |
1408744094 ps |
| T2434 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.3970083661 |
|
|
Aug 25 05:09:32 PM UTC 24 |
Aug 25 05:30:46 PM UTC 24 |
56925384933 ps |
| T2435 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2065254765 |
|
|
Aug 25 05:28:41 PM UTC 24 |
Aug 25 05:30:46 PM UTC 24 |
890478463 ps |
| T2436 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.378071499 |
|
|
Aug 25 04:54:00 PM UTC 24 |
Aug 25 05:30:51 PM UTC 24 |
89211511819 ps |
| T2437 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1246679877 |
|
|
Aug 25 05:10:49 PM UTC 24 |
Aug 25 05:30:56 PM UTC 24 |
46644035007 ps |
| T2438 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3627982349 |
|
|
Aug 25 05:27:44 PM UTC 24 |
Aug 25 05:30:57 PM UTC 24 |
388072991 ps |
| T2439 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2502757029 |
|
|
Aug 25 05:29:16 PM UTC 24 |
Aug 25 05:31:03 PM UTC 24 |
4924929115 ps |
| T2440 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.4136706353 |
|
|
Aug 25 05:29:14 PM UTC 24 |
Aug 25 05:31:05 PM UTC 24 |
5939950096 ps |
| T2441 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.654314762 |
|
|
Aug 25 05:30:52 PM UTC 24 |
Aug 25 05:31:10 PM UTC 24 |
126815358 ps |
| T2442 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3765062755 |
|
|
Aug 25 05:30:55 PM UTC 24 |
Aug 25 05:31:10 PM UTC 24 |
203740955 ps |
| T2443 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.244014529 |
|
|
Aug 25 05:29:32 PM UTC 24 |
Aug 25 05:31:11 PM UTC 24 |
1531970416 ps |
| T2444 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.2233753315 |
|
|
Aug 25 05:30:53 PM UTC 24 |
Aug 25 05:31:15 PM UTC 24 |
338999683 ps |
| T2445 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3134663250 |
|
|
Aug 25 05:31:16 PM UTC 24 |
Aug 25 05:31:27 PM UTC 24 |
48047595 ps |
| T2446 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.3343555537 |
|
|
Aug 25 05:30:54 PM UTC 24 |
Aug 25 05:31:28 PM UTC 24 |
270234731 ps |
| T2447 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3025167165 |
|
|
Aug 25 05:31:11 PM UTC 24 |
Aug 25 05:31:29 PM UTC 24 |
269006240 ps |
| T2448 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3058208677 |
|
|
Aug 25 05:30:36 PM UTC 24 |
Aug 25 05:31:34 PM UTC 24 |
520189569 ps |
| T2449 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.4219084994 |
|
|
Aug 25 05:14:01 PM UTC 24 |
Aug 25 05:31:41 PM UTC 24 |
40221292374 ps |
| T2450 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.201861587 |
|
|
Aug 25 05:31:01 PM UTC 24 |
Aug 25 05:31:52 PM UTC 24 |
278546524 ps |
| T2451 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.739510301 |
|
|
Aug 25 04:48:23 PM UTC 24 |
Aug 25 05:31:54 PM UTC 24 |
109833830684 ps |
| T2452 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.419845481 |
|
|
Aug 25 05:26:41 PM UTC 24 |
Aug 25 05:31:57 PM UTC 24 |
7101807261 ps |
| T2453 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.2129734419 |
|
|
Aug 25 05:30:47 PM UTC 24 |
Aug 25 05:32:01 PM UTC 24 |
511203378 ps |
| T2454 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.3257632893 |
|
|
Aug 25 05:30:18 PM UTC 24 |
Aug 25 05:32:02 PM UTC 24 |
5900603830 ps |
| T2455 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.361129907 |
|
|
Aug 25 05:31:50 PM UTC 24 |
Aug 25 05:32:05 PM UTC 24 |
114527651 ps |
| T2456 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.204438313 |
|
|
Aug 25 05:30:54 PM UTC 24 |
Aug 25 05:32:11 PM UTC 24 |
1137838431 ps |
| T2457 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.3264750779 |
|
|
Aug 25 05:31:51 PM UTC 24 |
Aug 25 05:32:27 PM UTC 24 |
177933917 ps |
| T2458 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2930105805 |
|
|
Aug 25 05:31:28 PM UTC 24 |
Aug 25 05:32:30 PM UTC 24 |
444168826 ps |
| T2459 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2851580278 |
|
|
Aug 25 05:32:24 PM UTC 24 |
Aug 25 05:32:36 PM UTC 24 |
217524706 ps |
| T2460 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3841295569 |
|
|
Aug 25 05:32:26 PM UTC 24 |
Aug 25 05:32:36 PM UTC 24 |
35904169 ps |
| T2461 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2785761751 |
|
|
Aug 25 05:25:44 PM UTC 24 |
Aug 25 05:32:37 PM UTC 24 |
3312819578 ps |
| T2462 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.632025610 |
|
|
Aug 25 05:29:46 PM UTC 24 |
Aug 25 05:32:40 PM UTC 24 |
1673480290 ps |
| T2463 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.4030287831 |
|
|
Aug 25 05:31:35 PM UTC 24 |
Aug 25 05:32:41 PM UTC 24 |
362171336 ps |
| T2464 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.143149049 |
|
|
Aug 25 05:29:43 PM UTC 24 |
Aug 25 05:32:41 PM UTC 24 |
3302095175 ps |
| T2465 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.125927429 |
|
|
Aug 25 05:31:54 PM UTC 24 |
Aug 25 05:32:46 PM UTC 24 |
1074873337 ps |
| T2466 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1003913577 |
|
|
Aug 25 05:25:47 PM UTC 24 |
Aug 25 05:32:46 PM UTC 24 |
5457534452 ps |
| T2467 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1094743296 |
|
|
Aug 25 05:07:13 PM UTC 24 |
Aug 25 05:32:48 PM UTC 24 |
64560998358 ps |
| T2468 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1468723799 |
|
|
Aug 25 05:30:25 PM UTC 24 |
Aug 25 05:32:55 PM UTC 24 |
6560304269 ps |
| T2469 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.61158630 |
|
|
Aug 25 05:11:51 PM UTC 24 |
Aug 25 05:32:56 PM UTC 24 |
87821397622 ps |
| T2470 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3060265187 |
|
|
Aug 25 05:19:52 PM UTC 24 |
Aug 25 05:33:01 PM UTC 24 |
14477728939 ps |
| T2471 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3114660212 |
|
|
Aug 25 05:31:51 PM UTC 24 |
Aug 25 05:33:04 PM UTC 24 |
1926973897 ps |
| T2472 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2172878059 |
|
|
Aug 25 05:31:06 PM UTC 24 |
Aug 25 05:33:13 PM UTC 24 |
264478407 ps |
| T2473 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.4021492373 |
|
|
Aug 25 05:32:17 PM UTC 24 |
Aug 25 05:33:13 PM UTC 24 |
90813198 ps |
| T2474 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1670289393 |
|
|
Aug 25 05:27:41 PM UTC 24 |
Aug 25 05:33:17 PM UTC 24 |
3029217262 ps |
| T2475 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.3997951391 |
|
|
Aug 25 05:04:17 PM UTC 24 |
Aug 25 05:33:22 PM UTC 24 |
98160294327 ps |
| T2476 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.3370160892 |
|
|
Aug 25 05:31:19 PM UTC 24 |
Aug 25 05:33:25 PM UTC 24 |
7305180322 ps |
| T2477 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.2794592689 |
|
|
Aug 25 05:33:08 PM UTC 24 |
Aug 25 05:33:26 PM UTC 24 |
177597178 ps |
| T2478 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.3617885629 |
|
|
Aug 25 05:31:26 PM UTC 24 |
Aug 25 05:33:29 PM UTC 24 |
2287005264 ps |
| T2479 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.497477014 |
|
|
Aug 25 05:18:00 PM UTC 24 |
Aug 25 05:33:32 PM UTC 24 |
58677801103 ps |
| T2480 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.331186229 |
|
|
Aug 25 05:33:11 PM UTC 24 |
Aug 25 05:33:35 PM UTC 24 |
160999820 ps |
| T2481 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1043165257 |
|
|
Aug 25 05:31:09 PM UTC 24 |
Aug 25 05:33:36 PM UTC 24 |
287754280 ps |
| T2482 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.3530376617 |
|
|
Aug 25 05:25:34 PM UTC 24 |
Aug 25 05:33:36 PM UTC 24 |
8171147162 ps |
| T2483 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.376513763 |
|
|
Aug 25 05:33:03 PM UTC 24 |
Aug 25 05:33:38 PM UTC 24 |
601324467 ps |
| T2484 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4003676813 |
|
|
Aug 25 05:31:21 PM UTC 24 |
Aug 25 05:33:39 PM UTC 24 |
6315512553 ps |
| T2485 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.2900402727 |
|
|
Aug 25 05:32:48 PM UTC 24 |
Aug 25 05:33:40 PM UTC 24 |
896157855 ps |
| T2486 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.159618812 |
|
|
Aug 25 05:21:26 PM UTC 24 |
Aug 25 05:33:40 PM UTC 24 |
14006226539 ps |
| T2487 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.285494298 |
|
|
Aug 25 05:33:27 PM UTC 24 |
Aug 25 05:33:42 PM UTC 24 |
198084199 ps |
| T2488 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.1633538807 |
|
|
Aug 25 05:19:28 PM UTC 24 |
Aug 25 05:33:42 PM UTC 24 |
39826447840 ps |
| T2489 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2428491612 |
|
|
Aug 25 05:33:35 PM UTC 24 |
Aug 25 05:33:47 PM UTC 24 |
55304672 ps |
| T2490 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2470598404 |
|
|
Aug 25 05:32:55 PM UTC 24 |
Aug 25 05:33:48 PM UTC 24 |
369448279 ps |
| T2491 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.138732553 |
|
|
Aug 25 05:32:20 PM UTC 24 |
Aug 25 05:33:48 PM UTC 24 |
595682007 ps |
| T2492 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1984149970 |
|
|
Aug 25 05:33:06 PM UTC 24 |
Aug 25 05:33:56 PM UTC 24 |
507339851 ps |
| T2493 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1841386081 |
|
|
Aug 25 05:33:46 PM UTC 24 |
Aug 25 05:33:57 PM UTC 24 |
36824893 ps |
| T2494 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3632970085 |
|
|
Aug 25 05:07:10 PM UTC 24 |
Aug 25 05:34:08 PM UTC 24 |
96401729597 ps |
| T2495 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.44111117 |
|
|
Aug 25 05:26:44 PM UTC 24 |
Aug 25 05:34:14 PM UTC 24 |
4644210685 ps |
| T2496 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2465439933 |
|
|
Aug 25 05:28:54 PM UTC 24 |
Aug 25 05:34:17 PM UTC 24 |
5604662755 ps |
| T2497 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1995469746 |
|
|
Aug 25 05:34:11 PM UTC 24 |
Aug 25 05:34:22 PM UTC 24 |
52235763 ps |
| T2498 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3912111649 |
|
|
Aug 25 05:33:49 PM UTC 24 |
Aug 25 05:34:23 PM UTC 24 |
204711899 ps |
| T2499 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2372662242 |
|
|
Aug 25 05:32:30 PM UTC 24 |
Aug 25 05:34:25 PM UTC 24 |
6456604974 ps |
| T2500 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3477099347 |
|
|
Aug 25 05:34:12 PM UTC 24 |
Aug 25 05:34:28 PM UTC 24 |
205084574 ps |
| T2501 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2983476200 |
|
|
Aug 25 05:34:02 PM UTC 24 |
Aug 25 05:34:29 PM UTC 24 |
297524473 ps |
| T2502 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.3860487205 |
|
|
Aug 25 05:34:00 PM UTC 24 |
Aug 25 05:34:30 PM UTC 24 |
193958505 ps |
| T2503 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.4188195489 |
|
|
Aug 25 05:33:59 PM UTC 24 |
Aug 25 05:34:31 PM UTC 24 |
293659270 ps |
| T2504 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2028313387 |
|
|
Aug 25 05:34:03 PM UTC 24 |
Aug 25 05:34:40 PM UTC 24 |
669534866 ps |
| T2505 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.315410987 |
|
|
Aug 25 05:32:35 PM UTC 24 |
Aug 25 05:34:51 PM UTC 24 |
5227090745 ps |
| T2506 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3160239500 |
|
|
Aug 25 05:22:56 PM UTC 24 |
Aug 25 05:34:54 PM UTC 24 |
45877437205 ps |
| T2507 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.3394247166 |
|
|
Aug 25 05:34:22 PM UTC 24 |
Aug 25 05:34:56 PM UTC 24 |
224801720 ps |
| T2508 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2874525000 |
|
|
Aug 25 05:33:36 PM UTC 24 |
Aug 25 05:35:08 PM UTC 24 |
6627220436 ps |
| T2509 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.138785367 |
|
|
Aug 25 05:28:13 PM UTC 24 |
Aug 25 05:35:09 PM UTC 24 |
24248848810 ps |
| T2510 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.1427713434 |
|
|
Aug 25 05:34:50 PM UTC 24 |
Aug 25 05:35:15 PM UTC 24 |
416455937 ps |
| T2511 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3518064692 |
|
|
Aug 25 05:33:42 PM UTC 24 |
Aug 25 05:35:23 PM UTC 24 |
4371111794 ps |
| T2512 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.1620858394 |
|
|
Aug 25 05:34:32 PM UTC 24 |
Aug 25 05:35:25 PM UTC 24 |
375106489 ps |