| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.20 | 95.56 | 94.20 | 95.32 | 95.08 | 97.53 | 99.53 |
| T2762 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.1811420612 | Aug 25 05:44:01 PM UTC 24 | Aug 25 05:52:20 PM UTC 24 | 33178640993 ps | ||
| T2763 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.2240240285 | Aug 25 05:46:41 PM UTC 24 | Aug 25 05:52:22 PM UTC 24 | 7997753976 ps | ||
| T2764 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.905478612 | Aug 25 05:52:07 PM UTC 24 | Aug 25 05:52:35 PM UTC 24 | 236358972 ps | ||
| T2765 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.47099753 | Aug 25 05:50:32 PM UTC 24 | Aug 25 05:52:40 PM UTC 24 | 5494557906 ps | ||
| T2766 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2928745594 | Aug 25 05:52:34 PM UTC 24 | Aug 25 05:52:46 PM UTC 24 | 48915850 ps | ||
| T2767 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.882465553 | Aug 25 05:52:34 PM UTC 24 | Aug 25 05:52:50 PM UTC 24 | 225484215 ps | ||
| T2768 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.3451747899 | Aug 25 05:50:26 PM UTC 24 | Aug 25 05:52:51 PM UTC 24 | 8310558640 ps | ||
| T2769 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.1094647814 | Aug 25 05:52:07 PM UTC 24 | Aug 25 05:52:52 PM UTC 24 | 217495173 ps | ||
| T2770 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.3317887409 | Aug 25 05:51:41 PM UTC 24 | Aug 25 05:52:58 PM UTC 24 | 1448147594 ps | ||
| T2771 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2187836745 | Aug 25 05:50:45 PM UTC 24 | Aug 25 05:53:01 PM UTC 24 | 2312878764 ps | ||
| T2772 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.1938122737 | Aug 25 05:52:10 PM UTC 24 | Aug 25 05:53:02 PM UTC 24 | 1086788129 ps | ||
| T2773 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3031594807 | Aug 25 05:51:43 PM UTC 24 | Aug 25 05:53:03 PM UTC 24 | 547477542 ps | ||
| T2774 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2350800449 | Aug 25 05:52:19 PM UTC 24 | Aug 25 05:53:06 PM UTC 24 | 848878392 ps | ||
| T2775 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3089782258 | Aug 25 05:43:27 PM UTC 24 | Aug 25 05:53:09 PM UTC 24 | 7446961926 ps | ||
| T2776 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.3673668622 | Aug 25 05:48:55 PM UTC 24 | Aug 25 05:53:14 PM UTC 24 | 2949286962 ps | ||
| T2777 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1511218555 | Aug 25 05:49:52 PM UTC 24 | Aug 25 05:53:15 PM UTC 24 | 314774726 ps | ||
| T2778 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.881660917 | Aug 25 05:28:29 PM UTC 24 | Aug 25 05:53:16 PM UTC 24 | 66507043839 ps | ||
| T2779 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.2893975338 | Aug 25 05:45:32 PM UTC 24 | Aug 25 05:53:21 PM UTC 24 | 4098561355 ps | ||
| T2780 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.686830460 | Aug 25 05:51:44 PM UTC 24 | Aug 25 05:53:24 PM UTC 24 | 5552359507 ps | ||
| T2781 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.551764075 | Aug 25 05:41:55 PM UTC 24 | Aug 25 05:53:24 PM UTC 24 | 7138060136 ps | ||
| T2782 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.4090915717 | Aug 25 05:51:31 PM UTC 24 | Aug 25 05:53:41 PM UTC 24 | 7909753465 ps | ||
| T2783 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.776387640 | Aug 25 05:52:46 PM UTC 24 | Aug 25 05:53:44 PM UTC 24 | 1166055680 ps | ||
| T2784 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.4261160400 | Aug 25 05:41:42 PM UTC 24 | Aug 25 05:53:44 PM UTC 24 | 28945350305 ps | ||
| T2785 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3618286858 | Aug 25 05:49:44 PM UTC 24 | Aug 25 05:53:45 PM UTC 24 | 10916627075 ps | ||
| T2786 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2677758747 | Aug 25 03:34:32 PM UTC 24 | Aug 25 05:53:45 PM UTC 24 | 37383731544 ps | ||
| T2787 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1491569478 | Aug 25 05:45:28 PM UTC 24 | Aug 25 05:53:46 PM UTC 24 | 11019388807 ps | ||
| T2788 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.2106271835 | Aug 25 05:52:59 PM UTC 24 | Aug 25 05:53:47 PM UTC 24 | 331847669 ps | ||
| T2789 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.2471929512 | Aug 25 05:53:26 PM UTC 24 | Aug 25 05:53:51 PM UTC 24 | 275829087 ps | ||
| T2790 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2650066645 | Aug 25 05:53:41 PM UTC 24 | Aug 25 05:53:51 PM UTC 24 | 50356664 ps | ||
| T2791 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.147193253 | Aug 25 05:53:39 PM UTC 24 | Aug 25 05:53:51 PM UTC 24 | 204365423 ps | ||
| T2792 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.3662171368 | Aug 25 05:47:11 PM UTC 24 | Aug 25 05:53:54 PM UTC 24 | 23223473398 ps | ||
| T2793 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2307305755 | Aug 25 05:51:37 PM UTC 24 | Aug 25 05:53:58 PM UTC 24 | 5471345185 ps | ||
| T2794 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3320041300 | Aug 25 05:43:39 PM UTC 24 | Aug 25 05:54:08 PM UTC 24 | 5488170940 ps | ||
| T2795 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.3164694182 | Aug 25 05:53:22 PM UTC 24 | Aug 25 05:54:09 PM UTC 24 | 462991040 ps | ||
| T2796 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1919985696 | Aug 25 05:48:52 PM UTC 24 | Aug 25 05:54:22 PM UTC 24 | 3547683932 ps | ||
| T2797 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2818021825 | Aug 25 05:53:13 PM UTC 24 | Aug 25 05:54:27 PM UTC 24 | 3005282545 ps | ||
| T2798 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1089209594 | Aug 25 05:54:15 PM UTC 24 | Aug 25 05:54:30 PM UTC 24 | 201187584 ps | ||
| T2799 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.2946448984 | Aug 25 05:52:44 PM UTC 24 | Aug 25 05:54:31 PM UTC 24 | 6885153703 ps | ||
| T2800 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1198853679 | Aug 25 05:53:26 PM UTC 24 | Aug 25 05:54:33 PM UTC 24 | 1365341348 ps | ||
| T2801 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.2920792750 | Aug 25 05:53:14 PM UTC 24 | Aug 25 05:54:39 PM UTC 24 | 1016072649 ps | ||
| T2802 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.103700914 | Aug 25 05:48:21 PM UTC 24 | Aug 25 05:54:43 PM UTC 24 | 22117907714 ps | ||
| T2803 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.921139409 | Aug 25 05:54:33 PM UTC 24 | Aug 25 05:54:43 PM UTC 24 | 42659035 ps | ||
| T2804 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.2603428738 | Aug 25 05:48:24 PM UTC 24 | Aug 25 05:54:44 PM UTC 24 | 14931341627 ps | ||
| T2805 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3893901751 | Aug 25 05:21:02 PM UTC 24 | Aug 25 05:54:47 PM UTC 24 | 84730657648 ps | ||
| T2806 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.124582669 | Aug 25 05:45:28 PM UTC 24 | Aug 25 05:54:52 PM UTC 24 | 1554498220 ps | ||
| T2807 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.691825065 | Aug 25 05:53:16 PM UTC 24 | Aug 25 05:54:56 PM UTC 24 | 2008965343 ps | ||
| T2808 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1374033360 | Aug 25 05:54:44 PM UTC 24 | Aug 25 05:54:56 PM UTC 24 | 60564650 ps | ||
| T2809 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3573954765 | Aug 25 05:52:27 PM UTC 24 | Aug 25 05:54:56 PM UTC 24 | 253542773 ps | ||
| T2810 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.42026692 | Aug 25 05:54:14 PM UTC 24 | Aug 25 05:54:57 PM UTC 24 | 751939740 ps | ||
| T2811 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1702091336 | Aug 25 05:52:45 PM UTC 24 | Aug 25 05:55:01 PM UTC 24 | 4890213863 ps | ||
| T2812 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1001729338 | Aug 25 05:54:11 PM UTC 24 | Aug 25 05:55:02 PM UTC 24 | 545437006 ps | ||
| T2813 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2715269859 | Aug 25 05:52:23 PM UTC 24 | Aug 25 05:55:03 PM UTC 24 | 289261433 ps | ||
| T2814 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3505475896 | Aug 25 05:53:48 PM UTC 24 | Aug 25 05:55:05 PM UTC 24 | 560210396 ps | ||
| T2815 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.1960730695 | Aug 25 05:51:58 PM UTC 24 | Aug 25 05:55:15 PM UTC 24 | 3213639575 ps | ||
| T2816 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.1861501602 | Aug 25 05:54:11 PM UTC 24 | Aug 25 05:55:23 PM UTC 24 | 1619771615 ps | ||
| T2817 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.3873105543 | Aug 25 05:55:16 PM UTC 24 | Aug 25 05:55:24 PM UTC 24 | 25774677 ps | ||
| T2818 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.3297565179 | Aug 25 05:52:24 PM UTC 24 | Aug 25 05:55:25 PM UTC 24 | 1423490815 ps | ||
| T2819 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3189278188 | Aug 25 05:09:45 PM UTC 24 | Aug 25 05:55:27 PM UTC 24 | 118092416219 ps | ||
| T2820 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.1412519697 | Aug 25 05:29:29 PM UTC 24 | Aug 25 05:55:28 PM UTC 24 | 62273827868 ps | ||
| T2821 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3947190822 | Aug 25 05:55:27 PM UTC 24 | Aug 25 05:55:37 PM UTC 24 | 42836345 ps | ||
| T2822 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.52737101 | Aug 25 05:55:30 PM UTC 24 | Aug 25 05:55:41 PM UTC 24 | 52210299 ps | ||
| T2823 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2860609849 | Aug 25 05:55:20 PM UTC 24 | Aug 25 05:55:43 PM UTC 24 | 399735597 ps | ||
| T2824 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.2635437799 | Aug 25 05:55:19 PM UTC 24 | Aug 25 05:55:49 PM UTC 24 | 388848186 ps | ||
| T2825 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.3252640129 | Aug 25 05:54:55 PM UTC 24 | Aug 25 05:55:50 PM UTC 24 | 516116921 ps | ||
| T2826 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.881559262 | Aug 25 05:53:49 PM UTC 24 | Aug 25 05:55:52 PM UTC 24 | 4554447955 ps | ||
| T2827 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1184594669 | Aug 25 05:54:55 PM UTC 24 | Aug 25 05:56:04 PM UTC 24 | 465575199 ps | ||
| T2828 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.3678105457 | Aug 25 05:53:45 PM UTC 24 | Aug 25 05:56:04 PM UTC 24 | 9175828513 ps | ||
| T2829 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.2380783231 | Aug 25 05:47:50 PM UTC 24 | Aug 25 05:56:07 PM UTC 24 | 8907231521 ps | ||
| T2830 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.2396916036 | Aug 25 05:55:10 PM UTC 24 | Aug 25 05:56:08 PM UTC 24 | 445511734 ps | ||
| T2831 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.2055934497 | Aug 25 05:49:35 PM UTC 24 | Aug 25 05:56:11 PM UTC 24 | 22101535717 ps | ||
| T2832 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.132447254 | Aug 25 05:55:48 PM UTC 24 | Aug 25 05:56:15 PM UTC 24 | 206764367 ps | ||
| T2833 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.2094101057 | Aug 25 05:56:13 PM UTC 24 | Aug 25 05:56:31 PM UTC 24 | 68157486 ps | ||
| T2834 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2452017640 | Aug 25 05:54:54 PM UTC 24 | Aug 25 05:56:42 PM UTC 24 | 5077740838 ps | ||
| T2835 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.1781804816 | Aug 25 05:54:09 PM UTC 24 | Aug 25 05:56:46 PM UTC 24 | 2714292090 ps | ||
| T2836 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.3851349305 | Aug 25 05:54:16 PM UTC 24 | Aug 25 05:56:52 PM UTC 24 | 1650945730 ps | ||
| T2837 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3671141313 | Aug 25 05:45:00 PM UTC 24 | Aug 25 05:56:55 PM UTC 24 | 41609140263 ps | ||
| T2838 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.2550750443 | Aug 25 05:56:06 PM UTC 24 | Aug 25 05:57:02 PM UTC 24 | 1178395605 ps | ||
| T2839 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.1033200575 | Aug 25 05:53:34 PM UTC 24 | Aug 25 05:57:04 PM UTC 24 | 1854049247 ps | ||
| T2840 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1437274513 | Aug 25 05:40:57 PM UTC 24 | Aug 25 05:57:04 PM UTC 24 | 17415531262 ps | ||
| T2841 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.4107359941 | Aug 25 05:55:47 PM UTC 24 | Aug 25 05:57:06 PM UTC 24 | 1709561870 ps | ||
| T2842 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.4121936182 | Aug 25 05:56:32 PM UTC 24 | Aug 25 05:57:08 PM UTC 24 | 70928014 ps | ||
| T2843 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1963557611 | Aug 25 05:48:48 PM UTC 24 | Aug 25 05:57:11 PM UTC 24 | 11053314784 ps | ||
| T2844 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.374285158 | Aug 25 05:56:13 PM UTC 24 | Aug 25 05:57:22 PM UTC 24 | 1057380672 ps | ||
| T2845 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.213720636 | Aug 25 05:52:20 PM UTC 24 | Aug 25 05:57:25 PM UTC 24 | 5340254532 ps | ||
| T2846 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.461034851 | Aug 25 05:35:56 PM UTC 24 | Aug 25 05:57:28 PM UTC 24 | 90178201849 ps | ||
| T2847 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.1280040834 | Aug 25 05:56:03 PM UTC 24 | Aug 25 05:57:35 PM UTC 24 | 1915865014 ps | ||
| T2848 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.575221248 | Aug 25 05:55:05 PM UTC 24 | Aug 25 05:57:38 PM UTC 24 | 5334894679 ps | ||
| T2849 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2037395389 | Aug 25 05:55:48 PM UTC 24 | Aug 25 05:57:39 PM UTC 24 | 1934868322 ps | ||
| T2850 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.3794950838 | Aug 25 05:55:08 PM UTC 24 | Aug 25 05:57:42 PM UTC 24 | 2330415419 ps | ||
| T2851 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.3050203337 | Aug 25 05:55:19 PM UTC 24 | Aug 25 05:57:47 PM UTC 24 | 3070413927 ps | ||
| T2852 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3594367890 | Aug 25 05:55:39 PM UTC 24 | Aug 25 05:57:54 PM UTC 24 | 5931142600 ps | ||
| T2853 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.3499926161 | Aug 25 03:29:42 PM UTC 24 | Aug 25 05:58:06 PM UTC 24 | 37818739158 ps | ||
| T2854 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.583949335 | Aug 25 05:54:51 PM UTC 24 | Aug 25 05:58:16 PM UTC 24 | 11214519297 ps | ||
| T2855 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1269034227 | Aug 25 05:55:39 PM UTC 24 | Aug 25 05:58:21 PM UTC 24 | 9344114794 ps | ||
| T2856 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.3269492782 | Aug 25 05:50:47 PM UTC 24 | Aug 25 05:58:26 PM UTC 24 | 20472172502 ps | ||
| T628 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3570848826 | Aug 25 05:47:52 PM UTC 24 | Aug 25 05:58:44 PM UTC 24 | 3300502970 ps | ||
| T2857 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.690954871 | Aug 25 05:47:36 PM UTC 24 | Aug 25 05:58:47 PM UTC 24 | 5170039633 ps | ||
| T2858 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.2145452865 | Aug 25 05:50:45 PM UTC 24 | Aug 25 05:58:52 PM UTC 24 | 35020075652 ps | ||
| T2859 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3423229360 | Aug 25 05:48:34 PM UTC 24 | Aug 25 05:58:55 PM UTC 24 | 24184303616 ps | ||
| T2860 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4155027883 | Aug 25 05:47:21 PM UTC 24 | Aug 25 05:58:58 PM UTC 24 | 32365388068 ps | ||
| T2861 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1549521042 | Aug 25 05:10:54 PM UTC 24 | Aug 25 05:59:03 PM UTC 24 | 111109291224 ps | ||
| T2862 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2571407590 | Aug 25 05:51:24 PM UTC 24 | Aug 25 05:59:09 PM UTC 24 | 798822600 ps | ||
| T2863 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.355692213 | Aug 25 05:49:10 PM UTC 24 | Aug 25 05:59:12 PM UTC 24 | 4362153519 ps | ||
| T2864 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.3789054304 | Aug 25 05:56:27 PM UTC 24 | Aug 25 05:59:59 PM UTC 24 | 2441020662 ps | ||
| T2865 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.3329644457 | Aug 25 05:51:22 PM UTC 24 | Aug 25 06:00:12 PM UTC 24 | 10003334490 ps | ||
| T2866 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1628290089 | Aug 25 05:44:26 PM UTC 24 | Aug 25 06:00:23 PM UTC 24 | 16528191008 ps | ||
| T2867 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.2001620313 | Aug 25 05:46:32 PM UTC 24 | Aug 25 06:00:29 PM UTC 24 | 17266221972 ps | ||
| T2868 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3193545113 | Aug 25 05:37:26 PM UTC 24 | Aug 25 06:00:32 PM UTC 24 | 95628823477 ps | ||
| T2869 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.180990278 | Aug 25 05:15:55 PM UTC 24 | Aug 25 06:00:37 PM UTC 24 | 109843772867 ps | ||
| T2870 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.3648347073 | Aug 25 05:55:23 PM UTC 24 | Aug 25 06:00:41 PM UTC 24 | 2657306160 ps | ||
| T2871 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.554583920 | Aug 25 05:38:45 PM UTC 24 | Aug 25 06:00:59 PM UTC 24 | 54276598306 ps | ||
| T2872 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.123156449 | Aug 25 05:44:25 PM UTC 24 | Aug 25 06:01:00 PM UTC 24 | 13816136752 ps | ||
| T2873 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.309820826 | Aug 25 05:51:12 PM UTC 24 | Aug 25 06:01:38 PM UTC 24 | 14784332278 ps | ||
| T2874 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1697089981 | Aug 25 05:54:32 PM UTC 24 | Aug 25 06:01:41 PM UTC 24 | 7720829836 ps | ||
| T2875 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2273351054 | Aug 25 05:54:22 PM UTC 24 | Aug 25 06:01:42 PM UTC 24 | 11493461988 ps | ||
| T2876 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.3368488061 | Aug 25 05:53:26 PM UTC 24 | Aug 25 06:01:48 PM UTC 24 | 9213238706 ps | ||
| T2877 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.221391936 | Aug 25 05:22:11 PM UTC 24 | Aug 25 06:02:09 PM UTC 24 | 106364678822 ps | ||
| T2878 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2162661144 | Aug 25 05:36:04 PM UTC 24 | Aug 25 06:02:13 PM UTC 24 | 69352001184 ps | ||
| T2879 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.3634009642 | Aug 25 05:54:09 PM UTC 24 | Aug 25 06:02:25 PM UTC 24 | 24453564213 ps | ||
| T2880 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.4277826132 | Aug 25 05:31:32 PM UTC 24 | Aug 25 06:02:25 PM UTC 24 | 118490991165 ps | ||
| T2881 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3044573358 | Aug 25 05:55:25 PM UTC 24 | Aug 25 06:02:25 PM UTC 24 | 2219561421 ps | ||
| T2882 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4014355512 | Aug 25 05:56:26 PM UTC 24 | Aug 25 06:02:37 PM UTC 24 | 649433701 ps | ||
| T2883 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.303995603 | Aug 25 05:54:18 PM UTC 24 | Aug 25 06:02:55 PM UTC 24 | 8152286880 ps | ||
| T2884 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.366970267 | Aug 25 05:37:35 PM UTC 24 | Aug 25 06:02:58 PM UTC 24 | 62381065207 ps | ||
| T2885 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.52509920 | Aug 25 05:46:09 PM UTC 24 | Aug 25 06:02:58 PM UTC 24 | 77023893942 ps | ||
| T2886 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.411861717 | Aug 25 05:55:49 PM UTC 24 | Aug 25 06:03:09 PM UTC 24 | 34794719499 ps | ||
| T2887 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2322774498 | Aug 25 05:53:30 PM UTC 24 | Aug 25 06:03:25 PM UTC 24 | 8638997497 ps | ||
| T2888 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3425557707 | Aug 25 05:30:51 PM UTC 24 | Aug 25 06:03:44 PM UTC 24 | 96958869989 ps | ||
| T2889 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.2496253506 | Aug 25 05:55:51 PM UTC 24 | Aug 25 06:03:48 PM UTC 24 | 24258296034 ps | ||
| T2890 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.2532823713 | Aug 25 05:53:04 PM UTC 24 | Aug 25 06:03:51 PM UTC 24 | 50170991435 ps | ||
| T2891 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3731521710 | Aug 25 05:27:29 PM UTC 24 | Aug 25 06:04:18 PM UTC 24 | 105927968627 ps | ||
| T2892 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2516279919 | Aug 25 03:28:43 PM UTC 24 | Aug 25 06:04:34 PM UTC 24 | 37336914910 ps | ||
| T2893 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.3011110213 | Aug 25 05:56:15 PM UTC 24 | Aug 25 06:04:45 PM UTC 24 | 14079489118 ps | ||
| T2894 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2897281236 | Aug 25 05:53:38 PM UTC 24 | Aug 25 06:04:46 PM UTC 24 | 13805127456 ps | ||
| T2895 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.5136142 | Aug 25 05:34:00 PM UTC 24 | Aug 25 06:04:47 PM UTC 24 | 80686682537 ps | ||
| T2896 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.3932410264 | Aug 25 05:54:08 PM UTC 24 | Aug 25 06:04:50 PM UTC 24 | 56577731891 ps | ||
| T2897 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2319426606 | Aug 25 05:24:13 PM UTC 24 | Aug 25 06:04:59 PM UTC 24 | 100878943764 ps | ||
| T2898 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2405561935 | Aug 25 05:56:00 PM UTC 24 | Aug 25 06:05:06 PM UTC 24 | 33358632421 ps | ||
| T2899 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.152020820 | Aug 25 05:26:32 PM UTC 24 | Aug 25 06:05:25 PM UTC 24 | 111866986262 ps | ||
| T2900 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.525574511 | Aug 25 05:46:12 PM UTC 24 | Aug 25 06:05:29 PM UTC 24 | 59336927342 ps | ||
| T2901 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2944806414 | Aug 25 05:55:20 PM UTC 24 | Aug 25 06:05:38 PM UTC 24 | 9226332530 ps | ||
| T2902 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2021595881 | Aug 25 05:46:08 PM UTC 24 | Aug 25 06:05:47 PM UTC 24 | 58157185489 ps | ||
| T2903 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.3528308449 | Aug 25 05:51:54 PM UTC 24 | Aug 25 06:05:53 PM UTC 24 | 48258321765 ps | ||
| T2904 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.2811215041 | Aug 25 05:41:29 PM UTC 24 | Aug 25 06:06:01 PM UTC 24 | 104335316090 ps | ||
| T2905 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2687697301 | Aug 25 05:19:33 PM UTC 24 | Aug 25 06:06:42 PM UTC 24 | 136827879556 ps | ||
| T2906 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.1489763916 | Aug 25 05:53:10 PM UTC 24 | Aug 25 06:07:34 PM UTC 24 | 46387112044 ps | ||
| T2907 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.2323019903 | Aug 25 05:49:37 PM UTC 24 | Aug 25 06:07:51 PM UTC 24 | 56973208333 ps | ||
| T2908 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3287076458 | Aug 25 05:54:10 PM UTC 24 | Aug 25 06:07:56 PM UTC 24 | 46717587320 ps | ||
| T2909 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2838636221 | Aug 25 03:28:51 PM UTC 24 | Aug 25 06:10:50 PM UTC 24 | 39498862484 ps | ||
| T2910 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3587077403 | Aug 25 03:34:23 PM UTC 24 | Aug 25 06:15:39 PM UTC 24 | 60258740588 ps | ||
| T2911 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1403796064 | Aug 25 05:55:01 PM UTC 24 | Aug 25 06:16:40 PM UTC 24 | 112200947265 ps | ||
| T2912 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1814437512 | Aug 25 05:50:51 PM UTC 24 | Aug 25 06:20:16 PM UTC 24 | 94355286100 ps | ||
| T2913 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1404466059 | Aug 25 05:44:09 PM UTC 24 | Aug 25 06:24:33 PM UTC 24 | 121463078317 ps | ||
| T2914 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1541445833 | Aug 25 05:39:03 PM UTC 24 | Aug 25 06:24:55 PM UTC 24 | 128915698907 ps | ||
| T2915 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1766248763 | Aug 25 05:40:28 PM UTC 24 | Aug 25 06:27:24 PM UTC 24 | 148372337858 ps | ||
| T2916 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3356194438 | Aug 25 05:45:10 PM UTC 24 | Aug 25 06:30:51 PM UTC 24 | 131307153419 ps | ||
| T2917 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1805465571 | Aug 25 05:52:03 PM UTC 24 | Aug 25 06:31:43 PM UTC 24 | 111668015285 ps | ||
| T2918 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2886029513 | Aug 25 05:55:06 PM UTC 24 | Aug 25 06:41:32 PM UTC 24 | 143329304977 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1487741290 | Aug 25 05:57:26 PM UTC 24 | Aug 25 06:01:09 PM UTC 24 | 5209897144 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3269230669 | Aug 25 05:56:36 PM UTC 24 | Aug 25 06:01:32 PM UTC 24 | 4443229560 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3106790346 | Aug 25 05:56:33 PM UTC 24 | Aug 25 06:01:33 PM UTC 24 | 4167992244 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.140691267 | Aug 25 05:56:38 PM UTC 24 | Aug 25 06:01:47 PM UTC 24 | 4332561222 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3474484554 | Aug 25 05:56:54 PM UTC 24 | Aug 25 06:02:29 PM UTC 24 | 3850951912 ps | ||
| T223 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3969783387 | Aug 25 05:57:19 PM UTC 24 | Aug 25 06:02:31 PM UTC 24 | 4833649463 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2387588596 | Aug 25 05:57:15 PM UTC 24 | Aug 25 06:02:33 PM UTC 24 | 4903345964 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.529622900 | Aug 25 05:57:05 PM UTC 24 | Aug 25 06:02:44 PM UTC 24 | 5517829126 ps | ||
| T226 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3221585720 | Aug 25 05:57:28 PM UTC 24 | Aug 25 06:03:04 PM UTC 24 | 4118826577 ps | ||
| T227 | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2347496682 | Aug 25 05:57:11 PM UTC 24 | Aug 25 06:03:28 PM UTC 24 | 6245163880 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1047033246 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3241445389 ps |
| CPU time | 232.92 seconds |
| Started | Aug 25 06:06:25 PM UTC 24 |
| Finished | Aug 25 06:10:21 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047033246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1047033246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.646438572 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 6173941775 ps |
| CPU time | 613.3 seconds |
| Started | Aug 25 03:28:50 PM UTC 24 |
| Finished | Aug 25 03:39:12 PM UTC 24 |
| Peak memory | 663412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=646438572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.646438572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.1481183284 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5762732944 ps |
| CPU time | 1503.89 seconds |
| Started | Aug 25 06:30:32 PM UTC 24 |
| Finished | Aug 25 06:56:05 PM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481183284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_plic_all_irqs_0.1481183284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1564910649 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 202449074 ps |
| CPU time | 26.61 seconds |
| Started | Aug 25 03:28:49 PM UTC 24 |
| Finished | Aug 25 03:29:16 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564910649 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1564910649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1115754360 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4760846568 ps |
| CPU time | 293.01 seconds |
| Started | Aug 25 06:05:44 PM UTC 24 |
| Finished | Aug 25 06:10:41 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1115754360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sleep_pin_retention.1115754360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1487741290 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5209897144 ps |
| CPU time | 218.28 seconds |
| Started | Aug 25 05:57:26 PM UTC 24 |
| Finished | Aug 25 06:01:09 PM UTC 24 |
| Peak memory | 672732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487741 290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 8.chip_ padctrl_attributes.1487741290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3723572005 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 79186797631 ps |
| CPU time | 1644.31 seconds |
| Started | Aug 25 03:32:44 PM UTC 24 |
| Finished | Aug 25 04:00:31 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723572005 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3723572005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.626216310 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 3163633414 ps |
| CPU time | 437.81 seconds |
| Started | Aug 25 06:20:40 PM UTC 24 |
| Finished | Aug 25 06:28:07 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=626216310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert _test.626216310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3551188486 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8572405142 ps |
| CPU time | 1481.08 seconds |
| Started | Aug 25 06:29:09 PM UTC 24 |
| Finished | Aug 25 06:54:16 PM UTC 24 |
| Peak memory | 626020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551188486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3551188486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1413986101 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 3387114878 ps |
| CPU time | 214.8 seconds |
| Started | Aug 25 03:57:43 PM UTC 24 |
| Finished | Aug 25 04:01:22 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413986101 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1413986101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1618623355 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 70449144690 ps |
| CPU time | 1581.63 seconds |
| Started | Aug 25 03:41:23 PM UTC 24 |
| Finished | Aug 25 04:08:05 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618623355 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1618623355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3952770775 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10423188398 ps |
| CPU time | 1018.92 seconds |
| Started | Aug 25 06:08:35 PM UTC 24 |
| Finished | Aug 25 06:25:52 PM UTC 24 |
| Peak memory | 640348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952770775 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3952770775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.18882069 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 142410111115 ps |
| CPU time | 3183.97 seconds |
| Started | Aug 25 03:39:51 PM UTC 24 |
| Finished | Aug 25 04:33:39 PM UTC 24 |
| Peak memory | 599560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18882069 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.18882069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.1926953070 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4629883692 ps |
| CPU time | 1121.82 seconds |
| Started | Aug 25 06:32:19 PM UTC 24 |
| Finished | Aug 25 06:51:22 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1926953070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_20.1926953070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.263973351 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 73884842419 ps |
| CPU time | 1645.5 seconds |
| Started | Aug 25 03:35:18 PM UTC 24 |
| Finished | Aug 25 04:03:05 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263973351 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.263973351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1540489207 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 13865342442 ps |
| CPU time | 2101.55 seconds |
| Started | Aug 25 10:12:20 PM UTC 24 |
| Finished | Aug 25 10:48:00 PM UTC 24 |
| Peak memory | 623248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154048 9207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_csr_rw.1540489207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3157979734 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5268086808 ps |
| CPU time | 2014.8 seconds |
| Started | Aug 25 06:55:37 PM UTC 24 |
| Finished | Aug 25 07:29:46 PM UTC 24 |
| Peak memory | 640516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157979734 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3157979734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3338855245 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2363227526 ps |
| CPU time | 146.53 seconds |
| Started | Aug 25 03:28:47 PM UTC 24 |
| Finished | Aug 25 03:31:17 PM UTC 24 |
| Peak memory | 599116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338855245 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3338855245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.912982563 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5446945528 ps |
| CPU time | 741.57 seconds |
| Started | Aug 25 06:10:19 PM UTC 24 |
| Finished | Aug 25 06:22:56 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912982563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctr l_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.912982563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1848309081 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4188211984 ps |
| CPU time | 272.83 seconds |
| Started | Aug 25 03:28:42 PM UTC 24 |
| Finished | Aug 25 03:33:20 PM UTC 24 |
| Peak memory | 624248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848309081 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1848309081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.2926895692 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12308207985 ps |
| CPU time | 1490.64 seconds |
| Started | Aug 25 06:34:59 PM UTC 24 |
| Finished | Aug 25 07:00:17 PM UTC 24 |
| Peak memory | 623248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292689 5692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_csr_rw.2926895692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2090346415 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2888832624 ps |
| CPU time | 449.31 seconds |
| Started | Aug 25 06:41:52 PM UTC 24 |
| Finished | Aug 25 06:49:32 PM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090346415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2090346415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.2136761186 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1046912612 ps |
| CPU time | 101.23 seconds |
| Started | Aug 25 03:47:42 PM UTC 24 |
| Finished | Aug 25 03:49:25 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136761186 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2136761186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.2707117764 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4075226936 ps |
| CPU time | 483.47 seconds |
| Started | Aug 25 06:05:38 PM UTC 24 |
| Finished | Aug 25 06:13:49 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2707117764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_gpio.2707117764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2733740810 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 10188348825 ps |
| CPU time | 939.76 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:44:42 PM UTC 24 |
| Peak memory | 598852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733740810 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.2733740810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.605915202 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 182183994 ps |
| CPU time | 11.66 seconds |
| Started | Aug 25 03:28:44 PM UTC 24 |
| Finished | Aug 25 03:28:57 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605915202 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.605915202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.475991545 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 80199056399 ps |
| CPU time | 1927.07 seconds |
| Started | Aug 25 03:49:49 PM UTC 24 |
| Finished | Aug 25 04:22:24 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475991545 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.475991545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.696709615 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 116048772470 ps |
| CPU time | 2881 seconds |
| Started | Aug 25 04:19:41 PM UTC 24 |
| Finished | Aug 25 05:08:21 PM UTC 24 |
| Peak memory | 599992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696709615 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.696709615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2533316707 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5046558930 ps |
| CPU time | 1520.36 seconds |
| Started | Aug 25 06:22:02 PM UTC 24 |
| Finished | Aug 25 06:47:52 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533316707 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_auto_mode.2533316707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3544429193 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9336248152 ps |
| CPU time | 1462.26 seconds |
| Started | Aug 25 06:21:17 PM UTC 24 |
| Finished | Aug 25 06:46:06 PM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544429193 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_hand ler_lpg_sleep_mode_pings.3544429193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.512539478 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 587961050 ps |
| CPU time | 316.98 seconds |
| Started | Aug 25 03:28:49 PM UTC 24 |
| Finished | Aug 25 03:34:12 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512539478 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.512539478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.2600304510 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3801829710 ps |
| CPU time | 760.59 seconds |
| Started | Aug 25 06:32:49 PM UTC 24 |
| Finished | Aug 25 06:45:46 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2600304510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_plic_all_irqs_10.2600304510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2855313339 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3861190204 ps |
| CPU time | 247.96 seconds |
| Started | Aug 25 06:07:06 PM UTC 24 |
| Finished | Aug 25 06:11:18 PM UTC 24 |
| Peak memory | 638060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855313339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2855313339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.4157146945 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 74146629584 ps |
| CPU time | 1850.53 seconds |
| Started | Aug 25 03:45:52 PM UTC 24 |
| Finished | Aug 25 04:17:10 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157146945 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.4157146945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1999909466 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4702109752 ps |
| CPU time | 537.48 seconds |
| Started | Aug 25 06:32:24 PM UTC 24 |
| Finished | Aug 25 06:41:32 PM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999909466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1999909466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2396972586 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1789396769 ps |
| CPU time | 96.33 seconds |
| Started | Aug 25 03:32:29 PM UTC 24 |
| Finished | Aug 25 03:34:07 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396972586 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2396972586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1395212051 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5049098816 ps |
| CPU time | 954 seconds |
| Started | Aug 25 03:29:34 PM UTC 24 |
| Finished | Aug 25 03:45:43 PM UTC 24 |
| Peak memory | 620088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395212051 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1395212051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1631955103 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 9624276574 ps |
| CPU time | 159.3 seconds |
| Started | Aug 25 03:28:45 PM UTC 24 |
| Finished | Aug 25 03:31:27 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631955103 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1631955103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3731629409 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3741776460 ps |
| CPU time | 638.69 seconds |
| Started | Aug 25 06:15:41 PM UTC 24 |
| Finished | Aug 25 06:26:33 PM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731629409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3731629409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.3076191782 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 44424376732 ps |
| CPU time | 7154.69 seconds |
| Started | Aug 25 06:06:53 PM UTC 24 |
| Finished | Aug 25 08:08:11 PM UTC 24 |
| Peak memory | 639392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076191782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3076191782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2385962421 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 10971501874 ps |
| CPU time | 3956.98 seconds |
| Started | Aug 25 07:06:30 PM UTC 24 |
| Finished | Aug 25 08:13:40 PM UTC 24 |
| Peak memory | 624016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385962421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2385962421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2792250702 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 4104895679 ps |
| CPU time | 566.07 seconds |
| Started | Aug 25 03:36:26 PM UTC 24 |
| Finished | Aug 25 03:46:02 PM UTC 24 |
| Peak memory | 624372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792250702 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2792250702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3795063358 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3026072943 ps |
| CPU time | 348.66 seconds |
| Started | Aug 25 07:17:58 PM UTC 24 |
| Finished | Aug 25 07:23:54 PM UTC 24 |
| Peak memory | 623812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795063358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3795063358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2090927968 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2209154178 ps |
| CPU time | 96.21 seconds |
| Started | Aug 25 03:28:55 PM UTC 24 |
| Finished | Aug 25 03:30:34 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090927968 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.2090927968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1222006416 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4198953360 ps |
| CPU time | 736.14 seconds |
| Started | Aug 25 06:15:02 PM UTC 24 |
| Finished | Aug 25 06:27:35 PM UTC 24 |
| Peak memory | 628200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1222006416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1222006416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3432653047 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7862678688 ps |
| CPU time | 489.47 seconds |
| Started | Aug 25 03:31:27 PM UTC 24 |
| Finished | Aug 25 03:39:44 PM UTC 24 |
| Peak memory | 683576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432653047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_reset.3432653047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.3496094574 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3541030568 ps |
| CPU time | 466.43 seconds |
| Started | Aug 25 06:08:50 PM UTC 24 |
| Finished | Aug 25 06:16:44 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496094574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3496094574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.3348089086 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4993969572 ps |
| CPU time | 1087.06 seconds |
| Started | Aug 25 06:13:44 PM UTC 24 |
| Finished | Aug 25 06:32:10 PM UTC 24 |
| Peak memory | 625964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348089086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3348089086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.4171198919 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2274420147 ps |
| CPU time | 107.59 seconds |
| Started | Aug 25 06:59:31 PM UTC 24 |
| Finished | Aug 25 07:01:21 PM UTC 24 |
| Peak memory | 633520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4171198919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.4171198919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1238900167 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 48459114 ps |
| CPU time | 8.83 seconds |
| Started | Aug 25 03:28:45 PM UTC 24 |
| Finished | Aug 25 03:28:55 PM UTC 24 |
| Peak memory | 597284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238900167 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1238900167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3172786653 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4646899478 ps |
| CPU time | 666.58 seconds |
| Started | Aug 25 03:59:17 PM UTC 24 |
| Finished | Aug 25 04:10:35 PM UTC 24 |
| Peak memory | 624248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172786653 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3172786653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3606189542 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3643551800 ps |
| CPU time | 471.04 seconds |
| Started | Aug 25 09:09:54 PM UTC 24 |
| Finished | Aug 25 09:17:54 PM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606189542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_ mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3606189542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.1245080129 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4737621434 ps |
| CPU time | 872 seconds |
| Started | Aug 25 06:13:29 PM UTC 24 |
| Finished | Aug 25 06:28:19 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245080129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_rstmgr_cpu_info.1245080129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.828123840 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 12085409153 ps |
| CPU time | 662 seconds |
| Started | Aug 25 03:28:50 PM UTC 24 |
| Finished | Aug 25 03:40:03 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828123840 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.828123840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1199681382 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 22710579912 ps |
| CPU time | 1359.46 seconds |
| Started | Aug 25 03:48:38 PM UTC 24 |
| Finished | Aug 25 04:11:37 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199681382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1199681382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1171204399 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 22094607608 ps |
| CPU time | 1744.31 seconds |
| Started | Aug 25 06:38:02 PM UTC 24 |
| Finished | Aug 25 07:07:35 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171204399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1171204399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2435382005 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5665116110 ps |
| CPU time | 796.9 seconds |
| Started | Aug 25 06:25:09 PM UTC 24 |
| Finished | Aug 25 06:38:41 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435382005 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_lc_hw_debug_en_test.2435382005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3330976304 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2573772764 ps |
| CPU time | 311.66 seconds |
| Started | Aug 25 06:08:53 PM UTC 24 |
| Finished | Aug 25 06:14:11 PM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330976304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_spi_host_tx_rx.3330976304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2699077974 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6021243864 ps |
| CPU time | 1009.08 seconds |
| Started | Aug 25 11:18:00 PM UTC 24 |
| Finished | Aug 25 11:35:09 PM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699077974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2699077974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1094500318 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 14727107217 ps |
| CPU time | 958.83 seconds |
| Started | Aug 25 03:48:41 PM UTC 24 |
| Finished | Aug 25 04:04:56 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094500318 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1094500318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1206888744 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 5150699368 ps |
| CPU time | 825.44 seconds |
| Started | Aug 25 11:01:37 PM UTC 24 |
| Finished | Aug 25 11:15:39 PM UTC 24 |
| Peak memory | 674300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206888744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1206888744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.143138925 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3962589868 ps |
| CPU time | 738.48 seconds |
| Started | Aug 25 11:20:16 PM UTC 24 |
| Finished | Aug 25 11:32:50 PM UTC 24 |
| Peak memory | 674496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143138925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.143138925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300248947 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4006989880 ps |
| CPU time | 542.72 seconds |
| Started | Aug 25 11:01:36 PM UTC 24 |
| Finished | Aug 25 11:10:50 PM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300248947 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3300248947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1543696219 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 4028866509 ps |
| CPU time | 322.16 seconds |
| Started | Aug 25 06:40:52 PM UTC 24 |
| Finished | Aug 25 06:46:20 PM UTC 24 |
| Peak memory | 650860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543696219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1543696219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3569144928 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3621530383 ps |
| CPU time | 275.62 seconds |
| Started | Aug 25 06:10:59 PM UTC 24 |
| Finished | Aug 25 06:15:40 PM UTC 24 |
| Peak memory | 636352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3569144928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3569144928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1586730273 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5747825544 ps |
| CPU time | 1281.24 seconds |
| Started | Aug 25 09:09:32 PM UTC 24 |
| Finished | Aug 25 09:31:18 PM UTC 24 |
| Peak memory | 625936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586730273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1586730273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.872879750 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5507510012 ps |
| CPU time | 493.76 seconds |
| Started | Aug 25 06:09:44 PM UTC 24 |
| Finished | Aug 25 06:18:08 PM UTC 24 |
| Peak memory | 625956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872879750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.872879750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2673006693 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 11947333480 ps |
| CPU time | 1907.01 seconds |
| Started | Aug 25 06:12:49 PM UTC 24 |
| Finished | Aug 25 06:45:12 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673006693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2673006693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.3980236403 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1239014234 ps |
| CPU time | 73.71 seconds |
| Started | Aug 25 03:29:10 PM UTC 24 |
| Finished | Aug 25 03:30:26 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980236403 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3980236403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3062815019 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 6203237900 ps |
| CPU time | 1033.46 seconds |
| Started | Aug 25 10:03:27 PM UTC 24 |
| Finished | Aug 25 10:21:02 PM UTC 24 |
| Peak memory | 623824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062815019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3062815019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.634456335 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5606698678 ps |
| CPU time | 1638.6 seconds |
| Started | Aug 25 10:06:48 PM UTC 24 |
| Finished | Aug 25 10:34:35 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634456335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_plic_all_irqs_0.634456335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3125434604 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 4718984520 ps |
| CPU time | 663.17 seconds |
| Started | Aug 25 06:32:34 PM UTC 24 |
| Finished | Aug 25 06:43:52 PM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3125434604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_otbn_trans.3125434604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3114878643 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 19281600714 ps |
| CPU time | 1051.21 seconds |
| Started | Aug 25 03:38:13 PM UTC 24 |
| Finished | Aug 25 03:56:00 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114878643 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3114878643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.2238032894 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3358022906 ps |
| CPU time | 410.11 seconds |
| Started | Aug 25 07:17:54 PM UTC 24 |
| Finished | Aug 25 07:24:52 PM UTC 24 |
| Peak memory | 623640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238032894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.2238032894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.1526176869 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 8374121966 ps |
| CPU time | 580.1 seconds |
| Started | Aug 25 03:36:04 PM UTC 24 |
| Finished | Aug 25 03:45:53 PM UTC 24 |
| Peak memory | 683580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526176869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_reset.1526176869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1495571799 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4509756007 ps |
| CPU time | 743.23 seconds |
| Started | Aug 25 04:04:02 PM UTC 24 |
| Finished | Aug 25 04:16:37 PM UTC 24 |
| Peak memory | 624248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495571799 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1495571799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.1365317217 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3728292358 ps |
| CPU time | 430.69 seconds |
| Started | Aug 25 06:01:44 PM UTC 24 |
| Finished | Aug 25 06:09:01 PM UTC 24 |
| Peak memory | 640216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365317217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1365317217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all.2303475371 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3917096689 ps |
| CPU time | 511.98 seconds |
| Started | Aug 25 04:18:07 PM UTC 24 |
| Finished | Aug 25 04:26:48 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303475371 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2303475371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.1795001092 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 44697576928 ps |
| CPU time | 8680.77 seconds |
| Started | Aug 25 07:37:08 PM UTC 24 |
| Finished | Aug 25 10:04:34 PM UTC 24 |
| Peak memory | 639140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795001092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1795001092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2355633533 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 3248066496 ps |
| CPU time | 579.79 seconds |
| Started | Aug 25 03:31:00 PM UTC 24 |
| Finished | Aug 25 03:40:48 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355633533 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2355633533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.4280597018 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4295085364 ps |
| CPU time | 1172.75 seconds |
| Started | Aug 25 08:40:24 PM UTC 24 |
| Finished | Aug 25 09:00:19 PM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4280597018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_20.4280597018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.1072282869 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 20198343182 ps |
| CPU time | 2077.71 seconds |
| Started | Aug 25 06:46:34 PM UTC 24 |
| Finished | Aug 25 07:21:47 PM UTC 24 |
| Peak memory | 632044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072282869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1072282869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.672274924 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5096061050 ps |
| CPU time | 691.1 seconds |
| Started | Aug 25 06:14:34 PM UTC 24 |
| Finished | Aug 25 06:26:20 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=672274924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.672274924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.506456381 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6142542360 ps |
| CPU time | 1681.2 seconds |
| Started | Aug 25 08:38:31 PM UTC 24 |
| Finished | Aug 25 09:07:04 PM UTC 24 |
| Peak memory | 623604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506456381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_plic_all_irqs_0.506456381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2748719787 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15199554581 ps |
| CPU time | 2108.08 seconds |
| Started | Aug 25 03:31:45 PM UTC 24 |
| Finished | Aug 25 04:07:21 PM UTC 24 |
| Peak memory | 614100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2748719787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.chip_same_csr_outstanding.2748719787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4136012993 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4850808624 ps |
| CPU time | 866.76 seconds |
| Started | Aug 25 06:33:57 PM UTC 24 |
| Finished | Aug 25 06:48:42 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136012993 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.4136012993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2658080704 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 11265040373 ps |
| CPU time | 1159.36 seconds |
| Started | Aug 25 03:56:13 PM UTC 24 |
| Finished | Aug 25 04:15:51 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658080704 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2658080704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2623043348 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5256545168 ps |
| CPU time | 1014.66 seconds |
| Started | Aug 25 06:30:47 PM UTC 24 |
| Finished | Aug 25 06:48:01 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623043348 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ct rl_scrambled_access_jitter_en.2623043348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.4109076501 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4288540470 ps |
| CPU time | 520.2 seconds |
| Started | Aug 25 03:42:49 PM UTC 24 |
| Finished | Aug 25 03:51:38 PM UTC 24 |
| Peak memory | 624184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109076501 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.4109076501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2930963695 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 451520412 ps |
| CPU time | 60.42 seconds |
| Started | Aug 25 03:28:55 PM UTC 24 |
| Finished | Aug 25 03:29:58 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930963695 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.2930963695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.1075323898 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 6170142216 ps |
| CPU time | 933.74 seconds |
| Started | Aug 25 06:32:55 PM UTC 24 |
| Finished | Aug 25 06:48:48 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075323898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1075323898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.750772369 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4589803750 ps |
| CPU time | 709 seconds |
| Started | Aug 25 06:39:34 PM UTC 24 |
| Finished | Aug 25 06:51:38 PM UTC 24 |
| Peak memory | 638000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750772369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_res et_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.750772369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1051216736 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2529663747 ps |
| CPU time | 210.57 seconds |
| Started | Aug 25 06:08:51 PM UTC 24 |
| Finished | Aug 25 06:12:25 PM UTC 24 |
| Peak memory | 640224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1051216736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1051216736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4064918025 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2829418729 ps |
| CPU time | 571.27 seconds |
| Started | Aug 25 03:31:27 PM UTC 24 |
| Finished | Aug 25 03:41:07 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064918025 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.4064918025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1296536672 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 29334104360 ps |
| CPU time | 5825.42 seconds |
| Started | Aug 25 06:53:56 PM UTC 24 |
| Finished | Aug 25 08:32:42 PM UTC 24 |
| Peak memory | 628940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296536672 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1296536672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.359717041 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 42597390647 ps |
| CPU time | 9494.54 seconds |
| Started | Aug 25 09:18:31 PM UTC 24 |
| Finished | Aug 25 11:59:37 PM UTC 24 |
| Peak memory | 639000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw _build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359717041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.359717041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1329664436 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4438769102 ps |
| CPU time | 650.88 seconds |
| Started | Aug 25 10:05:12 PM UTC 24 |
| Finished | Aug 25 10:16:15 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1329664436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_10.1329664436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_rst_inputs.3196653809 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 18591353400 ps |
| CPU time | 3597.4 seconds |
| Started | Aug 25 06:56:28 PM UTC 24 |
| Finished | Aug 25 07:57:28 PM UTC 24 |
| Peak memory | 628796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196653809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3196653809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3483005304 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4257690693 ps |
| CPU time | 331.58 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:34:25 PM UTC 24 |
| Peak memory | 683764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483005304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_reset.3483005304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.2472213072 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4566022372 ps |
| CPU time | 657.31 seconds |
| Started | Aug 25 06:05:50 PM UTC 24 |
| Finished | Aug 25 06:16:58 PM UTC 24 |
| Peak memory | 636196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472213072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2472213072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.339996989 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 7344005044 ps |
| CPU time | 1279.69 seconds |
| Started | Aug 25 04:37:33 PM UTC 24 |
| Finished | Aug 25 04:59:12 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339996989 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.339996989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.1627887176 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 48769461658 ps |
| CPU time | 9184.38 seconds |
| Started | Aug 25 06:09:51 PM UTC 24 |
| Finished | Aug 25 08:45:40 PM UTC 24 |
| Peak memory | 643372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627887176 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_dev.1627887176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2732466471 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 6104068750 ps |
| CPU time | 724.56 seconds |
| Started | Aug 25 03:42:18 PM UTC 24 |
| Finished | Aug 25 03:54:33 PM UTC 24 |
| Peak memory | 620220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732466471 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2732466471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3474484554 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3850951912 ps |
| CPU time | 328.67 seconds |
| Started | Aug 25 05:56:54 PM UTC 24 |
| Finished | Aug 25 06:02:29 PM UTC 24 |
| Peak memory | 666420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474484 554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 3.chip_ padctrl_attributes.3474484554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1064723834 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5708869880 ps |
| CPU time | 1015.36 seconds |
| Started | Aug 25 11:01:24 PM UTC 24 |
| Finished | Aug 25 11:18:38 PM UTC 24 |
| Peak memory | 674596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064723834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1064723834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1868409977 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5717262850 ps |
| CPU time | 923.46 seconds |
| Started | Aug 25 06:11:06 PM UTC 24 |
| Finished | Aug 25 06:26:46 PM UTC 24 |
| Peak memory | 625904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1868409977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1868409977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.3691160852 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2813493636 ps |
| CPU time | 206.07 seconds |
| Started | Aug 25 04:08:16 PM UTC 24 |
| Finished | Aug 25 04:11:46 PM UTC 24 |
| Peak memory | 624324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691160852 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3691160852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.67894987 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 58082244749 ps |
| CPU time | 1551.07 seconds |
| Started | Aug 25 03:37:20 PM UTC 24 |
| Finished | Aug 25 04:03:35 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67894987 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.67894987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1570208678 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 10210274437 ps |
| CPU time | 914.61 seconds |
| Started | Aug 25 04:27:12 PM UTC 24 |
| Finished | Aug 25 04:42:40 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570208678 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.1570208678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2963631378 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 4495520421 ps |
| CPU time | 734.8 seconds |
| Started | Aug 25 06:07:24 PM UTC 24 |
| Finished | Aug 25 06:19:52 PM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963631378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2963631378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.3533819459 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5089237640 ps |
| CPU time | 1062.39 seconds |
| Started | Aug 25 10:07:36 PM UTC 24 |
| Finished | Aug 25 10:25:40 PM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3533819459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_plic_all_irqs_20.3533819459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_plic_all_irqs_20/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2212971006 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 219433478 ps |
| CPU time | 85.76 seconds |
| Started | Aug 25 04:14:51 PM UTC 24 |
| Finished | Aug 25 04:16:19 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212971006 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2212971006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1478398101 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 8296767934 ps |
| CPU time | 910.46 seconds |
| Started | Aug 25 04:57:59 PM UTC 24 |
| Finished | Aug 25 05:13:24 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478398101 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_rand_reset.1478398101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.140703080 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4069314240 ps |
| CPU time | 694 seconds |
| Started | Aug 25 06:09:21 PM UTC 24 |
| Finished | Aug 25 06:21:08 PM UTC 24 |
| Peak memory | 640220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140703080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.140703080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.864605862 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2540873777 ps |
| CPU time | 355.8 seconds |
| Started | Aug 25 07:43:00 PM UTC 24 |
| Finished | Aug 25 07:49:03 PM UTC 24 |
| Peak memory | 639908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=864605862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.864605862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1914460928 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3754816984 ps |
| CPU time | 726.31 seconds |
| Started | Aug 25 09:16:58 PM UTC 24 |
| Finished | Aug 25 09:29:18 PM UTC 24 |
| Peak memory | 625852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1914460928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_gpio.1914460928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2022158466 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4964457914 ps |
| CPU time | 637.87 seconds |
| Started | Aug 25 06:40:07 PM UTC 24 |
| Finished | Aug 25 06:50:58 PM UTC 24 |
| Peak memory | 640168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022158466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2022158466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3359033107 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1512556013 ps |
| CPU time | 242.79 seconds |
| Started | Aug 25 04:37:49 PM UTC 24 |
| Finished | Aug 25 04:41:57 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359033107 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3359033107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1373134574 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4353997360 ps |
| CPU time | 801.22 seconds |
| Started | Aug 25 08:41:05 PM UTC 24 |
| Finished | Aug 25 08:54:42 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1373134574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_plic_all_irqs_10.1373134574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.2269524659 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5246791764 ps |
| CPU time | 927.38 seconds |
| Started | Aug 25 06:08:34 PM UTC 24 |
| Finished | Aug 25 06:24:20 PM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269524659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2269524659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.chip_tl_errors.4109289370 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3922796515 ps |
| CPU time | 388.6 seconds |
| Started | Aug 25 04:16:51 PM UTC 24 |
| Finished | Aug 25 04:23:25 PM UTC 24 |
| Peak memory | 624340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109289370 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.4109289370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_zero_delays.1862368895 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 314130884 ps |
| CPU time | 34.54 seconds |
| Started | Aug 25 04:25:58 PM UTC 24 |
| Finished | Aug 25 04:26:34 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862368895 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.1862368895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3296280420 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4196406292 ps |
| CPU time | 550.58 seconds |
| Started | Aug 25 06:21:14 PM UTC 24 |
| Finished | Aug 25 06:30:35 PM UTC 24 |
| Peak memory | 672428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296280420 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_s leep_mode_alerts.3296280420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.1579497943 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 50553403473 ps |
| CPU time | 10503 seconds |
| Started | Aug 25 06:09:09 PM UTC 24 |
| Finished | Aug 25 09:07:20 PM UTC 24 |
| Peak memory | 641320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579497943 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prod.1579497943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1708356620 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8128562790 ps |
| CPU time | 2173.04 seconds |
| Started | Aug 25 06:12:19 PM UTC 24 |
| Finished | Aug 25 06:49:13 PM UTC 24 |
| Peak memory | 625888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708356620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1708356620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.2383259477 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8555277272 ps |
| CPU time | 1974.64 seconds |
| Started | Aug 25 06:25:57 PM UTC 24 |
| Finished | Aug 25 06:59:27 PM UTC 24 |
| Peak memory | 624088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383259477 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2383259477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2903159733 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 79531365592 ps |
| CPU time | 21246.2 seconds |
| Started | Aug 25 07:20:58 PM UTC 24 |
| Finished | Aug 26 01:20:41 AM UTC 24 |
| Peak memory | 657752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903159733 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2903159733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1515417129 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 759499718 ps |
| CPU time | 473.66 seconds |
| Started | Aug 25 04:12:11 PM UTC 24 |
| Finished | Aug 25 04:20:12 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515417129 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.1515417129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3882457285 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 153275936 ps |
| CPU time | 42.08 seconds |
| Started | Aug 25 04:25:32 PM UTC 24 |
| Finished | Aug 25 04:26:16 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882457285 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.3882457285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1158574834 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 489657457 ps |
| CPU time | 283 seconds |
| Started | Aug 25 04:45:44 PM UTC 24 |
| Finished | Aug 25 04:50:32 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158574834 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.1158574834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3259155525 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 5730622960 ps |
| CPU time | 1014.52 seconds |
| Started | Aug 25 10:58:36 PM UTC 24 |
| Finished | Aug 25 11:15:51 PM UTC 24 |
| Peak memory | 674356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259155525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3259155525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817550248 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3595833904 ps |
| CPU time | 566.54 seconds |
| Started | Aug 25 10:58:33 PM UTC 24 |
| Finished | Aug 25 11:08:11 PM UTC 24 |
| Peak memory | 672356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817550248 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2817550248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.3485665778 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5662459600 ps |
| CPU time | 736.11 seconds |
| Started | Aug 25 10:58:55 PM UTC 24 |
| Finished | Aug 25 11:11:26 PM UTC 24 |
| Peak memory | 674276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485665778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.3485665778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2878909623 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3555442224 ps |
| CPU time | 460.21 seconds |
| Started | Aug 25 10:59:53 PM UTC 24 |
| Finished | Aug 25 11:07:43 PM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878909623 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2878909623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2387221204 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 6012516330 ps |
| CPU time | 909.46 seconds |
| Started | Aug 25 10:58:49 PM UTC 24 |
| Finished | Aug 25 11:14:16 PM UTC 24 |
| Peak memory | 674516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387221204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2387221204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3543433150 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4189748600 ps |
| CPU time | 604.44 seconds |
| Started | Aug 25 11:05:20 PM UTC 24 |
| Finished | Aug 25 11:15:38 PM UTC 24 |
| Peak memory | 670332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543433150 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3543433150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861397001 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3924186688 ps |
| CPU time | 534.39 seconds |
| Started | Aug 25 11:05:34 PM UTC 24 |
| Finished | Aug 25 11:14:40 PM UTC 24 |
| Peak memory | 672436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861397001 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3861397001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.485558888 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3932628056 ps |
| CPU time | 537.64 seconds |
| Started | Aug 25 11:07:51 PM UTC 24 |
| Finished | Aug 25 11:17:00 PM UTC 24 |
| Peak memory | 672244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485558888 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_alert_handler_lpg_s leep_mode_alerts.485558888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1768942556 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4702507680 ps |
| CPU time | 807.95 seconds |
| Started | Aug 25 11:06:16 PM UTC 24 |
| Finished | Aug 25 11:20:00 PM UTC 24 |
| Peak memory | 674356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768942556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1768942556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3470632001 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4144265980 ps |
| CPU time | 542.42 seconds |
| Started | Aug 25 11:09:47 PM UTC 24 |
| Finished | Aug 25 11:19:01 PM UTC 24 |
| Peak memory | 672448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470632001 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3470632001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.3823438001 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5244037936 ps |
| CPU time | 1112.86 seconds |
| Started | Aug 25 11:09:53 PM UTC 24 |
| Finished | Aug 25 11:28:48 PM UTC 24 |
| Peak memory | 674540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823438001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3823438001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442447163 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3772442306 ps |
| CPU time | 569.01 seconds |
| Started | Aug 25 11:09:55 PM UTC 24 |
| Finished | Aug 25 11:19:36 PM UTC 24 |
| Peak memory | 672224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442447163 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1442447163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3147105730 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3581530740 ps |
| CPU time | 536.91 seconds |
| Started | Aug 25 11:10:57 PM UTC 24 |
| Finished | Aug 25 11:20:05 PM UTC 24 |
| Peak memory | 672548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147105730 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3147105730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.553037892 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3562226758 ps |
| CPU time | 476.6 seconds |
| Started | Aug 25 09:46:49 PM UTC 24 |
| Finished | Aug 25 09:54:56 PM UTC 24 |
| Peak memory | 672248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553037892 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sl eep_mode_alerts.553037892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.778783503 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3710819650 ps |
| CPU time | 512.06 seconds |
| Started | Aug 25 11:11:32 PM UTC 24 |
| Finished | Aug 25 11:20:15 PM UTC 24 |
| Peak memory | 672248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778783503 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_alert_handler_lpg_s leep_mode_alerts.778783503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.2339261289 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5740938472 ps |
| CPU time | 969.21 seconds |
| Started | Aug 25 11:10:59 PM UTC 24 |
| Finished | Aug 25 11:27:26 PM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339261289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2339261289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220368348 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3151770232 ps |
| CPU time | 502.16 seconds |
| Started | Aug 25 11:12:32 PM UTC 24 |
| Finished | Aug 25 11:21:04 PM UTC 24 |
| Peak memory | 672456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220368348 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1220368348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.2925107347 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4880035320 ps |
| CPU time | 650.08 seconds |
| Started | Aug 25 11:12:34 PM UTC 24 |
| Finished | Aug 25 11:23:37 PM UTC 24 |
| Peak memory | 674412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925107347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2925107347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515446342 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3215351476 ps |
| CPU time | 587.25 seconds |
| Started | Aug 25 11:15:23 PM UTC 24 |
| Finished | Aug 25 11:25:22 PM UTC 24 |
| Peak memory | 672316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515446342 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2515446342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1441856598 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4801217816 ps |
| CPU time | 938.86 seconds |
| Started | Aug 25 11:15:25 PM UTC 24 |
| Finished | Aug 25 11:31:22 PM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441856598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1441856598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.602533671 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4086631768 ps |
| CPU time | 557.83 seconds |
| Started | Aug 25 11:18:10 PM UTC 24 |
| Finished | Aug 25 11:27:41 PM UTC 24 |
| Peak memory | 672408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602533671 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_alert_handler_lpg_s leep_mode_alerts.602533671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2491456047 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4365502800 ps |
| CPU time | 540.52 seconds |
| Started | Aug 25 11:15:39 PM UTC 24 |
| Finished | Aug 25 11:24:52 PM UTC 24 |
| Peak memory | 672616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491456047 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2491456047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952168601 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3513897184 ps |
| CPU time | 575.47 seconds |
| Started | Aug 25 11:17:58 PM UTC 24 |
| Finished | Aug 25 11:27:46 PM UTC 24 |
| Peak memory | 672416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952168601 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1952168601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552573360 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3943019104 ps |
| CPU time | 591.55 seconds |
| Started | Aug 25 11:17:53 PM UTC 24 |
| Finished | Aug 25 11:27:56 PM UTC 24 |
| Peak memory | 672296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552573360 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3552573360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2234106586 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4383049960 ps |
| CPU time | 821.33 seconds |
| Started | Aug 25 11:17:11 PM UTC 24 |
| Finished | Aug 25 11:31:09 PM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234106586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2234106586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.303486180 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4488866374 ps |
| CPU time | 836.38 seconds |
| Started | Aug 25 11:17:49 PM UTC 24 |
| Finished | Aug 25 11:32:02 PM UTC 24 |
| Peak memory | 674472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303486180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.303486180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749846188 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4302815720 ps |
| CPU time | 507.68 seconds |
| Started | Aug 25 10:39:39 PM UTC 24 |
| Finished | Aug 25 10:48:18 PM UTC 24 |
| Peak memory | 672504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749846188 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_alert_handler_lpg_s leep_mode_alerts.3749846188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2875264550 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 6436642060 ps |
| CPU time | 878.47 seconds |
| Started | Aug 25 11:18:08 PM UTC 24 |
| Finished | Aug 25 11:33:04 PM UTC 24 |
| Peak memory | 674572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875264550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2875264550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1847078150 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5678637196 ps |
| CPU time | 1003.9 seconds |
| Started | Aug 25 11:18:14 PM UTC 24 |
| Finished | Aug 25 11:35:17 PM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847078150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1847078150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3240537266 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5102286760 ps |
| CPU time | 718.62 seconds |
| Started | Aug 25 11:21:54 PM UTC 24 |
| Finished | Aug 25 11:34:06 PM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240537266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3240537266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.838795238 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3482762434 ps |
| CPU time | 521.03 seconds |
| Started | Aug 25 11:22:11 PM UTC 24 |
| Finished | Aug 25 11:31:02 PM UTC 24 |
| Peak memory | 672244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838795238 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_alert_handler_lpg_s leep_mode_alerts.838795238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3570792812 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4915916052 ps |
| CPU time | 972.22 seconds |
| Started | Aug 25 11:21:38 PM UTC 24 |
| Finished | Aug 25 11:38:09 PM UTC 24 |
| Peak memory | 674416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570792812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3570792812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1999841611 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5972803412 ps |
| CPU time | 1001.47 seconds |
| Started | Aug 25 11:22:11 PM UTC 24 |
| Finished | Aug 25 11:39:11 PM UTC 24 |
| Peak memory | 674344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999841611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1999841611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.658892711 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4648531080 ps |
| CPU time | 1026.4 seconds |
| Started | Aug 25 11:22:34 PM UTC 24 |
| Finished | Aug 25 11:40:00 PM UTC 24 |
| Peak memory | 674512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658892711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.658892711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.169897020 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3478373912 ps |
| CPU time | 552.96 seconds |
| Started | Aug 25 11:23:56 PM UTC 24 |
| Finished | Aug 25 11:33:21 PM UTC 24 |
| Peak memory | 672244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169897020 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_alert_handler_lpg_s leep_mode_alerts.169897020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.86308732 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3812348566 ps |
| CPU time | 614.98 seconds |
| Started | Aug 25 11:26:00 PM UTC 24 |
| Finished | Aug 25 11:36:26 PM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86308732 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_alert_handler_lpg_sl eep_mode_alerts.86308732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1969341565 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5465992496 ps |
| CPU time | 1113.16 seconds |
| Started | Aug 25 11:26:02 PM UTC 24 |
| Finished | Aug 25 11:44:55 PM UTC 24 |
| Peak memory | 674428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969341565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1969341565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.264953805 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 5195399764 ps |
| CPU time | 748.45 seconds |
| Started | Aug 25 11:26:01 PM UTC 24 |
| Finished | Aug 25 11:38:43 PM UTC 24 |
| Peak memory | 674376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264953805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.264953805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505244396 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3228194350 ps |
| CPU time | 434.71 seconds |
| Started | Aug 25 11:28:03 PM UTC 24 |
| Finished | Aug 25 11:35:27 PM UTC 24 |
| Peak memory | 672416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505244396 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3505244396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4237573634 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3653656972 ps |
| CPU time | 442.46 seconds |
| Started | Aug 25 11:30:22 PM UTC 24 |
| Finished | Aug 25 11:37:53 PM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237573634 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4237573634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1489762856 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4790597464 ps |
| CPU time | 973.66 seconds |
| Started | Aug 25 11:28:04 PM UTC 24 |
| Finished | Aug 25 11:44:35 PM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489762856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1489762856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.805634733 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4154397984 ps |
| CPU time | 693.92 seconds |
| Started | Aug 25 11:29:57 PM UTC 24 |
| Finished | Aug 25 11:41:43 PM UTC 24 |
| Peak memory | 674364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805634733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.805634733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1730685221 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5106928152 ps |
| CPU time | 719.52 seconds |
| Started | Aug 25 11:31:48 PM UTC 24 |
| Finished | Aug 25 11:44:01 PM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730685221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1730685221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177597408 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3501517124 ps |
| CPU time | 464.24 seconds |
| Started | Aug 25 10:50:56 PM UTC 24 |
| Finished | Aug 25 10:58:48 PM UTC 24 |
| Peak memory | 672400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177597408 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_alert_handler_lpg_s leep_mode_alerts.4177597408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3636429156 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4993070052 ps |
| CPU time | 811.63 seconds |
| Started | Aug 25 11:31:42 PM UTC 24 |
| Finished | Aug 25 11:45:29 PM UTC 24 |
| Peak memory | 674468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636429156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3636429156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.158426493 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 5998851634 ps |
| CPU time | 961.61 seconds |
| Started | Aug 25 11:35:22 PM UTC 24 |
| Finished | Aug 25 11:51:41 PM UTC 24 |
| Peak memory | 674400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158426493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.158426493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.833876928 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3980823790 ps |
| CPU time | 670.29 seconds |
| Started | Aug 25 11:37:07 PM UTC 24 |
| Finished | Aug 25 11:48:31 PM UTC 24 |
| Peak memory | 674436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833876928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.833876928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3228609772 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4315451928 ps |
| CPU time | 802.02 seconds |
| Started | Aug 25 11:38:01 PM UTC 24 |
| Finished | Aug 25 11:51:37 PM UTC 24 |
| Peak memory | 674360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228609772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3228609772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.988510125 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4576443820 ps |
| CPU time | 697.9 seconds |
| Started | Aug 25 11:37:04 PM UTC 24 |
| Finished | Aug 25 11:48:55 PM UTC 24 |
| Peak memory | 672452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988510125 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_alert_handler_lpg_s leep_mode_alerts.988510125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1781640931 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4233833358 ps |
| CPU time | 543.84 seconds |
| Started | Aug 25 11:39:05 PM UTC 24 |
| Finished | Aug 25 11:48:20 PM UTC 24 |
| Peak memory | 672336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781640931 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1781640931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.506908852 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3600055032 ps |
| CPU time | 598.9 seconds |
| Started | Aug 25 11:40:33 PM UTC 24 |
| Finished | Aug 25 11:50:43 PM UTC 24 |
| Peak memory | 672504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506908852 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_alert_handler_lpg_s leep_mode_alerts.506908852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939899207 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4536481870 ps |
| CPU time | 540.85 seconds |
| Started | Aug 25 11:40:56 PM UTC 24 |
| Finished | Aug 25 11:50:07 PM UTC 24 |
| Peak memory | 672296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939899207 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1939899207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2656781491 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5600195950 ps |
| CPU time | 766.57 seconds |
| Started | Aug 25 11:41:38 PM UTC 24 |
| Finished | Aug 25 11:54:38 PM UTC 24 |
| Peak memory | 674484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656781491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2656781491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.2126985428 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 6127877848 ps |
| CPU time | 682.37 seconds |
| Started | Aug 25 11:42:38 PM UTC 24 |
| Finished | Aug 25 11:54:12 PM UTC 24 |
| Peak memory | 674348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126985428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2126985428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1659234984 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5295692514 ps |
| CPU time | 699.97 seconds |
| Started | Aug 25 11:49:09 PM UTC 24 |
| Finished | Aug 26 12:00:59 AM UTC 24 |
| Peak memory | 674624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659234984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1659234984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085875698 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3530092928 ps |
| CPU time | 428.32 seconds |
| Started | Aug 25 11:49:56 PM UTC 24 |
| Finished | Aug 25 11:57:11 PM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085875698 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3085875698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000813573 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4006458170 ps |
| CPU time | 588.6 seconds |
| Started | Aug 25 10:57:09 PM UTC 24 |
| Finished | Aug 25 11:07:09 PM UTC 24 |
| Peak memory | 672456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000813573 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_alert_handler_lpg_s leep_mode_alerts.4000813573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.2049120742 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4973657404 ps |
| CPU time | 716.26 seconds |
| Started | Aug 25 11:51:28 PM UTC 24 |
| Finished | Aug 26 12:03:35 AM UTC 24 |
| Peak memory | 674520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049120742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2049120742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.424203288 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3883090324 ps |
| CPU time | 496.07 seconds |
| Started | Aug 25 11:51:29 PM UTC 24 |
| Finished | Aug 25 11:59:52 PM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424203288 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_alert_handler_lpg_s leep_mode_alerts.424203288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3796551557 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3948438088 ps |
| CPU time | 436 seconds |
| Started | Aug 25 11:55:05 PM UTC 24 |
| Finished | Aug 26 12:02:27 AM UTC 24 |
| Peak memory | 672384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796551557 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3796551557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4126574280 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4394619660 ps |
| CPU time | 502.1 seconds |
| Started | Aug 25 11:54:19 PM UTC 24 |
| Finished | Aug 26 12:02:49 AM UTC 24 |
| Peak memory | 672376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126574280 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4126574280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3052847631 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 6682657130 ps |
| CPU time | 707.06 seconds |
| Started | Aug 25 11:54:34 PM UTC 24 |
| Finished | Aug 26 12:06:31 AM UTC 24 |
| Peak memory | 674624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052847631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3052847631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.549506101 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7101720490 ps |
| CPU time | 615.83 seconds |
| Started | Aug 25 09:11:31 PM UTC 24 |
| Finished | Aug 25 09:21:59 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_i mages=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549506101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.549506101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.994887572 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4792879600 ps |
| CPU time | 949.34 seconds |
| Started | Aug 25 06:11:27 PM UTC 24 |
| Finished | Aug 25 06:27:35 PM UTC 24 |
| Peak memory | 623852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=994887572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.994887572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2285845688 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4385444328 ps |
| CPU time | 681.58 seconds |
| Started | Aug 25 06:37:14 PM UTC 24 |
| Finished | Aug 25 06:48:50 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2285845688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_pwrmgr_lowpower_cancel.2285845688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3119433771 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5093705336 ps |
| CPU time | 542.76 seconds |
| Started | Aug 25 06:39:00 PM UTC 24 |
| Finished | Aug 25 06:48:15 PM UTC 24 |
| Peak memory | 626028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119433771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3119433771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.2537164599 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5643496012 ps |
| CPU time | 851.71 seconds |
| Started | Aug 25 07:16:08 PM UTC 24 |
| Finished | Aug 25 07:30:37 PM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537164599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2537164599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1621207069 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6698167952 ps |
| CPU time | 1494.32 seconds |
| Started | Aug 25 06:32:35 PM UTC 24 |
| Finished | Aug 25 06:57:56 PM UTC 24 |
| Peak memory | 632020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621207069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key _derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1621207069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3368180908 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 8052154255 ps |
| CPU time | 667.54 seconds |
| Started | Aug 25 06:09:43 PM UTC 24 |
| Finished | Aug 25 06:21:02 PM UTC 24 |
| Peak memory | 625960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3368180908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_pwrmgr_full_aon_reset.3368180908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2051592766 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 20413316177 ps |
| CPU time | 4125.73 seconds |
| Started | Aug 25 06:17:01 PM UTC 24 |
| Finished | Aug 25 07:26:58 PM UTC 24 |
| Peak memory | 628848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2051592766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2051592766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_dev.783324572 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 6242741128 ps |
| CPU time | 875.69 seconds |
| Started | Aug 25 08:49:32 PM UTC 24 |
| Finished | Aug 25 09:04:25 PM UTC 24 |
| Peak memory | 650668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783324572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.783324572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.4236121255 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 36984587820 ps |
| CPU time | 1050.2 seconds |
| Started | Aug 25 03:28:58 PM UTC 24 |
| Finished | Aug 25 03:46:44 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236121255 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4236121255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.952070698 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 373744506 ps |
| CPU time | 168.33 seconds |
| Started | Aug 25 03:51:59 PM UTC 24 |
| Finished | Aug 25 03:54:50 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952070698 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.952070698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.639982526 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5663063458 ps |
| CPU time | 1228.66 seconds |
| Started | Aug 25 06:07:25 PM UTC 24 |
| Finished | Aug 25 06:28:16 PM UTC 24 |
| Peak memory | 623648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=639982526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.639982526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio.56236926 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3895606992 ps |
| CPU time | 526.72 seconds |
| Started | Aug 25 07:33:19 PM UTC 24 |
| Finished | Aug 25 07:42:17 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=56236926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_gpio.56236926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3720961999 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 13486178547 ps |
| CPU time | 680.41 seconds |
| Started | Aug 25 03:28:45 PM UTC 24 |
| Finished | Aug 25 03:40:15 PM UTC 24 |
| Peak memory | 609588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3720961999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. chip_rv_dm_lc_disabled.3720961999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2352623081 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 17926180238 ps |
| CPU time | 545.39 seconds |
| Started | Aug 25 06:16:46 PM UTC 24 |
| Finished | Aug 25 06:26:02 PM UTC 24 |
| Peak memory | 636088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352623081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2352623081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1853133240 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5565130140 ps |
| CPU time | 447.53 seconds |
| Started | Aug 25 06:11:28 PM UTC 24 |
| Finished | Aug 25 06:19:04 PM UTC 24 |
| Peak memory | 632108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853133240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1853133240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1317879527 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1907929599 ps |
| CPU time | 160.39 seconds |
| Started | Aug 25 09:24:44 PM UTC 24 |
| Finished | Aug 25 09:27:28 PM UTC 24 |
| Peak memory | 639460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_ access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1317879527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1317879527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_host_tx_rx.94825479 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2564391916 ps |
| CPU time | 324.33 seconds |
| Started | Aug 25 09:16:53 PM UTC 24 |
| Finished | Aug 25 09:22:24 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94825479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_spi_host_tx_rx.94825479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2208003493 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5287104644 ps |
| CPU time | 1123.95 seconds |
| Started | Aug 25 06:21:13 PM UTC 24 |
| Finished | Aug 25 06:40:19 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208003493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2208003493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.334749513 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 145327786429 ps |
| CPU time | 25789.8 seconds |
| Started | Aug 25 06:52:52 PM UTC 24 |
| Finished | Aug 26 02:09:19 AM UTC 24 |
| Peak memory | 627016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334749513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.334749513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1902690405 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4733519320 ps |
| CPU time | 554.1 seconds |
| Started | Aug 25 06:37:06 PM UTC 24 |
| Finished | Aug 25 06:46:32 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902690405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1902690405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.3293780290 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 46340134551 ps |
| CPU time | 8366.22 seconds |
| Started | Aug 25 06:11:29 PM UTC 24 |
| Finished | Aug 25 08:33:24 PM UTC 24 |
| Peak memory | 643364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293780290 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_rma.3293780290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3599103954 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 3571245408 ps |
| CPU time | 445.2 seconds |
| Started | Aug 25 03:28:53 PM UTC 24 |
| Finished | Aug 25 03:36:26 PM UTC 24 |
| Peak memory | 624324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599103954 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3599103954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2496609824 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 225619436 ps |
| CPU time | 27.8 seconds |
| Started | Aug 25 04:00:15 PM UTC 24 |
| Finished | Aug 25 04:00:44 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496609824 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2496609824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1558741589 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 4442551668 ps |
| CPU time | 496.63 seconds |
| Started | Aug 25 04:10:33 PM UTC 24 |
| Finished | Aug 25 04:18:58 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558741589 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1558741589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1853152886 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 11658982064 ps |
| CPU time | 692.36 seconds |
| Started | Aug 25 04:30:34 PM UTC 24 |
| Finished | Aug 25 04:42:17 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853152886 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1853152886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.261702130 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 228900925 ps |
| CPU time | 134.62 seconds |
| Started | Aug 25 05:20:04 PM UTC 24 |
| Finished | Aug 25 05:22:22 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261702130 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_reset_error.261702130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1353532847 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3834351149 ps |
| CPU time | 406.04 seconds |
| Started | Aug 25 05:35:14 PM UTC 24 |
| Finished | Aug 25 05:42:07 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353532847 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1353532847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3570848826 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3300502970 ps |
| CPU time | 640.04 seconds |
| Started | Aug 25 05:47:52 PM UTC 24 |
| Finished | Aug 25 05:58:44 PM UTC 24 |
| Peak memory | 599352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570848826 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_reset_error.3570848826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.256660769 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3405990098 ps |
| CPU time | 382.62 seconds |
| Started | Aug 25 06:10:57 PM UTC 24 |
| Finished | Aug 25 06:17:27 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=256660769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_flash_ctrl_idle_low_power.256660769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.1165892197 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2857906320 ps |
| CPU time | 390.02 seconds |
| Started | Aug 25 06:25:55 PM UTC 24 |
| Finished | Aug 25 06:32:32 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=1165892197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_enc.1165892197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.3841603586 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5369654878 ps |
| CPU time | 527.54 seconds |
| Started | Aug 25 06:02:42 PM UTC 24 |
| Finished | Aug 25 06:11:37 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3841603586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_i2c_host_tx_rx.3841603586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.524319522 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5570044920 ps |
| CPU time | 1056.01 seconds |
| Started | Aug 25 06:19:25 PM UTC 24 |
| Finished | Aug 25 06:37:21 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524319522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.524319522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_csr_rw.2813181073 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 9576572445 ps |
| CPU time | 1423.45 seconds |
| Started | Aug 25 08:44:26 PM UTC 24 |
| Finished | Aug 25 09:08:37 PM UTC 24 |
| Peak memory | 623312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281318 1073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_csr_rw.2813181073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1710519173 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5134519255 ps |
| CPU time | 828.6 seconds |
| Started | Aug 25 08:52:51 PM UTC 24 |
| Finished | Aug 25 09:06:56 PM UTC 24 |
| Peak memory | 623808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710519173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1710519173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.4041080724 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4432156828 ps |
| CPU time | 593.05 seconds |
| Started | Aug 25 06:40:16 PM UTC 24 |
| Finished | Aug 25 06:50:21 PM UTC 24 |
| Peak memory | 640628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041080724 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.4041080724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.2992334759 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3194466988 ps |
| CPU time | 627.06 seconds |
| Started | Aug 25 06:22:03 PM UTC 24 |
| Finished | Aug 25 06:32:41 PM UTC 24 |
| Peak memory | 626016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992334759 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_boot_mode.2992334759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4272621655 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 6523727266 ps |
| CPU time | 1300.92 seconds |
| Started | Aug 25 06:32:52 PM UTC 24 |
| Finished | Aug 25 06:54:58 PM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272621655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.4272621655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.2334382166 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 14451762682 ps |
| CPU time | 6069.61 seconds |
| Started | Aug 25 06:32:29 PM UTC 24 |
| Finished | Aug 25 08:15:26 PM UTC 24 |
| Peak memory | 629032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334382166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2334382166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3377310767 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 17044256440 ps |
| CPU time | 5826.25 seconds |
| Started | Aug 25 06:17:31 PM UTC 24 |
| Finished | Aug 25 07:56:17 PM UTC 24 |
| Peak memory | 626868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377310767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3377310767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2478684558 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 24482500094 ps |
| CPU time | 9711.4 seconds |
| Started | Aug 25 07:05:28 PM UTC 24 |
| Finished | Aug 25 09:50:21 PM UTC 24 |
| Peak memory | 626996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478684558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2478684558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2516279919 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 37336914910 ps |
| CPU time | 9222.14 seconds |
| Started | Aug 25 03:28:43 PM UTC 24 |
| Finished | Aug 25 06:04:34 PM UTC 24 |
| Peak memory | 616828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2516279919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_ csr_aliasing.2516279919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.635083521 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 8816192268 ps |
| CPU time | 1157.07 seconds |
| Started | Aug 25 03:28:44 PM UTC 24 |
| Finished | Aug 25 03:48:18 PM UTC 24 |
| Peak memory | 620288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=635083521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.chip_csr_bit_bash.635083521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.2090008555 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4834846203 ps |
| CPU time | 668.23 seconds |
| Started | Aug 25 03:28:51 PM UTC 24 |
| Finished | Aug 25 03:40:10 PM UTC 24 |
| Peak memory | 615992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090008555 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2090008555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1519311161 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 8288060370 ps |
| CPU time | 583.1 seconds |
| Started | Aug 25 03:28:45 PM UTC 24 |
| Finished | Aug 25 03:38:37 PM UTC 24 |
| Peak memory | 609788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519311161 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1519311161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.656242506 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 30585925888 ps |
| CPU time | 6557.47 seconds |
| Started | Aug 25 03:28:42 PM UTC 24 |
| Finished | Aug 25 05:19:34 PM UTC 24 |
| Peak memory | 615036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=656242506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.chip_same_csr_outstanding.656242506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1763178832 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 49202298396 ps |
| CPU time | 1088.34 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:47:11 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763178832 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.1763178832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1999541375 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 152788737 ps |
| CPU time | 28.6 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:29:18 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999541375 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1999541375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1624014052 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 224558112 ps |
| CPU time | 30.08 seconds |
| Started | Aug 25 03:28:46 PM UTC 24 |
| Finished | Aug 25 03:29:17 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624014052 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1624014052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3006557153 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 104164960719 ps |
| CPU time | 1608.32 seconds |
| Started | Aug 25 03:28:47 PM UTC 24 |
| Finished | Aug 25 03:55:58 PM UTC 24 |
| Peak memory | 599340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006557153 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3006557153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.4292867460 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 44424078224 ps |
| CPU time | 1060.82 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:46:44 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292867460 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4292867460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3209580632 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 34912430 ps |
| CPU time | 9.6 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:28:59 PM UTC 24 |
| Peak memory | 597264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209580632 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3209580632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.824026249 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 902040987 ps |
| CPU time | 43.96 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:29:33 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824026249 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.824026249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2464264374 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3961858610 ps |
| CPU time | 100.25 seconds |
| Started | Aug 25 03:28:45 PM UTC 24 |
| Finished | Aug 25 03:30:28 PM UTC 24 |
| Peak memory | 597076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464264374 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2464264374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1871825366 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 289948021 ps |
| CPU time | 18.63 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:29:08 PM UTC 24 |
| Peak memory | 597156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871825366 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1871825366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3563813224 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1242237962 ps |
| CPU time | 75.31 seconds |
| Started | Aug 25 03:28:48 PM UTC 24 |
| Finished | Aug 25 03:30:06 PM UTC 24 |
| Peak memory | 598740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563813224 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3563813224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2838636221 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 39498862484 ps |
| CPU time | 9587.93 seconds |
| Started | Aug 25 03:28:51 PM UTC 24 |
| Finished | Aug 25 06:10:50 PM UTC 24 |
| Peak memory | 621372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2838636221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_ csr_aliasing.2838636221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1460275147 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 11294315052 ps |
| CPU time | 1577.49 seconds |
| Started | Aug 25 03:28:52 PM UTC 24 |
| Finished | Aug 25 03:55:31 PM UTC 24 |
| Peak memory | 620156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1460275147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.chip_csr_bit_bash.1460275147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.243201755 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 7235835983 ps |
| CPU time | 543.18 seconds |
| Started | Aug 25 03:29:33 PM UTC 24 |
| Finished | Aug 25 03:38:44 PM UTC 24 |
| Peak memory | 683724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243201755 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_reset.243201755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3067282904 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 8005729778 ps |
| CPU time | 904.32 seconds |
| Started | Aug 25 03:29:39 PM UTC 24 |
| Finished | Aug 25 03:44:57 PM UTC 24 |
| Peak memory | 659392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3067282904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.chip_csr_mem_rw_with_rand_reset.3067282904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2474446063 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 15405591080 ps |
| CPU time | 835.29 seconds |
| Started | Aug 25 03:28:54 PM UTC 24 |
| Finished | Aug 25 03:43:01 PM UTC 24 |
| Peak memory | 611756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474446063 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2474446063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2863525062 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 8731060926 ps |
| CPU time | 412.26 seconds |
| Started | Aug 25 03:28:55 PM UTC 24 |
| Finished | Aug 25 03:35:53 PM UTC 24 |
| Peak memory | 609588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2863525062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. chip_rv_dm_lc_disabled.2863525062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1843231770 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 28348924715 ps |
| CPU time | 4975.38 seconds |
| Started | Aug 25 03:28:52 PM UTC 24 |
| Finished | Aug 25 04:52:54 PM UTC 24 |
| Peak memory | 614908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1843231770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.chip_same_csr_outstanding.1843231770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3542201430 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1153178333 ps |
| CPU time | 66.05 seconds |
| Started | Aug 25 03:28:57 PM UTC 24 |
| Finished | Aug 25 03:30:05 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542201430 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.3542201430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2326110618 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 444595436 ps |
| CPU time | 24.95 seconds |
| Started | Aug 25 03:29:17 PM UTC 24 |
| Finished | Aug 25 03:29:43 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326110618 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2326110618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2389129571 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 35672358 ps |
| CPU time | 8.03 seconds |
| Started | Aug 25 03:29:05 PM UTC 24 |
| Finished | Aug 25 03:29:14 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389129571 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2389129571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1665143817 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 48266806976 ps |
| CPU time | 842.14 seconds |
| Started | Aug 25 03:28:56 PM UTC 24 |
| Finished | Aug 25 03:43:09 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665143817 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1665143817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.823957212 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1723891428 ps |
| CPU time | 82.56 seconds |
| Started | Aug 25 03:28:58 PM UTC 24 |
| Finished | Aug 25 03:30:22 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823957212 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.823957212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.311692545 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 181633395 ps |
| CPU time | 12.61 seconds |
| Started | Aug 25 03:28:55 PM UTC 24 |
| Finished | Aug 25 03:29:09 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311692545 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.311692545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3840993895 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 7084575198 ps |
| CPU time | 110 seconds |
| Started | Aug 25 03:28:56 PM UTC 24 |
| Finished | Aug 25 03:30:48 PM UTC 24 |
| Peak memory | 597320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840993895 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3840993895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.334607254 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3951932728 ps |
| CPU time | 94.07 seconds |
| Started | Aug 25 03:28:54 PM UTC 24 |
| Finished | Aug 25 03:30:31 PM UTC 24 |
| Peak memory | 597068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334607254 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.334607254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.907961834 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 47095586 ps |
| CPU time | 6.98 seconds |
| Started | Aug 25 03:28:56 PM UTC 24 |
| Finished | Aug 25 03:29:04 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907961834 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.907961834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3197136042 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2839915597 ps |
| CPU time | 176.22 seconds |
| Started | Aug 25 03:29:20 PM UTC 24 |
| Finished | Aug 25 03:32:19 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197136042 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3197136042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1761562541 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2030237762 ps |
| CPU time | 130.53 seconds |
| Started | Aug 25 03:29:23 PM UTC 24 |
| Finished | Aug 25 03:31:37 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761562541 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1761562541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3722452829 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 185202487 ps |
| CPU time | 146.9 seconds |
| Started | Aug 25 03:29:22 PM UTC 24 |
| Finished | Aug 25 03:31:51 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722452829 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.3722452829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.235201969 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 121446448 ps |
| CPU time | 23.19 seconds |
| Started | Aug 25 03:29:29 PM UTC 24 |
| Finished | Aug 25 03:29:53 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235201969 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.235201969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3800613265 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 11507995046 ps |
| CPU time | 1265.08 seconds |
| Started | Aug 25 03:48:43 PM UTC 24 |
| Finished | Aug 25 04:10:08 PM UTC 24 |
| Peak memory | 673768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3800613265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 10.chip_csr_mem_rw_with_rand_reset.3800613265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.4076172009 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 4055262469 ps |
| CPU time | 592.86 seconds |
| Started | Aug 25 03:48:42 PM UTC 24 |
| Finished | Aug 25 03:58:45 PM UTC 24 |
| Peak memory | 620156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076172009 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.4076172009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.1648297973 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 15418976959 ps |
| CPU time | 2395.78 seconds |
| Started | Aug 25 03:46:27 PM UTC 24 |
| Finished | Aug 25 04:26:56 PM UTC 24 |
| Peak memory | 614320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1648297973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.chip_same_csr_outstanding.1648297973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1845462457 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 2843161624 ps |
| CPU time | 193.07 seconds |
| Started | Aug 25 03:47:06 PM UTC 24 |
| Finished | Aug 25 03:50:23 PM UTC 24 |
| Peak memory | 620088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845462457 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1845462457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.754892853 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 110119651729 ps |
| CPU time | 2378.65 seconds |
| Started | Aug 25 03:47:44 PM UTC 24 |
| Finished | Aug 25 04:27:54 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754892853 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.754892853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2934035921 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 88396769 ps |
| CPU time | 9.56 seconds |
| Started | Aug 25 03:48:12 PM UTC 24 |
| Finished | Aug 25 03:48:23 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934035921 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2934035921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3158163428 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 511070703 ps |
| CPU time | 63.7 seconds |
| Started | Aug 25 03:47:47 PM UTC 24 |
| Finished | Aug 25 03:48:53 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158163428 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3158163428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.3575835411 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 996945402 ps |
| CPU time | 45.86 seconds |
| Started | Aug 25 03:47:26 PM UTC 24 |
| Finished | Aug 25 03:48:13 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575835411 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3575835411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2918140978 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 62072806698 ps |
| CPU time | 953.54 seconds |
| Started | Aug 25 03:47:35 PM UTC 24 |
| Finished | Aug 25 04:03:42 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918140978 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2918140978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1604647202 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 29897215329 ps |
| CPU time | 665.85 seconds |
| Started | Aug 25 03:47:36 PM UTC 24 |
| Finished | Aug 25 03:58:52 PM UTC 24 |
| Peak memory | 599580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604647202 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1604647202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3304044596 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 566558579 ps |
| CPU time | 70.92 seconds |
| Started | Aug 25 03:47:31 PM UTC 24 |
| Finished | Aug 25 03:48:44 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304044596 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3304044596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.34533725 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2343981277 ps |
| CPU time | 108.87 seconds |
| Started | Aug 25 03:47:46 PM UTC 24 |
| Finished | Aug 25 03:49:38 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34533725 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.34533725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2133944262 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 197535244 ps |
| CPU time | 13.18 seconds |
| Started | Aug 25 03:47:07 PM UTC 24 |
| Finished | Aug 25 03:47:22 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133944262 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2133944262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1104784412 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 7513654571 ps |
| CPU time | 137.65 seconds |
| Started | Aug 25 03:47:23 PM UTC 24 |
| Finished | Aug 25 03:49:44 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104784412 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1104784412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2014621106 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 5994562180 ps |
| CPU time | 133.58 seconds |
| Started | Aug 25 03:47:23 PM UTC 24 |
| Finished | Aug 25 03:49:40 PM UTC 24 |
| Peak memory | 597380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014621106 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2014621106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.445750864 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 40499250 ps |
| CPU time | 10.32 seconds |
| Started | Aug 25 03:47:10 PM UTC 24 |
| Finished | Aug 25 03:47:22 PM UTC 24 |
| Peak memory | 597156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445750864 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.445750864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3078342010 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 9402017714 ps |
| CPU time | 499.36 seconds |
| Started | Aug 25 03:48:38 PM UTC 24 |
| Finished | Aug 25 03:57:06 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078342010 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3078342010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.630484968 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 703263609 ps |
| CPU time | 71.2 seconds |
| Started | Aug 25 03:48:41 PM UTC 24 |
| Finished | Aug 25 03:49:54 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630484968 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.630484968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4065691542 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 110541560 ps |
| CPU time | 20.06 seconds |
| Started | Aug 25 03:47:52 PM UTC 24 |
| Finished | Aug 25 03:48:13 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065691542 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.4065691542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1760984233 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 6460583276 ps |
| CPU time | 815.77 seconds |
| Started | Aug 25 03:50:44 PM UTC 24 |
| Finished | Aug 25 04:04:32 PM UTC 24 |
| Peak memory | 657008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1760984233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 11.chip_csr_mem_rw_with_rand_reset.1760984233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1783270460 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4589516090 ps |
| CPU time | 596.98 seconds |
| Started | Aug 25 03:50:39 PM UTC 24 |
| Finished | Aug 25 04:00:46 PM UTC 24 |
| Peak memory | 616120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783270460 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.1783270460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.3329035945 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 15965609921 ps |
| CPU time | 2218.56 seconds |
| Started | Aug 25 03:48:48 PM UTC 24 |
| Finished | Aug 25 04:26:18 PM UTC 24 |
| Peak memory | 613940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3329035945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.chip_same_csr_outstanding.3329035945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2303724410 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3769791792 ps |
| CPU time | 372.1 seconds |
| Started | Aug 25 03:48:50 PM UTC 24 |
| Finished | Aug 25 03:55:08 PM UTC 24 |
| Peak memory | 624188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303724410 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2303724410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.1103167775 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2389337411 ps |
| CPU time | 160.85 seconds |
| Started | Aug 25 03:49:45 PM UTC 24 |
| Finished | Aug 25 03:52:30 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103167775 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1103167775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2201053331 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 126167874 ps |
| CPU time | 22.96 seconds |
| Started | Aug 25 03:50:08 PM UTC 24 |
| Finished | Aug 25 03:50:33 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201053331 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2201053331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1766730620 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 580953398 ps |
| CPU time | 61.2 seconds |
| Started | Aug 25 03:50:02 PM UTC 24 |
| Finished | Aug 25 03:51:05 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766730620 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1766730620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.2578088461 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 130796057 ps |
| CPU time | 20 seconds |
| Started | Aug 25 03:49:27 PM UTC 24 |
| Finished | Aug 25 03:49:48 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578088461 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2578088461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1130110889 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 97853276514 ps |
| CPU time | 1503.74 seconds |
| Started | Aug 25 03:49:37 PM UTC 24 |
| Finished | Aug 25 04:15:01 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130110889 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1130110889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3293790604 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 29851963831 ps |
| CPU time | 679.61 seconds |
| Started | Aug 25 03:49:44 PM UTC 24 |
| Finished | Aug 25 04:01:14 PM UTC 24 |
| Peak memory | 599560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293790604 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3293790604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.491009858 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 90484010 ps |
| CPU time | 15.98 seconds |
| Started | Aug 25 03:49:31 PM UTC 24 |
| Finished | Aug 25 03:49:49 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491009858 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.491009858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.730468175 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 302510254 ps |
| CPU time | 19.43 seconds |
| Started | Aug 25 03:50:02 PM UTC 24 |
| Finished | Aug 25 03:50:22 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730468175 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.730468175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.358266216 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 225996160 ps |
| CPU time | 16.35 seconds |
| Started | Aug 25 03:48:56 PM UTC 24 |
| Finished | Aug 25 03:49:14 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358266216 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.358266216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.4144428506 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 7578032345 ps |
| CPU time | 122.41 seconds |
| Started | Aug 25 03:49:08 PM UTC 24 |
| Finished | Aug 25 03:51:13 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144428506 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.4144428506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2934005702 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 4419258731 ps |
| CPU time | 103.46 seconds |
| Started | Aug 25 03:49:17 PM UTC 24 |
| Finished | Aug 25 03:51:03 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934005702 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2934005702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2466251776 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 46822040 ps |
| CPU time | 9.15 seconds |
| Started | Aug 25 03:48:57 PM UTC 24 |
| Finished | Aug 25 03:49:07 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466251776 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2466251776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2302217877 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 9579025985 ps |
| CPU time | 514.56 seconds |
| Started | Aug 25 03:50:12 PM UTC 24 |
| Finished | Aug 25 03:58:55 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302217877 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2302217877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.4246858410 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3408286558 ps |
| CPU time | 397.35 seconds |
| Started | Aug 25 03:50:17 PM UTC 24 |
| Finished | Aug 25 03:57:02 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246858410 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4246858410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2052894496 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3816138203 ps |
| CPU time | 185.72 seconds |
| Started | Aug 25 03:50:12 PM UTC 24 |
| Finished | Aug 25 03:53:21 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052894496 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2052894496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4283973218 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 548600414 ps |
| CPU time | 269.96 seconds |
| Started | Aug 25 03:50:37 PM UTC 24 |
| Finished | Aug 25 03:55:12 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283973218 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.4283973218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.2931045114 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 506761693 ps |
| CPU time | 34.25 seconds |
| Started | Aug 25 03:50:01 PM UTC 24 |
| Finished | Aug 25 03:50:37 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931045114 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2931045114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3506827195 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 6417690420 ps |
| CPU time | 596.2 seconds |
| Started | Aug 25 03:52:46 PM UTC 24 |
| Finished | Aug 25 04:02:51 PM UTC 24 |
| Peak memory | 665572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3506827195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 12.chip_csr_mem_rw_with_rand_reset.3506827195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3496874791 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 5789546478 ps |
| CPU time | 1076.93 seconds |
| Started | Aug 25 03:52:08 PM UTC 24 |
| Finished | Aug 25 04:10:22 PM UTC 24 |
| Peak memory | 618028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496874791 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.3496874791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2628629242 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 16079402859 ps |
| CPU time | 3171.83 seconds |
| Started | Aug 25 03:50:47 PM UTC 24 |
| Finished | Aug 25 04:44:30 PM UTC 24 |
| Peak memory | 614176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2628629242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.chip_same_csr_outstanding.2628629242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1701526120 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3265168682 ps |
| CPU time | 251.08 seconds |
| Started | Aug 25 03:50:48 PM UTC 24 |
| Finished | Aug 25 03:55:03 PM UTC 24 |
| Peak memory | 624188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701526120 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1701526120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2099432788 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3307319338 ps |
| CPU time | 153.99 seconds |
| Started | Aug 25 03:51:28 PM UTC 24 |
| Finished | Aug 25 03:54:05 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099432788 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.2099432788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1451639178 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 48059808163 ps |
| CPU time | 1193.77 seconds |
| Started | Aug 25 03:51:31 PM UTC 24 |
| Finished | Aug 25 04:11:43 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451639178 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1451639178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.344193002 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 738542720 ps |
| CPU time | 31.26 seconds |
| Started | Aug 25 03:51:53 PM UTC 24 |
| Finished | Aug 25 03:52:26 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344193002 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.344193002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2484878639 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 987251281 ps |
| CPU time | 50.32 seconds |
| Started | Aug 25 03:51:36 PM UTC 24 |
| Finished | Aug 25 03:52:28 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484878639 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2484878639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1862008926 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 311004414 ps |
| CPU time | 22.24 seconds |
| Started | Aug 25 03:51:21 PM UTC 24 |
| Finished | Aug 25 03:51:45 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862008926 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1862008926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1428251204 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 90870962513 ps |
| CPU time | 1555.39 seconds |
| Started | Aug 25 03:51:25 PM UTC 24 |
| Finished | Aug 25 04:17:44 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428251204 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1428251204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1657134827 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 22254366572 ps |
| CPU time | 491.37 seconds |
| Started | Aug 25 03:51:26 PM UTC 24 |
| Finished | Aug 25 03:59:45 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657134827 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1657134827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.4120514383 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 125185369 ps |
| CPU time | 18.58 seconds |
| Started | Aug 25 03:51:23 PM UTC 24 |
| Finished | Aug 25 03:51:44 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120514383 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.4120514383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3709318785 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 464419813 ps |
| CPU time | 56.98 seconds |
| Started | Aug 25 03:51:34 PM UTC 24 |
| Finished | Aug 25 03:52:33 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709318785 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3709318785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1862823810 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 192928349 ps |
| CPU time | 12.24 seconds |
| Started | Aug 25 03:50:48 PM UTC 24 |
| Finished | Aug 25 03:51:01 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862823810 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1862823810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.463424138 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 8800551101 ps |
| CPU time | 141.27 seconds |
| Started | Aug 25 03:50:57 PM UTC 24 |
| Finished | Aug 25 03:53:21 PM UTC 24 |
| Peak memory | 597264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463424138 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.463424138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4107631112 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 4474712459 ps |
| CPU time | 99.86 seconds |
| Started | Aug 25 03:51:00 PM UTC 24 |
| Finished | Aug 25 03:52:42 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107631112 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.4107631112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2525949147 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 40560081 ps |
| CPU time | 9.83 seconds |
| Started | Aug 25 03:50:55 PM UTC 24 |
| Finished | Aug 25 03:51:06 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525949147 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2525949147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2193899059 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 761924391 ps |
| CPU time | 110.89 seconds |
| Started | Aug 25 03:51:53 PM UTC 24 |
| Finished | Aug 25 03:53:47 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193899059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2193899059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1382897216 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 8589839156 ps |
| CPU time | 366.92 seconds |
| Started | Aug 25 03:52:02 PM UTC 24 |
| Finished | Aug 25 03:58:14 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382897216 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1382897216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1818526102 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 488770462 ps |
| CPU time | 136.27 seconds |
| Started | Aug 25 03:52:08 PM UTC 24 |
| Finished | Aug 25 03:54:27 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818526102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1818526102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.4267868753 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 1065040213 ps |
| CPU time | 57.85 seconds |
| Started | Aug 25 03:51:38 PM UTC 24 |
| Finished | Aug 25 03:52:38 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267868753 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.4267868753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.403788483 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 6237943768 ps |
| CPU time | 580.28 seconds |
| Started | Aug 25 03:55:09 PM UTC 24 |
| Finished | Aug 25 04:04:58 PM UTC 24 |
| Peak memory | 661108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=403788483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.403788483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3317366609 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 3927369688 ps |
| CPU time | 553.09 seconds |
| Started | Aug 25 03:55:02 PM UTC 24 |
| Finished | Aug 25 04:04:25 PM UTC 24 |
| Peak memory | 618108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317366609 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3317366609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2195066911 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 28921645528 ps |
| CPU time | 4404.54 seconds |
| Started | Aug 25 03:52:50 PM UTC 24 |
| Finished | Aug 25 05:07:16 PM UTC 24 |
| Peak memory | 614776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2195066911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.chip_same_csr_outstanding.2195066911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3838670720 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3613346504 ps |
| CPU time | 453.12 seconds |
| Started | Aug 25 03:52:52 PM UTC 24 |
| Finished | Aug 25 04:00:33 PM UTC 24 |
| Peak memory | 624192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838670720 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.3838670720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.239700939 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 748003296 ps |
| CPU time | 47.55 seconds |
| Started | Aug 25 03:53:44 PM UTC 24 |
| Finished | Aug 25 03:54:34 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239700939 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.239700939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.853535195 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 116304788157 ps |
| CPU time | 2420.36 seconds |
| Started | Aug 25 03:53:47 PM UTC 24 |
| Finished | Aug 25 04:34:38 PM UTC 24 |
| Peak memory | 599640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853535195 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.853535195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3692615606 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 502670055 ps |
| CPU time | 28.73 seconds |
| Started | Aug 25 03:54:29 PM UTC 24 |
| Finished | Aug 25 03:54:59 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692615606 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3692615606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1615028182 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 828433565 ps |
| CPU time | 38.56 seconds |
| Started | Aug 25 03:54:12 PM UTC 24 |
| Finished | Aug 25 03:54:52 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615028182 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1615028182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1886222408 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 2224568851 ps |
| CPU time | 129.16 seconds |
| Started | Aug 25 03:53:07 PM UTC 24 |
| Finished | Aug 25 03:55:19 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886222408 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1886222408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3829274227 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 38901960463 ps |
| CPU time | 697.74 seconds |
| Started | Aug 25 03:53:34 PM UTC 24 |
| Finished | Aug 25 04:05:23 PM UTC 24 |
| Peak memory | 599524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829274227 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3829274227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.65451326 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 29312385622 ps |
| CPU time | 703.58 seconds |
| Started | Aug 25 03:53:43 PM UTC 24 |
| Finished | Aug 25 04:05:38 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65451326 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.65451326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3179443750 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 641466502 ps |
| CPU time | 70.9 seconds |
| Started | Aug 25 03:53:33 PM UTC 24 |
| Finished | Aug 25 03:54:46 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179443750 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.3179443750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3516389067 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 558316613 ps |
| CPU time | 54.84 seconds |
| Started | Aug 25 03:54:05 PM UTC 24 |
| Finished | Aug 25 03:55:02 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516389067 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3516389067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2923060934 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 229131675 ps |
| CPU time | 14.8 seconds |
| Started | Aug 25 03:52:54 PM UTC 24 |
| Finished | Aug 25 03:53:10 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923060934 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2923060934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.709188815 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 9896665990 ps |
| CPU time | 164.41 seconds |
| Started | Aug 25 03:53:02 PM UTC 24 |
| Finished | Aug 25 03:55:50 PM UTC 24 |
| Peak memory | 597460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709188815 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.709188815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2713246973 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 5434659594 ps |
| CPU time | 124.26 seconds |
| Started | Aug 25 03:53:06 PM UTC 24 |
| Finished | Aug 25 03:55:13 PM UTC 24 |
| Peak memory | 597364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713246973 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2713246973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3067971647 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 54508699 ps |
| CPU time | 10.51 seconds |
| Started | Aug 25 03:52:57 PM UTC 24 |
| Finished | Aug 25 03:53:08 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067971647 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3067971647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.3253548048 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3702707468 ps |
| CPU time | 192.38 seconds |
| Started | Aug 25 03:54:31 PM UTC 24 |
| Finished | Aug 25 03:57:47 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253548048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3253548048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1037350123 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2099002507 ps |
| CPU time | 256.58 seconds |
| Started | Aug 25 03:54:56 PM UTC 24 |
| Finished | Aug 25 03:59:18 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037350123 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1037350123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.248544038 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 164287117 ps |
| CPU time | 47.54 seconds |
| Started | Aug 25 03:54:51 PM UTC 24 |
| Finished | Aug 25 03:55:40 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248544038 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.248544038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1948892554 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 8056101845 ps |
| CPU time | 603.98 seconds |
| Started | Aug 25 03:54:59 PM UTC 24 |
| Finished | Aug 25 04:05:12 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948892554 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.1948892554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3632151550 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 217053453 ps |
| CPU time | 19.45 seconds |
| Started | Aug 25 03:54:19 PM UTC 24 |
| Finished | Aug 25 03:54:40 PM UTC 24 |
| Peak memory | 599224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632151550 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3632151550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2757745669 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 11209925373 ps |
| CPU time | 1430.39 seconds |
| Started | Aug 25 03:56:29 PM UTC 24 |
| Finished | Aug 25 04:20:42 PM UTC 24 |
| Peak memory | 673768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2757745669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.chip_csr_mem_rw_with_rand_reset.2757745669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1687431255 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 6282037325 ps |
| CPU time | 980.11 seconds |
| Started | Aug 25 03:56:24 PM UTC 24 |
| Finished | Aug 25 04:12:59 PM UTC 24 |
| Peak memory | 620256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687431255 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1687431255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2812742392 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 28634774476 ps |
| CPU time | 4639.58 seconds |
| Started | Aug 25 03:55:13 PM UTC 24 |
| Finished | Aug 25 05:13:38 PM UTC 24 |
| Peak memory | 614784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2812742392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.chip_same_csr_outstanding.2812742392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.657430208 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4939320003 ps |
| CPU time | 461.73 seconds |
| Started | Aug 25 03:55:14 PM UTC 24 |
| Finished | Aug 25 04:03:04 PM UTC 24 |
| Peak memory | 624388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657430208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.657430208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1254634110 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 237369951 ps |
| CPU time | 20.86 seconds |
| Started | Aug 25 03:55:36 PM UTC 24 |
| Finished | Aug 25 03:55:58 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254634110 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.1254634110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2116005307 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 70788327693 ps |
| CPU time | 1786.77 seconds |
| Started | Aug 25 03:55:42 PM UTC 24 |
| Finished | Aug 25 04:25:56 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116005307 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2116005307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.308642232 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 22623335 ps |
| CPU time | 7.68 seconds |
| Started | Aug 25 03:55:58 PM UTC 24 |
| Finished | Aug 25 03:56:06 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308642232 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.308642232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3032965966 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 94353223 ps |
| CPU time | 17 seconds |
| Started | Aug 25 03:55:51 PM UTC 24 |
| Finished | Aug 25 03:56:09 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032965966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3032965966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.168513807 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2043605961 ps |
| CPU time | 106.72 seconds |
| Started | Aug 25 03:55:28 PM UTC 24 |
| Finished | Aug 25 03:57:18 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168513807 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.168513807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.2906602782 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 43730460160 ps |
| CPU time | 604.87 seconds |
| Started | Aug 25 03:55:32 PM UTC 24 |
| Finished | Aug 25 04:05:45 PM UTC 24 |
| Peak memory | 599592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906602782 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2906602782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.2367704292 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 28270904008 ps |
| CPU time | 600.19 seconds |
| Started | Aug 25 03:55:35 PM UTC 24 |
| Finished | Aug 25 04:05:44 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367704292 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2367704292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2262012433 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 288978840 ps |
| CPU time | 39.42 seconds |
| Started | Aug 25 03:55:31 PM UTC 24 |
| Finished | Aug 25 03:56:12 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262012433 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2262012433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3559365446 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 643003979 ps |
| CPU time | 27.3 seconds |
| Started | Aug 25 03:55:54 PM UTC 24 |
| Finished | Aug 25 03:56:23 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559365446 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3559365446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.785210841 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 204536962 ps |
| CPU time | 14.58 seconds |
| Started | Aug 25 03:55:15 PM UTC 24 |
| Finished | Aug 25 03:55:31 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785210841 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.785210841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1788825108 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8089092346 ps |
| CPU time | 133.73 seconds |
| Started | Aug 25 03:55:24 PM UTC 24 |
| Finished | Aug 25 03:57:41 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788825108 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1788825108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1458972003 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 5052863133 ps |
| CPU time | 116.08 seconds |
| Started | Aug 25 03:55:26 PM UTC 24 |
| Finished | Aug 25 03:57:25 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458972003 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1458972003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2550703610 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 57149853 ps |
| CPU time | 10.39 seconds |
| Started | Aug 25 03:55:22 PM UTC 24 |
| Finished | Aug 25 03:55:34 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550703610 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2550703610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.2373582636 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 529509059 ps |
| CPU time | 81 seconds |
| Started | Aug 25 03:56:04 PM UTC 24 |
| Finished | Aug 25 03:57:27 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373582636 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2373582636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.915478213 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 1396287264 ps |
| CPU time | 175.14 seconds |
| Started | Aug 25 03:56:21 PM UTC 24 |
| Finished | Aug 25 03:59:21 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915478213 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.915478213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1610182589 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 7672413261 ps |
| CPU time | 745.05 seconds |
| Started | Aug 25 03:56:22 PM UTC 24 |
| Finished | Aug 25 04:08:59 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610182589 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1610182589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1011310263 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 44012506 ps |
| CPU time | 10.65 seconds |
| Started | Aug 25 03:55:58 PM UTC 24 |
| Finished | Aug 25 03:56:10 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011310263 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1011310263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3045966396 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 12464093040 ps |
| CPU time | 1502.73 seconds |
| Started | Aug 25 03:59:10 PM UTC 24 |
| Finished | Aug 25 04:24:36 PM UTC 24 |
| Peak memory | 663396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3045966396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 15.chip_csr_mem_rw_with_rand_reset.3045966396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.138055288 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 4459536790 ps |
| CPU time | 472.41 seconds |
| Started | Aug 25 03:59:10 PM UTC 24 |
| Finished | Aug 25 04:07:11 PM UTC 24 |
| Peak memory | 618024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138055288 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.138055288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_same_csr_outstanding.2059715405 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 14540788934 ps |
| CPU time | 2341.01 seconds |
| Started | Aug 25 03:56:33 PM UTC 24 |
| Finished | Aug 25 04:36:07 PM UTC 24 |
| Peak memory | 614132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2059715405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.chip_same_csr_outstanding.2059715405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.2061608972 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3702933733 ps |
| CPU time | 354.64 seconds |
| Started | Aug 25 03:56:34 PM UTC 24 |
| Finished | Aug 25 04:02:34 PM UTC 24 |
| Peak memory | 624380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061608972 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2061608972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1063199122 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 13819707957 ps |
| CPU time | 347.72 seconds |
| Started | Aug 25 03:57:47 PM UTC 24 |
| Finished | Aug 25 04:03:41 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063199122 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1063199122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2217415566 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 589834634 ps |
| CPU time | 35.05 seconds |
| Started | Aug 25 03:58:10 PM UTC 24 |
| Finished | Aug 25 03:58:47 PM UTC 24 |
| Peak memory | 599236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217415566 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2217415566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2936577466 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 2203886027 ps |
| CPU time | 121 seconds |
| Started | Aug 25 03:57:53 PM UTC 24 |
| Finished | Aug 25 03:59:57 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936577466 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2936577466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3554300658 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1792429406 ps |
| CPU time | 92.1 seconds |
| Started | Aug 25 03:57:19 PM UTC 24 |
| Finished | Aug 25 03:58:54 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554300658 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3554300658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.3783177376 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 58414778116 ps |
| CPU time | 993.37 seconds |
| Started | Aug 25 03:57:26 PM UTC 24 |
| Finished | Aug 25 04:14:14 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783177376 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3783177376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1429682879 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 60856873895 ps |
| CPU time | 1375.69 seconds |
| Started | Aug 25 03:57:29 PM UTC 24 |
| Finished | Aug 25 04:20:44 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429682879 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1429682879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2277779827 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 367915224 ps |
| CPU time | 43.99 seconds |
| Started | Aug 25 03:57:21 PM UTC 24 |
| Finished | Aug 25 03:58:06 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277779827 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.2277779827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2186633190 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 421530605 ps |
| CPU time | 43.54 seconds |
| Started | Aug 25 03:57:51 PM UTC 24 |
| Finished | Aug 25 03:58:37 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186633190 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2186633190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3861770011 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 247765248 ps |
| CPU time | 15.94 seconds |
| Started | Aug 25 03:56:37 PM UTC 24 |
| Finished | Aug 25 03:56:54 PM UTC 24 |
| Peak memory | 597216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861770011 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3861770011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.2548915880 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 8618615763 ps |
| CPU time | 140.25 seconds |
| Started | Aug 25 03:56:50 PM UTC 24 |
| Finished | Aug 25 03:59:14 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548915880 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2548915880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.890812320 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 5033266298 ps |
| CPU time | 121.95 seconds |
| Started | Aug 25 03:57:01 PM UTC 24 |
| Finished | Aug 25 03:59:06 PM UTC 24 |
| Peak memory | 597536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890812320 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.890812320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2750145147 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 43065302 ps |
| CPU time | 9.51 seconds |
| Started | Aug 25 03:56:46 PM UTC 24 |
| Finished | Aug 25 03:56:57 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750145147 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2750145147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2720086309 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 7601281902 ps |
| CPU time | 402.63 seconds |
| Started | Aug 25 03:58:28 PM UTC 24 |
| Finished | Aug 25 04:05:17 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720086309 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2720086309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.99008324 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 14785293222 ps |
| CPU time | 627.99 seconds |
| Started | Aug 25 03:58:38 PM UTC 24 |
| Finished | Aug 25 04:09:16 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99008324 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.99008324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3589330728 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 288020778 ps |
| CPU time | 199.48 seconds |
| Started | Aug 25 03:58:29 PM UTC 24 |
| Finished | Aug 25 04:01:53 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589330728 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.3589330728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1691596066 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 43243916 ps |
| CPU time | 18.26 seconds |
| Started | Aug 25 03:59:00 PM UTC 24 |
| Finished | Aug 25 03:59:20 PM UTC 24 |
| Peak memory | 597232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691596066 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.1691596066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3841686277 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 745093736 ps |
| CPU time | 49.77 seconds |
| Started | Aug 25 03:58:04 PM UTC 24 |
| Finished | Aug 25 03:58:55 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841686277 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3841686277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2775139149 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 12094392367 ps |
| CPU time | 1608.86 seconds |
| Started | Aug 25 04:01:08 PM UTC 24 |
| Finished | Aug 25 04:28:20 PM UTC 24 |
| Peak memory | 669732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2775139149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 16.chip_csr_mem_rw_with_rand_reset.2775139149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3971575437 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 5923501176 ps |
| CPU time | 802.57 seconds |
| Started | Aug 25 04:01:06 PM UTC 24 |
| Finished | Aug 25 04:14:40 PM UTC 24 |
| Peak memory | 620076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971575437 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3971575437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.721358887 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 32223017207 ps |
| CPU time | 4605.7 seconds |
| Started | Aug 25 03:59:17 PM UTC 24 |
| Finished | Aug 25 05:17:03 PM UTC 24 |
| Peak memory | 615012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=721358887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.chip_same_csr_outstanding.721358887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2601184134 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 63722860 ps |
| CPU time | 13.01 seconds |
| Started | Aug 25 03:59:52 PM UTC 24 |
| Finished | Aug 25 04:00:06 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601184134 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2601184134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.908798995 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 25979511314 ps |
| CPU time | 652.14 seconds |
| Started | Aug 25 03:59:58 PM UTC 24 |
| Finished | Aug 25 04:11:00 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908798995 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.908798995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1600212381 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 1291913387 ps |
| CPU time | 83.31 seconds |
| Started | Aug 25 04:00:22 PM UTC 24 |
| Finished | Aug 25 04:01:48 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600212381 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1600212381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.4161416521 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 44771831 ps |
| CPU time | 11.19 seconds |
| Started | Aug 25 03:59:40 PM UTC 24 |
| Finished | Aug 25 03:59:52 PM UTC 24 |
| Peak memory | 597160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161416521 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.4161416521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_large_delays.1577077542 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 79324687992 ps |
| CPU time | 1313.69 seconds |
| Started | Aug 25 03:59:43 PM UTC 24 |
| Finished | Aug 25 04:21:55 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577077542 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1577077542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.2163977443 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 21830284754 ps |
| CPU time | 471.42 seconds |
| Started | Aug 25 03:59:45 PM UTC 24 |
| Finished | Aug 25 04:07:43 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163977443 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2163977443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.342692432 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 84963398 ps |
| CPU time | 14.69 seconds |
| Started | Aug 25 03:59:43 PM UTC 24 |
| Finished | Aug 25 03:59:59 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342692432 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.342692432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.756418772 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 2191418134 ps |
| CPU time | 109.85 seconds |
| Started | Aug 25 04:00:09 PM UTC 24 |
| Finished | Aug 25 04:02:01 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756418772 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.756418772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.1620722306 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 173145837 ps |
| CPU time | 14.48 seconds |
| Started | Aug 25 03:59:19 PM UTC 24 |
| Finished | Aug 25 03:59:34 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620722306 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1620722306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3714598994 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 9272462593 ps |
| CPU time | 156.84 seconds |
| Started | Aug 25 03:59:19 PM UTC 24 |
| Finished | Aug 25 04:01:59 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714598994 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3714598994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1346204750 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 6042716663 ps |
| CPU time | 140.18 seconds |
| Started | Aug 25 03:59:31 PM UTC 24 |
| Finished | Aug 25 04:01:55 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346204750 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1346204750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.4105380852 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 46717231 ps |
| CPU time | 8.84 seconds |
| Started | Aug 25 03:59:19 PM UTC 24 |
| Finished | Aug 25 03:59:29 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105380852 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4105380852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3750558001 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 11207676701 ps |
| CPU time | 555.77 seconds |
| Started | Aug 25 04:00:31 PM UTC 24 |
| Finished | Aug 25 04:09:54 PM UTC 24 |
| Peak memory | 599612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750558001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3750558001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2319718438 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 1797178281 ps |
| CPU time | 86.89 seconds |
| Started | Aug 25 04:00:55 PM UTC 24 |
| Finished | Aug 25 04:02:25 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319718438 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2319718438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.740950596 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 57280519 ps |
| CPU time | 74.69 seconds |
| Started | Aug 25 04:00:55 PM UTC 24 |
| Finished | Aug 25 04:02:12 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740950596 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.740950596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3699228600 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 556659398 ps |
| CPU time | 241.29 seconds |
| Started | Aug 25 04:00:57 PM UTC 24 |
| Finished | Aug 25 04:05:02 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699228600 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.3699228600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3480009339 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 41445495 ps |
| CPU time | 10.4 seconds |
| Started | Aug 25 04:00:20 PM UTC 24 |
| Finished | Aug 25 04:00:32 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480009339 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3480009339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.1324723234 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 9359026325 ps |
| CPU time | 1489.56 seconds |
| Started | Aug 25 04:03:59 PM UTC 24 |
| Finished | Aug 25 04:29:12 PM UTC 24 |
| Peak memory | 673584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1324723234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 17.chip_csr_mem_rw_with_rand_reset.1324723234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.161649908 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 5511168400 ps |
| CPU time | 826.72 seconds |
| Started | Aug 25 04:03:37 PM UTC 24 |
| Finished | Aug 25 04:17:36 PM UTC 24 |
| Peak memory | 622340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161649908 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.161649908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.854297076 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 15220484621 ps |
| CPU time | 2980.41 seconds |
| Started | Aug 25 04:01:10 PM UTC 24 |
| Finished | Aug 25 04:51:35 PM UTC 24 |
| Peak memory | 614316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=854297076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.chip_same_csr_outstanding.854297076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2881118166 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 3025209748 ps |
| CPU time | 172.83 seconds |
| Started | Aug 25 04:01:38 PM UTC 24 |
| Finished | Aug 25 04:04:34 PM UTC 24 |
| Peak memory | 622284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881118166 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.2881118166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.3126170010 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1445538394 ps |
| CPU time | 85.2 seconds |
| Started | Aug 25 04:02:25 PM UTC 24 |
| Finished | Aug 25 04:03:52 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126170010 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3126170010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2008204230 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 88255292739 ps |
| CPU time | 1881.59 seconds |
| Started | Aug 25 04:02:36 PM UTC 24 |
| Finished | Aug 25 04:34:23 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008204230 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.2008204230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3141317413 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 343058465 ps |
| CPU time | 21.87 seconds |
| Started | Aug 25 04:03:14 PM UTC 24 |
| Finished | Aug 25 04:03:38 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141317413 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3141317413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.1837227388 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 555942670 ps |
| CPU time | 71.95 seconds |
| Started | Aug 25 04:02:59 PM UTC 24 |
| Finished | Aug 25 04:04:13 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837227388 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1837227388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.358749785 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 1346861958 ps |
| CPU time | 54.49 seconds |
| Started | Aug 25 04:02:17 PM UTC 24 |
| Finished | Aug 25 04:03:13 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358749785 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.358749785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_large_delays.1149876751 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 99625272126 ps |
| CPU time | 1716.4 seconds |
| Started | Aug 25 04:02:19 PM UTC 24 |
| Finished | Aug 25 04:31:20 PM UTC 24 |
| Peak memory | 599344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149876751 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1149876751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3138270122 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 30879378239 ps |
| CPU time | 683.16 seconds |
| Started | Aug 25 04:02:23 PM UTC 24 |
| Finished | Aug 25 04:13:56 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138270122 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3138270122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.770085983 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 297259393 ps |
| CPU time | 35.53 seconds |
| Started | Aug 25 04:02:20 PM UTC 24 |
| Finished | Aug 25 04:02:57 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770085983 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.770085983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.48998040 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 932028621 ps |
| CPU time | 48.84 seconds |
| Started | Aug 25 04:02:48 PM UTC 24 |
| Finished | Aug 25 04:03:39 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48998040 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.48998040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2068162227 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 49273749 ps |
| CPU time | 9.8 seconds |
| Started | Aug 25 04:01:39 PM UTC 24 |
| Finished | Aug 25 04:01:49 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068162227 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2068162227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.4283230760 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 8910175020 ps |
| CPU time | 149.34 seconds |
| Started | Aug 25 04:02:11 PM UTC 24 |
| Finished | Aug 25 04:04:44 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283230760 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4283230760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.467268294 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 5031356629 ps |
| CPU time | 129.14 seconds |
| Started | Aug 25 04:02:13 PM UTC 24 |
| Finished | Aug 25 04:04:25 PM UTC 24 |
| Peak memory | 597604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467268294 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.467268294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1990345668 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 42198883 ps |
| CPU time | 9.69 seconds |
| Started | Aug 25 04:01:44 PM UTC 24 |
| Finished | Aug 25 04:01:55 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990345668 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1990345668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3612141622 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1932540149 ps |
| CPU time | 215.89 seconds |
| Started | Aug 25 04:03:18 PM UTC 24 |
| Finished | Aug 25 04:06:58 PM UTC 24 |
| Peak memory | 599240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612141622 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3612141622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3659611439 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 10082515108 ps |
| CPU time | 550.55 seconds |
| Started | Aug 25 04:03:25 PM UTC 24 |
| Finished | Aug 25 04:12:44 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659611439 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3659611439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.705697893 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 219647785 ps |
| CPU time | 76.59 seconds |
| Started | Aug 25 04:03:25 PM UTC 24 |
| Finished | Aug 25 04:04:44 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705697893 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.705697893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4040195124 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 11946914061 ps |
| CPU time | 762.77 seconds |
| Started | Aug 25 04:03:29 PM UTC 24 |
| Finished | Aug 25 04:16:23 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040195124 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.4040195124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.1890305274 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 258067945 ps |
| CPU time | 42.29 seconds |
| Started | Aug 25 04:03:11 PM UTC 24 |
| Finished | Aug 25 04:03:55 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890305274 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1890305274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.4284621333 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 9559765624 ps |
| CPU time | 925.64 seconds |
| Started | Aug 25 04:05:46 PM UTC 24 |
| Finished | Aug 25 04:21:24 PM UTC 24 |
| Peak memory | 673572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4284621333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 18.chip_csr_mem_rw_with_rand_reset.4284621333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_csr_rw.1617349327 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 5722361469 ps |
| CPU time | 895.08 seconds |
| Started | Aug 25 04:05:42 PM UTC 24 |
| Finished | Aug 25 04:20:50 PM UTC 24 |
| Peak memory | 622128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617349327 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1617349327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3448505676 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 15160240270 ps |
| CPU time | 3070.17 seconds |
| Started | Aug 25 04:04:02 PM UTC 24 |
| Finished | Aug 25 04:55:57 PM UTC 24 |
| Peak memory | 614180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3448505676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.chip_same_csr_outstanding.3448505676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3565414139 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1325400014 ps |
| CPU time | 91.45 seconds |
| Started | Aug 25 04:04:50 PM UTC 24 |
| Finished | Aug 25 04:06:23 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565414139 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3565414139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1863049692 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 78640539449 ps |
| CPU time | 2033.46 seconds |
| Started | Aug 25 04:04:57 PM UTC 24 |
| Finished | Aug 25 04:39:20 PM UTC 24 |
| Peak memory | 599636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863049692 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1863049692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4057174454 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 54236744 ps |
| CPU time | 8.6 seconds |
| Started | Aug 25 04:05:19 PM UTC 24 |
| Finished | Aug 25 04:05:28 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057174454 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.4057174454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.485852382 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 1071200730 ps |
| CPU time | 48.16 seconds |
| Started | Aug 25 04:05:09 PM UTC 24 |
| Finished | Aug 25 04:05:59 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485852382 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.485852382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.4155879867 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 163531480 ps |
| CPU time | 22.99 seconds |
| Started | Aug 25 04:04:37 PM UTC 24 |
| Finished | Aug 25 04:05:01 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155879867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.4155879867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_large_delays.508379563 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 93773649265 ps |
| CPU time | 1553.1 seconds |
| Started | Aug 25 04:04:41 PM UTC 24 |
| Finished | Aug 25 04:30:55 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508379563 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.508379563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_slow_rsp.1857295125 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 63761534773 ps |
| CPU time | 1446.21 seconds |
| Started | Aug 25 04:04:49 PM UTC 24 |
| Finished | Aug 25 04:29:15 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857295125 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1857295125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3947194989 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 520947503 ps |
| CPU time | 73.82 seconds |
| Started | Aug 25 04:04:40 PM UTC 24 |
| Finished | Aug 25 04:05:56 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947194989 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3947194989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.721221890 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 1538303883 ps |
| CPU time | 75.97 seconds |
| Started | Aug 25 04:04:58 PM UTC 24 |
| Finished | Aug 25 04:06:16 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721221890 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.721221890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.731651920 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 59003742 ps |
| CPU time | 10.91 seconds |
| Started | Aug 25 04:04:05 PM UTC 24 |
| Finished | Aug 25 04:04:17 PM UTC 24 |
| Peak memory | 597236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731651920 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.731651920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1550272709 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 8507418162 ps |
| CPU time | 137.03 seconds |
| Started | Aug 25 04:04:15 PM UTC 24 |
| Finished | Aug 25 04:06:35 PM UTC 24 |
| Peak memory | 597576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550272709 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1550272709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3834589892 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 5860318258 ps |
| CPU time | 100.71 seconds |
| Started | Aug 25 04:04:17 PM UTC 24 |
| Finished | Aug 25 04:06:00 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834589892 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3834589892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1688582742 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 45999280 ps |
| CPU time | 9.34 seconds |
| Started | Aug 25 04:04:06 PM UTC 24 |
| Finished | Aug 25 04:04:17 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688582742 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1688582742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.872476680 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1169502575 ps |
| CPU time | 163.37 seconds |
| Started | Aug 25 04:05:23 PM UTC 24 |
| Finished | Aug 25 04:08:10 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872476680 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.872476680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3940511315 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 15189802688 ps |
| CPU time | 819.1 seconds |
| Started | Aug 25 04:05:26 PM UTC 24 |
| Finished | Aug 25 04:19:17 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940511315 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3940511315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3536494760 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 37490035 ps |
| CPU time | 27.99 seconds |
| Started | Aug 25 04:05:24 PM UTC 24 |
| Finished | Aug 25 04:05:53 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536494760 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3536494760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.545797911 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 8288491969 ps |
| CPU time | 573.89 seconds |
| Started | Aug 25 04:05:36 PM UTC 24 |
| Finished | Aug 25 04:15:20 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545797911 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.545797911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.982490813 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 57676053 ps |
| CPU time | 14.37 seconds |
| Started | Aug 25 04:05:07 PM UTC 24 |
| Finished | Aug 25 04:05:23 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982490813 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.982490813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4263130017 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 7965033670 ps |
| CPU time | 1433.66 seconds |
| Started | Aug 25 04:08:07 PM UTC 24 |
| Finished | Aug 25 04:32:22 PM UTC 24 |
| Peak memory | 673704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=4263130017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 19.chip_csr_mem_rw_with_rand_reset.4263130017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3367149251 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 6317141960 ps |
| CPU time | 740.68 seconds |
| Started | Aug 25 04:08:06 PM UTC 24 |
| Finished | Aug 25 04:20:38 PM UTC 24 |
| Peak memory | 618256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367149251 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.3367149251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2620976650 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 15530546268 ps |
| CPU time | 2568.51 seconds |
| Started | Aug 25 04:05:46 PM UTC 24 |
| Finished | Aug 25 04:49:12 PM UTC 24 |
| Peak memory | 611888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2620976650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.chip_same_csr_outstanding.2620976650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3301780134 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2950470452 ps |
| CPU time | 327.31 seconds |
| Started | Aug 25 04:05:52 PM UTC 24 |
| Finished | Aug 25 04:11:24 PM UTC 24 |
| Peak memory | 614140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301780134 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3301780134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1070299903 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 541942969 ps |
| CPU time | 41.53 seconds |
| Started | Aug 25 04:06:39 PM UTC 24 |
| Finished | Aug 25 04:07:22 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070299903 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1070299903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4164275206 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 35756170923 ps |
| CPU time | 747.68 seconds |
| Started | Aug 25 04:06:39 PM UTC 24 |
| Finished | Aug 25 04:19:18 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164275206 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.4164275206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2194419200 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 152009698 ps |
| CPU time | 13.64 seconds |
| Started | Aug 25 04:07:20 PM UTC 24 |
| Finished | Aug 25 04:07:35 PM UTC 24 |
| Peak memory | 597244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194419200 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2194419200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3376545177 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 2257740783 ps |
| CPU time | 111.07 seconds |
| Started | Aug 25 04:06:58 PM UTC 24 |
| Finished | Aug 25 04:08:52 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376545177 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3376545177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3154222596 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 508562808 ps |
| CPU time | 81.55 seconds |
| Started | Aug 25 04:06:18 PM UTC 24 |
| Finished | Aug 25 04:07:42 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154222596 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3154222596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_large_delays.1894701542 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 87439922597 ps |
| CPU time | 1451.87 seconds |
| Started | Aug 25 04:06:22 PM UTC 24 |
| Finished | Aug 25 04:30:57 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894701542 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1894701542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_slow_rsp.3157990247 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 55638533510 ps |
| CPU time | 1282.73 seconds |
| Started | Aug 25 04:06:31 PM UTC 24 |
| Finished | Aug 25 04:28:12 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157990247 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3157990247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3252772866 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 147115445 ps |
| CPU time | 25.55 seconds |
| Started | Aug 25 04:06:22 PM UTC 24 |
| Finished | Aug 25 04:06:49 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252772866 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3252772866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.1919519982 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 515423092 ps |
| CPU time | 62.69 seconds |
| Started | Aug 25 04:06:46 PM UTC 24 |
| Finished | Aug 25 04:07:51 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919519982 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1919519982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.1991774357 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 46580630 ps |
| CPU time | 10.23 seconds |
| Started | Aug 25 04:05:58 PM UTC 24 |
| Finished | Aug 25 04:06:09 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991774357 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1991774357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2917815092 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 9659519625 ps |
| CPU time | 162.91 seconds |
| Started | Aug 25 04:06:07 PM UTC 24 |
| Finished | Aug 25 04:08:54 PM UTC 24 |
| Peak memory | 597640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917815092 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2917815092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1680136903 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 5667075171 ps |
| CPU time | 124.6 seconds |
| Started | Aug 25 04:06:15 PM UTC 24 |
| Finished | Aug 25 04:08:22 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680136903 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1680136903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3936945660 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 47263475 ps |
| CPU time | 10.37 seconds |
| Started | Aug 25 04:06:06 PM UTC 24 |
| Finished | Aug 25 04:06:17 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936945660 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3936945660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.4201448690 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3804598927 ps |
| CPU time | 423.61 seconds |
| Started | Aug 25 04:07:35 PM UTC 24 |
| Finished | Aug 25 04:14:45 PM UTC 24 |
| Peak memory | 599116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201448690 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4201448690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1282078069 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3490187647 ps |
| CPU time | 322.09 seconds |
| Started | Aug 25 04:07:44 PM UTC 24 |
| Finished | Aug 25 04:13:11 PM UTC 24 |
| Peak memory | 599372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282078069 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1282078069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3245052001 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 158777069 ps |
| CPU time | 82.74 seconds |
| Started | Aug 25 04:07:46 PM UTC 24 |
| Finished | Aug 25 04:09:10 PM UTC 24 |
| Peak memory | 599560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245052001 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3245052001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3854333534 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 400358455 ps |
| CPU time | 126.79 seconds |
| Started | Aug 25 04:07:59 PM UTC 24 |
| Finished | Aug 25 04:10:09 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854333534 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.3854333534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2460773872 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 250638310 ps |
| CPU time | 51.73 seconds |
| Started | Aug 25 04:07:12 PM UTC 24 |
| Finished | Aug 25 04:08:06 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460773872 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2460773872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_aliasing.3499926161 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 37818739158 ps |
| CPU time | 8781.6 seconds |
| Started | Aug 25 03:29:42 PM UTC 24 |
| Finished | Aug 25 05:58:06 PM UTC 24 |
| Peak memory | 615004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3499926161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_ csr_aliasing.3499926161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1526522584 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6772552864 ps |
| CPU time | 1224.39 seconds |
| Started | Aug 25 03:29:40 PM UTC 24 |
| Finished | Aug 25 03:50:23 PM UTC 24 |
| Peak memory | 620324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1526522584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.chip_csr_bit_bash.1526522584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.367683428 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7312968790 ps |
| CPU time | 694.49 seconds |
| Started | Aug 25 03:31:40 PM UTC 24 |
| Finished | Aug 25 03:43:26 PM UTC 24 |
| Peak memory | 659064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=367683428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.367683428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3852237220 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4562215960 ps |
| CPU time | 574.01 seconds |
| Started | Aug 25 03:31:34 PM UTC 24 |
| Finished | Aug 25 03:41:16 PM UTC 24 |
| Peak memory | 618032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852237220 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3852237220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.3390533674 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 8795873786 ps |
| CPU time | 615.29 seconds |
| Started | Aug 25 03:29:58 PM UTC 24 |
| Finished | Aug 25 03:40:22 PM UTC 24 |
| Peak memory | 612012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390533674 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3390533674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4009870639 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 10513239062 ps |
| CPU time | 759.1 seconds |
| Started | Aug 25 03:29:58 PM UTC 24 |
| Finished | Aug 25 03:42:48 PM UTC 24 |
| Peak memory | 609588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_c pu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4009870639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. chip_rv_dm_lc_disabled.4009870639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1123969369 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 17135620508 ps |
| CPU time | 2690.19 seconds |
| Started | Aug 25 03:29:43 PM UTC 24 |
| Finished | Aug 25 04:15:11 PM UTC 24 |
| Peak memory | 613944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1123969369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.chip_same_csr_outstanding.1123969369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1471279085 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3407024068 ps |
| CPU time | 280.52 seconds |
| Started | Aug 25 03:29:56 PM UTC 24 |
| Finished | Aug 25 03:34:41 PM UTC 24 |
| Peak memory | 624324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471279085 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1471279085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3983249462 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 301795540 ps |
| CPU time | 33.63 seconds |
| Started | Aug 25 03:30:44 PM UTC 24 |
| Finished | Aug 25 03:31:20 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983249462 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.3983249462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2805496032 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 54295513327 ps |
| CPU time | 1330.92 seconds |
| Started | Aug 25 03:30:48 PM UTC 24 |
| Finished | Aug 25 03:53:18 PM UTC 24 |
| Peak memory | 599608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805496032 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.2805496032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4024556242 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1087753665 ps |
| CPU time | 63.73 seconds |
| Started | Aug 25 03:30:56 PM UTC 24 |
| Finished | Aug 25 03:32:02 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024556242 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.4024556242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.977001339 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 495584404 ps |
| CPU time | 29.09 seconds |
| Started | Aug 25 03:30:50 PM UTC 24 |
| Finished | Aug 25 03:31:20 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977001339 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.977001339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.3348534131 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 421859667 ps |
| CPU time | 61.58 seconds |
| Started | Aug 25 03:30:27 PM UTC 24 |
| Finished | Aug 25 03:31:31 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348534131 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3348534131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.273030310 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 115636123424 ps |
| CPU time | 1911.01 seconds |
| Started | Aug 25 03:30:28 PM UTC 24 |
| Finished | Aug 25 04:02:46 PM UTC 24 |
| Peak memory | 599360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273030310 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.273030310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.4245208223 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 17354065298 ps |
| CPU time | 372.73 seconds |
| Started | Aug 25 03:30:34 PM UTC 24 |
| Finished | Aug 25 03:36:52 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245208223 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4245208223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1437113728 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 387525454 ps |
| CPU time | 52.92 seconds |
| Started | Aug 25 03:30:30 PM UTC 24 |
| Finished | Aug 25 03:31:25 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437113728 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.1437113728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.731239177 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 746454925 ps |
| CPU time | 36.27 seconds |
| Started | Aug 25 03:30:45 PM UTC 24 |
| Finished | Aug 25 03:31:23 PM UTC 24 |
| Peak memory | 599368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731239177 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.731239177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.3171306319 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 206802575 ps |
| CPU time | 13.56 seconds |
| Started | Aug 25 03:30:08 PM UTC 24 |
| Finished | Aug 25 03:30:23 PM UTC 24 |
| Peak memory | 597228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171306319 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3171306319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.4075432464 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 6118534726 ps |
| CPU time | 98.87 seconds |
| Started | Aug 25 03:30:18 PM UTC 24 |
| Finished | Aug 25 03:31:59 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075432464 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4075432464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.620733685 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 5532650624 ps |
| CPU time | 147.05 seconds |
| Started | Aug 25 03:30:21 PM UTC 24 |
| Finished | Aug 25 03:32:51 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620733685 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.620733685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2057983406 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 38294593 ps |
| CPU time | 9.99 seconds |
| Started | Aug 25 03:30:08 PM UTC 24 |
| Finished | Aug 25 03:30:19 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057983406 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2057983406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2777769110 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2444466701 ps |
| CPU time | 232.03 seconds |
| Started | Aug 25 03:30:57 PM UTC 24 |
| Finished | Aug 25 03:34:53 PM UTC 24 |
| Peak memory | 599548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777769110 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2777769110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3516178411 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2222559545 ps |
| CPU time | 222.81 seconds |
| Started | Aug 25 03:31:12 PM UTC 24 |
| Finished | Aug 25 03:34:59 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516178411 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3516178411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2374758966 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 124135202 ps |
| CPU time | 21.52 seconds |
| Started | Aug 25 03:30:53 PM UTC 24 |
| Finished | Aug 25 03:31:16 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374758966 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2374758966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2692349916 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 266444701 ps |
| CPU time | 35.11 seconds |
| Started | Aug 25 04:09:18 PM UTC 24 |
| Finished | Aug 25 04:09:55 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692349916 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.2692349916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1159634071 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 83847429687 ps |
| CPU time | 2075.68 seconds |
| Started | Aug 25 04:09:24 PM UTC 24 |
| Finished | Aug 25 04:44:31 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159634071 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1159634071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2564334565 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1417074367 ps |
| CPU time | 75.24 seconds |
| Started | Aug 25 04:10:18 PM UTC 24 |
| Finished | Aug 25 04:11:35 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564334565 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.2564334565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3390207410 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 560327185 ps |
| CPU time | 80.86 seconds |
| Started | Aug 25 04:09:40 PM UTC 24 |
| Finished | Aug 25 04:11:03 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390207410 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3390207410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.760727581 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 383154148 ps |
| CPU time | 25.99 seconds |
| Started | Aug 25 04:09:06 PM UTC 24 |
| Finished | Aug 25 04:09:33 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760727581 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.760727581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1283920729 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 15994526160 ps |
| CPU time | 260.4 seconds |
| Started | Aug 25 04:09:16 PM UTC 24 |
| Finished | Aug 25 04:13:42 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283920729 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1283920729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_slow_rsp.3918866768 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 53689581008 ps |
| CPU time | 1090.64 seconds |
| Started | Aug 25 04:09:16 PM UTC 24 |
| Finished | Aug 25 04:27:42 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918866768 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3918866768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.62624454 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 434802929 ps |
| CPU time | 62.73 seconds |
| Started | Aug 25 04:09:07 PM UTC 24 |
| Finished | Aug 25 04:10:11 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62624454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.62624454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.585038245 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 860640580 ps |
| CPU time | 39.41 seconds |
| Started | Aug 25 04:09:35 PM UTC 24 |
| Finished | Aug 25 04:10:16 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585038245 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.585038245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2990569604 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 137528178 ps |
| CPU time | 11.08 seconds |
| Started | Aug 25 04:08:29 PM UTC 24 |
| Finished | Aug 25 04:08:42 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990569604 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2990569604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.3123827320 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 8962292441 ps |
| CPU time | 141.83 seconds |
| Started | Aug 25 04:08:34 PM UTC 24 |
| Finished | Aug 25 04:10:59 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123827320 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3123827320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2834233021 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 6251896889 ps |
| CPU time | 137.76 seconds |
| Started | Aug 25 04:08:47 PM UTC 24 |
| Finished | Aug 25 04:11:07 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834233021 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2834233021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2073495191 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 42640731 ps |
| CPU time | 10.19 seconds |
| Started | Aug 25 04:08:31 PM UTC 24 |
| Finished | Aug 25 04:08:42 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073495191 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.2073495191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all.1000843616 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 12754787530 ps |
| CPU time | 754.84 seconds |
| Started | Aug 25 04:10:19 PM UTC 24 |
| Finished | Aug 25 04:23:06 PM UTC 24 |
| Peak memory | 599672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000843616 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1000843616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1414712098 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 5754904356 ps |
| CPU time | 814.98 seconds |
| Started | Aug 25 04:10:32 PM UTC 24 |
| Finished | Aug 25 04:24:21 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414712098 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.1414712098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2804893038 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 8668789327 ps |
| CPU time | 583.7 seconds |
| Started | Aug 25 04:10:34 PM UTC 24 |
| Finished | Aug 25 04:20:27 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804893038 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2804893038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.1331954994 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 204726040 ps |
| CPU time | 42.38 seconds |
| Started | Aug 25 04:09:58 PM UTC 24 |
| Finished | Aug 25 04:10:42 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331954994 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1331954994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1107285737 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4506827760 ps |
| CPU time | 419.86 seconds |
| Started | Aug 25 04:10:40 PM UTC 24 |
| Finished | Aug 25 04:17:46 PM UTC 24 |
| Peak memory | 616064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107285737 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1107285737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.393992429 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 2355580575 ps |
| CPU time | 150.49 seconds |
| Started | Aug 25 04:11:30 PM UTC 24 |
| Finished | Aug 25 04:14:04 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393992429 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.393992429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1307452716 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 989718166 ps |
| CPU time | 53.69 seconds |
| Started | Aug 25 04:12:07 PM UTC 24 |
| Finished | Aug 25 04:13:02 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307452716 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.1307452716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.2798349716 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 212922297 ps |
| CPU time | 31.19 seconds |
| Started | Aug 25 04:11:59 PM UTC 24 |
| Finished | Aug 25 04:12:32 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798349716 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2798349716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.651184933 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 347402860 ps |
| CPU time | 49.98 seconds |
| Started | Aug 25 04:11:23 PM UTC 24 |
| Finished | Aug 25 04:12:15 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651184933 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.651184933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_large_delays.1824773539 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 74277782397 ps |
| CPU time | 1122.02 seconds |
| Started | Aug 25 04:11:26 PM UTC 24 |
| Finished | Aug 25 04:30:24 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824773539 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1824773539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.537938143 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 3328584086 ps |
| CPU time | 61.74 seconds |
| Started | Aug 25 04:11:29 PM UTC 24 |
| Finished | Aug 25 04:12:32 PM UTC 24 |
| Peak memory | 597264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537938143 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.537938143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4062063759 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 107104648 ps |
| CPU time | 21.18 seconds |
| Started | Aug 25 04:11:24 PM UTC 24 |
| Finished | Aug 25 04:11:47 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062063759 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.4062063759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1981246516 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 1101319907 ps |
| CPU time | 55.23 seconds |
| Started | Aug 25 04:11:48 PM UTC 24 |
| Finished | Aug 25 04:12:45 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981246516 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1981246516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.778260740 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 180794163 ps |
| CPU time | 11.27 seconds |
| Started | Aug 25 04:10:43 PM UTC 24 |
| Finished | Aug 25 04:10:56 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778260740 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.778260740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1926134446 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 6968015664 ps |
| CPU time | 108.93 seconds |
| Started | Aug 25 04:11:06 PM UTC 24 |
| Finished | Aug 25 04:12:58 PM UTC 24 |
| Peak memory | 597576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926134446 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1926134446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.666439139 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 4924015175 ps |
| CPU time | 108.34 seconds |
| Started | Aug 25 04:11:18 PM UTC 24 |
| Finished | Aug 25 04:13:10 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666439139 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.666439139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.365790381 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 39801069 ps |
| CPU time | 9.22 seconds |
| Started | Aug 25 04:10:58 PM UTC 24 |
| Finished | Aug 25 04:11:08 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365790381 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.365790381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1538072752 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2407541017 ps |
| CPU time | 333.34 seconds |
| Started | Aug 25 04:12:10 PM UTC 24 |
| Finished | Aug 25 04:17:49 PM UTC 24 |
| Peak memory | 599352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538072752 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1538072752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.340421194 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 10236032425 ps |
| CPU time | 434.71 seconds |
| Started | Aug 25 04:12:36 PM UTC 24 |
| Finished | Aug 25 04:19:58 PM UTC 24 |
| Peak memory | 599340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340421194 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.340421194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2382655446 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 15333358285 ps |
| CPU time | 978.86 seconds |
| Started | Aug 25 04:12:56 PM UTC 24 |
| Finished | Aug 25 04:29:29 PM UTC 24 |
| Peak memory | 603288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382655446 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2382655446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.887089188 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 879879346 ps |
| CPU time | 63.03 seconds |
| Started | Aug 25 04:12:02 PM UTC 24 |
| Finished | Aug 25 04:13:07 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887089188 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.887089188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.198076096 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 3395100594 ps |
| CPU time | 246.72 seconds |
| Started | Aug 25 04:12:55 PM UTC 24 |
| Finished | Aug 25 04:17:06 PM UTC 24 |
| Peak memory | 624324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198076096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.198076096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.1469278487 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 202688637 ps |
| CPU time | 35.71 seconds |
| Started | Aug 25 04:13:35 PM UTC 24 |
| Finished | Aug 25 04:14:13 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469278487 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.1469278487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1439565754 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 125173813344 ps |
| CPU time | 3063.32 seconds |
| Started | Aug 25 04:13:44 PM UTC 24 |
| Finished | Aug 25 05:05:33 PM UTC 24 |
| Peak memory | 600216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439565754 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1439565754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1281034730 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 70024535 ps |
| CPU time | 9.75 seconds |
| Started | Aug 25 04:14:20 PM UTC 24 |
| Finished | Aug 25 04:14:31 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281034730 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.1281034730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.626123528 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 175169302 ps |
| CPU time | 22.54 seconds |
| Started | Aug 25 04:14:05 PM UTC 24 |
| Finished | Aug 25 04:14:28 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626123528 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.626123528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.449140761 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 1430099632 ps |
| CPU time | 80.26 seconds |
| Started | Aug 25 04:13:24 PM UTC 24 |
| Finished | Aug 25 04:14:46 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449140761 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.449140761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.3876025527 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 107119930301 ps |
| CPU time | 1817.24 seconds |
| Started | Aug 25 04:13:31 PM UTC 24 |
| Finished | Aug 25 04:44:14 PM UTC 24 |
| Peak memory | 599412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876025527 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3876025527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_slow_rsp.172792018 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 37502166889 ps |
| CPU time | 791.56 seconds |
| Started | Aug 25 04:13:34 PM UTC 24 |
| Finished | Aug 25 04:26:57 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172792018 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.172792018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1269036060 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 143487758 ps |
| CPU time | 24.73 seconds |
| Started | Aug 25 04:13:27 PM UTC 24 |
| Finished | Aug 25 04:13:53 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269036060 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1269036060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1487097537 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1826618534 ps |
| CPU time | 76.21 seconds |
| Started | Aug 25 04:13:54 PM UTC 24 |
| Finished | Aug 25 04:15:12 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487097537 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1487097537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2725431590 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 269660379 ps |
| CPU time | 17.03 seconds |
| Started | Aug 25 04:13:10 PM UTC 24 |
| Finished | Aug 25 04:13:28 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725431590 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2725431590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.377741447 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 7179970200 ps |
| CPU time | 97.83 seconds |
| Started | Aug 25 04:13:22 PM UTC 24 |
| Finished | Aug 25 04:15:03 PM UTC 24 |
| Peak memory | 597268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377741447 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.377741447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3344889801 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 5116317718 ps |
| CPU time | 128.18 seconds |
| Started | Aug 25 04:13:23 PM UTC 24 |
| Finished | Aug 25 04:15:34 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344889801 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3344889801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4212978702 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 58737443 ps |
| CPU time | 10.95 seconds |
| Started | Aug 25 04:13:08 PM UTC 24 |
| Finished | Aug 25 04:13:20 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212978702 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.4212978702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all.2035732790 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 6965756579 ps |
| CPU time | 385.57 seconds |
| Started | Aug 25 04:14:29 PM UTC 24 |
| Finished | Aug 25 04:21:02 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035732790 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2035732790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.1280900546 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 1924889913 ps |
| CPU time | 108.33 seconds |
| Started | Aug 25 04:14:37 PM UTC 24 |
| Finished | Aug 25 04:16:28 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280900546 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1280900546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3271243826 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 97949944 ps |
| CPU time | 60.97 seconds |
| Started | Aug 25 04:14:35 PM UTC 24 |
| Finished | Aug 25 04:15:38 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271243826 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3271243826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3821540950 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 256215636 ps |
| CPU time | 48.79 seconds |
| Started | Aug 25 04:14:17 PM UTC 24 |
| Finished | Aug 25 04:15:08 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821540950 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3821540950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.chip_tl_errors.2136373707 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3533669040 ps |
| CPU time | 416.28 seconds |
| Started | Aug 25 04:14:53 PM UTC 24 |
| Finished | Aug 25 04:21:56 PM UTC 24 |
| Peak memory | 624192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136373707 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2136373707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.3263926720 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 1280975550 ps |
| CPU time | 74.36 seconds |
| Started | Aug 25 04:15:35 PM UTC 24 |
| Finished | Aug 25 04:16:51 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263926720 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.3263926720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1978401844 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 66789862604 ps |
| CPU time | 1484.07 seconds |
| Started | Aug 25 04:15:41 PM UTC 24 |
| Finished | Aug 25 04:40:48 PM UTC 24 |
| Peak memory | 599564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978401844 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.1978401844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4075539605 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 902145744 ps |
| CPU time | 57.49 seconds |
| Started | Aug 25 04:16:14 PM UTC 24 |
| Finished | Aug 25 04:17:13 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075539605 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.4075539605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.849882782 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 1461831048 ps |
| CPU time | 74.66 seconds |
| Started | Aug 25 04:15:59 PM UTC 24 |
| Finished | Aug 25 04:17:16 PM UTC 24 |
| Peak memory | 599404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849882782 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.849882782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1990561864 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 555343759 ps |
| CPU time | 75.33 seconds |
| Started | Aug 25 04:15:26 PM UTC 24 |
| Finished | Aug 25 04:16:43 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990561864 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1990561864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_large_delays.2511874611 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 21819102587 ps |
| CPU time | 317.77 seconds |
| Started | Aug 25 04:15:34 PM UTC 24 |
| Finished | Aug 25 04:20:57 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511874611 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2511874611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_slow_rsp.3501965410 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 66750135448 ps |
| CPU time | 1345.47 seconds |
| Started | Aug 25 04:15:35 PM UTC 24 |
| Finished | Aug 25 04:38:18 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501965410 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3501965410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.1628295940 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 486718499 ps |
| CPU time | 67.38 seconds |
| Started | Aug 25 04:15:32 PM UTC 24 |
| Finished | Aug 25 04:16:41 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628295940 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1628295940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3872920408 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 230158778 ps |
| CPU time | 13.57 seconds |
| Started | Aug 25 04:15:43 PM UTC 24 |
| Finished | Aug 25 04:15:57 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872920408 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3872920408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2274734200 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 44509325 ps |
| CPU time | 9.76 seconds |
| Started | Aug 25 04:15:02 PM UTC 24 |
| Finished | Aug 25 04:15:13 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274734200 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2274734200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1255614711 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 8774309283 ps |
| CPU time | 134.87 seconds |
| Started | Aug 25 04:15:07 PM UTC 24 |
| Finished | Aug 25 04:17:25 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255614711 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1255614711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3119582216 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 5135311808 ps |
| CPU time | 120.51 seconds |
| Started | Aug 25 04:15:24 PM UTC 24 |
| Finished | Aug 25 04:17:27 PM UTC 24 |
| Peak memory | 597392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119582216 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3119582216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1411661559 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 40371009 ps |
| CPU time | 7.56 seconds |
| Started | Aug 25 04:15:08 PM UTC 24 |
| Finished | Aug 25 04:15:17 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411661559 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.1411661559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.4250850506 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 3418170537 ps |
| CPU time | 214.96 seconds |
| Started | Aug 25 04:16:23 PM UTC 24 |
| Finished | Aug 25 04:20:02 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250850506 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4250850506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.4040953513 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 2096247662 ps |
| CPU time | 226.92 seconds |
| Started | Aug 25 04:16:43 PM UTC 24 |
| Finished | Aug 25 04:20:34 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040953513 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4040953513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1635275540 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 52354813 ps |
| CPU time | 46.92 seconds |
| Started | Aug 25 04:16:38 PM UTC 24 |
| Finished | Aug 25 04:17:27 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635275540 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.1635275540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3084700034 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 330048443 ps |
| CPU time | 153.85 seconds |
| Started | Aug 25 04:16:46 PM UTC 24 |
| Finished | Aug 25 04:19:23 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084700034 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3084700034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.3961934639 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 134514039 ps |
| CPU time | 13.09 seconds |
| Started | Aug 25 04:16:02 PM UTC 24 |
| Finished | Aug 25 04:16:16 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961934639 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3961934639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.3200591959 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 429547859 ps |
| CPU time | 41.15 seconds |
| Started | Aug 25 04:17:39 PM UTC 24 |
| Finished | Aug 25 04:18:22 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200591959 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.3200591959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3909473018 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 38720095159 ps |
| CPU time | 918 seconds |
| Started | Aug 25 04:17:42 PM UTC 24 |
| Finished | Aug 25 04:33:14 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909473018 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3909473018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2880509122 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 289975435 ps |
| CPU time | 42.02 seconds |
| Started | Aug 25 04:17:59 PM UTC 24 |
| Finished | Aug 25 04:18:42 PM UTC 24 |
| Peak memory | 599276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880509122 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.2880509122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3929904694 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 167057672 ps |
| CPU time | 23.81 seconds |
| Started | Aug 25 04:17:50 PM UTC 24 |
| Finished | Aug 25 04:18:15 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929904694 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3929904694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.4142508991 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 485723435 ps |
| CPU time | 69.54 seconds |
| Started | Aug 25 04:17:30 PM UTC 24 |
| Finished | Aug 25 04:18:41 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142508991 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.4142508991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.1922404454 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 6233147659 ps |
| CPU time | 107.12 seconds |
| Started | Aug 25 04:17:34 PM UTC 24 |
| Finished | Aug 25 04:19:24 PM UTC 24 |
| Peak memory | 597348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922404454 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1922404454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.391270894 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 62743833363 ps |
| CPU time | 1539.22 seconds |
| Started | Aug 25 04:17:35 PM UTC 24 |
| Finished | Aug 25 04:43:38 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391270894 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.391270894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.569643903 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 395933233 ps |
| CPU time | 51.43 seconds |
| Started | Aug 25 04:17:31 PM UTC 24 |
| Finished | Aug 25 04:18:24 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569643903 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.569643903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.634497272 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 718900285 ps |
| CPU time | 36.09 seconds |
| Started | Aug 25 04:17:44 PM UTC 24 |
| Finished | Aug 25 04:18:21 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634497272 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.634497272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.1873145418 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 44436953 ps |
| CPU time | 8.86 seconds |
| Started | Aug 25 04:16:57 PM UTC 24 |
| Finished | Aug 25 04:17:07 PM UTC 24 |
| Peak memory | 597172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873145418 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1873145418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2649795631 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 9643645068 ps |
| CPU time | 164.52 seconds |
| Started | Aug 25 04:17:08 PM UTC 24 |
| Finished | Aug 25 04:19:56 PM UTC 24 |
| Peak memory | 597572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649795631 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2649795631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2990372120 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 4484846301 ps |
| CPU time | 94.07 seconds |
| Started | Aug 25 04:17:15 PM UTC 24 |
| Finished | Aug 25 04:18:51 PM UTC 24 |
| Peak memory | 597476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990372120 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2990372120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4288325111 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 51797357 ps |
| CPU time | 10.93 seconds |
| Started | Aug 25 04:17:05 PM UTC 24 |
| Finished | Aug 25 04:17:18 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288325111 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.4288325111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.2697239341 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 6697106205 ps |
| CPU time | 407.41 seconds |
| Started | Aug 25 04:18:13 PM UTC 24 |
| Finished | Aug 25 04:25:08 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697239341 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2697239341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3370702061 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2748682046 ps |
| CPU time | 557.79 seconds |
| Started | Aug 25 04:18:08 PM UTC 24 |
| Finished | Aug 25 04:27:35 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370702061 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.3370702061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2037461670 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 229274091 ps |
| CPU time | 118.48 seconds |
| Started | Aug 25 04:18:38 PM UTC 24 |
| Finished | Aug 25 04:20:39 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037461670 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2037461670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.3752516512 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 902922411 ps |
| CPU time | 63.7 seconds |
| Started | Aug 25 04:17:50 PM UTC 24 |
| Finished | Aug 25 04:18:56 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752516512 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3752516512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.chip_tl_errors.552349406 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 4391946500 ps |
| CPU time | 708.79 seconds |
| Started | Aug 25 04:18:45 PM UTC 24 |
| Finished | Aug 25 04:30:45 PM UTC 24 |
| Peak memory | 624388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552349406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.552349406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device.680864275 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 919343413 ps |
| CPU time | 105.93 seconds |
| Started | Aug 25 04:19:21 PM UTC 24 |
| Finished | Aug 25 04:21:09 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680864275 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.680864275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3027800182 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 45645684 ps |
| CPU time | 8.87 seconds |
| Started | Aug 25 04:20:20 PM UTC 24 |
| Finished | Aug 25 04:20:30 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027800182 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3027800182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.3866817278 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 335809269 ps |
| CPU time | 37.55 seconds |
| Started | Aug 25 04:19:46 PM UTC 24 |
| Finished | Aug 25 04:20:25 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866817278 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3866817278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.2262352686 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 371332101 ps |
| CPU time | 54.65 seconds |
| Started | Aug 25 04:19:14 PM UTC 24 |
| Finished | Aug 25 04:20:11 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262352686 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2262352686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.3788525085 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 106525721230 ps |
| CPU time | 1487.82 seconds |
| Started | Aug 25 04:19:20 PM UTC 24 |
| Finished | Aug 25 04:44:26 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788525085 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3788525085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_slow_rsp.3841290061 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 46597018366 ps |
| CPU time | 1036.44 seconds |
| Started | Aug 25 04:19:23 PM UTC 24 |
| Finished | Aug 25 04:36:55 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841290061 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3841290061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.1967870188 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 547405634 ps |
| CPU time | 75.83 seconds |
| Started | Aug 25 04:19:17 PM UTC 24 |
| Finished | Aug 25 04:20:35 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967870188 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.1967870188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.2717571196 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 312380051 ps |
| CPU time | 16.7 seconds |
| Started | Aug 25 04:19:40 PM UTC 24 |
| Finished | Aug 25 04:19:58 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717571196 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2717571196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1958747579 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 48856840 ps |
| CPU time | 9.22 seconds |
| Started | Aug 25 04:18:45 PM UTC 24 |
| Finished | Aug 25 04:18:56 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958747579 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1958747579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_large_delays.88348695 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 8828485446 ps |
| CPU time | 130.05 seconds |
| Started | Aug 25 04:19:05 PM UTC 24 |
| Finished | Aug 25 04:21:17 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88348695 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.88348695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3352300989 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 5371688447 ps |
| CPU time | 118.8 seconds |
| Started | Aug 25 04:19:05 PM UTC 24 |
| Finished | Aug 25 04:21:06 PM UTC 24 |
| Peak memory | 597584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352300989 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3352300989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.443162928 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 44658415 ps |
| CPU time | 9.29 seconds |
| Started | Aug 25 04:18:49 PM UTC 24 |
| Finished | Aug 25 04:18:59 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443162928 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.443162928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all.4188878550 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1372315953 ps |
| CPU time | 81.84 seconds |
| Started | Aug 25 04:20:22 PM UTC 24 |
| Finished | Aug 25 04:21:46 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188878550 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.4188878550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_error.567585255 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 697633162 ps |
| CPU time | 66.15 seconds |
| Started | Aug 25 04:20:26 PM UTC 24 |
| Finished | Aug 25 04:21:34 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567585255 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.567585255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1215952702 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 424979250 ps |
| CPU time | 247.02 seconds |
| Started | Aug 25 04:20:22 PM UTC 24 |
| Finished | Aug 25 04:24:33 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215952702 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.1215952702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2690909582 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 563156421 ps |
| CPU time | 240.4 seconds |
| Started | Aug 25 04:20:34 PM UTC 24 |
| Finished | Aug 25 04:24:39 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690909582 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.2690909582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1204307727 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 676290293 ps |
| CPU time | 39.33 seconds |
| Started | Aug 25 04:19:47 PM UTC 24 |
| Finished | Aug 25 04:20:28 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204307727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1204307727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.chip_tl_errors.2951265153 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4491991472 ps |
| CPU time | 623.87 seconds |
| Started | Aug 25 04:20:36 PM UTC 24 |
| Finished | Aug 25 04:31:10 PM UTC 24 |
| Peak memory | 624432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951265153 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2951265153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device.4087584941 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 835386423 ps |
| CPU time | 99.43 seconds |
| Started | Aug 25 04:21:06 PM UTC 24 |
| Finished | Aug 25 04:22:48 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087584941 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.4087584941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1652991879 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 21584075290 ps |
| CPU time | 413.01 seconds |
| Started | Aug 25 04:21:07 PM UTC 24 |
| Finished | Aug 25 04:28:07 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652991879 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1652991879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2951533595 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 197508903 ps |
| CPU time | 35.83 seconds |
| Started | Aug 25 04:21:26 PM UTC 24 |
| Finished | Aug 25 04:22:04 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951533595 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.2951533595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_error_random.2257027286 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 282151759 ps |
| CPU time | 15.27 seconds |
| Started | Aug 25 04:21:20 PM UTC 24 |
| Finished | Aug 25 04:21:37 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257027286 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.2257027286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random.552173719 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 1395817514 ps |
| CPU time | 83.73 seconds |
| Started | Aug 25 04:20:59 PM UTC 24 |
| Finished | Aug 25 04:22:25 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552173719 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.552173719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_large_delays.527232216 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 20409830291 ps |
| CPU time | 296.61 seconds |
| Started | Aug 25 04:21:03 PM UTC 24 |
| Finished | Aug 25 04:26:04 PM UTC 24 |
| Peak memory | 599388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527232216 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.527232216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_slow_rsp.2074973061 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 2697626082 ps |
| CPU time | 69.4 seconds |
| Started | Aug 25 04:21:03 PM UTC 24 |
| Finished | Aug 25 04:22:15 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074973061 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2074973061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_random_zero_delays.709370260 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 472944626 ps |
| CPU time | 70.42 seconds |
| Started | Aug 25 04:20:59 PM UTC 24 |
| Finished | Aug 25 04:22:12 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709370260 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.709370260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_same_source.3055504599 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 504176322 ps |
| CPU time | 62.97 seconds |
| Started | Aug 25 04:21:13 PM UTC 24 |
| Finished | Aug 25 04:22:18 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055504599 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3055504599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke.2526851773 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 225179568 ps |
| CPU time | 15.44 seconds |
| Started | Aug 25 04:20:49 PM UTC 24 |
| Finished | Aug 25 04:21:06 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526851773 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2526851773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_large_delays.3420009806 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 9168069079 ps |
| CPU time | 162.04 seconds |
| Started | Aug 25 04:20:53 PM UTC 24 |
| Finished | Aug 25 04:23:38 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420009806 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3420009806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1800462942 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 5929917058 ps |
| CPU time | 147.72 seconds |
| Started | Aug 25 04:20:54 PM UTC 24 |
| Finished | Aug 25 04:23:24 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800462942 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1800462942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2273130294 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 47414961 ps |
| CPU time | 10.18 seconds |
| Started | Aug 25 04:20:51 PM UTC 24 |
| Finished | Aug 25 04:21:03 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273130294 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.2273130294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all.4105859442 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 4435182281 ps |
| CPU time | 637.61 seconds |
| Started | Aug 25 04:21:28 PM UTC 24 |
| Finished | Aug 25 04:32:17 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105859442 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.4105859442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_error.1719307566 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 12986361562 ps |
| CPU time | 668.35 seconds |
| Started | Aug 25 04:21:33 PM UTC 24 |
| Finished | Aug 25 04:32:52 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719307566 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1719307566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.668385377 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 36835461 ps |
| CPU time | 56.5 seconds |
| Started | Aug 25 04:21:29 PM UTC 24 |
| Finished | Aug 25 04:22:27 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668385377 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.668385377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2126222230 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 6089213903 ps |
| CPU time | 514.47 seconds |
| Started | Aug 25 04:21:41 PM UTC 24 |
| Finished | Aug 25 04:30:23 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126222230 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2126222230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/26.xbar_unmapped_addr.2804201687 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 69522668 ps |
| CPU time | 14.7 seconds |
| Started | Aug 25 04:21:26 PM UTC 24 |
| Finished | Aug 25 04:21:42 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804201687 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2804201687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.chip_tl_errors.741290602 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4346400474 ps |
| CPU time | 482.18 seconds |
| Started | Aug 25 04:21:47 PM UTC 24 |
| Finished | Aug 25 04:29:57 PM UTC 24 |
| Peak memory | 622388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741290602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.741290602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device.859738492 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 936546170 ps |
| CPU time | 124.07 seconds |
| Started | Aug 25 04:22:34 PM UTC 24 |
| Finished | Aug 25 04:24:40 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859738492 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.859738492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1206994583 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 18084791281 ps |
| CPU time | 477.48 seconds |
| Started | Aug 25 04:22:35 PM UTC 24 |
| Finished | Aug 25 04:30:41 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206994583 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1206994583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3950811126 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1058023823 ps |
| CPU time | 51.66 seconds |
| Started | Aug 25 04:22:49 PM UTC 24 |
| Finished | Aug 25 04:23:42 PM UTC 24 |
| Peak memory | 599232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950811126 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.3950811126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_error_random.4277962102 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 492950380 ps |
| CPU time | 63.3 seconds |
| Started | Aug 25 04:22:40 PM UTC 24 |
| Finished | Aug 25 04:23:46 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277962102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.4277962102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random.595061215 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 102351985 ps |
| CPU time | 18.04 seconds |
| Started | Aug 25 04:22:18 PM UTC 24 |
| Finished | Aug 25 04:22:38 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595061215 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.595061215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.1848585896 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 85000764839 ps |
| CPU time | 1455.93 seconds |
| Started | Aug 25 04:22:28 PM UTC 24 |
| Finished | Aug 25 04:47:08 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848585896 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1848585896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_slow_rsp.3722378324 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 18332479993 ps |
| CPU time | 459.15 seconds |
| Started | Aug 25 04:22:33 PM UTC 24 |
| Finished | Aug 25 04:30:20 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722378324 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3722378324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_zero_delays.1430162260 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 178030754 ps |
| CPU time | 27.37 seconds |
| Started | Aug 25 04:22:18 PM UTC 24 |
| Finished | Aug 25 04:22:46 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430162260 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.1430162260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_same_source.1222735365 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 2326630339 ps |
| CPU time | 101.71 seconds |
| Started | Aug 25 04:22:39 PM UTC 24 |
| Finished | Aug 25 04:24:23 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222735365 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1222735365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke.3466230624 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 49587567 ps |
| CPU time | 11.13 seconds |
| Started | Aug 25 04:21:57 PM UTC 24 |
| Finished | Aug 25 04:22:10 PM UTC 24 |
| Peak memory | 597348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466230624 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3466230624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_large_delays.3369549973 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 7916568787 ps |
| CPU time | 135.1 seconds |
| Started | Aug 25 04:22:06 PM UTC 24 |
| Finished | Aug 25 04:24:23 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369549973 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3369549973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1151565847 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 5435335484 ps |
| CPU time | 129.91 seconds |
| Started | Aug 25 04:22:09 PM UTC 24 |
| Finished | Aug 25 04:24:22 PM UTC 24 |
| Peak memory | 597268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151565847 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1151565847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3249186283 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 45551922 ps |
| CPU time | 9.07 seconds |
| Started | Aug 25 04:22:00 PM UTC 24 |
| Finished | Aug 25 04:22:11 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249186283 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.3249186283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all.2049949889 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 5160459912 ps |
| CPU time | 682.78 seconds |
| Started | Aug 25 04:22:54 PM UTC 24 |
| Finished | Aug 25 04:34:28 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049949889 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2049949889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_error.4017174268 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 6946090725 ps |
| CPU time | 333.88 seconds |
| Started | Aug 25 04:23:11 PM UTC 24 |
| Finished | Aug 25 04:28:51 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017174268 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4017174268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2737668423 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4402625080 ps |
| CPU time | 446.95 seconds |
| Started | Aug 25 04:23:02 PM UTC 24 |
| Finished | Aug 25 04:30:36 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737668423 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.2737668423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.49396715 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2474670956 ps |
| CPU time | 320.22 seconds |
| Started | Aug 25 04:23:13 PM UTC 24 |
| Finished | Aug 25 04:28:39 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49396715 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.49396715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_unmapped_addr.1743266840 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 995303107 ps |
| CPU time | 52.92 seconds |
| Started | Aug 25 04:22:48 PM UTC 24 |
| Finished | Aug 25 04:23:42 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743266840 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1743266840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.chip_tl_errors.1055946092 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 4678057175 ps |
| CPU time | 792.06 seconds |
| Started | Aug 25 04:23:32 PM UTC 24 |
| Finished | Aug 25 04:36:57 PM UTC 24 |
| Peak memory | 624248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055946092 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1055946092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device.3470869905 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 195966129 ps |
| CPU time | 33.09 seconds |
| Started | Aug 25 04:24:45 PM UTC 24 |
| Finished | Aug 25 04:25:20 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470869905 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.3470869905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1677205068 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 143537049636 ps |
| CPU time | 3268.86 seconds |
| Started | Aug 25 04:24:46 PM UTC 24 |
| Finished | Aug 25 05:20:00 PM UTC 24 |
| Peak memory | 600288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677205068 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1677205068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2771677439 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 200001162 ps |
| CPU time | 14.91 seconds |
| Started | Aug 25 04:25:01 PM UTC 24 |
| Finished | Aug 25 04:25:17 PM UTC 24 |
| Peak memory | 598708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771677439 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2771677439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_error_random.421141846 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 494915105 ps |
| CPU time | 65.11 seconds |
| Started | Aug 25 04:24:48 PM UTC 24 |
| Finished | Aug 25 04:25:55 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421141846 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.421141846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random.1937653827 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 516569531 ps |
| CPU time | 73.16 seconds |
| Started | Aug 25 04:24:07 PM UTC 24 |
| Finished | Aug 25 04:25:23 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937653827 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1937653827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_large_delays.237323090 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 44949957349 ps |
| CPU time | 732.45 seconds |
| Started | Aug 25 04:24:25 PM UTC 24 |
| Finished | Aug 25 04:36:50 PM UTC 24 |
| Peak memory | 599356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237323090 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.237323090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_slow_rsp.676956469 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 8592396185 ps |
| CPU time | 214.58 seconds |
| Started | Aug 25 04:24:29 PM UTC 24 |
| Finished | Aug 25 04:28:08 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676956469 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.676956469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_random_zero_delays.1290481667 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 170475060 ps |
| CPU time | 25.23 seconds |
| Started | Aug 25 04:24:10 PM UTC 24 |
| Finished | Aug 25 04:24:36 PM UTC 24 |
| Peak memory | 599356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290481667 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.1290481667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_same_source.4174533688 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 355893793 ps |
| CPU time | 45.26 seconds |
| Started | Aug 25 04:24:47 PM UTC 24 |
| Finished | Aug 25 04:25:34 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174533688 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4174533688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke.2412549518 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 267619768 ps |
| CPU time | 15.23 seconds |
| Started | Aug 25 04:23:49 PM UTC 24 |
| Finished | Aug 25 04:24:05 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412549518 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2412549518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_large_delays.1939175748 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 5101270109 ps |
| CPU time | 78.94 seconds |
| Started | Aug 25 04:24:03 PM UTC 24 |
| Finished | Aug 25 04:25:24 PM UTC 24 |
| Peak memory | 597368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939175748 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1939175748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3586280683 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 2758286989 ps |
| CPU time | 71.58 seconds |
| Started | Aug 25 04:24:06 PM UTC 24 |
| Finished | Aug 25 04:25:19 PM UTC 24 |
| Peak memory | 597208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586280683 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3586280683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3537344628 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 43009731 ps |
| CPU time | 9.58 seconds |
| Started | Aug 25 04:23:49 PM UTC 24 |
| Finished | Aug 25 04:24:00 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537344628 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3537344628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all.3486130015 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 3409718637 ps |
| CPU time | 368.81 seconds |
| Started | Aug 25 04:25:01 PM UTC 24 |
| Finished | Aug 25 04:31:15 PM UTC 24 |
| Peak memory | 598824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486130015 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3486130015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_error.2771214024 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 3142752949 ps |
| CPU time | 364.25 seconds |
| Started | Aug 25 04:25:03 PM UTC 24 |
| Finished | Aug 25 04:31:14 PM UTC 24 |
| Peak memory | 599348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771214024 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2771214024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3161181898 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 11348611984 ps |
| CPU time | 893.83 seconds |
| Started | Aug 25 04:25:03 PM UTC 24 |
| Finished | Aug 25 04:40:10 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161181898 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.3161181898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_unmapped_addr.2222032987 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 301486776 ps |
| CPU time | 23.91 seconds |
| Started | Aug 25 04:24:58 PM UTC 24 |
| Finished | Aug 25 04:25:23 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222032987 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2222032987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.chip_tl_errors.3338571755 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 4393760920 ps |
| CPU time | 544.94 seconds |
| Started | Aug 25 04:25:42 PM UTC 24 |
| Finished | Aug 25 04:34:56 PM UTC 24 |
| Peak memory | 624252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338571755 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3338571755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device.663388677 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 286221069 ps |
| CPU time | 23.16 seconds |
| Started | Aug 25 04:26:20 PM UTC 24 |
| Finished | Aug 25 04:26:45 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663388677 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.663388677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2506458284 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 63660438970 ps |
| CPU time | 1568.91 seconds |
| Started | Aug 25 04:26:21 PM UTC 24 |
| Finished | Aug 25 04:52:53 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506458284 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2506458284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3580579077 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 715437547 ps |
| CPU time | 40.99 seconds |
| Started | Aug 25 04:26:58 PM UTC 24 |
| Finished | Aug 25 04:27:40 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580579077 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.3580579077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_error_random.2398089403 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 596872352 ps |
| CPU time | 63.72 seconds |
| Started | Aug 25 04:26:41 PM UTC 24 |
| Finished | Aug 25 04:27:46 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398089403 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2398089403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random.483231352 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2576327461 ps |
| CPU time | 119.45 seconds |
| Started | Aug 25 04:25:48 PM UTC 24 |
| Finished | Aug 25 04:27:50 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483231352 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.483231352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_large_delays.3987321449 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 14756906939 ps |
| CPU time | 229 seconds |
| Started | Aug 25 04:26:19 PM UTC 24 |
| Finished | Aug 25 04:30:12 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987321449 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3987321449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.443024449 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 36234910292 ps |
| CPU time | 883.1 seconds |
| Started | Aug 25 04:26:19 PM UTC 24 |
| Finished | Aug 25 04:41:16 PM UTC 24 |
| Peak memory | 599392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443024449 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.443024449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_same_source.1104660048 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 277262129 ps |
| CPU time | 16.42 seconds |
| Started | Aug 25 04:26:29 PM UTC 24 |
| Finished | Aug 25 04:26:46 PM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104660048 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1104660048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke.425864511 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 39425580 ps |
| CPU time | 9.46 seconds |
| Started | Aug 25 04:25:43 PM UTC 24 |
| Finished | Aug 25 04:25:54 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425864511 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.425864511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_large_delays.4290517817 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 7930971110 ps |
| CPU time | 122.09 seconds |
| Started | Aug 25 04:25:48 PM UTC 24 |
| Finished | Aug 25 04:27:52 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290517817 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.4290517817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1155117671 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 4397364558 ps |
| CPU time | 108.36 seconds |
| Started | Aug 25 04:25:47 PM UTC 24 |
| Finished | Aug 25 04:27:38 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155117671 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1155117671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_smoke_zero_delays.874728922 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 51028163 ps |
| CPU time | 9.25 seconds |
| Started | Aug 25 04:25:45 PM UTC 24 |
| Finished | Aug 25 04:25:55 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874728922 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.874728922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all.3720049592 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 490740244 ps |
| CPU time | 61.59 seconds |
| Started | Aug 25 04:27:09 PM UTC 24 |
| Finished | Aug 25 04:28:13 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720049592 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3720049592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_error.620404318 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 966248197 ps |
| CPU time | 82.46 seconds |
| Started | Aug 25 04:27:13 PM UTC 24 |
| Finished | Aug 25 04:28:37 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620404318 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.620404318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2309264407 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3886697543 ps |
| CPU time | 431.17 seconds |
| Started | Aug 25 04:27:20 PM UTC 24 |
| Finished | Aug 25 04:34:38 PM UTC 24 |
| Peak memory | 599348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309264407 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2309264407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_unmapped_addr.873966596 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 707110215 ps |
| CPU time | 52.33 seconds |
| Started | Aug 25 04:26:44 PM UTC 24 |
| Finished | Aug 25 04:27:38 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873966596 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.873966596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1182433719 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 29648560531 ps |
| CPU time | 7930.37 seconds |
| Started | Aug 25 03:31:44 PM UTC 24 |
| Finished | Aug 25 05:45:48 PM UTC 24 |
| Peak memory | 621148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1182433719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_ csr_aliasing.1182433719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2322871147 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3527300700 ps |
| CPU time | 372.14 seconds |
| Started | Aug 25 03:31:41 PM UTC 24 |
| Finished | Aug 25 03:38:00 PM UTC 24 |
| Peak memory | 619964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2322871147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.chip_csr_bit_bash.2322871147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2255423092 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4682994375 ps |
| CPU time | 350.28 seconds |
| Started | Aug 25 03:34:05 PM UTC 24 |
| Finished | Aug 25 03:40:02 PM UTC 24 |
| Peak memory | 684020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255423092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_reset.2255423092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1434718378 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6000254100 ps |
| CPU time | 757.83 seconds |
| Started | Aug 25 03:34:17 PM UTC 24 |
| Finished | Aug 25 03:47:08 PM UTC 24 |
| Peak memory | 659060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1434718378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.chip_csr_mem_rw_with_rand_reset.1434718378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2424227036 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4072011528 ps |
| CPU time | 374.42 seconds |
| Started | Aug 25 03:34:13 PM UTC 24 |
| Finished | Aug 25 03:40:33 PM UTC 24 |
| Peak memory | 618116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424227036 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2424227036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.1131426715 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2455004996 ps |
| CPU time | 199.21 seconds |
| Started | Aug 25 03:31:48 PM UTC 24 |
| Finished | Aug 25 03:35:11 PM UTC 24 |
| Peak memory | 624184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131426715 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.1131426715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4029820738 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 315902407 ps |
| CPU time | 20.44 seconds |
| Started | Aug 25 03:33:38 PM UTC 24 |
| Finished | Aug 25 03:34:00 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029820738 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.4029820738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3131561882 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2632966872 ps |
| CPU time | 127.7 seconds |
| Started | Aug 25 03:33:16 PM UTC 24 |
| Finished | Aug 25 03:35:26 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131561882 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3131561882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.4228823655 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 526591249 ps |
| CPU time | 78.1 seconds |
| Started | Aug 25 03:32:15 PM UTC 24 |
| Finished | Aug 25 03:33:35 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228823655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.4228823655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.423828328 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 20517049109 ps |
| CPU time | 334.49 seconds |
| Started | Aug 25 03:32:24 PM UTC 24 |
| Finished | Aug 25 03:38:04 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423828328 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.423828328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3457099749 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 45118459867 ps |
| CPU time | 1050.62 seconds |
| Started | Aug 25 03:32:26 PM UTC 24 |
| Finished | Aug 25 03:50:13 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457099749 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3457099749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3021301323 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 228714998 ps |
| CPU time | 28.87 seconds |
| Started | Aug 25 03:32:25 PM UTC 24 |
| Finished | Aug 25 03:32:55 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021301323 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3021301323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.117795367 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 501832060 ps |
| CPU time | 60.01 seconds |
| Started | Aug 25 03:33:10 PM UTC 24 |
| Finished | Aug 25 03:34:12 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117795367 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.117795367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.3968352265 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 41768095 ps |
| CPU time | 8.81 seconds |
| Started | Aug 25 03:31:50 PM UTC 24 |
| Finished | Aug 25 03:32:00 PM UTC 24 |
| Peak memory | 597444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968352265 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3968352265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.979690379 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 5014464570 ps |
| CPU time | 103.32 seconds |
| Started | Aug 25 03:31:56 PM UTC 24 |
| Finished | Aug 25 03:33:41 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979690379 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.979690379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3651775298 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 4279091145 ps |
| CPU time | 106.29 seconds |
| Started | Aug 25 03:32:01 PM UTC 24 |
| Finished | Aug 25 03:33:50 PM UTC 24 |
| Peak memory | 597200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651775298 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3651775298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.366904538 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 53269233 ps |
| CPU time | 10.49 seconds |
| Started | Aug 25 03:31:53 PM UTC 24 |
| Finished | Aug 25 03:32:05 PM UTC 24 |
| Peak memory | 594400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366904538 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.366904538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1630598066 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 669239361 ps |
| CPU time | 68.51 seconds |
| Started | Aug 25 03:33:44 PM UTC 24 |
| Finished | Aug 25 03:34:54 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630598066 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1630598066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1391229787 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1784143664 ps |
| CPU time | 70.51 seconds |
| Started | Aug 25 03:33:55 PM UTC 24 |
| Finished | Aug 25 03:35:08 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391229787 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1391229787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2181034928 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 270661215 ps |
| CPU time | 91.82 seconds |
| Started | Aug 25 03:33:46 PM UTC 24 |
| Finished | Aug 25 03:35:20 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181034928 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.2181034928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.251137606 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 1783970263 ps |
| CPU time | 238.83 seconds |
| Started | Aug 25 03:34:01 PM UTC 24 |
| Finished | Aug 25 03:38:04 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251137606 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.251137606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.508445619 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1254725223 ps |
| CPU time | 82.11 seconds |
| Started | Aug 25 03:33:19 PM UTC 24 |
| Finished | Aug 25 03:34:44 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508445619 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.508445619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device.1135286500 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2281649555 ps |
| CPU time | 124.44 seconds |
| Started | Aug 25 04:28:15 PM UTC 24 |
| Finished | Aug 25 04:30:22 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135286500 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.1135286500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1669579837 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 10817149811 ps |
| CPU time | 257.11 seconds |
| Started | Aug 25 04:28:16 PM UTC 24 |
| Finished | Aug 25 04:32:38 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669579837 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1669579837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.511831047 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 1315610858 ps |
| CPU time | 58.23 seconds |
| Started | Aug 25 04:28:32 PM UTC 24 |
| Finished | Aug 25 04:29:32 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511831047 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.511831047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_error_random.2019376926 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 115775022 ps |
| CPU time | 11.25 seconds |
| Started | Aug 25 04:28:31 PM UTC 24 |
| Finished | Aug 25 04:28:43 PM UTC 24 |
| Peak memory | 597460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019376926 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2019376926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random.965971696 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 111875954 ps |
| CPU time | 18.53 seconds |
| Started | Aug 25 04:28:02 PM UTC 24 |
| Finished | Aug 25 04:28:22 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965971696 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.965971696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.311979301 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 47690069493 ps |
| CPU time | 780.71 seconds |
| Started | Aug 25 04:28:06 PM UTC 24 |
| Finished | Aug 25 04:41:18 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311979301 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.311979301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.3656691206 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 38777240405 ps |
| CPU time | 1011.83 seconds |
| Started | Aug 25 04:28:10 PM UTC 24 |
| Finished | Aug 25 04:45:18 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656691206 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3656691206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_zero_delays.2298004716 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 298628151 ps |
| CPU time | 43.69 seconds |
| Started | Aug 25 04:28:04 PM UTC 24 |
| Finished | Aug 25 04:28:49 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298004716 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.2298004716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_same_source.2101558085 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1620104858 ps |
| CPU time | 77.6 seconds |
| Started | Aug 25 04:28:18 PM UTC 24 |
| Finished | Aug 25 04:29:38 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101558085 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2101558085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke.969683741 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 40582957 ps |
| CPU time | 9.98 seconds |
| Started | Aug 25 04:27:22 PM UTC 24 |
| Finished | Aug 25 04:27:33 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969683741 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.969683741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_large_delays.3864501324 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 4952473372 ps |
| CPU time | 88 seconds |
| Started | Aug 25 04:28:00 PM UTC 24 |
| Finished | Aug 25 04:29:30 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864501324 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3864501324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.4194153840 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 6023876902 ps |
| CPU time | 136.3 seconds |
| Started | Aug 25 04:28:02 PM UTC 24 |
| Finished | Aug 25 04:30:21 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194153840 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.4194153840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_smoke_zero_delays.4112330898 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 46446195 ps |
| CPU time | 8.91 seconds |
| Started | Aug 25 04:27:58 PM UTC 24 |
| Finished | Aug 25 04:28:08 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112330898 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.4112330898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all.2945612145 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 3639305681 ps |
| CPU time | 191.46 seconds |
| Started | Aug 25 04:28:36 PM UTC 24 |
| Finished | Aug 25 04:31:51 PM UTC 24 |
| Peak memory | 599544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945612145 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2945612145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_error.417392497 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 3171903062 ps |
| CPU time | 316.49 seconds |
| Started | Aug 25 04:28:45 PM UTC 24 |
| Finished | Aug 25 04:34:07 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417392497 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.417392497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2978192453 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 178460789 ps |
| CPU time | 113.25 seconds |
| Started | Aug 25 04:28:37 PM UTC 24 |
| Finished | Aug 25 04:30:33 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978192453 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.2978192453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1452629846 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 689397458 ps |
| CPU time | 281.94 seconds |
| Started | Aug 25 04:28:45 PM UTC 24 |
| Finished | Aug 25 04:33:32 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452629846 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.1452629846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_unmapped_addr.2772879919 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 229684735 ps |
| CPU time | 45.59 seconds |
| Started | Aug 25 04:28:32 PM UTC 24 |
| Finished | Aug 25 04:29:19 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772879919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2772879919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device.2212925644 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 389997087 ps |
| CPU time | 45.41 seconds |
| Started | Aug 25 04:29:35 PM UTC 24 |
| Finished | Aug 25 04:30:22 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212925644 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.2212925644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3607507533 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 145921484144 ps |
| CPU time | 3164.19 seconds |
| Started | Aug 25 04:29:39 PM UTC 24 |
| Finished | Aug 25 05:23:03 PM UTC 24 |
| Peak memory | 600284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607507533 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3607507533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3951385308 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 657654842 ps |
| CPU time | 41.07 seconds |
| Started | Aug 25 04:29:56 PM UTC 24 |
| Finished | Aug 25 04:30:39 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951385308 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.3951385308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_error_random.1308785419 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 230206603 ps |
| CPU time | 33.44 seconds |
| Started | Aug 25 04:29:54 PM UTC 24 |
| Finished | Aug 25 04:30:29 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308785419 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1308785419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random.4050414473 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 193936975 ps |
| CPU time | 30.85 seconds |
| Started | Aug 25 04:29:13 PM UTC 24 |
| Finished | Aug 25 04:29:46 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050414473 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.4050414473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2312539911 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 96985699142 ps |
| CPU time | 1470.02 seconds |
| Started | Aug 25 04:29:34 PM UTC 24 |
| Finished | Aug 25 04:54:22 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312539911 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2312539911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_slow_rsp.1409581688 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 12826932349 ps |
| CPU time | 302.35 seconds |
| Started | Aug 25 04:29:33 PM UTC 24 |
| Finished | Aug 25 04:34:41 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409581688 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1409581688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_zero_delays.4124905947 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 453478681 ps |
| CPU time | 69.71 seconds |
| Started | Aug 25 04:29:15 PM UTC 24 |
| Finished | Aug 25 04:30:27 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124905947 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.4124905947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_same_source.230915550 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 361837314 ps |
| CPU time | 45.15 seconds |
| Started | Aug 25 04:29:43 PM UTC 24 |
| Finished | Aug 25 04:30:30 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230915550 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.230915550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke.2837836804 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 60954047 ps |
| CPU time | 11.88 seconds |
| Started | Aug 25 04:28:58 PM UTC 24 |
| Finished | Aug 25 04:29:11 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837836804 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2837836804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_large_delays.2315713022 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 9669192403 ps |
| CPU time | 145.52 seconds |
| Started | Aug 25 04:29:03 PM UTC 24 |
| Finished | Aug 25 04:31:31 PM UTC 24 |
| Peak memory | 597264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315713022 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2315713022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2115986146 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 4104785732 ps |
| CPU time | 93.2 seconds |
| Started | Aug 25 04:29:07 PM UTC 24 |
| Finished | Aug 25 04:30:43 PM UTC 24 |
| Peak memory | 597068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115986146 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2115986146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_smoke_zero_delays.4208042513 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 42666921 ps |
| CPU time | 10.18 seconds |
| Started | Aug 25 04:29:00 PM UTC 24 |
| Finished | Aug 25 04:29:12 PM UTC 24 |
| Peak memory | 597508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208042513 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.4208042513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all.4234483551 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 10078957745 ps |
| CPU time | 430.66 seconds |
| Started | Aug 25 04:30:01 PM UTC 24 |
| Finished | Aug 25 04:37:18 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234483551 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.4234483551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.1292654543 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 14132781482 ps |
| CPU time | 773.49 seconds |
| Started | Aug 25 04:30:20 PM UTC 24 |
| Finished | Aug 25 04:43:27 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292654543 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1292654543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1224836189 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 2860007577 ps |
| CPU time | 389.21 seconds |
| Started | Aug 25 04:30:10 PM UTC 24 |
| Finished | Aug 25 04:36:46 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224836189 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1224836189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_unmapped_addr.1338647948 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 75589444 ps |
| CPU time | 19.29 seconds |
| Started | Aug 25 04:29:55 PM UTC 24 |
| Finished | Aug 25 04:30:16 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338647948 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1338647948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device.3376045810 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 111004590 ps |
| CPU time | 22.61 seconds |
| Started | Aug 25 04:30:54 PM UTC 24 |
| Finished | Aug 25 04:31:18 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376045810 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3376045810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1363094321 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 117566233807 ps |
| CPU time | 2961.82 seconds |
| Started | Aug 25 04:30:54 PM UTC 24 |
| Finished | Aug 25 05:20:59 PM UTC 24 |
| Peak memory | 600012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363094321 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1363094321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3778045118 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 1001509683 ps |
| CPU time | 60.9 seconds |
| Started | Aug 25 04:31:05 PM UTC 24 |
| Finished | Aug 25 04:32:08 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778045118 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.3778045118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_error_random.752552349 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 402978618 ps |
| CPU time | 27.22 seconds |
| Started | Aug 25 04:31:00 PM UTC 24 |
| Finished | Aug 25 04:31:28 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752552349 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.752552349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random.75563337 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 261463010 ps |
| CPU time | 15.75 seconds |
| Started | Aug 25 04:30:46 PM UTC 24 |
| Finished | Aug 25 04:31:02 PM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75563337 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.75563337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.4216494993 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 50306696119 ps |
| CPU time | 730.47 seconds |
| Started | Aug 25 04:30:48 PM UTC 24 |
| Finished | Aug 25 04:43:09 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216494993 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.4216494993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2064830268 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 37645586761 ps |
| CPU time | 838.86 seconds |
| Started | Aug 25 04:30:52 PM UTC 24 |
| Finished | Aug 25 04:45:02 PM UTC 24 |
| Peak memory | 599556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064830268 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2064830268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_zero_delays.3330289558 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 478870633 ps |
| CPU time | 66.01 seconds |
| Started | Aug 25 04:30:47 PM UTC 24 |
| Finished | Aug 25 04:31:55 PM UTC 24 |
| Peak memory | 599480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330289558 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.3330289558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_same_source.2707162782 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 656469880 ps |
| CPU time | 34.36 seconds |
| Started | Aug 25 04:30:57 PM UTC 24 |
| Finished | Aug 25 04:31:33 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707162782 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2707162782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke.3272463300 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 166061944 ps |
| CPU time | 11.3 seconds |
| Started | Aug 25 04:30:39 PM UTC 24 |
| Finished | Aug 25 04:30:52 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272463300 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3272463300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_large_delays.2435848629 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 7359195632 ps |
| CPU time | 123.4 seconds |
| Started | Aug 25 04:30:46 PM UTC 24 |
| Finished | Aug 25 04:32:52 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435848629 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2435848629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.430280967 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 5042497868 ps |
| CPU time | 119.39 seconds |
| Started | Aug 25 04:30:45 PM UTC 24 |
| Finished | Aug 25 04:32:47 PM UTC 24 |
| Peak memory | 597344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430280967 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.430280967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_smoke_zero_delays.807399007 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 52676654 ps |
| CPU time | 10.86 seconds |
| Started | Aug 25 04:30:45 PM UTC 24 |
| Finished | Aug 25 04:30:57 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807399007 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.807399007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all.1978843971 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 681275691 ps |
| CPU time | 80.63 seconds |
| Started | Aug 25 04:31:08 PM UTC 24 |
| Finished | Aug 25 04:32:31 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978843971 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1978843971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_error.1097413857 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 9240105757 ps |
| CPU time | 403.45 seconds |
| Started | Aug 25 04:31:15 PM UTC 24 |
| Finished | Aug 25 04:38:04 PM UTC 24 |
| Peak memory | 599372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097413857 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1097413857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.313242117 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 632272942 ps |
| CPU time | 486.05 seconds |
| Started | Aug 25 04:31:09 PM UTC 24 |
| Finished | Aug 25 04:39:24 PM UTC 24 |
| Peak memory | 599496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313242117 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.313242117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.4255788954 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 888024694 ps |
| CPU time | 56.01 seconds |
| Started | Aug 25 04:31:19 PM UTC 24 |
| Finished | Aug 25 04:32:17 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255788954 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.4255788954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_unmapped_addr.1690213088 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 128562532 ps |
| CPU time | 25.91 seconds |
| Started | Aug 25 04:31:03 PM UTC 24 |
| Finished | Aug 25 04:31:30 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690213088 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1690213088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device.265030998 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 933533931 ps |
| CPU time | 118.68 seconds |
| Started | Aug 25 04:31:53 PM UTC 24 |
| Finished | Aug 25 04:33:54 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265030998 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.265030998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1081377225 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 57786125490 ps |
| CPU time | 1212.5 seconds |
| Started | Aug 25 04:31:55 PM UTC 24 |
| Finished | Aug 25 04:52:23 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081377225 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1081377225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3609058196 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 496110284 ps |
| CPU time | 33.04 seconds |
| Started | Aug 25 04:31:57 PM UTC 24 |
| Finished | Aug 25 04:32:32 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609058196 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3609058196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_error_random.1236786939 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 1174351987 ps |
| CPU time | 64.82 seconds |
| Started | Aug 25 04:31:56 PM UTC 24 |
| Finished | Aug 25 04:33:03 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236786939 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1236786939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random.2199525429 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 1593736336 ps |
| CPU time | 81.09 seconds |
| Started | Aug 25 04:31:40 PM UTC 24 |
| Finished | Aug 25 04:33:03 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199525429 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2199525429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_large_delays.4243269967 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 30848353130 ps |
| CPU time | 470.23 seconds |
| Started | Aug 25 04:31:43 PM UTC 24 |
| Finished | Aug 25 04:39:40 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243269967 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4243269967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_slow_rsp.3169199778 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 20732613434 ps |
| CPU time | 510.62 seconds |
| Started | Aug 25 04:31:44 PM UTC 24 |
| Finished | Aug 25 04:40:23 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169199778 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3169199778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_random_zero_delays.4053974654 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 559614015 ps |
| CPU time | 61.16 seconds |
| Started | Aug 25 04:31:39 PM UTC 24 |
| Finished | Aug 25 04:32:42 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053974654 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.4053974654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_same_source.309188527 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 2575750044 ps |
| CPU time | 115.11 seconds |
| Started | Aug 25 04:31:56 PM UTC 24 |
| Finished | Aug 25 04:33:54 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309188527 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.309188527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke.1510580465 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 50742248 ps |
| CPU time | 10.36 seconds |
| Started | Aug 25 04:31:21 PM UTC 24 |
| Finished | Aug 25 04:31:32 PM UTC 24 |
| Peak memory | 597188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510580465 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1510580465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_large_delays.1425872718 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 5123622629 ps |
| CPU time | 81.79 seconds |
| Started | Aug 25 04:31:26 PM UTC 24 |
| Finished | Aug 25 04:32:50 PM UTC 24 |
| Peak memory | 597364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425872718 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1425872718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2374617739 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 5916705292 ps |
| CPU time | 127.57 seconds |
| Started | Aug 25 04:31:32 PM UTC 24 |
| Finished | Aug 25 04:33:42 PM UTC 24 |
| Peak memory | 597328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374617739 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2374617739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_smoke_zero_delays.737817141 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 44816580 ps |
| CPU time | 10.15 seconds |
| Started | Aug 25 04:31:21 PM UTC 24 |
| Finished | Aug 25 04:31:33 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737817141 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.737817141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.4137892648 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 11772093952 ps |
| CPU time | 569.85 seconds |
| Started | Aug 25 04:32:15 PM UTC 24 |
| Finished | Aug 25 04:41:54 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137892648 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.4137892648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_error.1469318405 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 2498654797 ps |
| CPU time | 305.11 seconds |
| Started | Aug 25 04:32:32 PM UTC 24 |
| Finished | Aug 25 04:37:43 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469318405 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1469318405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2343074783 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 10173116782 ps |
| CPU time | 1724.36 seconds |
| Started | Aug 25 04:32:19 PM UTC 24 |
| Finished | Aug 25 05:01:30 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343074783 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2343074783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1213263256 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 149511687 ps |
| CPU time | 87.56 seconds |
| Started | Aug 25 04:32:40 PM UTC 24 |
| Finished | Aug 25 04:34:09 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213263256 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1213263256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_unmapped_addr.2176624223 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 146153696 ps |
| CPU time | 31.67 seconds |
| Started | Aug 25 04:31:56 PM UTC 24 |
| Finished | Aug 25 04:32:29 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176624223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2176624223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device.4198904628 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 14552944 ps |
| CPU time | 9.8 seconds |
| Started | Aug 25 04:33:16 PM UTC 24 |
| Finished | Aug 25 04:33:27 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198904628 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.4198904628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1846822592 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 107483893604 ps |
| CPU time | 2747.82 seconds |
| Started | Aug 25 04:33:18 PM UTC 24 |
| Finished | Aug 25 05:19:46 PM UTC 24 |
| Peak memory | 599912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846822592 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.1846822592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2374894141 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 1230560761 ps |
| CPU time | 86.86 seconds |
| Started | Aug 25 04:33:28 PM UTC 24 |
| Finished | Aug 25 04:34:57 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374894141 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2374894141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_error_random.153290291 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 604294224 ps |
| CPU time | 72.56 seconds |
| Started | Aug 25 04:33:20 PM UTC 24 |
| Finished | Aug 25 04:34:35 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153290291 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.153290291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random.1930692544 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 277217787 ps |
| CPU time | 39.22 seconds |
| Started | Aug 25 04:32:57 PM UTC 24 |
| Finished | Aug 25 04:33:38 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930692544 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1930692544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.4053121807 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 114049104472 ps |
| CPU time | 1509.39 seconds |
| Started | Aug 25 04:33:05 PM UTC 24 |
| Finished | Aug 25 04:58:34 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053121807 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.4053121807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2089393275 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 40475995962 ps |
| CPU time | 1022.66 seconds |
| Started | Aug 25 04:33:11 PM UTC 24 |
| Finished | Aug 25 04:50:31 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089393275 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2089393275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_zero_delays.1151815045 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 201182136 ps |
| CPU time | 29.53 seconds |
| Started | Aug 25 04:33:02 PM UTC 24 |
| Finished | Aug 25 04:33:33 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151815045 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.1151815045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_same_source.2607148773 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 261381408 ps |
| CPU time | 34.48 seconds |
| Started | Aug 25 04:33:15 PM UTC 24 |
| Finished | Aug 25 04:33:51 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607148773 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2607148773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke.3139365211 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 161307788 ps |
| CPU time | 11.39 seconds |
| Started | Aug 25 04:32:43 PM UTC 24 |
| Finished | Aug 25 04:32:55 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139365211 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3139365211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_large_delays.261640571 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 9151638988 ps |
| CPU time | 140.53 seconds |
| Started | Aug 25 04:32:54 PM UTC 24 |
| Finished | Aug 25 04:35:17 PM UTC 24 |
| Peak memory | 597572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261640571 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.261640571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3974346219 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 5195513281 ps |
| CPU time | 126.1 seconds |
| Started | Aug 25 04:32:56 PM UTC 24 |
| Finished | Aug 25 04:35:05 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974346219 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3974346219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2788485352 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 44800357 ps |
| CPU time | 8.84 seconds |
| Started | Aug 25 04:32:47 PM UTC 24 |
| Finished | Aug 25 04:32:57 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788485352 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.2788485352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all.2534311682 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 530294805 ps |
| CPU time | 84.46 seconds |
| Started | Aug 25 04:33:28 PM UTC 24 |
| Finished | Aug 25 04:34:55 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534311682 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2534311682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_error.199431863 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 2674738415 ps |
| CPU time | 319.53 seconds |
| Started | Aug 25 04:33:51 PM UTC 24 |
| Finished | Aug 25 04:39:17 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199431863 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.199431863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.415346569 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 310649524 ps |
| CPU time | 184.15 seconds |
| Started | Aug 25 04:33:38 PM UTC 24 |
| Finished | Aug 25 04:36:46 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415346569 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.415346569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2184693674 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 6162346654 ps |
| CPU time | 424.2 seconds |
| Started | Aug 25 04:33:57 PM UTC 24 |
| Finished | Aug 25 04:41:08 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184693674 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2184693674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_unmapped_addr.352675401 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 904106600 ps |
| CPU time | 59.47 seconds |
| Started | Aug 25 04:33:21 PM UTC 24 |
| Finished | Aug 25 04:34:22 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352675401 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.352675401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device.2127680760 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 2314034982 ps |
| CPU time | 110.98 seconds |
| Started | Aug 25 04:34:32 PM UTC 24 |
| Finished | Aug 25 04:36:26 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127680760 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2127680760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.4190471423 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 125246005764 ps |
| CPU time | 2740.02 seconds |
| Started | Aug 25 04:34:35 PM UTC 24 |
| Finished | Aug 25 05:20:52 PM UTC 24 |
| Peak memory | 600092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190471423 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.4190471423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3270339518 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 217142981 ps |
| CPU time | 36.44 seconds |
| Started | Aug 25 04:34:52 PM UTC 24 |
| Finished | Aug 25 04:35:30 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270339518 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.3270339518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_error_random.3418151074 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 1951814839 ps |
| CPU time | 109.97 seconds |
| Started | Aug 25 04:34:46 PM UTC 24 |
| Finished | Aug 25 04:36:39 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418151074 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.3418151074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random.1952017443 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 568191785 ps |
| CPU time | 77.82 seconds |
| Started | Aug 25 04:34:16 PM UTC 24 |
| Finished | Aug 25 04:35:36 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952017443 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1952017443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3636916706 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 102827164044 ps |
| CPU time | 1507.17 seconds |
| Started | Aug 25 04:34:19 PM UTC 24 |
| Finished | Aug 25 04:59:45 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636916706 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3636916706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_slow_rsp.4290351858 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 4635586450 ps |
| CPU time | 116.78 seconds |
| Started | Aug 25 04:34:31 PM UTC 24 |
| Finished | Aug 25 04:36:30 PM UTC 24 |
| Peak memory | 597628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290351858 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4290351858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_zero_delays.99094355 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 352840755 ps |
| CPU time | 44.9 seconds |
| Started | Aug 25 04:34:17 PM UTC 24 |
| Finished | Aug 25 04:35:03 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99094355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.99094355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_same_source.259358748 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 170127645 ps |
| CPU time | 23.54 seconds |
| Started | Aug 25 04:34:36 PM UTC 24 |
| Finished | Aug 25 04:35:01 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259358748 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.259358748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke.571372363 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 44909697 ps |
| CPU time | 10.02 seconds |
| Started | Aug 25 04:33:56 PM UTC 24 |
| Finished | Aug 25 04:34:07 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571372363 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.571372363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_large_delays.3563521192 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 10008165651 ps |
| CPU time | 179.15 seconds |
| Started | Aug 25 04:34:02 PM UTC 24 |
| Finished | Aug 25 04:37:05 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563521192 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3563521192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4249238542 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 5978507806 ps |
| CPU time | 149.02 seconds |
| Started | Aug 25 04:34:06 PM UTC 24 |
| Finished | Aug 25 04:36:38 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249238542 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4249238542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_smoke_zero_delays.212475040 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 48294880 ps |
| CPU time | 9.49 seconds |
| Started | Aug 25 04:34:02 PM UTC 24 |
| Finished | Aug 25 04:34:12 PM UTC 24 |
| Peak memory | 597344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212475040 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.212475040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3181968253 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 6640273828 ps |
| CPU time | 399.52 seconds |
| Started | Aug 25 04:34:56 PM UTC 24 |
| Finished | Aug 25 04:41:43 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181968253 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3181968253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_error.1052660989 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 7416808597 ps |
| CPU time | 310.33 seconds |
| Started | Aug 25 04:35:01 PM UTC 24 |
| Finished | Aug 25 04:40:17 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052660989 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1052660989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.4244434958 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 594894240 ps |
| CPU time | 364.23 seconds |
| Started | Aug 25 04:35:02 PM UTC 24 |
| Finished | Aug 25 04:41:12 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244434958 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.4244434958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3980745395 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 1733255320 ps |
| CPU time | 458.27 seconds |
| Started | Aug 25 04:35:03 PM UTC 24 |
| Finished | Aug 25 04:42:49 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980745395 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3980745395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_unmapped_addr.1380334573 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 69433752 ps |
| CPU time | 7.91 seconds |
| Started | Aug 25 04:34:47 PM UTC 24 |
| Finished | Aug 25 04:34:56 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380334573 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1380334573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device.2244050579 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 156351915 ps |
| CPU time | 20.87 seconds |
| Started | Aug 25 04:35:41 PM UTC 24 |
| Finished | Aug 25 04:36:03 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244050579 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2244050579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1343132973 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 95216593203 ps |
| CPU time | 2041.7 seconds |
| Started | Aug 25 04:35:43 PM UTC 24 |
| Finished | Aug 25 05:10:11 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343132973 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1343132973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3120923966 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 162029969 ps |
| CPU time | 30.69 seconds |
| Started | Aug 25 04:36:00 PM UTC 24 |
| Finished | Aug 25 04:36:33 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120923966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.3120923966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_error_random.2449479394 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 489897114 ps |
| CPU time | 28.6 seconds |
| Started | Aug 25 04:35:53 PM UTC 24 |
| Finished | Aug 25 04:36:23 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449479394 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2449479394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random.2753239841 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 157278638 ps |
| CPU time | 13.64 seconds |
| Started | Aug 25 04:35:20 PM UTC 24 |
| Finished | Aug 25 04:35:35 PM UTC 24 |
| Peak memory | 597400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753239841 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2753239841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2787812414 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 30972565199 ps |
| CPU time | 547.52 seconds |
| Started | Aug 25 04:35:28 PM UTC 24 |
| Finished | Aug 25 04:44:45 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787812414 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2787812414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.3567212123 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 63585797693 ps |
| CPU time | 1644.18 seconds |
| Started | Aug 25 04:35:29 PM UTC 24 |
| Finished | Aug 25 05:03:18 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567212123 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3567212123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_zero_delays.3632815707 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 543902817 ps |
| CPU time | 70.93 seconds |
| Started | Aug 25 04:35:26 PM UTC 24 |
| Finished | Aug 25 04:36:39 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632815707 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3632815707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_same_source.3056871255 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 224658354 ps |
| CPU time | 29.18 seconds |
| Started | Aug 25 04:35:53 PM UTC 24 |
| Finished | Aug 25 04:36:24 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056871255 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3056871255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke.1653144387 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 157082408 ps |
| CPU time | 12.99 seconds |
| Started | Aug 25 04:35:05 PM UTC 24 |
| Finished | Aug 25 04:35:19 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653144387 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1653144387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_large_delays.2883605629 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 9572962322 ps |
| CPU time | 170.13 seconds |
| Started | Aug 25 04:35:19 PM UTC 24 |
| Finished | Aug 25 04:38:13 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883605629 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2883605629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.792420588 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 3267702015 ps |
| CPU time | 67.1 seconds |
| Started | Aug 25 04:35:16 PM UTC 24 |
| Finished | Aug 25 04:36:25 PM UTC 24 |
| Peak memory | 597408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792420588 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.792420588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_smoke_zero_delays.956458819 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 40925121 ps |
| CPU time | 9.29 seconds |
| Started | Aug 25 04:35:19 PM UTC 24 |
| Finished | Aug 25 04:35:30 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956458819 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.956458819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all.2998939893 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 3774758937 ps |
| CPU time | 164.24 seconds |
| Started | Aug 25 04:36:28 PM UTC 24 |
| Finished | Aug 25 04:39:15 PM UTC 24 |
| Peak memory | 599356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998939893 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2998939893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2143875226 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 3003030698 ps |
| CPU time | 360.18 seconds |
| Started | Aug 25 04:36:48 PM UTC 24 |
| Finished | Aug 25 04:42:55 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143875226 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2143875226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.152446244 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 147386603 ps |
| CPU time | 115.42 seconds |
| Started | Aug 25 04:36:31 PM UTC 24 |
| Finished | Aug 25 04:38:30 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152446244 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.152446244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3591212757 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6908612779 ps |
| CPU time | 729.73 seconds |
| Started | Aug 25 04:36:48 PM UTC 24 |
| Finished | Aug 25 04:49:10 PM UTC 24 |
| Peak memory | 599480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591212757 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3591212757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_unmapped_addr.730384906 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 1293486207 ps |
| CPU time | 71.72 seconds |
| Started | Aug 25 04:35:57 PM UTC 24 |
| Finished | Aug 25 04:37:11 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730384906 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.730384906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device.516307540 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 107609958 ps |
| CPU time | 20.38 seconds |
| Started | Aug 25 04:37:11 PM UTC 24 |
| Finished | Aug 25 04:37:33 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516307540 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.516307540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.346279090 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 31496296366 ps |
| CPU time | 693 seconds |
| Started | Aug 25 04:37:14 PM UTC 24 |
| Finished | Aug 25 04:48:57 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346279090 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.346279090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2858320796 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 1106278219 ps |
| CPU time | 57.54 seconds |
| Started | Aug 25 04:37:27 PM UTC 24 |
| Finished | Aug 25 04:38:27 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858320796 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2858320796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_error_random.3259381517 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 255555225 ps |
| CPU time | 33.64 seconds |
| Started | Aug 25 04:37:21 PM UTC 24 |
| Finished | Aug 25 04:37:57 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259381517 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3259381517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random.2593635353 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 275810967 ps |
| CPU time | 22.91 seconds |
| Started | Aug 25 04:37:02 PM UTC 24 |
| Finished | Aug 25 04:37:26 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593635353 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2593635353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2830358823 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 78892949862 ps |
| CPU time | 1313.49 seconds |
| Started | Aug 25 04:37:04 PM UTC 24 |
| Finished | Aug 25 04:59:17 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830358823 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2830358823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.3815820347 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 47259366720 ps |
| CPU time | 1080 seconds |
| Started | Aug 25 04:37:11 PM UTC 24 |
| Finished | Aug 25 04:55:27 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815820347 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3815820347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_zero_delays.3097086150 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 575119365 ps |
| CPU time | 76.68 seconds |
| Started | Aug 25 04:37:03 PM UTC 24 |
| Finished | Aug 25 04:38:22 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097086150 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3097086150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_same_source.2896681175 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 70379492 ps |
| CPU time | 10.71 seconds |
| Started | Aug 25 04:37:17 PM UTC 24 |
| Finished | Aug 25 04:37:29 PM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896681175 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2896681175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke.2564845921 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 221771165 ps |
| CPU time | 14.02 seconds |
| Started | Aug 25 04:36:50 PM UTC 24 |
| Finished | Aug 25 04:37:05 PM UTC 24 |
| Peak memory | 597204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564845921 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2564845921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_large_delays.1129540354 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 10193600603 ps |
| CPU time | 174.55 seconds |
| Started | Aug 25 04:36:55 PM UTC 24 |
| Finished | Aug 25 04:39:53 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129540354 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1129540354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.560843538 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 4199678612 ps |
| CPU time | 109.69 seconds |
| Started | Aug 25 04:36:57 PM UTC 24 |
| Finished | Aug 25 04:38:49 PM UTC 24 |
| Peak memory | 597284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560843538 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.560843538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1223253221 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 47691880 ps |
| CPU time | 8.91 seconds |
| Started | Aug 25 04:36:50 PM UTC 24 |
| Finished | Aug 25 04:37:00 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223253221 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1223253221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.353230561 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 3804950814 ps |
| CPU time | 381.25 seconds |
| Started | Aug 25 04:37:27 PM UTC 24 |
| Finished | Aug 25 04:43:55 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353230561 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.353230561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3042391923 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 6179966735 ps |
| CPU time | 331.44 seconds |
| Started | Aug 25 04:37:43 PM UTC 24 |
| Finished | Aug 25 04:43:20 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042391923 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3042391923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_unmapped_addr.1689112568 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 1525689522 ps |
| CPU time | 89.91 seconds |
| Started | Aug 25 04:37:24 PM UTC 24 |
| Finished | Aug 25 04:38:56 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689112568 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1689112568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device.638870417 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 1642711451 ps |
| CPU time | 100.03 seconds |
| Started | Aug 25 04:38:37 PM UTC 24 |
| Finished | Aug 25 04:40:19 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638870417 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.638870417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2627021245 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 35744401690 ps |
| CPU time | 788.01 seconds |
| Started | Aug 25 04:38:42 PM UTC 24 |
| Finished | Aug 25 04:52:01 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627021245 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2627021245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.69876392 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 211446720 ps |
| CPU time | 30.64 seconds |
| Started | Aug 25 04:39:12 PM UTC 24 |
| Finished | Aug 25 04:39:43 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69876392 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.69876392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_error_random.1125052563 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 42719496 ps |
| CPU time | 8.74 seconds |
| Started | Aug 25 04:38:49 PM UTC 24 |
| Finished | Aug 25 04:39:00 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125052563 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.1125052563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random.1106479804 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 521866954 ps |
| CPU time | 55.53 seconds |
| Started | Aug 25 04:38:29 PM UTC 24 |
| Finished | Aug 25 04:39:26 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106479804 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1106479804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.741433993 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 107623257364 ps |
| CPU time | 1720.66 seconds |
| Started | Aug 25 04:38:31 PM UTC 24 |
| Finished | Aug 25 05:07:33 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741433993 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.741433993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.3825767152 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 67336290043 ps |
| CPU time | 1692.1 seconds |
| Started | Aug 25 04:38:33 PM UTC 24 |
| Finished | Aug 25 05:07:10 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825767152 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3825767152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_zero_delays.684289038 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 215356912 ps |
| CPU time | 32.74 seconds |
| Started | Aug 25 04:38:30 PM UTC 24 |
| Finished | Aug 25 04:39:04 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684289038 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.684289038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_same_source.191372256 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 520862685 ps |
| CPU time | 21.45 seconds |
| Started | Aug 25 04:38:46 PM UTC 24 |
| Finished | Aug 25 04:39:09 PM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191372256 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.191372256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke.1351510550 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 238655710 ps |
| CPU time | 14.11 seconds |
| Started | Aug 25 04:37:53 PM UTC 24 |
| Finished | Aug 25 04:38:08 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351510550 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1351510550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_large_delays.3450911756 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 7965153928 ps |
| CPU time | 129.9 seconds |
| Started | Aug 25 04:38:06 PM UTC 24 |
| Finished | Aug 25 04:40:19 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450911756 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3450911756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3571853617 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4988363687 ps |
| CPU time | 119.73 seconds |
| Started | Aug 25 04:38:21 PM UTC 24 |
| Finished | Aug 25 04:40:23 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571853617 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3571853617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1527045986 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 45088373 ps |
| CPU time | 9.19 seconds |
| Started | Aug 25 04:37:56 PM UTC 24 |
| Finished | Aug 25 04:38:06 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527045986 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1527045986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all.1295943829 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 2360548989 ps |
| CPU time | 98.98 seconds |
| Started | Aug 25 04:39:20 PM UTC 24 |
| Finished | Aug 25 04:41:01 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295943829 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1295943829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1578328797 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 3184350908 ps |
| CPU time | 365.58 seconds |
| Started | Aug 25 04:39:27 PM UTC 24 |
| Finished | Aug 25 04:45:40 PM UTC 24 |
| Peak memory | 599360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578328797 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1578328797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.531503885 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 14690044113 ps |
| CPU time | 1095.15 seconds |
| Started | Aug 25 04:39:23 PM UTC 24 |
| Finished | Aug 25 04:57:56 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531503885 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.531503885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3443749705 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 9232304498 ps |
| CPU time | 848.58 seconds |
| Started | Aug 25 04:39:31 PM UTC 24 |
| Finished | Aug 25 04:53:54 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443749705 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.3443749705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_unmapped_addr.4073773896 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 1233210659 ps |
| CPU time | 80.94 seconds |
| Started | Aug 25 04:38:51 PM UTC 24 |
| Finished | Aug 25 04:40:15 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073773896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4073773896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.4022173387 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 1697592452 ps |
| CPU time | 112.02 seconds |
| Started | Aug 25 04:40:17 PM UTC 24 |
| Finished | Aug 25 04:42:12 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022173387 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.4022173387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.4268325085 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 104857318629 ps |
| CPU time | 2526.93 seconds |
| Started | Aug 25 04:40:17 PM UTC 24 |
| Finished | Aug 25 05:23:01 PM UTC 24 |
| Peak memory | 600164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268325085 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.4268325085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.789301490 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 63139857 ps |
| CPU time | 15.33 seconds |
| Started | Aug 25 04:40:42 PM UTC 24 |
| Finished | Aug 25 04:40:59 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789301490 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.789301490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1519856616 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 558868173 ps |
| CPU time | 31.36 seconds |
| Started | Aug 25 04:40:38 PM UTC 24 |
| Finished | Aug 25 04:41:12 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519856616 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1519856616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random.535446577 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 784439222 ps |
| CPU time | 43.95 seconds |
| Started | Aug 25 04:39:49 PM UTC 24 |
| Finished | Aug 25 04:40:35 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535446577 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.535446577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1429023540 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 70181916293 ps |
| CPU time | 1041.27 seconds |
| Started | Aug 25 04:40:08 PM UTC 24 |
| Finished | Aug 25 04:57:44 PM UTC 24 |
| Peak memory | 599600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429023540 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1429023540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.2741996854 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 25670081373 ps |
| CPU time | 622.15 seconds |
| Started | Aug 25 04:40:13 PM UTC 24 |
| Finished | Aug 25 04:50:45 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741996854 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2741996854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_zero_delays.1712386764 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 131766052 ps |
| CPU time | 18.62 seconds |
| Started | Aug 25 04:40:04 PM UTC 24 |
| Finished | Aug 25 04:40:24 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712386764 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1712386764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_same_source.3426042383 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 100656537 ps |
| CPU time | 16.48 seconds |
| Started | Aug 25 04:40:35 PM UTC 24 |
| Finished | Aug 25 04:40:53 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426042383 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3426042383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke.1080135338 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 57128139 ps |
| CPU time | 9.67 seconds |
| Started | Aug 25 04:39:38 PM UTC 24 |
| Finished | Aug 25 04:39:50 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080135338 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1080135338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3217892138 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 9084428535 ps |
| CPU time | 140.45 seconds |
| Started | Aug 25 04:39:45 PM UTC 24 |
| Finished | Aug 25 04:42:08 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217892138 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3217892138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.181376988 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 6310787199 ps |
| CPU time | 177.7 seconds |
| Started | Aug 25 04:39:48 PM UTC 24 |
| Finished | Aug 25 04:42:50 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181376988 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.181376988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3863790680 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 54419079 ps |
| CPU time | 10.92 seconds |
| Started | Aug 25 04:39:41 PM UTC 24 |
| Finished | Aug 25 04:39:53 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863790680 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.3863790680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.572946394 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 4630480293 ps |
| CPU time | 204.27 seconds |
| Started | Aug 25 04:40:43 PM UTC 24 |
| Finished | Aug 25 04:44:12 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572946394 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.572946394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.670509251 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 814980198 ps |
| CPU time | 87.23 seconds |
| Started | Aug 25 04:40:47 PM UTC 24 |
| Finished | Aug 25 04:42:17 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670509251 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.670509251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.597899127 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4401479263 ps |
| CPU time | 722.39 seconds |
| Started | Aug 25 04:40:47 PM UTC 24 |
| Finished | Aug 25 04:53:01 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597899127 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.597899127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2598083938 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 2824679586 ps |
| CPU time | 154.35 seconds |
| Started | Aug 25 04:40:48 PM UTC 24 |
| Finished | Aug 25 04:43:25 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598083938 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.2598083938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1306970732 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 851053342 ps |
| CPU time | 61.14 seconds |
| Started | Aug 25 04:40:41 PM UTC 24 |
| Finished | Aug 25 04:41:45 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306970732 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1306970732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_aliasing.2677758747 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 37383731544 ps |
| CPU time | 8243.2 seconds |
| Started | Aug 25 03:34:32 PM UTC 24 |
| Finished | Aug 25 05:53:45 PM UTC 24 |
| Peak memory | 620924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 + stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2677758747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_ csr_aliasing.2677758747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_bit_bash.3587077403 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 60258740588 ps |
| CPU time | 9543.34 seconds |
| Started | Aug 25 03:34:23 PM UTC 24 |
| Finished | Aug 25 06:15:39 PM UTC 24 |
| Peak memory | 621152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_b it_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3587077403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_bit_bash.3587077403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.219452359 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 9088814214 ps |
| CPU time | 1043.13 seconds |
| Started | Aug 25 03:36:17 PM UTC 24 |
| Finished | Aug 25 03:53:56 PM UTC 24 |
| Peak memory | 673648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=219452359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.219452359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3852371839 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 6438994721 ps |
| CPU time | 1059.13 seconds |
| Started | Aug 25 03:36:11 PM UTC 24 |
| Finished | Aug 25 03:54:08 PM UTC 24 |
| Peak memory | 620224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852371839 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3852371839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2570179048 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 29645192008 ps |
| CPU time | 5522.81 seconds |
| Started | Aug 25 03:34:35 PM UTC 24 |
| Finished | Aug 25 05:07:52 PM UTC 24 |
| Peak memory | 614780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2570179048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.chip_same_csr_outstanding.2570179048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3157500361 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 3024433911 ps |
| CPU time | 326.81 seconds |
| Started | Aug 25 03:34:35 PM UTC 24 |
| Finished | Aug 25 03:40:07 PM UTC 24 |
| Peak memory | 624324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157500361 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3157500361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.210472819 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2257014981 ps |
| CPU time | 107.51 seconds |
| Started | Aug 25 03:35:17 PM UTC 24 |
| Finished | Aug 25 03:37:07 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210472819 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.210472819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3925263076 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 600520400 ps |
| CPU time | 45.64 seconds |
| Started | Aug 25 03:35:36 PM UTC 24 |
| Finished | Aug 25 03:36:23 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925263076 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3925263076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.440876767 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 64315254 ps |
| CPU time | 11.31 seconds |
| Started | Aug 25 03:35:24 PM UTC 24 |
| Finished | Aug 25 03:35:36 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440876767 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.440876767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.3536037635 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 335472865 ps |
| CPU time | 19.11 seconds |
| Started | Aug 25 03:35:09 PM UTC 24 |
| Finished | Aug 25 03:35:29 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536037635 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3536037635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.732488969 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4019683972 ps |
| CPU time | 71.25 seconds |
| Started | Aug 25 03:35:11 PM UTC 24 |
| Finished | Aug 25 03:36:24 PM UTC 24 |
| Peak memory | 597516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732488969 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.732488969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.3765526130 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 27255956488 ps |
| CPU time | 717.33 seconds |
| Started | Aug 25 03:35:17 PM UTC 24 |
| Finished | Aug 25 03:47:26 PM UTC 24 |
| Peak memory | 599368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765526130 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3765526130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.782243399 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 352557413 ps |
| CPU time | 38.57 seconds |
| Started | Aug 25 03:35:08 PM UTC 24 |
| Finished | Aug 25 03:35:48 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782243399 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.782243399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1620129118 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1713241333 ps |
| CPU time | 75.84 seconds |
| Started | Aug 25 03:35:23 PM UTC 24 |
| Finished | Aug 25 03:36:41 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620129118 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1620129118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2496058067 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 47579754 ps |
| CPU time | 8.84 seconds |
| Started | Aug 25 03:34:42 PM UTC 24 |
| Finished | Aug 25 03:34:52 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496058067 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2496058067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.3822900251 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 7301031699 ps |
| CPU time | 125.47 seconds |
| Started | Aug 25 03:34:49 PM UTC 24 |
| Finished | Aug 25 03:36:57 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822900251 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3822900251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3073761010 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5222647754 ps |
| CPU time | 125.32 seconds |
| Started | Aug 25 03:35:05 PM UTC 24 |
| Finished | Aug 25 03:37:13 PM UTC 24 |
| Peak memory | 597396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073761010 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3073761010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3018557572 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 50396845 ps |
| CPU time | 10.21 seconds |
| Started | Aug 25 03:34:48 PM UTC 24 |
| Finished | Aug 25 03:35:00 PM UTC 24 |
| Peak memory | 597184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018557572 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3018557572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.1365834424 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 7690211531 ps |
| CPU time | 301.16 seconds |
| Started | Aug 25 03:35:43 PM UTC 24 |
| Finished | Aug 25 03:40:49 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365834424 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1365834424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3364481075 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 10304000433 ps |
| CPU time | 541.74 seconds |
| Started | Aug 25 03:35:53 PM UTC 24 |
| Finished | Aug 25 03:45:03 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364481075 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3364481075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.977247066 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1513706141 ps |
| CPU time | 272.9 seconds |
| Started | Aug 25 03:35:50 PM UTC 24 |
| Finished | Aug 25 03:40:27 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977247066 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.977247066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2755964074 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1461343907 ps |
| CPU time | 286.41 seconds |
| Started | Aug 25 03:36:00 PM UTC 24 |
| Finished | Aug 25 03:40:51 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755964074 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2755964074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3776987055 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 277007655 ps |
| CPU time | 25.47 seconds |
| Started | Aug 25 03:35:31 PM UTC 24 |
| Finished | Aug 25 03:35:57 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776987055 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3776987055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.4008122797 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1364059510 ps |
| CPU time | 84.68 seconds |
| Started | Aug 25 04:41:37 PM UTC 24 |
| Finished | Aug 25 04:43:04 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008122797 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.4008122797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3028566323 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 61365035464 ps |
| CPU time | 1485.56 seconds |
| Started | Aug 25 04:41:41 PM UTC 24 |
| Finished | Aug 25 05:06:48 PM UTC 24 |
| Peak memory | 599644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028566323 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3028566323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3274388762 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 1040927312 ps |
| CPU time | 56.22 seconds |
| Started | Aug 25 04:42:09 PM UTC 24 |
| Finished | Aug 25 04:43:07 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274388762 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.3274388762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.2786481002 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 107003642 ps |
| CPU time | 9.55 seconds |
| Started | Aug 25 04:41:45 PM UTC 24 |
| Finished | Aug 25 04:41:56 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786481002 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2786481002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.4055608332 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 304232105 ps |
| CPU time | 44.72 seconds |
| Started | Aug 25 04:41:26 PM UTC 24 |
| Finished | Aug 25 04:42:12 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055608332 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.4055608332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2295098404 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 61436998520 ps |
| CPU time | 1078.54 seconds |
| Started | Aug 25 04:41:33 PM UTC 24 |
| Finished | Aug 25 04:59:49 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295098404 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2295098404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3721816315 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 3665876802 ps |
| CPU time | 101.32 seconds |
| Started | Aug 25 04:41:37 PM UTC 24 |
| Finished | Aug 25 04:43:21 PM UTC 24 |
| Peak memory | 597308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721816315 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3721816315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.2387339289 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 220226427 ps |
| CPU time | 32.35 seconds |
| Started | Aug 25 04:41:33 PM UTC 24 |
| Finished | Aug 25 04:42:06 PM UTC 24 |
| Peak memory | 599144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387339289 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2387339289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.795176635 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1169265913 ps |
| CPU time | 44.92 seconds |
| Started | Aug 25 04:41:43 PM UTC 24 |
| Finished | Aug 25 04:42:29 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795176635 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.795176635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3198256471 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 51488414 ps |
| CPU time | 10.76 seconds |
| Started | Aug 25 04:40:58 PM UTC 24 |
| Finished | Aug 25 04:41:10 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198256471 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3198256471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3145341660 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 8543440070 ps |
| CPU time | 142.14 seconds |
| Started | Aug 25 04:41:17 PM UTC 24 |
| Finished | Aug 25 04:43:42 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145341660 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3145341660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.541008749 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 4456279296 ps |
| CPU time | 104.78 seconds |
| Started | Aug 25 04:41:23 PM UTC 24 |
| Finished | Aug 25 04:43:11 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541008749 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.541008749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4039127022 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 43701031 ps |
| CPU time | 8.37 seconds |
| Started | Aug 25 04:41:11 PM UTC 24 |
| Finished | Aug 25 04:41:21 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039127022 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.4039127022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.4107694338 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 6967377518 ps |
| CPU time | 390.28 seconds |
| Started | Aug 25 04:42:16 PM UTC 24 |
| Finished | Aug 25 04:48:53 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107694338 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.4107694338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.2025963060 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 910367560 ps |
| CPU time | 107.81 seconds |
| Started | Aug 25 04:42:20 PM UTC 24 |
| Finished | Aug 25 04:44:11 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025963060 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2025963060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3863492519 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 7894446291 ps |
| CPU time | 712.6 seconds |
| Started | Aug 25 04:42:19 PM UTC 24 |
| Finished | Aug 25 04:54:24 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863492519 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3863492519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2851653643 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 265349494 ps |
| CPU time | 119.14 seconds |
| Started | Aug 25 04:42:30 PM UTC 24 |
| Finished | Aug 25 04:44:32 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851653643 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2851653643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2609825202 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 269155100 ps |
| CPU time | 53.69 seconds |
| Started | Aug 25 04:42:07 PM UTC 24 |
| Finished | Aug 25 04:43:02 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609825202 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2609825202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.1078155818 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 1009751002 ps |
| CPU time | 64.11 seconds |
| Started | Aug 25 04:43:10 PM UTC 24 |
| Finished | Aug 25 04:44:16 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078155818 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.1078155818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1341272749 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 22042722589 ps |
| CPU time | 553.19 seconds |
| Started | Aug 25 04:43:14 PM UTC 24 |
| Finished | Aug 25 04:52:37 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341272749 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.1341272749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2121079234 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 920147375 ps |
| CPU time | 50.17 seconds |
| Started | Aug 25 04:43:27 PM UTC 24 |
| Finished | Aug 25 04:44:20 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121079234 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.2121079234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.94814190 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 2050835867 ps |
| CPU time | 86.68 seconds |
| Started | Aug 25 04:43:18 PM UTC 24 |
| Finished | Aug 25 04:44:47 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94814190 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.94814190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3466006687 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 1920965513 ps |
| CPU time | 99.9 seconds |
| Started | Aug 25 04:42:40 PM UTC 24 |
| Finished | Aug 25 04:44:23 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466006687 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3466006687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.152474736 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 23410571736 ps |
| CPU time | 325.1 seconds |
| Started | Aug 25 04:43:04 PM UTC 24 |
| Finished | Aug 25 04:48:34 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152474736 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.152474736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.3150968227 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 64314382693 ps |
| CPU time | 1605.37 seconds |
| Started | Aug 25 04:43:08 PM UTC 24 |
| Finished | Aug 25 05:10:18 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150968227 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3150968227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.95519870 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 371946359 ps |
| CPU time | 53.86 seconds |
| Started | Aug 25 04:42:50 PM UTC 24 |
| Finished | Aug 25 04:43:46 PM UTC 24 |
| Peak memory | 599216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95519870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.95519870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_same_source.3770596406 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 1497415582 ps |
| CPU time | 68.43 seconds |
| Started | Aug 25 04:43:12 PM UTC 24 |
| Finished | Aug 25 04:44:23 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770596406 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3770596406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2912652083 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 184969371 ps |
| CPU time | 11.64 seconds |
| Started | Aug 25 04:42:33 PM UTC 24 |
| Finished | Aug 25 04:42:46 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912652083 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2912652083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1606426958 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 9189795664 ps |
| CPU time | 160.59 seconds |
| Started | Aug 25 04:42:36 PM UTC 24 |
| Finished | Aug 25 04:45:20 PM UTC 24 |
| Peak memory | 597580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606426958 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1606426958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2531419339 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 5608718561 ps |
| CPU time | 122 seconds |
| Started | Aug 25 04:42:41 PM UTC 24 |
| Finished | Aug 25 04:44:45 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531419339 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2531419339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3174914875 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 42419329 ps |
| CPU time | 9.29 seconds |
| Started | Aug 25 04:42:36 PM UTC 24 |
| Finished | Aug 25 04:42:46 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174914875 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.3174914875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3496196329 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 6399881321 ps |
| CPU time | 314.5 seconds |
| Started | Aug 25 04:43:30 PM UTC 24 |
| Finished | Aug 25 04:48:51 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496196329 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3496196329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2148041046 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 1550293486 ps |
| CPU time | 70.19 seconds |
| Started | Aug 25 04:43:34 PM UTC 24 |
| Finished | Aug 25 04:44:46 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148041046 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2148041046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1200581152 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 1514962640 ps |
| CPU time | 317.82 seconds |
| Started | Aug 25 04:43:32 PM UTC 24 |
| Finished | Aug 25 04:48:55 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200581152 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1200581152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4075179468 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 83077156 ps |
| CPU time | 41.94 seconds |
| Started | Aug 25 04:43:44 PM UTC 24 |
| Finished | Aug 25 04:44:27 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075179468 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.4075179468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.1747950043 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 829613443 ps |
| CPU time | 48.71 seconds |
| Started | Aug 25 04:43:26 PM UTC 24 |
| Finished | Aug 25 04:44:16 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747950043 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1747950043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1451484702 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1839178103 ps |
| CPU time | 116.85 seconds |
| Started | Aug 25 04:44:25 PM UTC 24 |
| Finished | Aug 25 04:46:25 PM UTC 24 |
| Peak memory | 599504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451484702 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1451484702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.809333931 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 102891321265 ps |
| CPU time | 2624.07 seconds |
| Started | Aug 25 04:44:36 PM UTC 24 |
| Finished | Aug 25 05:29:00 PM UTC 24 |
| Peak memory | 600284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809333931 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.809333931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.524157568 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 521355867 ps |
| CPU time | 36.02 seconds |
| Started | Aug 25 04:44:39 PM UTC 24 |
| Finished | Aug 25 04:45:17 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524157568 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.524157568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3554847259 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 778322405 ps |
| CPU time | 48.74 seconds |
| Started | Aug 25 04:44:38 PM UTC 24 |
| Finished | Aug 25 04:45:29 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554847259 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3554847259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1835499687 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 342350622 ps |
| CPU time | 48.36 seconds |
| Started | Aug 25 04:44:07 PM UTC 24 |
| Finished | Aug 25 04:44:57 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835499687 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1835499687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.649922068 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 41137457997 ps |
| CPU time | 599.04 seconds |
| Started | Aug 25 04:44:18 PM UTC 24 |
| Finished | Aug 25 04:54:25 PM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649922068 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.649922068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.916153378 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 3434867553 ps |
| CPU time | 82.26 seconds |
| Started | Aug 25 04:44:14 PM UTC 24 |
| Finished | Aug 25 04:45:39 PM UTC 24 |
| Peak memory | 597080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916153378 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.916153378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.1964607826 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 177918603 ps |
| CPU time | 23.59 seconds |
| Started | Aug 25 04:44:08 PM UTC 24 |
| Finished | Aug 25 04:44:34 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964607826 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1964607826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3415869303 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 1776407843 ps |
| CPU time | 82.26 seconds |
| Started | Aug 25 04:44:38 PM UTC 24 |
| Finished | Aug 25 04:46:02 PM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415869303 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.3415869303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.2619304034 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 43548403 ps |
| CPU time | 9.87 seconds |
| Started | Aug 25 04:43:44 PM UTC 24 |
| Finished | Aug 25 04:43:54 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619304034 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2619304034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.2033781235 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 10276976940 ps |
| CPU time | 177.17 seconds |
| Started | Aug 25 04:43:48 PM UTC 24 |
| Finished | Aug 25 04:46:48 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033781235 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2033781235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.933834699 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 5228758997 ps |
| CPU time | 115.44 seconds |
| Started | Aug 25 04:44:01 PM UTC 24 |
| Finished | Aug 25 04:45:59 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933834699 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.933834699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.779689669 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 49107861 ps |
| CPU time | 10.58 seconds |
| Started | Aug 25 04:43:49 PM UTC 24 |
| Finished | Aug 25 04:44:01 PM UTC 24 |
| Peak memory | 597184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779689669 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.779689669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1235630374 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 4453425573 ps |
| CPU time | 234.43 seconds |
| Started | Aug 25 04:44:44 PM UTC 24 |
| Finished | Aug 25 04:48:43 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235630374 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1235630374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.800739568 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 2770500086 ps |
| CPU time | 261.38 seconds |
| Started | Aug 25 04:44:46 PM UTC 24 |
| Finished | Aug 25 04:49:12 PM UTC 24 |
| Peak memory | 599368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800739568 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.800739568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1100469307 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 708351992 ps |
| CPU time | 322.93 seconds |
| Started | Aug 25 04:44:45 PM UTC 24 |
| Finished | Aug 25 04:50:13 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100469307 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1100469307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.4086526999 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 3182113104 ps |
| CPU time | 543.62 seconds |
| Started | Aug 25 04:44:51 PM UTC 24 |
| Finished | Aug 25 04:54:03 PM UTC 24 |
| Peak memory | 599352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086526999 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.4086526999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2680115107 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 643000892 ps |
| CPU time | 46.71 seconds |
| Started | Aug 25 04:44:39 PM UTC 24 |
| Finished | Aug 25 04:45:28 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680115107 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2680115107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.808945866 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 2336837434 ps |
| CPU time | 120.77 seconds |
| Started | Aug 25 04:45:11 PM UTC 24 |
| Finished | Aug 25 04:47:14 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808945866 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.808945866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1038524777 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 19037918399 ps |
| CPU time | 399.57 seconds |
| Started | Aug 25 04:45:19 PM UTC 24 |
| Finished | Aug 25 04:52:05 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038524777 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1038524777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3534747976 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 622988941 ps |
| CPU time | 39.45 seconds |
| Started | Aug 25 04:45:42 PM UTC 24 |
| Finished | Aug 25 04:46:23 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534747976 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.3534747976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3096273383 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 633742131 ps |
| CPU time | 37.82 seconds |
| Started | Aug 25 04:45:27 PM UTC 24 |
| Finished | Aug 25 04:46:06 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096273383 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3096273383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.3112693327 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 2147865874 ps |
| CPU time | 126.11 seconds |
| Started | Aug 25 04:44:58 PM UTC 24 |
| Finished | Aug 25 04:47:07 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112693327 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3112693327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.864493026 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 34992342313 ps |
| CPU time | 546.32 seconds |
| Started | Aug 25 04:45:09 PM UTC 24 |
| Finished | Aug 25 04:54:24 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864493026 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.864493026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1880457233 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 54839204236 ps |
| CPU time | 1406.56 seconds |
| Started | Aug 25 04:45:09 PM UTC 24 |
| Finished | Aug 25 05:08:58 PM UTC 24 |
| Peak memory | 599364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880457233 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1880457233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.2367153498 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 558043641 ps |
| CPU time | 79.81 seconds |
| Started | Aug 25 04:45:08 PM UTC 24 |
| Finished | Aug 25 04:46:30 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367153498 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2367153498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.3726314924 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 409897333 ps |
| CPU time | 23.2 seconds |
| Started | Aug 25 04:45:27 PM UTC 24 |
| Finished | Aug 25 04:45:51 PM UTC 24 |
| Peak memory | 599156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726314924 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3726314924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1616916627 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 139915900 ps |
| CPU time | 12.13 seconds |
| Started | Aug 25 04:44:49 PM UTC 24 |
| Finished | Aug 25 04:45:03 PM UTC 24 |
| Peak memory | 597188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616916627 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1616916627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.8734982 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 10424461877 ps |
| CPU time | 147.82 seconds |
| Started | Aug 25 04:44:55 PM UTC 24 |
| Finished | Aug 25 04:47:25 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8734982 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.8734982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3568617837 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 5145325063 ps |
| CPU time | 130.21 seconds |
| Started | Aug 25 04:44:54 PM UTC 24 |
| Finished | Aug 25 04:47:08 PM UTC 24 |
| Peak memory | 597456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568617837 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3568617837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1071438180 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 50310891 ps |
| CPU time | 9.36 seconds |
| Started | Aug 25 04:44:52 PM UTC 24 |
| Finished | Aug 25 04:45:03 PM UTC 24 |
| Peak memory | 597500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071438180 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1071438180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2633001896 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 2968732983 ps |
| CPU time | 363.01 seconds |
| Started | Aug 25 04:45:42 PM UTC 24 |
| Finished | Aug 25 04:51:51 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633001896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2633001896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2306596404 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 663284001 ps |
| CPU time | 93.71 seconds |
| Started | Aug 25 04:45:53 PM UTC 24 |
| Finished | Aug 25 04:47:29 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306596404 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2306596404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3835343978 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 11320522929 ps |
| CPU time | 755.77 seconds |
| Started | Aug 25 04:45:51 PM UTC 24 |
| Finished | Aug 25 04:58:39 PM UTC 24 |
| Peak memory | 599412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835343978 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3835343978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1253701697 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 168986118 ps |
| CPU time | 15.88 seconds |
| Started | Aug 25 04:45:26 PM UTC 24 |
| Finished | Aug 25 04:45:43 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253701697 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1253701697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.694246534 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 266270631 ps |
| CPU time | 39.71 seconds |
| Started | Aug 25 04:46:40 PM UTC 24 |
| Finished | Aug 25 04:47:21 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694246534 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.694246534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3044999810 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 107429623409 ps |
| CPU time | 2585.55 seconds |
| Started | Aug 25 04:46:47 PM UTC 24 |
| Finished | Aug 25 05:30:31 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044999810 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3044999810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3057297346 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 257814307 ps |
| CPU time | 17.04 seconds |
| Started | Aug 25 04:47:14 PM UTC 24 |
| Finished | Aug 25 04:47:33 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057297346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.3057297346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.1266540346 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 2360069562 ps |
| CPU time | 135.28 seconds |
| Started | Aug 25 04:46:55 PM UTC 24 |
| Finished | Aug 25 04:49:13 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266540346 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1266540346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.650533154 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 457767153 ps |
| CPU time | 25.49 seconds |
| Started | Aug 25 04:46:23 PM UTC 24 |
| Finished | Aug 25 04:46:50 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650533154 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.650533154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2796983106 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 48434505937 ps |
| CPU time | 721.16 seconds |
| Started | Aug 25 04:46:31 PM UTC 24 |
| Finished | Aug 25 04:58:43 PM UTC 24 |
| Peak memory | 599540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796983106 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.2796983106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1178294946 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 26555565918 ps |
| CPU time | 565.36 seconds |
| Started | Aug 25 04:46:38 PM UTC 24 |
| Finished | Aug 25 04:56:12 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178294946 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1178294946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.4261915788 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 586089165 ps |
| CPU time | 82.36 seconds |
| Started | Aug 25 04:46:25 PM UTC 24 |
| Finished | Aug 25 04:47:50 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261915788 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.4261915788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1770750726 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 1126272319 ps |
| CPU time | 55.75 seconds |
| Started | Aug 25 04:46:50 PM UTC 24 |
| Finished | Aug 25 04:47:47 PM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770750726 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1770750726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1432285456 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 229829245 ps |
| CPU time | 13.02 seconds |
| Started | Aug 25 04:46:03 PM UTC 24 |
| Finished | Aug 25 04:46:17 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432285456 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1432285456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1566602436 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 7674254243 ps |
| CPU time | 117.95 seconds |
| Started | Aug 25 04:46:07 PM UTC 24 |
| Finished | Aug 25 04:48:08 PM UTC 24 |
| Peak memory | 597320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566602436 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1566602436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.146846790 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 5440900062 ps |
| CPU time | 131.71 seconds |
| Started | Aug 25 04:46:15 PM UTC 24 |
| Finished | Aug 25 04:48:30 PM UTC 24 |
| Peak memory | 597288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146846790 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.146846790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3478677828 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 46122732 ps |
| CPU time | 10.28 seconds |
| Started | Aug 25 04:46:04 PM UTC 24 |
| Finished | Aug 25 04:46:15 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478677828 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.3478677828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.867599519 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 489534882 ps |
| CPU time | 48.15 seconds |
| Started | Aug 25 04:47:31 PM UTC 24 |
| Finished | Aug 25 04:48:21 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867599519 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.867599519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1218298311 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 2743378863 ps |
| CPU time | 320.87 seconds |
| Started | Aug 25 04:47:32 PM UTC 24 |
| Finished | Aug 25 04:52:59 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218298311 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1218298311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3301853666 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 5590029406 ps |
| CPU time | 526.6 seconds |
| Started | Aug 25 04:47:31 PM UTC 24 |
| Finished | Aug 25 04:56:26 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301853666 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3301853666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.647068610 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 1730219811 ps |
| CPU time | 275.95 seconds |
| Started | Aug 25 04:47:38 PM UTC 24 |
| Finished | Aug 25 04:52:19 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647068610 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.647068610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.2181984806 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 97343634 ps |
| CPU time | 20.83 seconds |
| Started | Aug 25 04:47:12 PM UTC 24 |
| Finished | Aug 25 04:47:34 PM UTC 24 |
| Peak memory | 599392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181984806 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2181984806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.3665045364 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 106051050 ps |
| CPU time | 15.21 seconds |
| Started | Aug 25 04:48:16 PM UTC 24 |
| Finished | Aug 25 04:48:33 PM UTC 24 |
| Peak memory | 597460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665045364 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3665045364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.739510301 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 109833830684 ps |
| CPU time | 2576.27 seconds |
| Started | Aug 25 04:48:23 PM UTC 24 |
| Finished | Aug 25 05:31:54 PM UTC 24 |
| Peak memory | 599928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739510301 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.739510301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2313738008 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 227116979 ps |
| CPU time | 39.1 seconds |
| Started | Aug 25 04:48:49 PM UTC 24 |
| Finished | Aug 25 04:49:30 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313738008 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2313738008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.837173262 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 579949045 ps |
| CPU time | 34.55 seconds |
| Started | Aug 25 04:48:36 PM UTC 24 |
| Finished | Aug 25 04:49:12 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837173262 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.837173262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.738231234 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 86864286 ps |
| CPU time | 15.58 seconds |
| Started | Aug 25 04:47:56 PM UTC 24 |
| Finished | Aug 25 04:48:13 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738231234 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.738231234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.2742667638 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 65501908295 ps |
| CPU time | 1146.31 seconds |
| Started | Aug 25 04:48:13 PM UTC 24 |
| Finished | Aug 25 05:07:37 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742667638 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2742667638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1646646001 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 49920645699 ps |
| CPU time | 1219.27 seconds |
| Started | Aug 25 04:48:15 PM UTC 24 |
| Finished | Aug 25 05:08:54 PM UTC 24 |
| Peak memory | 599592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646646001 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1646646001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.1949321273 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 202991868 ps |
| CPU time | 25.82 seconds |
| Started | Aug 25 04:47:59 PM UTC 24 |
| Finished | Aug 25 04:48:26 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949321273 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.1949321273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2017126983 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 363390315 ps |
| CPU time | 44.35 seconds |
| Started | Aug 25 04:48:32 PM UTC 24 |
| Finished | Aug 25 04:49:18 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017126983 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2017126983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4261488415 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 149243560 ps |
| CPU time | 11.87 seconds |
| Started | Aug 25 04:47:39 PM UTC 24 |
| Finished | Aug 25 04:47:52 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261488415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.4261488415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2483420834 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 6724720543 ps |
| CPU time | 110.82 seconds |
| Started | Aug 25 04:47:50 PM UTC 24 |
| Finished | Aug 25 04:49:43 PM UTC 24 |
| Peak memory | 597380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483420834 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2483420834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1064737577 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 2970081542 ps |
| CPU time | 78.47 seconds |
| Started | Aug 25 04:47:54 PM UTC 24 |
| Finished | Aug 25 04:49:15 PM UTC 24 |
| Peak memory | 597068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064737577 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1064737577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3899201347 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 54203209 ps |
| CPU time | 10.82 seconds |
| Started | Aug 25 04:47:46 PM UTC 24 |
| Finished | Aug 25 04:47:58 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899201347 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3899201347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3515968106 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 2523117142 ps |
| CPU time | 121.36 seconds |
| Started | Aug 25 04:48:52 PM UTC 24 |
| Finished | Aug 25 04:50:56 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515968106 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3515968106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4280756400 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 3935528371 ps |
| CPU time | 386.42 seconds |
| Started | Aug 25 04:48:55 PM UTC 24 |
| Finished | Aug 25 04:55:27 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280756400 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4280756400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.394389107 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 1212567133 ps |
| CPU time | 507.14 seconds |
| Started | Aug 25 04:48:55 PM UTC 24 |
| Finished | Aug 25 04:57:30 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394389107 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.394389107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3659177295 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 1977873406 ps |
| CPU time | 247.13 seconds |
| Started | Aug 25 04:49:07 PM UTC 24 |
| Finished | Aug 25 04:53:18 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659177295 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3659177295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3921579304 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 162131713 ps |
| CPU time | 12.93 seconds |
| Started | Aug 25 04:48:44 PM UTC 24 |
| Finished | Aug 25 04:48:58 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921579304 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3921579304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.4067658060 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1286923585 ps |
| CPU time | 72.73 seconds |
| Started | Aug 25 04:49:36 PM UTC 24 |
| Finished | Aug 25 04:50:51 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067658060 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.4067658060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.4069249696 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 147842002598 ps |
| CPU time | 3391.46 seconds |
| Started | Aug 25 04:49:38 PM UTC 24 |
| Finished | Aug 25 05:46:55 PM UTC 24 |
| Peak memory | 600284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069249696 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.4069249696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3195002968 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 528416849 ps |
| CPU time | 28.4 seconds |
| Started | Aug 25 04:49:50 PM UTC 24 |
| Finished | Aug 25 04:50:20 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195002968 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.3195002968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.1856401343 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 1264040765 ps |
| CPU time | 68.85 seconds |
| Started | Aug 25 04:49:41 PM UTC 24 |
| Finished | Aug 25 04:50:52 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856401343 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1856401343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2139924678 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 143903871 ps |
| CPU time | 21.12 seconds |
| Started | Aug 25 04:49:21 PM UTC 24 |
| Finished | Aug 25 04:49:43 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139924678 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2139924678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.101916222 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 67095899064 ps |
| CPU time | 1135.61 seconds |
| Started | Aug 25 04:49:36 PM UTC 24 |
| Finished | Aug 25 05:08:50 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101916222 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.101916222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.3692600762 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 14036234893 ps |
| CPU time | 314.87 seconds |
| Started | Aug 25 04:49:37 PM UTC 24 |
| Finished | Aug 25 04:54:58 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692600762 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3692600762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.4012285634 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 133726259 ps |
| CPU time | 20.01 seconds |
| Started | Aug 25 04:49:36 PM UTC 24 |
| Finished | Aug 25 04:49:57 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012285634 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.4012285634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.1328005565 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 235478132 ps |
| CPU time | 32.29 seconds |
| Started | Aug 25 04:49:39 PM UTC 24 |
| Finished | Aug 25 04:50:13 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328005565 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1328005565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1340813698 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 41805053 ps |
| CPU time | 9.93 seconds |
| Started | Aug 25 04:49:15 PM UTC 24 |
| Finished | Aug 25 04:49:26 PM UTC 24 |
| Peak memory | 597332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340813698 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1340813698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3732257952 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 7714439945 ps |
| CPU time | 134.85 seconds |
| Started | Aug 25 04:49:19 PM UTC 24 |
| Finished | Aug 25 04:51:37 PM UTC 24 |
| Peak memory | 597320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732257952 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3732257952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2207176529 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 4508189974 ps |
| CPU time | 99.82 seconds |
| Started | Aug 25 04:49:21 PM UTC 24 |
| Finished | Aug 25 04:51:03 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207176529 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2207176529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.162346133 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 42454248 ps |
| CPU time | 10.06 seconds |
| Started | Aug 25 04:49:15 PM UTC 24 |
| Finished | Aug 25 04:49:27 PM UTC 24 |
| Peak memory | 597156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162346133 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.162346133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.31322483 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 4540386651 ps |
| CPU time | 221.85 seconds |
| Started | Aug 25 04:49:51 PM UTC 24 |
| Finished | Aug 25 04:53:37 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31322483 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.31322483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3660618769 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 4354580146 ps |
| CPU time | 229.43 seconds |
| Started | Aug 25 04:50:07 PM UTC 24 |
| Finished | Aug 25 04:54:01 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660618769 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3660618769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3627202560 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 1725729675 ps |
| CPU time | 213.98 seconds |
| Started | Aug 25 04:49:54 PM UTC 24 |
| Finished | Aug 25 04:53:32 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627202560 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.3627202560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.16612648 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 6601633903 ps |
| CPU time | 511.16 seconds |
| Started | Aug 25 04:50:09 PM UTC 24 |
| Finished | Aug 25 04:58:49 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16612648 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.16612648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.922783402 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 940353587 ps |
| CPU time | 54.78 seconds |
| Started | Aug 25 04:49:42 PM UTC 24 |
| Finished | Aug 25 04:50:38 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922783402 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.922783402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.4060358551 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 2337064741 ps |
| CPU time | 125.37 seconds |
| Started | Aug 25 04:51:09 PM UTC 24 |
| Finished | Aug 25 04:53:17 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060358551 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.4060358551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.836830336 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 58278816793 ps |
| CPU time | 1453.14 seconds |
| Started | Aug 25 04:51:12 PM UTC 24 |
| Finished | Aug 25 05:15:48 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836830336 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.836830336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2990628445 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 43229303 ps |
| CPU time | 9.82 seconds |
| Started | Aug 25 04:51:25 PM UTC 24 |
| Finished | Aug 25 04:51:36 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990628445 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.2990628445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.268746670 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 571539371 ps |
| CPU time | 56.29 seconds |
| Started | Aug 25 04:51:16 PM UTC 24 |
| Finished | Aug 25 04:52:15 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268746670 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.268746670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.2620317559 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 2332949852 ps |
| CPU time | 88.14 seconds |
| Started | Aug 25 04:50:55 PM UTC 24 |
| Finished | Aug 25 04:52:26 PM UTC 24 |
| Peak memory | 599388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620317559 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2620317559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2701579136 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 10544699662 ps |
| CPU time | 184.86 seconds |
| Started | Aug 25 04:50:58 PM UTC 24 |
| Finished | Aug 25 04:54:06 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701579136 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2701579136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.4253261426 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 30966633521 ps |
| CPU time | 812.84 seconds |
| Started | Aug 25 04:51:02 PM UTC 24 |
| Finished | Aug 25 05:04:48 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253261426 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4253261426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1597296999 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 130961622 ps |
| CPU time | 23.47 seconds |
| Started | Aug 25 04:50:56 PM UTC 24 |
| Finished | Aug 25 04:51:21 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597296999 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.1597296999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2859065531 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 110981224 ps |
| CPU time | 16.07 seconds |
| Started | Aug 25 04:51:16 PM UTC 24 |
| Finished | Aug 25 04:51:33 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859065531 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2859065531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1386748873 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 201659982 ps |
| CPU time | 12.63 seconds |
| Started | Aug 25 04:50:21 PM UTC 24 |
| Finished | Aug 25 04:50:35 PM UTC 24 |
| Peak memory | 597188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386748873 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1386748873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2653487544 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 7688020814 ps |
| CPU time | 125.21 seconds |
| Started | Aug 25 04:50:39 PM UTC 24 |
| Finished | Aug 25 04:52:47 PM UTC 24 |
| Peak memory | 597520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653487544 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2653487544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2232251608 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 5091903301 ps |
| CPU time | 121.93 seconds |
| Started | Aug 25 04:50:43 PM UTC 24 |
| Finished | Aug 25 04:52:48 PM UTC 24 |
| Peak memory | 597212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232251608 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2232251608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1192446061 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 46074813 ps |
| CPU time | 10.31 seconds |
| Started | Aug 25 04:50:37 PM UTC 24 |
| Finished | Aug 25 04:50:49 PM UTC 24 |
| Peak memory | 597440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192446061 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.1192446061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2757572033 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 4383986446 ps |
| CPU time | 247.63 seconds |
| Started | Aug 25 04:51:44 PM UTC 24 |
| Finished | Aug 25 04:55:57 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757572033 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2757572033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3083217494 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 4124220792 ps |
| CPU time | 374.39 seconds |
| Started | Aug 25 04:52:00 PM UTC 24 |
| Finished | Aug 25 04:58:21 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083217494 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3083217494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.55610121 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 156512492 ps |
| CPU time | 102.38 seconds |
| Started | Aug 25 04:51:56 PM UTC 24 |
| Finished | Aug 25 04:53:41 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55610121 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.55610121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.588326043 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 37679948 ps |
| CPU time | 40.38 seconds |
| Started | Aug 25 04:52:01 PM UTC 24 |
| Finished | Aug 25 04:52:43 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588326043 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.588326043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.4094353237 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 93816330 ps |
| CPU time | 21.1 seconds |
| Started | Aug 25 04:51:20 PM UTC 24 |
| Finished | Aug 25 04:51:42 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094353237 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.4094353237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.797798692 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 2393649492 ps |
| CPU time | 111.32 seconds |
| Started | Aug 25 04:52:40 PM UTC 24 |
| Finished | Aug 25 04:54:34 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797798692 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.797798692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1835954682 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 30849918206 ps |
| CPU time | 780.48 seconds |
| Started | Aug 25 04:52:44 PM UTC 24 |
| Finished | Aug 25 05:05:56 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835954682 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1835954682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2566633640 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 644268345 ps |
| CPU time | 32.68 seconds |
| Started | Aug 25 04:53:07 PM UTC 24 |
| Finished | Aug 25 04:53:41 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566633640 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.2566633640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3507522966 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 415972109 ps |
| CPU time | 51.86 seconds |
| Started | Aug 25 04:52:50 PM UTC 24 |
| Finished | Aug 25 04:53:44 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507522966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3507522966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.756794439 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 716402073 ps |
| CPU time | 29.43 seconds |
| Started | Aug 25 04:52:24 PM UTC 24 |
| Finished | Aug 25 04:52:55 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756794439 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.756794439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.2940021273 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 21020155177 ps |
| CPU time | 348.68 seconds |
| Started | Aug 25 04:52:38 PM UTC 24 |
| Finished | Aug 25 04:58:32 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940021273 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2940021273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3127664370 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 19764598519 ps |
| CPU time | 437.92 seconds |
| Started | Aug 25 04:52:39 PM UTC 24 |
| Finished | Aug 25 05:00:03 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127664370 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3127664370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.404247099 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 484567015 ps |
| CPU time | 50.18 seconds |
| Started | Aug 25 04:52:28 PM UTC 24 |
| Finished | Aug 25 04:53:20 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404247099 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.404247099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.142125396 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 2389981438 ps |
| CPU time | 112.05 seconds |
| Started | Aug 25 04:52:48 PM UTC 24 |
| Finished | Aug 25 04:54:43 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142125396 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.142125396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3826345671 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 202828393 ps |
| CPU time | 13.01 seconds |
| Started | Aug 25 04:52:02 PM UTC 24 |
| Finished | Aug 25 04:52:16 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826345671 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3826345671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2429549737 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 7221060862 ps |
| CPU time | 132.63 seconds |
| Started | Aug 25 04:52:06 PM UTC 24 |
| Finished | Aug 25 04:54:21 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429549737 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2429549737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1447709234 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 6147634768 ps |
| CPU time | 137.12 seconds |
| Started | Aug 25 04:52:15 PM UTC 24 |
| Finished | Aug 25 04:54:35 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447709234 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1447709234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2510849465 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 40645175 ps |
| CPU time | 9.79 seconds |
| Started | Aug 25 04:52:02 PM UTC 24 |
| Finished | Aug 25 04:52:13 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510849465 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.2510849465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2536011476 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 10611341181 ps |
| CPU time | 565.41 seconds |
| Started | Aug 25 04:53:11 PM UTC 24 |
| Finished | Aug 25 05:02:46 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536011476 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2536011476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3006503862 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 10412773335 ps |
| CPU time | 540.32 seconds |
| Started | Aug 25 04:53:18 PM UTC 24 |
| Finished | Aug 25 05:02:27 PM UTC 24 |
| Peak memory | 599560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006503862 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3006503862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.73176595 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 111131630 ps |
| CPU time | 63.65 seconds |
| Started | Aug 25 04:53:12 PM UTC 24 |
| Finished | Aug 25 04:54:18 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73176595 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.73176595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1371547924 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 1523428752 ps |
| CPU time | 356.08 seconds |
| Started | Aug 25 04:53:20 PM UTC 24 |
| Finished | Aug 25 04:59:22 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371547924 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.1371547924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2552251442 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 730007874 ps |
| CPU time | 49.1 seconds |
| Started | Aug 25 04:53:02 PM UTC 24 |
| Finished | Aug 25 04:53:53 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552251442 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2552251442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3698917853 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 636884983 ps |
| CPU time | 78.11 seconds |
| Started | Aug 25 04:54:00 PM UTC 24 |
| Finished | Aug 25 04:55:21 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698917853 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.3698917853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.378071499 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 89211511819 ps |
| CPU time | 2178.94 seconds |
| Started | Aug 25 04:54:00 PM UTC 24 |
| Finished | Aug 25 05:30:51 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378071499 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.378071499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1084500559 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 454547775 ps |
| CPU time | 30.92 seconds |
| Started | Aug 25 04:54:17 PM UTC 24 |
| Finished | Aug 25 04:54:50 PM UTC 24 |
| Peak memory | 599120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084500559 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.1084500559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.931425567 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 1088868708 ps |
| CPU time | 59.22 seconds |
| Started | Aug 25 04:54:07 PM UTC 24 |
| Finished | Aug 25 04:55:08 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931425567 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.931425567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3919427870 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 953649434 ps |
| CPU time | 58.37 seconds |
| Started | Aug 25 04:53:43 PM UTC 24 |
| Finished | Aug 25 04:54:44 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919427870 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3919427870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.100978283 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 52648208760 ps |
| CPU time | 894.99 seconds |
| Started | Aug 25 04:53:56 PM UTC 24 |
| Finished | Aug 25 05:09:04 PM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100978283 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.100978283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.953887205 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 4472965403 ps |
| CPU time | 110.12 seconds |
| Started | Aug 25 04:53:57 PM UTC 24 |
| Finished | Aug 25 04:55:50 PM UTC 24 |
| Peak memory | 597328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953887205 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.953887205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.2332150009 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 473499274 ps |
| CPU time | 64.44 seconds |
| Started | Aug 25 04:53:44 PM UTC 24 |
| Finished | Aug 25 04:54:50 PM UTC 24 |
| Peak memory | 599332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332150009 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.2332150009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3821858162 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 88176021 ps |
| CPU time | 12.38 seconds |
| Started | Aug 25 04:54:06 PM UTC 24 |
| Finished | Aug 25 04:54:20 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821858162 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3821858162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3648055337 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 209813375 ps |
| CPU time | 14.38 seconds |
| Started | Aug 25 04:53:19 PM UTC 24 |
| Finished | Aug 25 04:53:35 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648055337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3648055337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.470132726 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 10313048893 ps |
| CPU time | 169.63 seconds |
| Started | Aug 25 04:53:26 PM UTC 24 |
| Finished | Aug 25 04:56:19 PM UTC 24 |
| Peak memory | 597460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470132726 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.470132726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1106390659 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 5534156388 ps |
| CPU time | 129.51 seconds |
| Started | Aug 25 04:53:42 PM UTC 24 |
| Finished | Aug 25 04:55:55 PM UTC 24 |
| Peak memory | 597396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106390659 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1106390659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3066972326 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 35183958 ps |
| CPU time | 9.41 seconds |
| Started | Aug 25 04:53:22 PM UTC 24 |
| Finished | Aug 25 04:53:32 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066972326 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3066972326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.2977133556 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 942897896 ps |
| CPU time | 137.96 seconds |
| Started | Aug 25 04:54:18 PM UTC 24 |
| Finished | Aug 25 04:56:39 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977133556 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2977133556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.624196941 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 8966524666 ps |
| CPU time | 436.36 seconds |
| Started | Aug 25 04:54:27 PM UTC 24 |
| Finished | Aug 25 05:01:51 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624196941 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.624196941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.425244892 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 418918726 ps |
| CPU time | 363.5 seconds |
| Started | Aug 25 04:54:26 PM UTC 24 |
| Finished | Aug 25 05:00:36 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425244892 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.425244892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2711542808 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 4264248260 ps |
| CPU time | 482.84 seconds |
| Started | Aug 25 04:54:30 PM UTC 24 |
| Finished | Aug 25 05:02:40 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711542808 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2711542808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.1933364012 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 1087475394 ps |
| CPU time | 63.62 seconds |
| Started | Aug 25 04:54:09 PM UTC 24 |
| Finished | Aug 25 04:55:15 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933364012 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1933364012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.988880948 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 7516683180 ps |
| CPU time | 695.32 seconds |
| Started | Aug 25 03:38:29 PM UTC 24 |
| Finished | Aug 25 03:50:15 PM UTC 24 |
| Peak memory | 661300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=988880948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.988880948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.2921816786 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4630515800 ps |
| CPU time | 579.91 seconds |
| Started | Aug 25 03:38:28 PM UTC 24 |
| Finished | Aug 25 03:48:17 PM UTC 24 |
| Peak memory | 618180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921816786 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2921816786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_same_csr_outstanding.2740180233 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 28381608436 ps |
| CPU time | 6271.98 seconds |
| Started | Aug 25 03:36:22 PM UTC 24 |
| Finished | Aug 25 05:22:20 PM UTC 24 |
| Peak memory | 614780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2740180233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.chip_same_csr_outstanding.2740180233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.536650002 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2175281605 ps |
| CPU time | 129.82 seconds |
| Started | Aug 25 03:37:16 PM UTC 24 |
| Finished | Aug 25 03:39:28 PM UTC 24 |
| Peak memory | 599580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536650002 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.536650002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1094902489 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 38813945 ps |
| CPU time | 9.9 seconds |
| Started | Aug 25 03:37:38 PM UTC 24 |
| Finished | Aug 25 03:37:49 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094902489 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1094902489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.355540068 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 988387358 ps |
| CPU time | 51.52 seconds |
| Started | Aug 25 03:37:29 PM UTC 24 |
| Finished | Aug 25 03:38:22 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355540068 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.355540068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.339538906 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1944899601 ps |
| CPU time | 109.57 seconds |
| Started | Aug 25 03:37:00 PM UTC 24 |
| Finished | Aug 25 03:38:52 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339538906 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.339538906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1481065987 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 14521785268 ps |
| CPU time | 220.9 seconds |
| Started | Aug 25 03:37:13 PM UTC 24 |
| Finished | Aug 25 03:40:58 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481065987 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1481065987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.957724882 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 45514045002 ps |
| CPU time | 1134.98 seconds |
| Started | Aug 25 03:37:14 PM UTC 24 |
| Finished | Aug 25 03:56:27 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957724882 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.957724882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1356152498 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 583748889 ps |
| CPU time | 71.1 seconds |
| Started | Aug 25 03:37:03 PM UTC 24 |
| Finished | Aug 25 03:38:16 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356152498 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.1356152498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.2879310219 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2564567931 ps |
| CPU time | 99.31 seconds |
| Started | Aug 25 03:37:22 PM UTC 24 |
| Finished | Aug 25 03:39:04 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879310219 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2879310219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2405255726 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 217364307 ps |
| CPU time | 14.57 seconds |
| Started | Aug 25 03:36:49 PM UTC 24 |
| Finished | Aug 25 03:37:04 PM UTC 24 |
| Peak memory | 597424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405255726 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2405255726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.4122653972 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 11602675261 ps |
| CPU time | 213.58 seconds |
| Started | Aug 25 03:36:50 PM UTC 24 |
| Finished | Aug 25 03:40:27 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122653972 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.4122653972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1582762736 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5771288836 ps |
| CPU time | 99.9 seconds |
| Started | Aug 25 03:36:57 PM UTC 24 |
| Finished | Aug 25 03:38:39 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582762736 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1582762736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.890346379 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 40962394 ps |
| CPU time | 9.59 seconds |
| Started | Aug 25 03:36:49 PM UTC 24 |
| Finished | Aug 25 03:37:00 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890346379 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.890346379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3131604042 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1836674607 ps |
| CPU time | 236.44 seconds |
| Started | Aug 25 03:38:18 PM UTC 24 |
| Finished | Aug 25 03:42:19 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131604042 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3131604042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3282842938 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10054470869 ps |
| CPU time | 764.5 seconds |
| Started | Aug 25 03:38:15 PM UTC 24 |
| Finished | Aug 25 03:51:11 PM UTC 24 |
| Peak memory | 599332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282842938 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3282842938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3377164313 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5257943904 ps |
| CPU time | 551.91 seconds |
| Started | Aug 25 03:38:25 PM UTC 24 |
| Finished | Aug 25 03:47:46 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377164313 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3377164313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.929322108 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 109037037 ps |
| CPU time | 23.61 seconds |
| Started | Aug 25 03:37:31 PM UTC 24 |
| Finished | Aug 25 03:37:56 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929322108 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.929322108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2721866256 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 1609405947 ps |
| CPU time | 96.06 seconds |
| Started | Aug 25 04:54:58 PM UTC 24 |
| Finished | Aug 25 04:56:36 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721866256 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device.2721866256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1275796294 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 40864703065 ps |
| CPU time | 921.33 seconds |
| Started | Aug 25 04:55:06 PM UTC 24 |
| Finished | Aug 25 05:10:42 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275796294 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device_slow_rsp.1275796294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1646228711 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 222347818 ps |
| CPU time | 28.98 seconds |
| Started | Aug 25 04:55:15 PM UTC 24 |
| Finished | Aug 25 04:55:45 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646228711 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.1646228711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2689896375 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 397170440 ps |
| CPU time | 18.63 seconds |
| Started | Aug 25 04:55:13 PM UTC 24 |
| Finished | Aug 25 04:55:33 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689896375 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2689896375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.4182829136 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 581794808 ps |
| CPU time | 75.53 seconds |
| Started | Aug 25 04:54:45 PM UTC 24 |
| Finished | Aug 25 04:56:03 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182829136 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.4182829136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.2380919433 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 61434633266 ps |
| CPU time | 932.47 seconds |
| Started | Aug 25 04:54:49 PM UTC 24 |
| Finished | Aug 25 05:10:34 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380919433 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.2380919433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.3455512279 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 34744318450 ps |
| CPU time | 787.02 seconds |
| Started | Aug 25 04:54:55 PM UTC 24 |
| Finished | Aug 25 05:08:15 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455512279 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3455512279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.3420635443 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 118631366 ps |
| CPU time | 20.59 seconds |
| Started | Aug 25 04:54:47 PM UTC 24 |
| Finished | Aug 25 04:55:09 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420635443 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_delays.3420635443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.4103030557 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 319990163 ps |
| CPU time | 40 seconds |
| Started | Aug 25 04:55:07 PM UTC 24 |
| Finished | Aug 25 04:55:49 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103030557 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.4103030557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3029328905 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 225531879 ps |
| CPU time | 12.59 seconds |
| Started | Aug 25 04:54:40 PM UTC 24 |
| Finished | Aug 25 04:54:54 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029328905 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3029328905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3658121793 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 8623091107 ps |
| CPU time | 133.07 seconds |
| Started | Aug 25 04:54:43 PM UTC 24 |
| Finished | Aug 25 04:56:59 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658121793 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3658121793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3177929179 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 5399192159 ps |
| CPU time | 114.07 seconds |
| Started | Aug 25 04:54:44 PM UTC 24 |
| Finished | Aug 25 04:56:41 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177929179 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3177929179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1715121776 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 39984069 ps |
| CPU time | 8.86 seconds |
| Started | Aug 25 04:54:41 PM UTC 24 |
| Finished | Aug 25 04:54:51 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715121776 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays.1715121776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.555211164 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 8369175371 ps |
| CPU time | 413.91 seconds |
| Started | Aug 25 04:55:16 PM UTC 24 |
| Finished | Aug 25 05:02:17 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555211164 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.555211164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2594389066 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 2461521802 ps |
| CPU time | 133.18 seconds |
| Started | Aug 25 04:55:32 PM UTC 24 |
| Finished | Aug 25 04:57:49 PM UTC 24 |
| Peak memory | 599368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594389066 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2594389066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2089777064 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 256566244 ps |
| CPU time | 219.02 seconds |
| Started | Aug 25 04:55:21 PM UTC 24 |
| Finished | Aug 25 04:59:04 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089777064 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_rand_reset.2089777064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2269449173 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 3187644099 ps |
| CPU time | 673.87 seconds |
| Started | Aug 25 04:55:33 PM UTC 24 |
| Finished | Aug 25 05:06:58 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269449173 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_reset_error.2269449173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3673936756 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 887675460 ps |
| CPU time | 58.63 seconds |
| Started | Aug 25 04:55:14 PM UTC 24 |
| Finished | Aug 25 04:56:14 PM UTC 24 |
| Peak memory | 599332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673936756 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.3673936756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.400622975 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 697470733 ps |
| CPU time | 41.89 seconds |
| Started | Aug 25 04:56:15 PM UTC 24 |
| Finished | Aug 25 04:56:59 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400622975 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device.400622975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2250455215 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 57491366972 ps |
| CPU time | 1441.47 seconds |
| Started | Aug 25 04:56:14 PM UTC 24 |
| Finished | Aug 25 05:20:37 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250455215 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device_slow_rsp.2250455215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2875594082 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 178003838 ps |
| CPU time | 14.2 seconds |
| Started | Aug 25 04:56:22 PM UTC 24 |
| Finished | Aug 25 04:56:37 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875594082 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr.2875594082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.385208152 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 551716467 ps |
| CPU time | 58.08 seconds |
| Started | Aug 25 04:56:18 PM UTC 24 |
| Finished | Aug 25 04:57:18 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385208152 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.385208152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.501759955 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 67092573 ps |
| CPU time | 13.19 seconds |
| Started | Aug 25 04:55:56 PM UTC 24 |
| Finished | Aug 25 04:56:11 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501759955 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.501759955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3499932194 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 54494276963 ps |
| CPU time | 863.57 seconds |
| Started | Aug 25 04:56:10 PM UTC 24 |
| Finished | Aug 25 05:10:46 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499932194 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3499932194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.593988314 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 29434636977 ps |
| CPU time | 714.29 seconds |
| Started | Aug 25 04:56:13 PM UTC 24 |
| Finished | Aug 25 05:08:18 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593988314 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.593988314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3017187725 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 460685395 ps |
| CPU time | 49.31 seconds |
| Started | Aug 25 04:56:00 PM UTC 24 |
| Finished | Aug 25 04:56:51 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017187725 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_delays.3017187725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.3589347749 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 554504249 ps |
| CPU time | 66.6 seconds |
| Started | Aug 25 04:56:19 PM UTC 24 |
| Finished | Aug 25 04:57:27 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589347749 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3589347749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.323836221 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 208069041 ps |
| CPU time | 12.38 seconds |
| Started | Aug 25 04:55:38 PM UTC 24 |
| Finished | Aug 25 04:55:51 PM UTC 24 |
| Peak memory | 596992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323836221 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.323836221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2950915564 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 7747356861 ps |
| CPU time | 105.14 seconds |
| Started | Aug 25 04:55:51 PM UTC 24 |
| Finished | Aug 25 04:57:38 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950915564 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2950915564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1009320771 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 6685724774 ps |
| CPU time | 175.58 seconds |
| Started | Aug 25 04:55:48 PM UTC 24 |
| Finished | Aug 25 04:58:48 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009320771 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1009320771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2924889220 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 52441995 ps |
| CPU time | 8.9 seconds |
| Started | Aug 25 04:55:44 PM UTC 24 |
| Finished | Aug 25 04:55:54 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924889220 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays.2924889220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.3220280350 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 12922643696 ps |
| CPU time | 601 seconds |
| Started | Aug 25 04:56:25 PM UTC 24 |
| Finished | Aug 25 05:06:36 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220280350 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3220280350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2166734468 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 1904769722 ps |
| CPU time | 111.79 seconds |
| Started | Aug 25 04:56:36 PM UTC 24 |
| Finished | Aug 25 04:58:30 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166734468 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2166734468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2226849080 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 4147320089 ps |
| CPU time | 711.44 seconds |
| Started | Aug 25 04:56:35 PM UTC 24 |
| Finished | Aug 25 05:08:38 PM UTC 24 |
| Peak memory | 599616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226849080 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_rand_reset.2226849080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2600545601 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 1993111047 ps |
| CPU time | 293 seconds |
| Started | Aug 25 04:56:38 PM UTC 24 |
| Finished | Aug 25 05:01:36 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600545601 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_reset_error.2600545601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.693569756 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 1080756666 ps |
| CPU time | 73.21 seconds |
| Started | Aug 25 04:56:20 PM UTC 24 |
| Finished | Aug 25 04:57:36 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693569756 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.693569756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.982160551 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 2127479412 ps |
| CPU time | 105.49 seconds |
| Started | Aug 25 04:57:21 PM UTC 24 |
| Finished | Aug 25 04:59:09 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982160551 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device.982160551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3574552252 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 110639071932 ps |
| CPU time | 2752.59 seconds |
| Started | Aug 25 04:57:23 PM UTC 24 |
| Finished | Aug 25 05:43:56 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574552252 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device_slow_rsp.3574552252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2376873325 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 839304792 ps |
| CPU time | 55.48 seconds |
| Started | Aug 25 04:57:51 PM UTC 24 |
| Finished | Aug 25 04:58:48 PM UTC 24 |
| Peak memory | 599232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376873325 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_addr.2376873325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3918877708 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 86117722 ps |
| CPU time | 10.54 seconds |
| Started | Aug 25 04:57:39 PM UTC 24 |
| Finished | Aug 25 04:57:51 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918877708 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3918877708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.1206410816 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 2264596721 ps |
| CPU time | 109.53 seconds |
| Started | Aug 25 04:57:01 PM UTC 24 |
| Finished | Aug 25 04:58:53 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206410816 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1206410816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.341288017 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 83482642538 ps |
| CPU time | 1292.7 seconds |
| Started | Aug 25 04:57:14 PM UTC 24 |
| Finished | Aug 25 05:19:04 PM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341288017 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.341288017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3974949192 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 56692792039 ps |
| CPU time | 1220.22 seconds |
| Started | Aug 25 04:57:19 PM UTC 24 |
| Finished | Aug 25 05:17:56 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974949192 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3974949192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1038176194 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 106578876 ps |
| CPU time | 14.94 seconds |
| Started | Aug 25 04:57:04 PM UTC 24 |
| Finished | Aug 25 04:57:20 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038176194 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delays.1038176194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.4255412021 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 75196537 ps |
| CPU time | 11.5 seconds |
| Started | Aug 25 04:57:23 PM UTC 24 |
| Finished | Aug 25 04:57:35 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255412021 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.4255412021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2756415275 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 229677696 ps |
| CPU time | 11.59 seconds |
| Started | Aug 25 04:56:41 PM UTC 24 |
| Finished | Aug 25 04:56:54 PM UTC 24 |
| Peak memory | 596992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756415275 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2756415275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2402762759 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 4842448766 ps |
| CPU time | 90.29 seconds |
| Started | Aug 25 04:57:00 PM UTC 24 |
| Finished | Aug 25 04:58:33 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402762759 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2402762759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1461493430 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 3246262541 ps |
| CPU time | 73.3 seconds |
| Started | Aug 25 04:57:01 PM UTC 24 |
| Finished | Aug 25 04:58:17 PM UTC 24 |
| Peak memory | 597076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461493430 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1461493430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1376565948 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 45092738 ps |
| CPU time | 7.68 seconds |
| Started | Aug 25 04:56:50 PM UTC 24 |
| Finished | Aug 25 04:56:59 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376565948 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays.1376565948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.939726499 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 1393418017 ps |
| CPU time | 161.44 seconds |
| Started | Aug 25 04:57:54 PM UTC 24 |
| Finished | Aug 25 05:00:39 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939726499 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.939726499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1795591501 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 7811228215 ps |
| CPU time | 407.88 seconds |
| Started | Aug 25 04:57:59 PM UTC 24 |
| Finished | Aug 25 05:04:53 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795591501 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1795591501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1172508848 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 20627870253 ps |
| CPU time | 1203.57 seconds |
| Started | Aug 25 04:58:01 PM UTC 24 |
| Finished | Aug 25 05:18:22 PM UTC 24 |
| Peak memory | 603288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172508848 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_reset_error.1172508848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2252292794 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 178035991 ps |
| CPU time | 29.81 seconds |
| Started | Aug 25 04:57:45 PM UTC 24 |
| Finished | Aug 25 04:58:17 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252292794 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2252292794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1200117095 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 2613468546 ps |
| CPU time | 150.88 seconds |
| Started | Aug 25 04:58:44 PM UTC 24 |
| Finished | Aug 25 05:01:18 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200117095 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device.1200117095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2667397853 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 441115313 ps |
| CPU time | 31.82 seconds |
| Started | Aug 25 04:59:03 PM UTC 24 |
| Finished | Aug 25 04:59:37 PM UTC 24 |
| Peak memory | 599236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667397853 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.2667397853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.2496371676 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 2123184525 ps |
| CPU time | 110.85 seconds |
| Started | Aug 25 04:58:55 PM UTC 24 |
| Finished | Aug 25 05:00:49 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496371676 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2496371676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.4034628014 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 942369075 ps |
| CPU time | 42.29 seconds |
| Started | Aug 25 04:58:42 PM UTC 24 |
| Finished | Aug 25 04:59:26 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034628014 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.4034628014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.4101983522 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 45558185930 ps |
| CPU time | 666.83 seconds |
| Started | Aug 25 04:58:43 PM UTC 24 |
| Finished | Aug 25 05:09:59 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101983522 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.4101983522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_slow_rsp.1618012870 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 55215145520 ps |
| CPU time | 1383.98 seconds |
| Started | Aug 25 04:58:44 PM UTC 24 |
| Finished | Aug 25 05:22:09 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618012870 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1618012870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3219409222 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 491339770 ps |
| CPU time | 67.66 seconds |
| Started | Aug 25 04:58:40 PM UTC 24 |
| Finished | Aug 25 04:59:50 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219409222 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_delays.3219409222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1960168705 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 2020202590 ps |
| CPU time | 82.27 seconds |
| Started | Aug 25 04:58:57 PM UTC 24 |
| Finished | Aug 25 05:00:21 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960168705 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1960168705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2783981926 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 48056795 ps |
| CPU time | 10.5 seconds |
| Started | Aug 25 04:58:08 PM UTC 24 |
| Finished | Aug 25 04:58:20 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783981926 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2783981926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.2751734102 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 10476765490 ps |
| CPU time | 159.63 seconds |
| Started | Aug 25 04:58:15 PM UTC 24 |
| Finished | Aug 25 05:00:58 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751734102 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2751734102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1867343875 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 5701121176 ps |
| CPU time | 126.38 seconds |
| Started | Aug 25 04:58:19 PM UTC 24 |
| Finished | Aug 25 05:00:28 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867343875 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1867343875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1401784401 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 54226450 ps |
| CPU time | 9.22 seconds |
| Started | Aug 25 04:58:13 PM UTC 24 |
| Finished | Aug 25 04:58:24 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401784401 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays.1401784401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.210894223 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 12940157952 ps |
| CPU time | 622.62 seconds |
| Started | Aug 25 04:59:06 PM UTC 24 |
| Finished | Aug 25 05:09:38 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210894223 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.210894223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2221558706 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 1414909725 ps |
| CPU time | 198.42 seconds |
| Started | Aug 25 04:59:13 PM UTC 24 |
| Finished | Aug 25 05:02:36 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221558706 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2221558706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4096622257 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 3041027014 ps |
| CPU time | 447.45 seconds |
| Started | Aug 25 04:59:10 PM UTC 24 |
| Finished | Aug 25 05:06:46 PM UTC 24 |
| Peak memory | 599560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096622257 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_rand_reset.4096622257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2228492683 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 5470296720 ps |
| CPU time | 526.11 seconds |
| Started | Aug 25 04:59:13 PM UTC 24 |
| Finished | Aug 25 05:08:08 PM UTC 24 |
| Peak memory | 599596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228492683 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_reset_error.2228492683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.4217532133 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 126845420 ps |
| CPU time | 20.66 seconds |
| Started | Aug 25 04:58:57 PM UTC 24 |
| Finished | Aug 25 04:59:19 PM UTC 24 |
| Peak memory | 599496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217532133 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.4217532133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1478584223 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 622479369 ps |
| CPU time | 80.03 seconds |
| Started | Aug 25 04:59:50 PM UTC 24 |
| Finished | Aug 25 05:01:12 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478584223 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device.1478584223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1886290563 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 114706450368 ps |
| CPU time | 2906.13 seconds |
| Started | Aug 25 05:00:00 PM UTC 24 |
| Finished | Aug 25 05:49:15 PM UTC 24 |
| Peak memory | 600096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886290563 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device_slow_rsp.1886290563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1324801967 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 975109146 ps |
| CPU time | 47.04 seconds |
| Started | Aug 25 05:00:15 PM UTC 24 |
| Finished | Aug 25 05:01:03 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324801967 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.1324801967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.3006473354 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 1762721694 ps |
| CPU time | 90.92 seconds |
| Started | Aug 25 05:00:09 PM UTC 24 |
| Finished | Aug 25 05:01:43 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006473354 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3006473354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.608637585 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 51448968 ps |
| CPU time | 12.29 seconds |
| Started | Aug 25 04:59:42 PM UTC 24 |
| Finished | Aug 25 04:59:56 PM UTC 24 |
| Peak memory | 597080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608637585 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.608637585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.2083255648 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 72055896673 ps |
| CPU time | 1145.75 seconds |
| Started | Aug 25 04:59:46 PM UTC 24 |
| Finished | Aug 25 05:19:08 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083255648 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2083255648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.2130001342 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 48314256119 ps |
| CPU time | 1084.5 seconds |
| Started | Aug 25 04:59:49 PM UTC 24 |
| Finished | Aug 25 05:18:10 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130001342 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2130001342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.2666485622 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 153537258 ps |
| CPU time | 21.23 seconds |
| Started | Aug 25 04:59:43 PM UTC 24 |
| Finished | Aug 25 05:00:05 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666485622 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delays.2666485622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3240698427 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 282944472 ps |
| CPU time | 33.24 seconds |
| Started | Aug 25 05:00:02 PM UTC 24 |
| Finished | Aug 25 05:00:41 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240698427 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3240698427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3599416606 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 53888223 ps |
| CPU time | 9.82 seconds |
| Started | Aug 25 04:59:13 PM UTC 24 |
| Finished | Aug 25 04:59:25 PM UTC 24 |
| Peak memory | 597188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599416606 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3599416606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2796975879 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 7886096405 ps |
| CPU time | 118.92 seconds |
| Started | Aug 25 04:59:31 PM UTC 24 |
| Finished | Aug 25 05:01:32 PM UTC 24 |
| Peak memory | 597320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796975879 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.2796975879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1036531897 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 4980012922 ps |
| CPU time | 117.53 seconds |
| Started | Aug 25 04:59:36 PM UTC 24 |
| Finished | Aug 25 05:01:36 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036531897 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1036531897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1620578458 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 51017630 ps |
| CPU time | 10.91 seconds |
| Started | Aug 25 04:59:27 PM UTC 24 |
| Finished | Aug 25 04:59:39 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620578458 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays.1620578458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1122889513 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 5484811179 ps |
| CPU time | 316.69 seconds |
| Started | Aug 25 05:00:20 PM UTC 24 |
| Finished | Aug 25 05:05:43 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122889513 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1122889513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2705060524 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 5924917669 ps |
| CPU time | 267.52 seconds |
| Started | Aug 25 05:00:35 PM UTC 24 |
| Finished | Aug 25 05:05:07 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705060524 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2705060524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3212534438 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 1725027839 ps |
| CPU time | 309.06 seconds |
| Started | Aug 25 05:00:34 PM UTC 24 |
| Finished | Aug 25 05:05:49 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212534438 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_rand_reset.3212534438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2796954807 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 4281063768 ps |
| CPU time | 486.58 seconds |
| Started | Aug 25 05:00:46 PM UTC 24 |
| Finished | Aug 25 05:08:59 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796954807 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_reset_error.2796954807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3949576315 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 129072183 ps |
| CPU time | 23.02 seconds |
| Started | Aug 25 05:00:15 PM UTC 24 |
| Finished | Aug 25 05:00:39 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949576315 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3949576315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.4212349197 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 697758422 ps |
| CPU time | 50.93 seconds |
| Started | Aug 25 05:01:25 PM UTC 24 |
| Finished | Aug 25 05:02:17 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212349197 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device.4212349197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.726817004 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 1134122784 ps |
| CPU time | 76.43 seconds |
| Started | Aug 25 05:01:58 PM UTC 24 |
| Finished | Aug 25 05:03:16 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726817004 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.726817004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1994258228 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 1873693975 ps |
| CPU time | 82.96 seconds |
| Started | Aug 25 05:01:44 PM UTC 24 |
| Finished | Aug 25 05:03:09 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994258228 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1994258228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.630749649 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 1866017561 ps |
| CPU time | 93.47 seconds |
| Started | Aug 25 05:01:04 PM UTC 24 |
| Finished | Aug 25 05:02:39 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630749649 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.630749649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_large_delays.636334851 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 102545964441 ps |
| CPU time | 1607.11 seconds |
| Started | Aug 25 05:01:21 PM UTC 24 |
| Finished | Aug 25 05:28:32 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636334851 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.636334851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_slow_rsp.962237392 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 71499471604 ps |
| CPU time | 1452.05 seconds |
| Started | Aug 25 05:01:24 PM UTC 24 |
| Finished | Aug 25 05:25:57 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962237392 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.962237392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.2397728977 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 66683526 ps |
| CPU time | 14.16 seconds |
| Started | Aug 25 05:01:14 PM UTC 24 |
| Finished | Aug 25 05:01:30 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397728977 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_delays.2397728977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.1331759909 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 1447815647 ps |
| CPU time | 61.82 seconds |
| Started | Aug 25 05:01:37 PM UTC 24 |
| Finished | Aug 25 05:02:40 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331759909 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1331759909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.792181270 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 47599044 ps |
| CPU time | 10.31 seconds |
| Started | Aug 25 05:00:52 PM UTC 24 |
| Finished | Aug 25 05:01:03 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792181270 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.792181270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.550797338 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 6799972747 ps |
| CPU time | 108.53 seconds |
| Started | Aug 25 05:01:01 PM UTC 24 |
| Finished | Aug 25 05:02:53 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550797338 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.550797338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3075207791 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 4809582370 ps |
| CPU time | 122.24 seconds |
| Started | Aug 25 05:01:04 PM UTC 24 |
| Finished | Aug 25 05:03:09 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075207791 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3075207791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3311162642 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 36468960 ps |
| CPU time | 8.42 seconds |
| Started | Aug 25 05:01:00 PM UTC 24 |
| Finished | Aug 25 05:01:09 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311162642 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.3311162642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3480303880 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 1800672556 ps |
| CPU time | 201.37 seconds |
| Started | Aug 25 05:01:59 PM UTC 24 |
| Finished | Aug 25 05:05:24 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480303880 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3480303880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.4102483215 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 884180185 ps |
| CPU time | 48.35 seconds |
| Started | Aug 25 05:02:00 PM UTC 24 |
| Finished | Aug 25 05:02:50 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102483215 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.4102483215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2445667781 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 7825780 ps |
| CPU time | 17.58 seconds |
| Started | Aug 25 05:02:00 PM UTC 24 |
| Finished | Aug 25 05:02:19 PM UTC 24 |
| Peak memory | 596936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445667781 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_rand_reset.2445667781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2311770359 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 250975925 ps |
| CPU time | 84.18 seconds |
| Started | Aug 25 05:02:07 PM UTC 24 |
| Finished | Aug 25 05:03:33 PM UTC 24 |
| Peak memory | 599476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311770359 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_reset_error.2311770359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.595370725 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 857035455 ps |
| CPU time | 60.14 seconds |
| Started | Aug 25 05:01:54 PM UTC 24 |
| Finished | Aug 25 05:02:56 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595370725 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.595370725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.362691479 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 572513450 ps |
| CPU time | 60.87 seconds |
| Started | Aug 25 05:03:00 PM UTC 24 |
| Finished | Aug 25 05:04:03 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362691479 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device.362691479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2049470648 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 113470835823 ps |
| CPU time | 2588.04 seconds |
| Started | Aug 25 05:03:05 PM UTC 24 |
| Finished | Aug 25 05:46:47 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049470648 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device_slow_rsp.2049470648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1227586816 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 237160823 ps |
| CPU time | 33.59 seconds |
| Started | Aug 25 05:03:14 PM UTC 24 |
| Finished | Aug 25 05:03:49 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227586816 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr.1227586816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.2458277135 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 1379292196 ps |
| CPU time | 72.51 seconds |
| Started | Aug 25 05:03:05 PM UTC 24 |
| Finished | Aug 25 05:04:20 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458277135 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2458277135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.329650790 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 1369210706 ps |
| CPU time | 57.81 seconds |
| Started | Aug 25 05:02:43 PM UTC 24 |
| Finished | Aug 25 05:03:42 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329650790 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.329650790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1203226698 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 28032960150 ps |
| CPU time | 446.48 seconds |
| Started | Aug 25 05:02:51 PM UTC 24 |
| Finished | Aug 25 05:10:25 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203226698 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1203226698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.100270294 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 30444520332 ps |
| CPU time | 707.68 seconds |
| Started | Aug 25 05:02:57 PM UTC 24 |
| Finished | Aug 25 05:14:55 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100270294 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.100270294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1396923814 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 443154155 ps |
| CPU time | 61.92 seconds |
| Started | Aug 25 05:02:47 PM UTC 24 |
| Finished | Aug 25 05:03:51 PM UTC 24 |
| Peak memory | 599144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396923814 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_delays.1396923814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4159945616 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 2185998448 ps |
| CPU time | 103.71 seconds |
| Started | Aug 25 05:03:04 PM UTC 24 |
| Finished | Aug 25 05:04:50 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159945616 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.4159945616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2006792838 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 39868974 ps |
| CPU time | 9.26 seconds |
| Started | Aug 25 05:02:13 PM UTC 24 |
| Finished | Aug 25 05:02:23 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006792838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2006792838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3177502866 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 8737729659 ps |
| CPU time | 139.34 seconds |
| Started | Aug 25 05:02:41 PM UTC 24 |
| Finished | Aug 25 05:05:03 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177502866 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3177502866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2742604456 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 5030181332 ps |
| CPU time | 127.95 seconds |
| Started | Aug 25 05:02:41 PM UTC 24 |
| Finished | Aug 25 05:04:52 PM UTC 24 |
| Peak memory | 597208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742604456 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2742604456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.216868893 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 38266858 ps |
| CPU time | 8.5 seconds |
| Started | Aug 25 05:02:23 PM UTC 24 |
| Finished | Aug 25 05:02:32 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216868893 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays.216868893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.717488129 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 2931093642 ps |
| CPU time | 400.42 seconds |
| Started | Aug 25 05:03:17 PM UTC 24 |
| Finished | Aug 25 05:10:05 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717488129 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.717488129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.3243819150 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 588951291 ps |
| CPU time | 80.1 seconds |
| Started | Aug 25 05:03:33 PM UTC 24 |
| Finished | Aug 25 05:04:55 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243819150 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3243819150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.26234118 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 6289538184 ps |
| CPU time | 694.79 seconds |
| Started | Aug 25 05:03:20 PM UTC 24 |
| Finished | Aug 25 05:15:07 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26234118 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_rand_reset.26234118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1617721603 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 10740581502 ps |
| CPU time | 859.41 seconds |
| Started | Aug 25 05:03:33 PM UTC 24 |
| Finished | Aug 25 05:18:06 PM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617721603 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_reset_error.1617721603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.3734313743 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 633409764 ps |
| CPU time | 49.28 seconds |
| Started | Aug 25 05:03:09 PM UTC 24 |
| Finished | Aug 25 05:04:00 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734313743 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3734313743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2373515706 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 1636259952 ps |
| CPU time | 92 seconds |
| Started | Aug 25 05:04:23 PM UTC 24 |
| Finished | Aug 25 05:05:58 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373515706 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.2373515706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3137708348 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 109068856886 ps |
| CPU time | 2624.77 seconds |
| Started | Aug 25 05:04:27 PM UTC 24 |
| Finished | Aug 25 05:48:51 PM UTC 24 |
| Peak memory | 600056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137708348 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device_slow_rsp.3137708348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.4120772063 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 301965958 ps |
| CPU time | 40.74 seconds |
| Started | Aug 25 05:05:17 PM UTC 24 |
| Finished | Aug 25 05:05:59 PM UTC 24 |
| Peak memory | 599548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120772063 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.4120772063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1947578930 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 39641369 ps |
| CPU time | 10.16 seconds |
| Started | Aug 25 05:05:13 PM UTC 24 |
| Finished | Aug 25 05:05:25 PM UTC 24 |
| Peak memory | 597160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947578930 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1947578930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.522970123 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 315782911 ps |
| CPU time | 38.6 seconds |
| Started | Aug 25 05:04:13 PM UTC 24 |
| Finished | Aug 25 05:04:53 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522970123 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.522970123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_large_delays.3997951391 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 98160294327 ps |
| CPU time | 1721.2 seconds |
| Started | Aug 25 05:04:17 PM UTC 24 |
| Finished | Aug 25 05:33:22 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997951391 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3997951391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_slow_rsp.2744821092 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 63165322287 ps |
| CPU time | 1360.68 seconds |
| Started | Aug 25 05:04:18 PM UTC 24 |
| Finished | Aug 25 05:27:17 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744821092 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2744821092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.3543299552 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 675633783 ps |
| CPU time | 75.87 seconds |
| Started | Aug 25 05:04:14 PM UTC 24 |
| Finished | Aug 25 05:05:32 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543299552 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_delays.3543299552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2581499661 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 64362498 ps |
| CPU time | 10.8 seconds |
| Started | Aug 25 05:04:43 PM UTC 24 |
| Finished | Aug 25 05:04:55 PM UTC 24 |
| Peak memory | 599348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581499661 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2581499661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.2101888461 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 187260201 ps |
| CPU time | 11.84 seconds |
| Started | Aug 25 05:03:40 PM UTC 24 |
| Finished | Aug 25 05:03:53 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101888461 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2101888461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.3095067433 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 8126810467 ps |
| CPU time | 146.09 seconds |
| Started | Aug 25 05:03:56 PM UTC 24 |
| Finished | Aug 25 05:06:25 PM UTC 24 |
| Peak memory | 597576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095067433 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.3095067433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2474718289 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 4504698732 ps |
| CPU time | 103.57 seconds |
| Started | Aug 25 05:04:04 PM UTC 24 |
| Finished | Aug 25 05:05:50 PM UTC 24 |
| Peak memory | 597632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474718289 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2474718289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2046876609 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 50815265 ps |
| CPU time | 10.72 seconds |
| Started | Aug 25 05:03:42 PM UTC 24 |
| Finished | Aug 25 05:03:54 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046876609 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays.2046876609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all.2525476662 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 18599998386 ps |
| CPU time | 959.94 seconds |
| Started | Aug 25 05:05:17 PM UTC 24 |
| Finished | Aug 25 05:21:31 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525476662 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2525476662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.4084569655 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 3924738746 ps |
| CPU time | 189.09 seconds |
| Started | Aug 25 05:05:20 PM UTC 24 |
| Finished | Aug 25 05:08:33 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084569655 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.4084569655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2663270787 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 7375600 ps |
| CPU time | 28.3 seconds |
| Started | Aug 25 05:05:18 PM UTC 24 |
| Finished | Aug 25 05:05:47 PM UTC 24 |
| Peak memory | 597172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663270787 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_rand_reset.2663270787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.762122909 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 265132665 ps |
| CPU time | 74.97 seconds |
| Started | Aug 25 05:05:21 PM UTC 24 |
| Finished | Aug 25 05:06:38 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762122909 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_reset_error.762122909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.124638978 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 77993179 ps |
| CPU time | 18.65 seconds |
| Started | Aug 25 05:05:14 PM UTC 24 |
| Finished | Aug 25 05:05:34 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124638978 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.124638978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1922244741 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 138369298 ps |
| CPU time | 18.75 seconds |
| Started | Aug 25 05:06:08 PM UTC 24 |
| Finished | Aug 25 05:06:27 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922244741 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.1922244741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.407521031 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 49842158132 ps |
| CPU time | 1101.39 seconds |
| Started | Aug 25 05:06:08 PM UTC 24 |
| Finished | Aug 25 05:24:44 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407521031 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device_slow_rsp.407521031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3951342557 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 95050909 ps |
| CPU time | 19.89 seconds |
| Started | Aug 25 05:06:21 PM UTC 24 |
| Finished | Aug 25 05:06:42 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951342557 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr.3951342557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.66379985 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 351922413 ps |
| CPU time | 20.07 seconds |
| Started | Aug 25 05:06:13 PM UTC 24 |
| Finished | Aug 25 05:06:34 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66379985 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.66379985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.4253944612 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 245194659 ps |
| CPU time | 35.44 seconds |
| Started | Aug 25 05:05:57 PM UTC 24 |
| Finished | Aug 25 05:06:35 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253944612 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4253944612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_large_delays.1469438791 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 63398615095 ps |
| CPU time | 1040.36 seconds |
| Started | Aug 25 05:05:59 PM UTC 24 |
| Finished | Aug 25 05:23:35 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469438791 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.1469438791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3498061078 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 31567421155 ps |
| CPU time | 686.98 seconds |
| Started | Aug 25 05:06:07 PM UTC 24 |
| Finished | Aug 25 05:17:44 PM UTC 24 |
| Peak memory | 599580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498061078 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3498061078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1050513460 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 537818669 ps |
| CPU time | 59.69 seconds |
| Started | Aug 25 05:05:56 PM UTC 24 |
| Finished | Aug 25 05:06:58 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050513460 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_delays.1050513460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.4216284245 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 38801047 ps |
| CPU time | 9.98 seconds |
| Started | Aug 25 05:06:12 PM UTC 24 |
| Finished | Aug 25 05:06:23 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216284245 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.4216284245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3224220094 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 185823857 ps |
| CPU time | 13.78 seconds |
| Started | Aug 25 05:05:28 PM UTC 24 |
| Finished | Aug 25 05:05:43 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224220094 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3224220094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1161369122 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 8143789095 ps |
| CPU time | 146.38 seconds |
| Started | Aug 25 05:05:49 PM UTC 24 |
| Finished | Aug 25 05:08:18 PM UTC 24 |
| Peak memory | 597396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161369122 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1161369122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3991823658 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 5130923743 ps |
| CPU time | 135.84 seconds |
| Started | Aug 25 05:05:49 PM UTC 24 |
| Finished | Aug 25 05:08:08 PM UTC 24 |
| Peak memory | 597464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991823658 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3991823658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3881030585 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 46418060 ps |
| CPU time | 10.24 seconds |
| Started | Aug 25 05:05:31 PM UTC 24 |
| Finished | Aug 25 05:05:43 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881030585 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.3881030585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1772861747 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 11735888528 ps |
| CPU time | 517.31 seconds |
| Started | Aug 25 05:06:22 PM UTC 24 |
| Finished | Aug 25 05:15:07 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772861747 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1772861747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1934782827 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 885189282 ps |
| CPU time | 123.4 seconds |
| Started | Aug 25 05:06:48 PM UTC 24 |
| Finished | Aug 25 05:08:55 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934782827 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1934782827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1698378020 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 1648707386 ps |
| CPU time | 178.59 seconds |
| Started | Aug 25 05:06:23 PM UTC 24 |
| Finished | Aug 25 05:09:25 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698378020 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_rand_reset.1698378020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1385698474 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 26366924 ps |
| CPU time | 40.72 seconds |
| Started | Aug 25 05:06:49 PM UTC 24 |
| Finished | Aug 25 05:07:31 PM UTC 24 |
| Peak memory | 597232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385698474 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_reset_error.1385698474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2731388492 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 951684785 ps |
| CPU time | 62.48 seconds |
| Started | Aug 25 05:06:14 PM UTC 24 |
| Finished | Aug 25 05:07:19 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731388492 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2731388492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3581021878 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 364867235 ps |
| CPU time | 31.32 seconds |
| Started | Aug 25 05:07:21 PM UTC 24 |
| Finished | Aug 25 05:07:54 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581021878 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device.3581021878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3860595680 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 48939360271 ps |
| CPU time | 1012.45 seconds |
| Started | Aug 25 05:07:23 PM UTC 24 |
| Finished | Aug 25 05:24:30 PM UTC 24 |
| Peak memory | 599536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860595680 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device_slow_rsp.3860595680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3625051578 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 258666889 ps |
| CPU time | 45.6 seconds |
| Started | Aug 25 05:07:41 PM UTC 24 |
| Finished | Aug 25 05:08:29 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625051578 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr.3625051578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.201332341 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 1624429538 ps |
| CPU time | 83 seconds |
| Started | Aug 25 05:07:34 PM UTC 24 |
| Finished | Aug 25 05:08:59 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201332341 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.201332341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3191324116 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 413615659 ps |
| CPU time | 58.18 seconds |
| Started | Aug 25 05:07:01 PM UTC 24 |
| Finished | Aug 25 05:08:01 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191324116 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3191324116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_large_delays.3632970085 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 96401729597 ps |
| CPU time | 1591.94 seconds |
| Started | Aug 25 05:07:10 PM UTC 24 |
| Finished | Aug 25 05:34:08 PM UTC 24 |
| Peak memory | 599608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632970085 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3632970085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_slow_rsp.1094743296 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 64560998358 ps |
| CPU time | 1513.24 seconds |
| Started | Aug 25 05:07:13 PM UTC 24 |
| Finished | Aug 25 05:32:48 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094743296 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1094743296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2732460852 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 243028431 ps |
| CPU time | 32.29 seconds |
| Started | Aug 25 05:07:07 PM UTC 24 |
| Finished | Aug 25 05:07:41 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732460852 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_delays.2732460852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1284667362 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 86125963 ps |
| CPU time | 14.97 seconds |
| Started | Aug 25 05:07:32 PM UTC 24 |
| Finished | Aug 25 05:07:48 PM UTC 24 |
| Peak memory | 599044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284667362 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1284667362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.3723955825 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 195909694 ps |
| CPU time | 15.13 seconds |
| Started | Aug 25 05:06:51 PM UTC 24 |
| Finished | Aug 25 05:07:08 PM UTC 24 |
| Peak memory | 597396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723955825 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3723955825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.985772559 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 8109345268 ps |
| CPU time | 122.48 seconds |
| Started | Aug 25 05:07:00 PM UTC 24 |
| Finished | Aug 25 05:09:05 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985772559 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.985772559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.4196188618 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 6042904280 ps |
| CPU time | 149.7 seconds |
| Started | Aug 25 05:07:00 PM UTC 24 |
| Finished | Aug 25 05:09:33 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196188618 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.4196188618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.741502975 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 54846775 ps |
| CPU time | 10.96 seconds |
| Started | Aug 25 05:06:59 PM UTC 24 |
| Finished | Aug 25 05:07:11 PM UTC 24 |
| Peak memory | 597200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741502975 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays.741502975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1132449097 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 12481440446 ps |
| CPU time | 638.95 seconds |
| Started | Aug 25 05:07:43 PM UTC 24 |
| Finished | Aug 25 05:18:31 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132449097 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1132449097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.4196631770 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 10394876274 ps |
| CPU time | 527.04 seconds |
| Started | Aug 25 05:07:58 PM UTC 24 |
| Finished | Aug 25 05:16:54 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196631770 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4196631770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2359779595 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 3560681681 ps |
| CPU time | 512.26 seconds |
| Started | Aug 25 05:07:56 PM UTC 24 |
| Finished | Aug 25 05:16:37 PM UTC 24 |
| Peak memory | 599372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359779595 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_rand_reset.2359779595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1576766294 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 6540537559 ps |
| CPU time | 675.22 seconds |
| Started | Aug 25 05:08:01 PM UTC 24 |
| Finished | Aug 25 05:19:26 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576766294 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_reset_error.1576766294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.980403685 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 785142442 ps |
| CPU time | 55.62 seconds |
| Started | Aug 25 05:07:36 PM UTC 24 |
| Finished | Aug 25 05:08:33 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980403685 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.980403685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3393059080 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 7307894201 ps |
| CPU time | 844.44 seconds |
| Started | Aug 25 03:40:51 PM UTC 24 |
| Finished | Aug 25 03:55:08 PM UTC 24 |
| Peak memory | 659252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3393059080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 6.chip_csr_mem_rw_with_rand_reset.3393059080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.2112804765 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5706589000 ps |
| CPU time | 987.24 seconds |
| Started | Aug 25 03:40:47 PM UTC 24 |
| Finished | Aug 25 03:57:30 PM UTC 24 |
| Peak memory | 618040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112804765 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2112804765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_same_csr_outstanding.1358200437 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 17462133652 ps |
| CPU time | 3318.65 seconds |
| Started | Aug 25 03:38:33 PM UTC 24 |
| Finished | Aug 25 04:34:38 PM UTC 24 |
| Peak memory | 613944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1358200437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.chip_same_csr_outstanding.1358200437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3218325607 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3061855912 ps |
| CPU time | 249.77 seconds |
| Started | Aug 25 03:38:41 PM UTC 24 |
| Finished | Aug 25 03:42:54 PM UTC 24 |
| Peak memory | 624376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218325607 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3218325607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3214539655 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 992107723 ps |
| CPU time | 98.83 seconds |
| Started | Aug 25 03:39:36 PM UTC 24 |
| Finished | Aug 25 03:41:17 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214539655 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3214539655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3918942971 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 106291700 ps |
| CPU time | 19.56 seconds |
| Started | Aug 25 03:40:24 PM UTC 24 |
| Finished | Aug 25 03:40:45 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918942971 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.3918942971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2252789607 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 476467488 ps |
| CPU time | 54.15 seconds |
| Started | Aug 25 03:40:08 PM UTC 24 |
| Finished | Aug 25 03:41:04 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252789607 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2252789607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.638092744 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 42849951 ps |
| CPU time | 9.98 seconds |
| Started | Aug 25 03:39:16 PM UTC 24 |
| Finished | Aug 25 03:39:27 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638092744 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.638092744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.4124717853 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 57840513293 ps |
| CPU time | 953.79 seconds |
| Started | Aug 25 03:39:29 PM UTC 24 |
| Finished | Aug 25 03:55:36 PM UTC 24 |
| Peak memory | 599628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124717853 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.4124717853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.3033287366 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 4028332103 ps |
| CPU time | 83.04 seconds |
| Started | Aug 25 03:39:34 PM UTC 24 |
| Finished | Aug 25 03:40:59 PM UTC 24 |
| Peak memory | 597076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033287366 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3033287366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.3218819834 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 123810597 ps |
| CPU time | 20.3 seconds |
| Started | Aug 25 03:39:26 PM UTC 24 |
| Finished | Aug 25 03:39:48 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218819834 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.3218819834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.2810527382 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 702340366 ps |
| CPU time | 33.84 seconds |
| Started | Aug 25 03:39:52 PM UTC 24 |
| Finished | Aug 25 03:40:27 PM UTC 24 |
| Peak memory | 599492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810527382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2810527382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1520619919 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 231075513 ps |
| CPU time | 15.88 seconds |
| Started | Aug 25 03:38:46 PM UTC 24 |
| Finished | Aug 25 03:39:03 PM UTC 24 |
| Peak memory | 597228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520619919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1520619919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.4283236490 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 7022218210 ps |
| CPU time | 116.89 seconds |
| Started | Aug 25 03:39:00 PM UTC 24 |
| Finished | Aug 25 03:41:00 PM UTC 24 |
| Peak memory | 597564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283236490 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4283236490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.104739466 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 4494820893 ps |
| CPU time | 91.59 seconds |
| Started | Aug 25 03:39:07 PM UTC 24 |
| Finished | Aug 25 03:40:40 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104739466 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.104739466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3197075689 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 44291953 ps |
| CPU time | 9.41 seconds |
| Started | Aug 25 03:39:01 PM UTC 24 |
| Finished | Aug 25 03:39:12 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197075689 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3197075689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1135489415 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1447713736 ps |
| CPU time | 189.59 seconds |
| Started | Aug 25 03:40:28 PM UTC 24 |
| Finished | Aug 25 03:43:41 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135489415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1135489415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3009195945 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3961513099 ps |
| CPU time | 201.56 seconds |
| Started | Aug 25 03:40:35 PM UTC 24 |
| Finished | Aug 25 03:44:00 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009195945 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3009195945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1299307336 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 548081247 ps |
| CPU time | 304.53 seconds |
| Started | Aug 25 03:40:31 PM UTC 24 |
| Finished | Aug 25 03:45:41 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299307336 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1299307336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2588999152 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1244922540 ps |
| CPU time | 295.91 seconds |
| Started | Aug 25 03:40:41 PM UTC 24 |
| Finished | Aug 25 03:45:42 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588999152 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.2588999152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1758242517 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1404341909 ps |
| CPU time | 86.59 seconds |
| Started | Aug 25 03:40:13 PM UTC 24 |
| Finished | Aug 25 03:41:42 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758242517 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1758242517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3923118117 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 897062331 ps |
| CPU time | 107.93 seconds |
| Started | Aug 25 05:08:40 PM UTC 24 |
| Finished | Aug 25 05:10:30 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923118117 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device.3923118117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1130455870 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 29838107682 ps |
| CPU time | 773.06 seconds |
| Started | Aug 25 05:08:43 PM UTC 24 |
| Finished | Aug 25 05:21:49 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130455870 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device_slow_rsp.1130455870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4071548835 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 326719606 ps |
| CPU time | 24.99 seconds |
| Started | Aug 25 05:08:54 PM UTC 24 |
| Finished | Aug 25 05:09:20 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071548835 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr.4071548835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1999687689 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 614252399 ps |
| CPU time | 29.68 seconds |
| Started | Aug 25 05:08:46 PM UTC 24 |
| Finished | Aug 25 05:09:18 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999687689 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1999687689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.604900506 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 1197706984 ps |
| CPU time | 65.6 seconds |
| Started | Aug 25 05:08:26 PM UTC 24 |
| Finished | Aug 25 05:09:34 PM UTC 24 |
| Peak memory | 599220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604900506 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.604900506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_large_delays.2377800568 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 78000550404 ps |
| CPU time | 1147.6 seconds |
| Started | Aug 25 05:08:32 PM UTC 24 |
| Finished | Aug 25 05:27:54 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377800568 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2377800568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.143766735 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 33113641352 ps |
| CPU time | 663.42 seconds |
| Started | Aug 25 05:08:39 PM UTC 24 |
| Finished | Aug 25 05:19:52 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143766735 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.143766735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.4030079729 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 418729973 ps |
| CPU time | 59.23 seconds |
| Started | Aug 25 05:08:32 PM UTC 24 |
| Finished | Aug 25 05:09:33 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030079729 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_delays.4030079729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2618088594 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 2344582352 ps |
| CPU time | 105.66 seconds |
| Started | Aug 25 05:08:41 PM UTC 24 |
| Finished | Aug 25 05:10:29 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618088594 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2618088594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4156985059 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 50487840 ps |
| CPU time | 10.56 seconds |
| Started | Aug 25 05:08:05 PM UTC 24 |
| Finished | Aug 25 05:08:16 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156985059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.4156985059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1294663805 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 9309260515 ps |
| CPU time | 164.04 seconds |
| Started | Aug 25 05:08:15 PM UTC 24 |
| Finished | Aug 25 05:11:02 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294663805 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1294663805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3428861910 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 5052487046 ps |
| CPU time | 119.87 seconds |
| Started | Aug 25 05:08:19 PM UTC 24 |
| Finished | Aug 25 05:10:21 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428861910 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3428861910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2413447075 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 48208323 ps |
| CPU time | 10.62 seconds |
| Started | Aug 25 05:08:12 PM UTC 24 |
| Finished | Aug 25 05:08:24 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413447075 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.2413447075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.2791462801 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 2413847773 ps |
| CPU time | 123.84 seconds |
| Started | Aug 25 05:08:58 PM UTC 24 |
| Finished | Aug 25 05:11:05 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791462801 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2791462801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1057334097 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 4584161922 ps |
| CPU time | 520.98 seconds |
| Started | Aug 25 05:09:03 PM UTC 24 |
| Finished | Aug 25 05:17:53 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057334097 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1057334097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2020875087 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 18483366266 ps |
| CPU time | 1141.97 seconds |
| Started | Aug 25 05:08:59 PM UTC 24 |
| Finished | Aug 25 05:28:16 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020875087 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_rand_reset.2020875087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1757772010 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 10471258018 ps |
| CPU time | 924.64 seconds |
| Started | Aug 25 05:09:15 PM UTC 24 |
| Finished | Aug 25 05:24:55 PM UTC 24 |
| Peak memory | 599672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757772010 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_reset_error.1757772010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.3991304397 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 74359205 ps |
| CPU time | 17.87 seconds |
| Started | Aug 25 05:08:48 PM UTC 24 |
| Finished | Aug 25 05:09:07 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991304397 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.3991304397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2582477812 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 668390062 ps |
| CPU time | 79.61 seconds |
| Started | Aug 25 05:09:41 PM UTC 24 |
| Finished | Aug 25 05:11:03 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582477812 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.2582477812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3189278188 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 118092416219 ps |
| CPU time | 2702.59 seconds |
| Started | Aug 25 05:09:45 PM UTC 24 |
| Finished | Aug 25 05:55:27 PM UTC 24 |
| Peak memory | 600288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189278188 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device_slow_rsp.3189278188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2028845889 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 1480192613 ps |
| CPU time | 76.98 seconds |
| Started | Aug 25 05:09:57 PM UTC 24 |
| Finished | Aug 25 05:11:16 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028845889 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr.2028845889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.3925393786 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 788283040 ps |
| CPU time | 44.85 seconds |
| Started | Aug 25 05:09:54 PM UTC 24 |
| Finished | Aug 25 05:10:41 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925393786 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3925393786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1545236821 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 916730846 ps |
| CPU time | 56.17 seconds |
| Started | Aug 25 05:09:24 PM UTC 24 |
| Finished | Aug 25 05:10:22 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545236821 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1545236821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_large_delays.709414378 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 47617875870 ps |
| CPU time | 768.04 seconds |
| Started | Aug 25 05:09:30 PM UTC 24 |
| Finished | Aug 25 05:22:29 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709414378 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.709414378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_slow_rsp.3970083661 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 56925384933 ps |
| CPU time | 1257.02 seconds |
| Started | Aug 25 05:09:32 PM UTC 24 |
| Finished | Aug 25 05:30:46 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970083661 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3970083661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.575404838 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 85148350 ps |
| CPU time | 16.45 seconds |
| Started | Aug 25 05:09:29 PM UTC 24 |
| Finished | Aug 25 05:09:46 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575404838 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_delays.575404838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3144776009 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 642696646 ps |
| CPU time | 28.14 seconds |
| Started | Aug 25 05:09:50 PM UTC 24 |
| Finished | Aug 25 05:10:20 PM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144776009 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3144776009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3148411344 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 45915226 ps |
| CPU time | 8.87 seconds |
| Started | Aug 25 05:09:19 PM UTC 24 |
| Finished | Aug 25 05:09:29 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148411344 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3148411344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2016332008 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 5952776103 ps |
| CPU time | 104.85 seconds |
| Started | Aug 25 05:09:22 PM UTC 24 |
| Finished | Aug 25 05:11:10 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016332008 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2016332008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2592694302 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 4695045021 ps |
| CPU time | 122.51 seconds |
| Started | Aug 25 05:09:24 PM UTC 24 |
| Finished | Aug 25 05:11:29 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592694302 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2592694302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.939145933 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 47934798 ps |
| CPU time | 10.49 seconds |
| Started | Aug 25 05:09:20 PM UTC 24 |
| Finished | Aug 25 05:09:32 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939145933 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays.939145933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all.2376559572 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 13695200996 ps |
| CPU time | 711.66 seconds |
| Started | Aug 25 05:09:59 PM UTC 24 |
| Finished | Aug 25 05:22:02 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376559572 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2376559572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_error.3650702408 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 17183311977 ps |
| CPU time | 985.69 seconds |
| Started | Aug 25 05:10:03 PM UTC 24 |
| Finished | Aug 25 05:26:44 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650702408 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3650702408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.16683841 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 1062760052 ps |
| CPU time | 333.59 seconds |
| Started | Aug 25 05:09:58 PM UTC 24 |
| Finished | Aug 25 05:15:38 PM UTC 24 |
| Peak memory | 599140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16683841 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_rand_reset.16683841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.686839185 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 274039824 ps |
| CPU time | 130.93 seconds |
| Started | Aug 25 05:10:11 PM UTC 24 |
| Finished | Aug 25 05:12:25 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686839185 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_reset_error.686839185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.143459121 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 332270872 ps |
| CPU time | 59.51 seconds |
| Started | Aug 25 05:09:57 PM UTC 24 |
| Finished | Aug 25 05:10:59 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143459121 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.143459121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.648128580 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 787531163 ps |
| CPU time | 66.55 seconds |
| Started | Aug 25 05:10:53 PM UTC 24 |
| Finished | Aug 25 05:12:01 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648128580 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.648128580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1549521042 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 111109291224 ps |
| CPU time | 2845.51 seconds |
| Started | Aug 25 05:10:54 PM UTC 24 |
| Finished | Aug 25 05:59:03 PM UTC 24 |
| Peak memory | 600284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549521042 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device_slow_rsp.1549521042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.824413443 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 135931483 ps |
| CPU time | 21.56 seconds |
| Started | Aug 25 05:11:06 PM UTC 24 |
| Finished | Aug 25 05:11:28 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824413443 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr.824413443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.4043646936 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 2566498314 ps |
| CPU time | 130.23 seconds |
| Started | Aug 25 05:11:00 PM UTC 24 |
| Finished | Aug 25 05:13:13 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043646936 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.4043646936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.338048960 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 498402476 ps |
| CPU time | 65.49 seconds |
| Started | Aug 25 05:10:44 PM UTC 24 |
| Finished | Aug 25 05:11:51 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338048960 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.338048960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_large_delays.925213821 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 57864974583 ps |
| CPU time | 884.55 seconds |
| Started | Aug 25 05:10:46 PM UTC 24 |
| Finished | Aug 25 05:25:43 PM UTC 24 |
| Peak memory | 599180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925213821 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.925213821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_slow_rsp.1246679877 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 46644035007 ps |
| CPU time | 1189.49 seconds |
| Started | Aug 25 05:10:49 PM UTC 24 |
| Finished | Aug 25 05:30:56 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246679877 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1246679877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.486555719 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 479810615 ps |
| CPU time | 69.6 seconds |
| Started | Aug 25 05:10:45 PM UTC 24 |
| Finished | Aug 25 05:11:56 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486555719 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_delays.486555719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3250268265 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 1172548518 ps |
| CPU time | 60.68 seconds |
| Started | Aug 25 05:10:58 PM UTC 24 |
| Finished | Aug 25 05:12:01 PM UTC 24 |
| Peak memory | 599228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250268265 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3250268265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.724950261 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 54519234 ps |
| CPU time | 11.01 seconds |
| Started | Aug 25 05:10:23 PM UTC 24 |
| Finished | Aug 25 05:10:35 PM UTC 24 |
| Peak memory | 594340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724950261 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.724950261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.740636809 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 7088238289 ps |
| CPU time | 125.25 seconds |
| Started | Aug 25 05:10:35 PM UTC 24 |
| Finished | Aug 25 05:12:44 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740636809 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.740636809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3748080987 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 5884744363 ps |
| CPU time | 156.97 seconds |
| Started | Aug 25 05:10:43 PM UTC 24 |
| Finished | Aug 25 05:13:23 PM UTC 24 |
| Peak memory | 597344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748080987 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3748080987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3796115193 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 39472740 ps |
| CPU time | 9.63 seconds |
| Started | Aug 25 05:10:30 PM UTC 24 |
| Finished | Aug 25 05:10:41 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796115193 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays.3796115193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all.620463245 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 13128044805 ps |
| CPU time | 728.26 seconds |
| Started | Aug 25 05:11:05 PM UTC 24 |
| Finished | Aug 25 05:23:25 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620463245 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.620463245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2817969964 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 5629260853 ps |
| CPU time | 342.47 seconds |
| Started | Aug 25 05:11:23 PM UTC 24 |
| Finished | Aug 25 05:17:12 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817969964 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2817969964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1304568107 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 9512238188 ps |
| CPU time | 798.9 seconds |
| Started | Aug 25 05:11:10 PM UTC 24 |
| Finished | Aug 25 05:24:41 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304568107 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_rand_reset.1304568107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2324883651 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 253018070 ps |
| CPU time | 119.13 seconds |
| Started | Aug 25 05:11:27 PM UTC 24 |
| Finished | Aug 25 05:13:29 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324883651 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_reset_error.2324883651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.1956715405 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 692062799 ps |
| CPU time | 51.35 seconds |
| Started | Aug 25 05:11:04 PM UTC 24 |
| Finished | Aug 25 05:11:57 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956715405 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1956715405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.3345144888 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 980786451 ps |
| CPU time | 111.55 seconds |
| Started | Aug 25 05:12:07 PM UTC 24 |
| Finished | Aug 25 05:14:01 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345144888 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device.3345144888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.4204739531 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 28960730894 ps |
| CPU time | 738.14 seconds |
| Started | Aug 25 05:12:17 PM UTC 24 |
| Finished | Aug 25 05:24:46 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204739531 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device_slow_rsp.4204739531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.450408166 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 39744771 ps |
| CPU time | 11.15 seconds |
| Started | Aug 25 05:12:25 PM UTC 24 |
| Finished | Aug 25 05:12:38 PM UTC 24 |
| Peak memory | 597416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450408166 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr.450408166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.305423360 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 1701202116 ps |
| CPU time | 90.58 seconds |
| Started | Aug 25 05:12:23 PM UTC 24 |
| Finished | Aug 25 05:13:55 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305423360 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.305423360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3831623212 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 2077122603 ps |
| CPU time | 82.1 seconds |
| Started | Aug 25 05:11:40 PM UTC 24 |
| Finished | Aug 25 05:13:04 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831623212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3831623212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_large_delays.61158630 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 87821397622 ps |
| CPU time | 1247.81 seconds |
| Started | Aug 25 05:11:51 PM UTC 24 |
| Finished | Aug 25 05:32:56 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61158630 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.61158630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_slow_rsp.1814991338 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 34759367585 ps |
| CPU time | 867.71 seconds |
| Started | Aug 25 05:12:03 PM UTC 24 |
| Finished | Aug 25 05:26:44 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814991338 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1814991338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.326275835 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 32878352 ps |
| CPU time | 9.98 seconds |
| Started | Aug 25 05:11:51 PM UTC 24 |
| Finished | Aug 25 05:12:03 PM UTC 24 |
| Peak memory | 597160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326275835 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_delays.326275835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1083318542 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 299498473 ps |
| CPU time | 38.04 seconds |
| Started | Aug 25 05:12:22 PM UTC 24 |
| Finished | Aug 25 05:13:01 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083318542 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1083318542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.595603027 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 224114589 ps |
| CPU time | 15.65 seconds |
| Started | Aug 25 05:11:26 PM UTC 24 |
| Finished | Aug 25 05:11:43 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595603027 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.595603027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3204673929 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 9317154823 ps |
| CPU time | 171.64 seconds |
| Started | Aug 25 05:11:33 PM UTC 24 |
| Finished | Aug 25 05:14:28 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204673929 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3204673929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2836748593 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 3728220004 ps |
| CPU time | 88.47 seconds |
| Started | Aug 25 05:11:34 PM UTC 24 |
| Finished | Aug 25 05:13:04 PM UTC 24 |
| Peak memory | 597212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836748593 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2836748593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1632251890 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 36140212 ps |
| CPU time | 9.23 seconds |
| Started | Aug 25 05:11:29 PM UTC 24 |
| Finished | Aug 25 05:11:39 PM UTC 24 |
| Peak memory | 597160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632251890 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays.1632251890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all.3337573737 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 12345045113 ps |
| CPU time | 588.86 seconds |
| Started | Aug 25 05:12:28 PM UTC 24 |
| Finished | Aug 25 05:22:26 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337573737 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3337573737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.144174786 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 933242017 ps |
| CPU time | 49.33 seconds |
| Started | Aug 25 05:13:02 PM UTC 24 |
| Finished | Aug 25 05:13:53 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144174786 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.144174786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3257404288 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 281255700 ps |
| CPU time | 249.58 seconds |
| Started | Aug 25 05:12:49 PM UTC 24 |
| Finished | Aug 25 05:17:04 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257404288 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_rand_reset.3257404288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3847952691 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 631535067 ps |
| CPU time | 361.02 seconds |
| Started | Aug 25 05:13:08 PM UTC 24 |
| Finished | Aug 25 05:19:14 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847952691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_reset_error.3847952691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3432532919 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 1176146015 ps |
| CPU time | 76.15 seconds |
| Started | Aug 25 05:12:26 PM UTC 24 |
| Finished | Aug 25 05:13:44 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432532919 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3432532919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.934534190 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 934568923 ps |
| CPU time | 120.8 seconds |
| Started | Aug 25 05:14:03 PM UTC 24 |
| Finished | Aug 25 05:16:07 PM UTC 24 |
| Peak memory | 599504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934534190 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device.934534190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.4219084994 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 40221292374 ps |
| CPU time | 1043.87 seconds |
| Started | Aug 25 05:14:01 PM UTC 24 |
| Finished | Aug 25 05:31:41 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219084994 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device_slow_rsp.4219084994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.531467747 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 100099856 ps |
| CPU time | 15.61 seconds |
| Started | Aug 25 05:14:20 PM UTC 24 |
| Finished | Aug 25 05:14:37 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531467747 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.531467747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.830448785 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 396807516 ps |
| CPU time | 49.71 seconds |
| Started | Aug 25 05:14:17 PM UTC 24 |
| Finished | Aug 25 05:15:08 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830448785 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.830448785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.2706956573 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 42690816 ps |
| CPU time | 10.94 seconds |
| Started | Aug 25 05:13:47 PM UTC 24 |
| Finished | Aug 25 05:13:59 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706956573 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2706956573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3866008292 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 106861388889 ps |
| CPU time | 1843.67 seconds |
| Started | Aug 25 05:13:52 PM UTC 24 |
| Finished | Aug 25 05:45:03 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866008292 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3866008292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_slow_rsp.3880006894 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 22623028169 ps |
| CPU time | 577.5 seconds |
| Started | Aug 25 05:14:00 PM UTC 24 |
| Finished | Aug 25 05:23:47 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880006894 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3880006894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3665199922 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 441268531 ps |
| CPU time | 61.89 seconds |
| Started | Aug 25 05:13:50 PM UTC 24 |
| Finished | Aug 25 05:14:54 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665199922 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_delays.3665199922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.1082899588 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 414983866 ps |
| CPU time | 23.64 seconds |
| Started | Aug 25 05:14:07 PM UTC 24 |
| Finished | Aug 25 05:14:32 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082899588 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.1082899588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.2810916891 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 260026344 ps |
| CPU time | 16.64 seconds |
| Started | Aug 25 05:13:20 PM UTC 24 |
| Finished | Aug 25 05:13:38 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810916891 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2810916891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.2241126685 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 6470695237 ps |
| CPU time | 111.09 seconds |
| Started | Aug 25 05:13:29 PM UTC 24 |
| Finished | Aug 25 05:15:23 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241126685 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2241126685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.571285882 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 3966234816 ps |
| CPU time | 91.86 seconds |
| Started | Aug 25 05:13:35 PM UTC 24 |
| Finished | Aug 25 05:15:09 PM UTC 24 |
| Peak memory | 597068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571285882 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.571285882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.213029440 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 48685153 ps |
| CPU time | 9.74 seconds |
| Started | Aug 25 05:13:28 PM UTC 24 |
| Finished | Aug 25 05:13:39 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213029440 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays.213029440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.1892110398 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 1628210297 ps |
| CPU time | 198.44 seconds |
| Started | Aug 25 05:14:23 PM UTC 24 |
| Finished | Aug 25 05:17:45 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892110398 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1892110398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_error.2793215418 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 8580231439 ps |
| CPU time | 387.31 seconds |
| Started | Aug 25 05:14:56 PM UTC 24 |
| Finished | Aug 25 05:21:29 PM UTC 24 |
| Peak memory | 599692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793215418 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2793215418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.575935396 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 3461877591 ps |
| CPU time | 521.18 seconds |
| Started | Aug 25 05:14:49 PM UTC 24 |
| Finished | Aug 25 05:23:39 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575935396 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_rand_reset.575935396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3204280112 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 8534332887 ps |
| CPU time | 730.42 seconds |
| Started | Aug 25 05:14:59 PM UTC 24 |
| Finished | Aug 25 05:27:22 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204280112 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_reset_error.3204280112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.516188468 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 427662479 ps |
| CPU time | 28.15 seconds |
| Started | Aug 25 05:14:17 PM UTC 24 |
| Finished | Aug 25 05:14:47 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516188468 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.516188468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.3763891241 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 739942456 ps |
| CPU time | 92.45 seconds |
| Started | Aug 25 05:15:52 PM UTC 24 |
| Finished | Aug 25 05:17:27 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763891241 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.3763891241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.180990278 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 109843772867 ps |
| CPU time | 2642.59 seconds |
| Started | Aug 25 05:15:55 PM UTC 24 |
| Finished | Aug 25 06:00:37 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180990278 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device_slow_rsp.180990278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2129994373 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 813529241 ps |
| CPU time | 45.6 seconds |
| Started | Aug 25 05:16:49 PM UTC 24 |
| Finished | Aug 25 05:17:36 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129994373 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.2129994373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3767410958 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 130028883 ps |
| CPU time | 12.93 seconds |
| Started | Aug 25 05:16:12 PM UTC 24 |
| Finished | Aug 25 05:16:26 PM UTC 24 |
| Peak memory | 597416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767410958 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3767410958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.454790030 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 508824925 ps |
| CPU time | 59.36 seconds |
| Started | Aug 25 05:15:32 PM UTC 24 |
| Finished | Aug 25 05:16:34 PM UTC 24 |
| Peak memory | 599240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454790030 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.454790030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.3990417294 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 94267518338 ps |
| CPU time | 1586.87 seconds |
| Started | Aug 25 05:15:35 PM UTC 24 |
| Finished | Aug 25 05:42:26 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990417294 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3990417294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_slow_rsp.3696246045 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 24728683581 ps |
| CPU time | 580.71 seconds |
| Started | Aug 25 05:15:48 PM UTC 24 |
| Finished | Aug 25 05:25:38 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696246045 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3696246045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1964718283 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 468110474 ps |
| CPU time | 65.81 seconds |
| Started | Aug 25 05:15:34 PM UTC 24 |
| Finished | Aug 25 05:16:42 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964718283 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_delays.1964718283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.886553242 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 1925696092 ps |
| CPU time | 94.39 seconds |
| Started | Aug 25 05:16:03 PM UTC 24 |
| Finished | Aug 25 05:17:40 PM UTC 24 |
| Peak memory | 599492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886553242 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.886553242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2014867555 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 224320760 ps |
| CPU time | 14.32 seconds |
| Started | Aug 25 05:15:11 PM UTC 24 |
| Finished | Aug 25 05:15:27 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014867555 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2014867555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.396660646 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 6965873830 ps |
| CPU time | 120.28 seconds |
| Started | Aug 25 05:15:20 PM UTC 24 |
| Finished | Aug 25 05:17:22 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396660646 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.396660646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.859681071 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 6317090464 ps |
| CPU time | 162.21 seconds |
| Started | Aug 25 05:15:32 PM UTC 24 |
| Finished | Aug 25 05:18:18 PM UTC 24 |
| Peak memory | 597524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859681071 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.859681071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1039660714 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 43816363 ps |
| CPU time | 10.08 seconds |
| Started | Aug 25 05:15:19 PM UTC 24 |
| Finished | Aug 25 05:15:30 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039660714 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays.1039660714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all.4212412343 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 2362900919 ps |
| CPU time | 277.13 seconds |
| Started | Aug 25 05:16:57 PM UTC 24 |
| Finished | Aug 25 05:21:39 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212412343 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.4212412343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_error.4282573277 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 2116009797 ps |
| CPU time | 214.05 seconds |
| Started | Aug 25 05:17:02 PM UTC 24 |
| Finished | Aug 25 05:20:41 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282573277 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.4282573277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.393354786 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 5400321638 ps |
| CPU time | 520.34 seconds |
| Started | Aug 25 05:16:58 PM UTC 24 |
| Finished | Aug 25 05:25:46 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393354786 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_rand_reset.393354786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2529265923 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 8946760355 ps |
| CPU time | 752.72 seconds |
| Started | Aug 25 05:17:17 PM UTC 24 |
| Finished | Aug 25 05:30:02 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529265923 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_reset_error.2529265923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3818122754 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 170996749 ps |
| CPU time | 34.06 seconds |
| Started | Aug 25 05:16:31 PM UTC 24 |
| Finished | Aug 25 05:17:07 PM UTC 24 |
| Peak memory | 599508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818122754 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3818122754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2293652580 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 1149235547 ps |
| CPU time | 59.31 seconds |
| Started | Aug 25 05:18:03 PM UTC 24 |
| Finished | Aug 25 05:19:05 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293652580 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device.2293652580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.25897512 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 74599253903 ps |
| CPU time | 1785.86 seconds |
| Started | Aug 25 05:18:03 PM UTC 24 |
| Finished | Aug 25 05:48:15 PM UTC 24 |
| Peak memory | 599632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25897512 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device_slow_rsp.25897512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.411387400 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 1016949402 ps |
| CPU time | 62.24 seconds |
| Started | Aug 25 05:18:20 PM UTC 24 |
| Finished | Aug 25 05:19:24 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411387400 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr.411387400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.33537527 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 1087178531 ps |
| CPU time | 62.5 seconds |
| Started | Aug 25 05:18:10 PM UTC 24 |
| Finished | Aug 25 05:19:14 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33537527 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.33537527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.611166076 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 749862930 ps |
| CPU time | 36.96 seconds |
| Started | Aug 25 05:17:47 PM UTC 24 |
| Finished | Aug 25 05:18:25 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611166076 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.611166076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_large_delays.497477014 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 58677801103 ps |
| CPU time | 918.34 seconds |
| Started | Aug 25 05:18:00 PM UTC 24 |
| Finished | Aug 25 05:33:32 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497477014 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.497477014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_slow_rsp.712398130 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 17059659194 ps |
| CPU time | 431.34 seconds |
| Started | Aug 25 05:18:03 PM UTC 24 |
| Finished | Aug 25 05:25:22 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712398130 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.712398130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3790314335 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 122152227 ps |
| CPU time | 21.36 seconds |
| Started | Aug 25 05:17:52 PM UTC 24 |
| Finished | Aug 25 05:18:15 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790314335 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_delays.3790314335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3364151621 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 454770419 ps |
| CPU time | 26.21 seconds |
| Started | Aug 25 05:18:08 PM UTC 24 |
| Finished | Aug 25 05:18:36 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364151621 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3364151621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2491947242 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 42135225 ps |
| CPU time | 9.52 seconds |
| Started | Aug 25 05:17:27 PM UTC 24 |
| Finished | Aug 25 05:17:38 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491947242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.2491947242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.1993220011 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 7782959188 ps |
| CPU time | 133.78 seconds |
| Started | Aug 25 05:17:31 PM UTC 24 |
| Finished | Aug 25 05:19:48 PM UTC 24 |
| Peak memory | 597628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993220011 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1993220011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1918097562 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 4310083011 ps |
| CPU time | 109.95 seconds |
| Started | Aug 25 05:17:36 PM UTC 24 |
| Finished | Aug 25 05:19:29 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918097562 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1918097562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4134745096 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 51912499 ps |
| CPU time | 10.73 seconds |
| Started | Aug 25 05:17:28 PM UTC 24 |
| Finished | Aug 25 05:17:40 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134745096 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.4134745096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3158770643 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1035188681 ps |
| CPU time | 55.17 seconds |
| Started | Aug 25 05:18:31 PM UTC 24 |
| Finished | Aug 25 05:19:28 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158770643 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3158770643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_error.465895363 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 2893810804 ps |
| CPU time | 272.75 seconds |
| Started | Aug 25 05:18:39 PM UTC 24 |
| Finished | Aug 25 05:23:16 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465895363 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.465895363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.957343498 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 7073607231 ps |
| CPU time | 686.53 seconds |
| Started | Aug 25 05:18:35 PM UTC 24 |
| Finished | Aug 25 05:30:12 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957343498 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_rand_reset.957343498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3682484766 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 2080889484 ps |
| CPU time | 387.8 seconds |
| Started | Aug 25 05:18:42 PM UTC 24 |
| Finished | Aug 25 05:25:16 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682484766 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_reset_error.3682484766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.3775434558 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 116575327 ps |
| CPU time | 25.8 seconds |
| Started | Aug 25 05:18:17 PM UTC 24 |
| Finished | Aug 25 05:18:44 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775434558 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3775434558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.268177928 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 108438782 ps |
| CPU time | 9.39 seconds |
| Started | Aug 25 05:19:29 PM UTC 24 |
| Finished | Aug 25 05:19:39 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268177928 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device.268177928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2687697301 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 136827879556 ps |
| CPU time | 2792.42 seconds |
| Started | Aug 25 05:19:33 PM UTC 24 |
| Finished | Aug 25 06:06:42 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687697301 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device_slow_rsp.2687697301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.459630609 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 52671748 ps |
| CPU time | 13.57 seconds |
| Started | Aug 25 05:19:51 PM UTC 24 |
| Finished | Aug 25 05:20:06 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459630609 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr.459630609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_random.2957565741 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 1452380725 ps |
| CPU time | 84.45 seconds |
| Started | Aug 25 05:19:39 PM UTC 24 |
| Finished | Aug 25 05:21:06 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957565741 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2957565741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random.2263292934 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 1711385994 ps |
| CPU time | 96.55 seconds |
| Started | Aug 25 05:19:08 PM UTC 24 |
| Finished | Aug 25 05:20:47 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263292934 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2263292934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3517627533 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 82827494477 ps |
| CPU time | 1424.53 seconds |
| Started | Aug 25 05:19:27 PM UTC 24 |
| Finished | Aug 25 05:43:35 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517627533 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3517627533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_slow_rsp.1633538807 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 39826447840 ps |
| CPU time | 842.52 seconds |
| Started | Aug 25 05:19:28 PM UTC 24 |
| Finished | Aug 25 05:33:42 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633538807 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1633538807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.2017795182 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 232990930 ps |
| CPU time | 37.02 seconds |
| Started | Aug 25 05:19:23 PM UTC 24 |
| Finished | Aug 25 05:20:01 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017795182 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delays.2017795182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.3185278260 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 395246184 ps |
| CPU time | 37.22 seconds |
| Started | Aug 25 05:19:38 PM UTC 24 |
| Finished | Aug 25 05:20:17 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185278260 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3185278260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1010456142 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 48853504 ps |
| CPU time | 10.55 seconds |
| Started | Aug 25 05:18:46 PM UTC 24 |
| Finished | Aug 25 05:18:58 PM UTC 24 |
| Peak memory | 596992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010456142 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1010456142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_large_delays.1898363728 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 7546048187 ps |
| CPU time | 134.76 seconds |
| Started | Aug 25 05:18:55 PM UTC 24 |
| Finished | Aug 25 05:21:13 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898363728 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1898363728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.881238942 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 4572190377 ps |
| CPU time | 116.91 seconds |
| Started | Aug 25 05:19:01 PM UTC 24 |
| Finished | Aug 25 05:21:00 PM UTC 24 |
| Peak memory | 597212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881238942 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.881238942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4023864676 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 51952519 ps |
| CPU time | 10.97 seconds |
| Started | Aug 25 05:18:50 PM UTC 24 |
| Finished | Aug 25 05:19:02 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023864676 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays.4023864676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all.3060265187 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 14477728939 ps |
| CPU time | 777.11 seconds |
| Started | Aug 25 05:19:52 PM UTC 24 |
| Finished | Aug 25 05:33:01 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060265187 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3060265187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_error.580342143 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 3177108020 ps |
| CPU time | 183.31 seconds |
| Started | Aug 25 05:19:59 PM UTC 24 |
| Finished | Aug 25 05:23:06 PM UTC 24 |
| Peak memory | 599520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580342143 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.580342143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1199829300 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 12701419897 ps |
| CPU time | 952.14 seconds |
| Started | Aug 25 05:19:53 PM UTC 24 |
| Finished | Aug 25 05:36:00 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199829300 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_rand_reset.1199829300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_unmapped_addr.2675624031 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1062498444 ps |
| CPU time | 71.96 seconds |
| Started | Aug 25 05:19:48 PM UTC 24 |
| Finished | Aug 25 05:21:02 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675624031 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2675624031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device.513618042 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 156997323 ps |
| CPU time | 27.3 seconds |
| Started | Aug 25 05:20:45 PM UTC 24 |
| Finished | Aug 25 05:21:14 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513618042 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.513618042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3893901751 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 84730657648 ps |
| CPU time | 1998.17 seconds |
| Started | Aug 25 05:21:02 PM UTC 24 |
| Finished | Aug 25 05:54:47 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893901751 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device_slow_rsp.3893901751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2456749457 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 293514084 ps |
| CPU time | 41.56 seconds |
| Started | Aug 25 05:21:16 PM UTC 24 |
| Finished | Aug 25 05:21:59 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456749457 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr.2456749457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_error_random.717239345 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 92277332 ps |
| CPU time | 16.42 seconds |
| Started | Aug 25 05:21:13 PM UTC 24 |
| Finished | Aug 25 05:21:30 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717239345 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.717239345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random.304083611 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 510728095 ps |
| CPU time | 27.87 seconds |
| Started | Aug 25 05:20:24 PM UTC 24 |
| Finished | Aug 25 05:20:53 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304083611 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.304083611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3605557697 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 109267561829 ps |
| CPU time | 1762.3 seconds |
| Started | Aug 25 05:20:37 PM UTC 24 |
| Finished | Aug 25 05:50:23 PM UTC 24 |
| Peak memory | 599600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605557697 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3605557697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.1814462499 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 46229375543 ps |
| CPU time | 1045.87 seconds |
| Started | Aug 25 05:20:42 PM UTC 24 |
| Finished | Aug 25 05:38:24 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814462499 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.1814462499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_zero_delays.2782059232 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 240201805 ps |
| CPU time | 35.24 seconds |
| Started | Aug 25 05:20:31 PM UTC 24 |
| Finished | Aug 25 05:21:08 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782059232 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_delays.2782059232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_same_source.2601066369 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1445966106 ps |
| CPU time | 68.71 seconds |
| Started | Aug 25 05:21:05 PM UTC 24 |
| Finished | Aug 25 05:22:16 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601066369 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2601066369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.4285433896 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 40333937 ps |
| CPU time | 10.08 seconds |
| Started | Aug 25 05:20:09 PM UTC 24 |
| Finished | Aug 25 05:20:20 PM UTC 24 |
| Peak memory | 597332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285433896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.4285433896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_large_delays.3282590718 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 6615029999 ps |
| CPU time | 104.48 seconds |
| Started | Aug 25 05:20:15 PM UTC 24 |
| Finished | Aug 25 05:22:02 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282590718 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3282590718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.777729710 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 5417101386 ps |
| CPU time | 124.43 seconds |
| Started | Aug 25 05:20:23 PM UTC 24 |
| Finished | Aug 25 05:22:30 PM UTC 24 |
| Peak memory | 597348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777729710 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.777729710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3034576948 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 47453337 ps |
| CPU time | 9.15 seconds |
| Started | Aug 25 05:20:12 PM UTC 24 |
| Finished | Aug 25 05:20:22 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034576948 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.3034576948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all.1020412748 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 122254293 ps |
| CPU time | 25.89 seconds |
| Started | Aug 25 05:21:23 PM UTC 24 |
| Finished | Aug 25 05:21:50 PM UTC 24 |
| Peak memory | 599476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020412748 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1020412748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_error.159618812 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 14006226539 ps |
| CPU time | 722.04 seconds |
| Started | Aug 25 05:21:26 PM UTC 24 |
| Finished | Aug 25 05:33:40 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159618812 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.159618812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2556946617 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 20921478336 ps |
| CPU time | 1151.15 seconds |
| Started | Aug 25 05:21:25 PM UTC 24 |
| Finished | Aug 25 05:40:53 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556946617 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_rand_reset.2556946617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3927728838 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1131017836 ps |
| CPU time | 284.74 seconds |
| Started | Aug 25 05:21:31 PM UTC 24 |
| Finished | Aug 25 05:26:21 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927728838 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_reset_error.3927728838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_unmapped_addr.3398513272 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 78022670 ps |
| CPU time | 18.9 seconds |
| Started | Aug 25 05:21:14 PM UTC 24 |
| Finished | Aug 25 05:21:34 PM UTC 24 |
| Peak memory | 599504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398513272 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3398513272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device.4048594382 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 441189115 ps |
| CPU time | 23.08 seconds |
| Started | Aug 25 05:22:08 PM UTC 24 |
| Finished | Aug 25 05:22:33 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048594382 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.4048594382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.221391936 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 106364678822 ps |
| CPU time | 2363.75 seconds |
| Started | Aug 25 05:22:11 PM UTC 24 |
| Finished | Aug 25 06:02:09 PM UTC 24 |
| Peak memory | 600248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221391936 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device_slow_rsp.221391936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3094717296 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 164062336 ps |
| CPU time | 20.33 seconds |
| Started | Aug 25 05:22:27 PM UTC 24 |
| Finished | Aug 25 05:22:49 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094717296 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.3094717296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_error_random.3303804631 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 626792141 ps |
| CPU time | 58.28 seconds |
| Started | Aug 25 05:22:13 PM UTC 24 |
| Finished | Aug 25 05:23:13 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303804631 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3303804631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random.2477835559 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 283396242 ps |
| CPU time | 32.07 seconds |
| Started | Aug 25 05:21:54 PM UTC 24 |
| Finished | Aug 25 05:22:27 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477835559 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2477835559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_large_delays.38255531 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 18131231316 ps |
| CPU time | 299.73 seconds |
| Started | Aug 25 05:21:58 PM UTC 24 |
| Finished | Aug 25 05:27:03 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38255531 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.38255531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_slow_rsp.980773143 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 16647020156 ps |
| CPU time | 428.13 seconds |
| Started | Aug 25 05:22:03 PM UTC 24 |
| Finished | Aug 25 05:29:19 PM UTC 24 |
| Peak memory | 599588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980773143 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.980773143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_random_zero_delays.924191106 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 65695053 ps |
| CPU time | 14.5 seconds |
| Started | Aug 25 05:21:56 PM UTC 24 |
| Finished | Aug 25 05:22:11 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924191106 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delays.924191106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_same_source.4172757752 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 798256807 ps |
| CPU time | 39.63 seconds |
| Started | Aug 25 05:22:12 PM UTC 24 |
| Finished | Aug 25 05:22:54 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172757752 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.4172757752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke.841648461 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 187119210 ps |
| CPU time | 11.54 seconds |
| Started | Aug 25 05:21:32 PM UTC 24 |
| Finished | Aug 25 05:21:45 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841648461 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.841648461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_large_delays.48679216 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 8519364876 ps |
| CPU time | 126.53 seconds |
| Started | Aug 25 05:21:40 PM UTC 24 |
| Finished | Aug 25 05:23:49 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48679216 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.48679216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3934294203 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 3979949184 ps |
| CPU time | 90.38 seconds |
| Started | Aug 25 05:21:52 PM UTC 24 |
| Finished | Aug 25 05:23:25 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934294203 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3934294203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_smoke_zero_delays.17876151 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 39191256 ps |
| CPU time | 8.41 seconds |
| Started | Aug 25 05:21:38 PM UTC 24 |
| Finished | Aug 25 05:21:48 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17876151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays.17876151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all.109271756 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 1986390125 ps |
| CPU time | 96.16 seconds |
| Started | Aug 25 05:22:27 PM UTC 24 |
| Finished | Aug 25 05:24:06 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109271756 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.109271756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_error.545279579 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 1629869660 ps |
| CPU time | 210.51 seconds |
| Started | Aug 25 05:22:34 PM UTC 24 |
| Finished | Aug 25 05:26:09 PM UTC 24 |
| Peak memory | 599524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545279579 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.545279579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2070694260 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 58154824 ps |
| CPU time | 27.01 seconds |
| Started | Aug 25 05:22:32 PM UTC 24 |
| Finished | Aug 25 05:23:01 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070694260 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_rand_reset.2070694260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2133432517 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 83667873 ps |
| CPU time | 73.34 seconds |
| Started | Aug 25 05:22:39 PM UTC 24 |
| Finished | Aug 25 05:23:54 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133432517 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_reset_error.2133432517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/69.xbar_unmapped_addr.718520172 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 229747097 ps |
| CPU time | 42.37 seconds |
| Started | Aug 25 05:22:23 PM UTC 24 |
| Finished | Aug 25 05:23:07 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718520172 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.718520172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3960174993 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 6978997605 ps |
| CPU time | 734.85 seconds |
| Started | Aug 25 03:42:37 PM UTC 24 |
| Finished | Aug 25 03:55:04 PM UTC 24 |
| Peak memory | 663284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3960174993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 7.chip_csr_mem_rw_with_rand_reset.3960174993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_same_csr_outstanding.3734998036 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 30089393475 ps |
| CPU time | 6405.88 seconds |
| Started | Aug 25 03:40:51 PM UTC 24 |
| Finished | Aug 25 05:29:11 PM UTC 24 |
| Peak memory | 614780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3734998036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.chip_same_csr_outstanding.3734998036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.4288916194 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3674540489 ps |
| CPU time | 252.87 seconds |
| Started | Aug 25 03:40:52 PM UTC 24 |
| Finished | Aug 25 03:45:09 PM UTC 24 |
| Peak memory | 624184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288916194 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.4288916194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.3228785222 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 388216629 ps |
| CPU time | 63.16 seconds |
| Started | Aug 25 03:41:24 PM UTC 24 |
| Finished | Aug 25 03:42:29 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228785222 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.3228785222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3816868904 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 76955013 ps |
| CPU time | 15.08 seconds |
| Started | Aug 25 03:41:38 PM UTC 24 |
| Finished | Aug 25 03:41:54 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816868904 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3816868904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1917336804 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1275559040 ps |
| CPU time | 59.37 seconds |
| Started | Aug 25 03:41:29 PM UTC 24 |
| Finished | Aug 25 03:42:30 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917336804 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1917336804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3188575370 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1504090725 ps |
| CPU time | 70.25 seconds |
| Started | Aug 25 03:41:13 PM UTC 24 |
| Finished | Aug 25 03:42:26 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188575370 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3188575370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.3835918081 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 37605811812 ps |
| CPU time | 584.11 seconds |
| Started | Aug 25 03:41:21 PM UTC 24 |
| Finished | Aug 25 03:51:14 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835918081 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3835918081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3061913308 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 45225724997 ps |
| CPU time | 1143.75 seconds |
| Started | Aug 25 03:41:21 PM UTC 24 |
| Finished | Aug 25 04:00:43 PM UTC 24 |
| Peak memory | 599668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061913308 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3061913308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1071318955 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 457504218 ps |
| CPU time | 56.66 seconds |
| Started | Aug 25 03:41:15 PM UTC 24 |
| Finished | Aug 25 03:42:13 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071318955 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1071318955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.829903392 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2467319807 ps |
| CPU time | 94.92 seconds |
| Started | Aug 25 03:41:27 PM UTC 24 |
| Finished | Aug 25 03:43:04 PM UTC 24 |
| Peak memory | 599116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829903392 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.829903392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.952510672 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 156934385 ps |
| CPU time | 12.27 seconds |
| Started | Aug 25 03:40:58 PM UTC 24 |
| Finished | Aug 25 03:41:11 PM UTC 24 |
| Peak memory | 597332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952510672 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.952510672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.451054710 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 9652714577 ps |
| CPU time | 178.72 seconds |
| Started | Aug 25 03:41:09 PM UTC 24 |
| Finished | Aug 25 03:44:11 PM UTC 24 |
| Peak memory | 597356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451054710 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.451054710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3153702150 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 4059919872 ps |
| CPU time | 76.94 seconds |
| Started | Aug 25 03:41:11 PM UTC 24 |
| Finished | Aug 25 03:42:29 PM UTC 24 |
| Peak memory | 597076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153702150 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3153702150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3669781860 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 39825440 ps |
| CPU time | 10.04 seconds |
| Started | Aug 25 03:41:03 PM UTC 24 |
| Finished | Aug 25 03:41:15 PM UTC 24 |
| Peak memory | 597260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669781860 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3669781860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2311272457 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 6571993898 ps |
| CPU time | 332.59 seconds |
| Started | Aug 25 03:41:39 PM UTC 24 |
| Finished | Aug 25 03:47:17 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311272457 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2311272457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.371645901 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 746714127 ps |
| CPU time | 96.37 seconds |
| Started | Aug 25 03:42:06 PM UTC 24 |
| Finished | Aug 25 03:43:45 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371645901 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.371645901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3563581115 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 788345699 ps |
| CPU time | 579.79 seconds |
| Started | Aug 25 03:41:40 PM UTC 24 |
| Finished | Aug 25 03:51:29 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563581115 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.3563581115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3265389185 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 605995704 ps |
| CPU time | 125.04 seconds |
| Started | Aug 25 03:42:11 PM UTC 24 |
| Finished | Aug 25 03:44:18 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265389185 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3265389185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.927231358 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 35474927 ps |
| CPU time | 10.84 seconds |
| Started | Aug 25 03:41:35 PM UTC 24 |
| Finished | Aug 25 03:41:47 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927231358 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.927231358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device.3859797280 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 959160465 ps |
| CPU time | 125.97 seconds |
| Started | Aug 25 05:23:16 PM UTC 24 |
| Finished | Aug 25 05:25:25 PM UTC 24 |
| Peak memory | 599144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859797280 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.3859797280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3176986433 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 72633043961 ps |
| CPU time | 1546.49 seconds |
| Started | Aug 25 05:23:17 PM UTC 24 |
| Finished | Aug 25 05:49:24 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176986433 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device_slow_rsp.3176986433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.1712211062 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 801965860 ps |
| CPU time | 45.41 seconds |
| Started | Aug 25 05:23:27 PM UTC 24 |
| Finished | Aug 25 05:24:14 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712211062 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr.1712211062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_error_random.231297416 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 507389613 ps |
| CPU time | 47.46 seconds |
| Started | Aug 25 05:23:20 PM UTC 24 |
| Finished | Aug 25 05:24:09 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231297416 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.231297416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random.805322965 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 1846599230 ps |
| CPU time | 93.43 seconds |
| Started | Aug 25 05:22:52 PM UTC 24 |
| Finished | Aug 25 05:24:28 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805322965 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.805322965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_large_delays.3160239500 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 45877437205 ps |
| CPU time | 707.88 seconds |
| Started | Aug 25 05:22:56 PM UTC 24 |
| Finished | Aug 25 05:34:54 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160239500 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3160239500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_slow_rsp.2389507621 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 17768206224 ps |
| CPU time | 430.58 seconds |
| Started | Aug 25 05:23:13 PM UTC 24 |
| Finished | Aug 25 05:30:31 PM UTC 24 |
| Peak memory | 599328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389507621 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2389507621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_random_zero_delays.3840127135 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 275381243 ps |
| CPU time | 31.93 seconds |
| Started | Aug 25 05:22:54 PM UTC 24 |
| Finished | Aug 25 05:23:27 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840127135 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_delays.3840127135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_same_source.3440509104 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 87049679 ps |
| CPU time | 11.56 seconds |
| Started | Aug 25 05:23:18 PM UTC 24 |
| Finished | Aug 25 05:23:31 PM UTC 24 |
| Peak memory | 599052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440509104 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3440509104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke.932942157 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 235660078 ps |
| CPU time | 12.72 seconds |
| Started | Aug 25 05:22:42 PM UTC 24 |
| Finished | Aug 25 05:22:56 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932942157 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.932942157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_large_delays.3470477994 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 7837425073 ps |
| CPU time | 126.05 seconds |
| Started | Aug 25 05:22:50 PM UTC 24 |
| Finished | Aug 25 05:24:59 PM UTC 24 |
| Peak memory | 597360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470477994 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3470477994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.2272054719 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 5478772666 ps |
| CPU time | 136.9 seconds |
| Started | Aug 25 05:22:51 PM UTC 24 |
| Finished | Aug 25 05:25:11 PM UTC 24 |
| Peak memory | 597396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272054719 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.2272054719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1051393223 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 44907497 ps |
| CPU time | 6.99 seconds |
| Started | Aug 25 05:22:45 PM UTC 24 |
| Finished | Aug 25 05:22:53 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051393223 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.1051393223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all.819105761 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 393164583 ps |
| CPU time | 24.54 seconds |
| Started | Aug 25 05:23:27 PM UTC 24 |
| Finished | Aug 25 05:23:53 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819105761 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.819105761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_error.3933947932 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 6624000693 ps |
| CPU time | 278.1 seconds |
| Started | Aug 25 05:23:32 PM UTC 24 |
| Finished | Aug 25 05:28:14 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933947932 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3933947932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.4206230219 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 9309695164 ps |
| CPU time | 898.61 seconds |
| Started | Aug 25 05:23:29 PM UTC 24 |
| Finished | Aug 25 05:38:43 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206230219 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_rand_reset.4206230219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3131867227 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 712599472 ps |
| CPU time | 308.37 seconds |
| Started | Aug 25 05:23:38 PM UTC 24 |
| Finished | Aug 25 05:28:51 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131867227 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_reset_error.3131867227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_unmapped_addr.1131724633 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 254341101 ps |
| CPU time | 42.88 seconds |
| Started | Aug 25 05:23:25 PM UTC 24 |
| Finished | Aug 25 05:24:10 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131724633 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.1131724633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device.2582688826 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 3854479289 ps |
| CPU time | 234.97 seconds |
| Started | Aug 25 05:24:13 PM UTC 24 |
| Finished | Aug 25 05:28:13 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582688826 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.2582688826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2319426606 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 100878943764 ps |
| CPU time | 2409.4 seconds |
| Started | Aug 25 05:24:13 PM UTC 24 |
| Finished | Aug 25 06:04:59 PM UTC 24 |
| Peak memory | 600272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319426606 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device_slow_rsp.2319426606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3121093224 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 1305748094 ps |
| CPU time | 81.09 seconds |
| Started | Aug 25 05:24:29 PM UTC 24 |
| Finished | Aug 25 05:25:53 PM UTC 24 |
| Peak memory | 599248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121093224 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.3121093224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_error_random.1030060623 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 107093241 ps |
| CPU time | 13.86 seconds |
| Started | Aug 25 05:24:19 PM UTC 24 |
| Finished | Aug 25 05:24:34 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030060623 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1030060623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random.20898341 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 533918716 ps |
| CPU time | 34.11 seconds |
| Started | Aug 25 05:23:54 PM UTC 24 |
| Finished | Aug 25 05:24:30 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20898341 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.20898341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.3939983359 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 59928608804 ps |
| CPU time | 963.47 seconds |
| Started | Aug 25 05:24:03 PM UTC 24 |
| Finished | Aug 25 05:40:21 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939983359 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.3939983359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_slow_rsp.2043759220 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 4231534475 ps |
| CPU time | 88.7 seconds |
| Started | Aug 25 05:24:10 PM UTC 24 |
| Finished | Aug 25 05:25:41 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043759220 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2043759220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_zero_delays.2117053567 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 393847879 ps |
| CPU time | 58.41 seconds |
| Started | Aug 25 05:23:59 PM UTC 24 |
| Finished | Aug 25 05:25:00 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117053567 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_delays.2117053567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_same_source.880966909 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 334731471 ps |
| CPU time | 34.1 seconds |
| Started | Aug 25 05:24:17 PM UTC 24 |
| Finished | Aug 25 05:24:53 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880966909 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.880966909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke.2558674303 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 41427162 ps |
| CPU time | 9.45 seconds |
| Started | Aug 25 05:23:39 PM UTC 24 |
| Finished | Aug 25 05:23:50 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558674303 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2558674303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_large_delays.2564615393 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 9334544446 ps |
| CPU time | 137.23 seconds |
| Started | Aug 25 05:23:49 PM UTC 24 |
| Finished | Aug 25 05:26:09 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564615393 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2564615393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1195845893 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 5073364164 ps |
| CPU time | 134.98 seconds |
| Started | Aug 25 05:23:51 PM UTC 24 |
| Finished | Aug 25 05:26:09 PM UTC 24 |
| Peak memory | 597580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195845893 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1195845893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1736107200 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 54595600 ps |
| CPU time | 9.28 seconds |
| Started | Aug 25 05:23:49 PM UTC 24 |
| Finished | Aug 25 05:23:59 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736107200 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delays.1736107200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all.1861421128 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 3647092583 ps |
| CPU time | 164.86 seconds |
| Started | Aug 25 05:24:33 PM UTC 24 |
| Finished | Aug 25 05:27:21 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861421128 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1861421128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_error.278436117 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 218849177 ps |
| CPU time | 29.78 seconds |
| Started | Aug 25 05:24:38 PM UTC 24 |
| Finished | Aug 25 05:25:09 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278436117 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.278436117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4232570415 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 2196944480 ps |
| CPU time | 116.44 seconds |
| Started | Aug 25 05:24:34 PM UTC 24 |
| Finished | Aug 25 05:26:33 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232570415 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_rand_reset.4232570415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.4250405622 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2407343845 ps |
| CPU time | 210.61 seconds |
| Started | Aug 25 05:24:52 PM UTC 24 |
| Finished | Aug 25 05:28:27 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250405622 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_reset_error.4250405622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_unmapped_addr.4152063615 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 165415195 ps |
| CPU time | 26.2 seconds |
| Started | Aug 25 05:24:23 PM UTC 24 |
| Finished | Aug 25 05:24:51 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152063615 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.4152063615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device.2151337972 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 899379289 ps |
| CPU time | 51.79 seconds |
| Started | Aug 25 05:25:20 PM UTC 24 |
| Finished | Aug 25 05:26:13 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151337972 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device.2151337972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.517556080 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 48299408579 ps |
| CPU time | 1183.02 seconds |
| Started | Aug 25 05:25:22 PM UTC 24 |
| Finished | Aug 25 05:45:23 PM UTC 24 |
| Peak memory | 599580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517556080 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device_slow_rsp.517556080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.194072049 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 1062468806 ps |
| CPU time | 50.29 seconds |
| Started | Aug 25 05:25:31 PM UTC 24 |
| Finished | Aug 25 05:26:23 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194072049 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr.194072049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_error_random.2252154157 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 1353994647 ps |
| CPU time | 69.03 seconds |
| Started | Aug 25 05:25:24 PM UTC 24 |
| Finished | Aug 25 05:26:36 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252154157 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2252154157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random.930776380 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 469541933 ps |
| CPU time | 46.98 seconds |
| Started | Aug 25 05:25:08 PM UTC 24 |
| Finished | Aug 25 05:25:57 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930776380 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.930776380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.2433942445 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 77897296714 ps |
| CPU time | 1170.62 seconds |
| Started | Aug 25 05:25:14 PM UTC 24 |
| Finished | Aug 25 05:45:00 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433942445 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2433942445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1972751249 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 61318249826 ps |
| CPU time | 1599.26 seconds |
| Started | Aug 25 05:25:15 PM UTC 24 |
| Finished | Aug 25 05:52:20 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972751249 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1972751249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_zero_delays.3491294757 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 227564119 ps |
| CPU time | 34.36 seconds |
| Started | Aug 25 05:25:11 PM UTC 24 |
| Finished | Aug 25 05:25:47 PM UTC 24 |
| Peak memory | 599468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491294757 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delays.3491294757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_same_source.138822191 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 115171115 ps |
| CPU time | 16.55 seconds |
| Started | Aug 25 05:25:23 PM UTC 24 |
| Finished | Aug 25 05:25:41 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138822191 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.138822191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke.1707489304 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 161500516 ps |
| CPU time | 10.62 seconds |
| Started | Aug 25 05:24:54 PM UTC 24 |
| Finished | Aug 25 05:25:06 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707489304 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1707489304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_large_delays.619879886 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 5337637608 ps |
| CPU time | 94.34 seconds |
| Started | Aug 25 05:24:57 PM UTC 24 |
| Finished | Aug 25 05:26:34 PM UTC 24 |
| Peak memory | 597556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619879886 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.619879886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.947362754 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 4222984109 ps |
| CPU time | 118.2 seconds |
| Started | Aug 25 05:25:05 PM UTC 24 |
| Finished | Aug 25 05:27:06 PM UTC 24 |
| Peak memory | 597464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947362754 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.947362754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3068747037 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 34904613 ps |
| CPU time | 9.39 seconds |
| Started | Aug 25 05:24:53 PM UTC 24 |
| Finished | Aug 25 05:25:03 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068747037 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays.3068747037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all.3530376617 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 8171147162 ps |
| CPU time | 473.13 seconds |
| Started | Aug 25 05:25:34 PM UTC 24 |
| Finished | Aug 25 05:33:36 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530376617 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3530376617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_error.2785761751 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 3312819578 ps |
| CPU time | 405.95 seconds |
| Started | Aug 25 05:25:44 PM UTC 24 |
| Finished | Aug 25 05:32:37 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785761751 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2785761751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1161740543 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 316129164 ps |
| CPU time | 105.72 seconds |
| Started | Aug 25 05:25:38 PM UTC 24 |
| Finished | Aug 25 05:27:26 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161740543 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_rand_reset.1161740543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1003913577 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 5457534452 ps |
| CPU time | 412.31 seconds |
| Started | Aug 25 05:25:47 PM UTC 24 |
| Finished | Aug 25 05:32:46 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003913577 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_reset_error.1003913577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_unmapped_addr.3093371151 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 1379759830 ps |
| CPU time | 75.95 seconds |
| Started | Aug 25 05:25:30 PM UTC 24 |
| Finished | Aug 25 05:26:48 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093371151 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3093371151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device.43123404 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 713109307 ps |
| CPU time | 42.51 seconds |
| Started | Aug 25 05:26:17 PM UTC 24 |
| Finished | Aug 25 05:27:01 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43123404 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device.43123404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.152020820 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 111866986262 ps |
| CPU time | 2299.58 seconds |
| Started | Aug 25 05:26:32 PM UTC 24 |
| Finished | Aug 25 06:05:25 PM UTC 24 |
| Peak memory | 600092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152020820 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device_slow_rsp.152020820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1857013942 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 844588739 ps |
| CPU time | 54.18 seconds |
| Started | Aug 25 05:26:37 PM UTC 24 |
| Finished | Aug 25 05:27:33 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857013942 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr.1857013942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_error_random.1835012360 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 600805158 ps |
| CPU time | 29.24 seconds |
| Started | Aug 25 05:26:33 PM UTC 24 |
| Finished | Aug 25 05:27:04 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835012360 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1835012360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random.1920579803 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 246627591 ps |
| CPU time | 30.53 seconds |
| Started | Aug 25 05:26:10 PM UTC 24 |
| Finished | Aug 25 05:26:42 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920579803 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1920579803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.1502084132 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 85240497855 ps |
| CPU time | 1262.24 seconds |
| Started | Aug 25 05:26:15 PM UTC 24 |
| Finished | Aug 25 05:47:34 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502084132 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1502084132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_slow_rsp.1195399386 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 2984204215 ps |
| CPU time | 67.05 seconds |
| Started | Aug 25 05:26:19 PM UTC 24 |
| Finished | Aug 25 05:27:28 PM UTC 24 |
| Peak memory | 597516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195399386 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.1195399386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_zero_delays.1641193618 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 218965510 ps |
| CPU time | 34.22 seconds |
| Started | Aug 25 05:26:09 PM UTC 24 |
| Finished | Aug 25 05:26:45 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641193618 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delays.1641193618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_same_source.2858615847 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 476737174 ps |
| CPU time | 57.01 seconds |
| Started | Aug 25 05:26:33 PM UTC 24 |
| Finished | Aug 25 05:27:32 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858615847 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2858615847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke.685741404 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 246211537 ps |
| CPU time | 15.77 seconds |
| Started | Aug 25 05:26:01 PM UTC 24 |
| Finished | Aug 25 05:26:18 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685741404 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.685741404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_large_delays.1794841851 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 4475191045 ps |
| CPU time | 69.93 seconds |
| Started | Aug 25 05:26:04 PM UTC 24 |
| Finished | Aug 25 05:27:15 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794841851 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1794841851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.13860373 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 5024862394 ps |
| CPU time | 117.45 seconds |
| Started | Aug 25 05:26:07 PM UTC 24 |
| Finished | Aug 25 05:28:07 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13860373 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.13860373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2927286328 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 47992826 ps |
| CPU time | 10.57 seconds |
| Started | Aug 25 05:26:02 PM UTC 24 |
| Finished | Aug 25 05:26:14 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927286328 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays.2927286328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all.419845481 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 7101807261 ps |
| CPU time | 309.81 seconds |
| Started | Aug 25 05:26:41 PM UTC 24 |
| Finished | Aug 25 05:31:57 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419845481 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.419845481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_error.44111117 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 4644210685 ps |
| CPU time | 442.5 seconds |
| Started | Aug 25 05:26:44 PM UTC 24 |
| Finished | Aug 25 05:34:14 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44111117 -assert nopostproc +UVM_TESTNAME= xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.44111117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3737525573 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 1008442782 ps |
| CPU time | 557.17 seconds |
| Started | Aug 25 05:26:45 PM UTC 24 |
| Finished | Aug 25 05:36:12 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737525573 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_rand_reset.3737525573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3826675866 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 183809863 ps |
| CPU time | 47.9 seconds |
| Started | Aug 25 05:26:56 PM UTC 24 |
| Finished | Aug 25 05:27:45 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826675866 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_reset_error.3826675866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_unmapped_addr.2271678143 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 317031741 ps |
| CPU time | 57.79 seconds |
| Started | Aug 25 05:26:34 PM UTC 24 |
| Finished | Aug 25 05:27:34 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271678143 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.2271678143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device.3538285697 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 487567365 ps |
| CPU time | 59.38 seconds |
| Started | Aug 25 05:27:26 PM UTC 24 |
| Finished | Aug 25 05:28:28 PM UTC 24 |
| Peak memory | 599472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538285697 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.3538285697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3731521710 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 105927968627 ps |
| CPU time | 2178.24 seconds |
| Started | Aug 25 05:27:29 PM UTC 24 |
| Finished | Aug 25 06:04:18 PM UTC 24 |
| Peak memory | 599644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731521710 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device_slow_rsp.3731521710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1751885404 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 168101007 ps |
| CPU time | 30.81 seconds |
| Started | Aug 25 05:27:40 PM UTC 24 |
| Finished | Aug 25 05:28:12 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751885404 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.1751885404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_error_random.2325779777 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 1898589391 ps |
| CPU time | 93.05 seconds |
| Started | Aug 25 05:27:34 PM UTC 24 |
| Finished | Aug 25 05:29:10 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325779777 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2325779777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random.61896819 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 2101726779 ps |
| CPU time | 109.53 seconds |
| Started | Aug 25 05:27:08 PM UTC 24 |
| Finished | Aug 25 05:29:00 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61896819 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.61896819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2588228771 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 56913639597 ps |
| CPU time | 935.99 seconds |
| Started | Aug 25 05:27:13 PM UTC 24 |
| Finished | Aug 25 05:43:03 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588228771 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2588228771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_slow_rsp.1496103795 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 6584298391 ps |
| CPU time | 173.34 seconds |
| Started | Aug 25 05:27:25 PM UTC 24 |
| Finished | Aug 25 05:30:23 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496103795 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1496103795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_zero_delays.2693177968 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 285047705 ps |
| CPU time | 33.29 seconds |
| Started | Aug 25 05:27:09 PM UTC 24 |
| Finished | Aug 25 05:27:44 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693177968 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delays.2693177968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_same_source.2925742170 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 2158099595 ps |
| CPU time | 101.29 seconds |
| Started | Aug 25 05:27:31 PM UTC 24 |
| Finished | Aug 25 05:29:14 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925742170 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.2925742170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke.506499219 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 181498216 ps |
| CPU time | 14.22 seconds |
| Started | Aug 25 05:26:59 PM UTC 24 |
| Finished | Aug 25 05:27:15 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506499219 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.506499219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_large_delays.1240635011 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 8088978549 ps |
| CPU time | 134.05 seconds |
| Started | Aug 25 05:27:06 PM UTC 24 |
| Finished | Aug 25 05:29:23 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240635011 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.1240635011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.3496206532 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 4464495820 ps |
| CPU time | 114.05 seconds |
| Started | Aug 25 05:27:09 PM UTC 24 |
| Finished | Aug 25 05:29:06 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496206532 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.3496206532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3609577353 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 45504593 ps |
| CPU time | 10.37 seconds |
| Started | Aug 25 05:27:00 PM UTC 24 |
| Finished | Aug 25 05:27:11 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609577353 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays.3609577353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all.1670289393 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 3029217262 ps |
| CPU time | 330.55 seconds |
| Started | Aug 25 05:27:41 PM UTC 24 |
| Finished | Aug 25 05:33:17 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670289393 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.1670289393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_error.2063132966 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 561912744 ps |
| CPU time | 54.16 seconds |
| Started | Aug 25 05:27:46 PM UTC 24 |
| Finished | Aug 25 05:28:42 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063132966 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2063132966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3627982349 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 388072991 ps |
| CPU time | 188.74 seconds |
| Started | Aug 25 05:27:44 PM UTC 24 |
| Finished | Aug 25 05:30:57 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627982349 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_rand_reset.3627982349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.471364323 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 17647359316 ps |
| CPU time | 1201.13 seconds |
| Started | Aug 25 05:27:51 PM UTC 24 |
| Finished | Aug 25 05:48:12 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471364323 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_reset_error.471364323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_unmapped_addr.2454360660 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 62586837 ps |
| CPU time | 8.53 seconds |
| Started | Aug 25 05:27:39 PM UTC 24 |
| Finished | Aug 25 05:27:49 PM UTC 24 |
| Peak memory | 597196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454360660 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2454360660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device.3573565249 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 34437239 ps |
| CPU time | 17.71 seconds |
| Started | Aug 25 05:28:29 PM UTC 24 |
| Finished | Aug 25 05:28:49 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573565249 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.3573565249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.881660917 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 66507043839 ps |
| CPU time | 1468.25 seconds |
| Started | Aug 25 05:28:29 PM UTC 24 |
| Finished | Aug 25 05:53:16 PM UTC 24 |
| Peak memory | 599356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881660917 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device_slow_rsp.881660917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2197720811 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 72763729 ps |
| CPU time | 16.43 seconds |
| Started | Aug 25 05:28:36 PM UTC 24 |
| Finished | Aug 25 05:28:53 PM UTC 24 |
| Peak memory | 599140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197720811 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr.2197720811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_error_random.4072249969 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 2604968338 ps |
| CPU time | 111.63 seconds |
| Started | Aug 25 05:28:34 PM UTC 24 |
| Finished | Aug 25 05:30:28 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072249969 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.4072249969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random.387482174 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 1499429318 ps |
| CPU time | 75.94 seconds |
| Started | Aug 25 05:28:05 PM UTC 24 |
| Finished | Aug 25 05:29:23 PM UTC 24 |
| Peak memory | 599504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387482174 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.387482174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_large_delays.138785367 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 24248848810 ps |
| CPU time | 409.48 seconds |
| Started | Aug 25 05:28:13 PM UTC 24 |
| Finished | Aug 25 05:35:09 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138785367 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.138785367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.1979857077 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 39986340920 ps |
| CPU time | 895.7 seconds |
| Started | Aug 25 05:28:17 PM UTC 24 |
| Finished | Aug 25 05:43:25 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979857077 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.1979857077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_zero_delays.3691394355 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 314923616 ps |
| CPU time | 33.48 seconds |
| Started | Aug 25 05:28:09 PM UTC 24 |
| Finished | Aug 25 05:28:44 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691394355 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_delays.3691394355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_same_source.3073206338 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 2219891431 ps |
| CPU time | 78.08 seconds |
| Started | Aug 25 05:28:32 PM UTC 24 |
| Finished | Aug 25 05:29:52 PM UTC 24 |
| Peak memory | 599120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073206338 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3073206338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke.1733096615 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 222621058 ps |
| CPU time | 12.76 seconds |
| Started | Aug 25 05:27:51 PM UTC 24 |
| Finished | Aug 25 05:28:05 PM UTC 24 |
| Peak memory | 597064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733096615 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1733096615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_large_delays.198784956 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 4823638330 ps |
| CPU time | 70.49 seconds |
| Started | Aug 25 05:27:57 PM UTC 24 |
| Finished | Aug 25 05:29:09 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198784956 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.198784956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2864885728 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 7009649052 ps |
| CPU time | 148.99 seconds |
| Started | Aug 25 05:27:57 PM UTC 24 |
| Finished | Aug 25 05:30:29 PM UTC 24 |
| Peak memory | 597464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864885728 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2864885728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_smoke_zero_delays.4016699489 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 53732387 ps |
| CPU time | 10.61 seconds |
| Started | Aug 25 05:27:56 PM UTC 24 |
| Finished | Aug 25 05:28:08 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016699489 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.4016699489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all.2065254765 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 890478463 ps |
| CPU time | 122.31 seconds |
| Started | Aug 25 05:28:41 PM UTC 24 |
| Finished | Aug 25 05:30:46 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065254765 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2065254765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_error.1872210009 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 1290334044 ps |
| CPU time | 109.93 seconds |
| Started | Aug 25 05:28:50 PM UTC 24 |
| Finished | Aug 25 05:30:43 PM UTC 24 |
| Peak memory | 599136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872210009 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1872210009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.83920327 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 5987791150 ps |
| CPU time | 734.26 seconds |
| Started | Aug 25 05:28:51 PM UTC 24 |
| Finished | Aug 25 05:41:17 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83920327 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_rand_reset.83920327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2465439933 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 5604662755 ps |
| CPU time | 317.01 seconds |
| Started | Aug 25 05:28:54 PM UTC 24 |
| Finished | Aug 25 05:34:17 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465439933 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_reset_error.2465439933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_unmapped_addr.2677206596 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 260906977 ps |
| CPU time | 38.03 seconds |
| Started | Aug 25 05:28:37 PM UTC 24 |
| Finished | Aug 25 05:29:16 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677206596 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2677206596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device.244014529 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 1531970416 ps |
| CPU time | 96.64 seconds |
| Started | Aug 25 05:29:32 PM UTC 24 |
| Finished | Aug 25 05:31:11 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244014529 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device.244014529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3077509815 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 27250643345 ps |
| CPU time | 705.03 seconds |
| Started | Aug 25 05:29:35 PM UTC 24 |
| Finished | Aug 25 05:41:31 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077509815 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device_slow_rsp.3077509815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2693283076 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 867632668 ps |
| CPU time | 47.28 seconds |
| Started | Aug 25 05:29:40 PM UTC 24 |
| Finished | Aug 25 05:30:29 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693283076 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr.2693283076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_error_random.2517497411 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 91302419 ps |
| CPU time | 14.41 seconds |
| Started | Aug 25 05:29:38 PM UTC 24 |
| Finished | Aug 25 05:29:54 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517497411 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2517497411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random.2027053600 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 1240845104 ps |
| CPU time | 69.52 seconds |
| Started | Aug 25 05:29:16 PM UTC 24 |
| Finished | Aug 25 05:30:28 PM UTC 24 |
| Peak memory | 599332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027053600 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2027053600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.781996817 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 49881321430 ps |
| CPU time | 889.25 seconds |
| Started | Aug 25 05:29:23 PM UTC 24 |
| Finished | Aug 25 05:44:27 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781996817 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.781996817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_slow_rsp.1412519697 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 62273827868 ps |
| CPU time | 1534.43 seconds |
| Started | Aug 25 05:29:29 PM UTC 24 |
| Finished | Aug 25 05:55:28 PM UTC 24 |
| Peak memory | 599368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412519697 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1412519697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_zero_delays.1387429506 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 191832082 ps |
| CPU time | 22.26 seconds |
| Started | Aug 25 05:29:23 PM UTC 24 |
| Finished | Aug 25 05:29:47 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387429506 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_delays.1387429506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_same_source.2807809979 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 1408744094 ps |
| CPU time | 70.42 seconds |
| Started | Aug 25 05:29:33 PM UTC 24 |
| Finished | Aug 25 05:30:46 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807809979 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2807809979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke.1632613344 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 196663523 ps |
| CPU time | 12.77 seconds |
| Started | Aug 25 05:29:07 PM UTC 24 |
| Finished | Aug 25 05:29:21 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632613344 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1632613344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_large_delays.4136706353 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 5939950096 ps |
| CPU time | 108.7 seconds |
| Started | Aug 25 05:29:14 PM UTC 24 |
| Finished | Aug 25 05:31:05 PM UTC 24 |
| Peak memory | 597224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136706353 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.4136706353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2502757029 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 4924929115 ps |
| CPU time | 104.5 seconds |
| Started | Aug 25 05:29:16 PM UTC 24 |
| Finished | Aug 25 05:31:03 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502757029 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.2502757029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_smoke_zero_delays.2680441787 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 43211071 ps |
| CPU time | 10.24 seconds |
| Started | Aug 25 05:29:06 PM UTC 24 |
| Finished | Aug 25 05:29:17 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680441787 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.2680441787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all.143149049 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 3302095175 ps |
| CPU time | 173.88 seconds |
| Started | Aug 25 05:29:43 PM UTC 24 |
| Finished | Aug 25 05:32:41 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143149049 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.143149049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_error.632025610 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 1673480290 ps |
| CPU time | 170.42 seconds |
| Started | Aug 25 05:29:46 PM UTC 24 |
| Finished | Aug 25 05:32:40 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632025610 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.632025610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3837707867 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 7735298613 ps |
| CPU time | 647.85 seconds |
| Started | Aug 25 05:29:44 PM UTC 24 |
| Finished | Aug 25 05:40:42 PM UTC 24 |
| Peak memory | 599388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837707867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_rand_reset.3837707867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3261463102 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 6302261737 ps |
| CPU time | 486.7 seconds |
| Started | Aug 25 05:29:47 PM UTC 24 |
| Finished | Aug 25 05:38:02 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261463102 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_reset_error.3261463102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_unmapped_addr.323236945 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 853196152 ps |
| CPU time | 57.26 seconds |
| Started | Aug 25 05:29:39 PM UTC 24 |
| Finished | Aug 25 05:30:38 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323236945 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.323236945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device.654314762 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 126815358 ps |
| CPU time | 16.51 seconds |
| Started | Aug 25 05:30:52 PM UTC 24 |
| Finished | Aug 25 05:31:10 PM UTC 24 |
| Peak memory | 599144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654314762 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device.654314762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3425557707 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 96958869989 ps |
| CPU time | 1946.19 seconds |
| Started | Aug 25 05:30:51 PM UTC 24 |
| Finished | Aug 25 06:03:44 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425557707 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device_slow_rsp.3425557707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3765062755 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 203740955 ps |
| CPU time | 13.63 seconds |
| Started | Aug 25 05:30:55 PM UTC 24 |
| Finished | Aug 25 05:31:10 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765062755 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.3765062755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_error_random.3343555537 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 270234731 ps |
| CPU time | 32.09 seconds |
| Started | Aug 25 05:30:54 PM UTC 24 |
| Finished | Aug 25 05:31:28 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343555537 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3343555537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random.3058208677 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 520189569 ps |
| CPU time | 56.6 seconds |
| Started | Aug 25 05:30:36 PM UTC 24 |
| Finished | Aug 25 05:31:34 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058208677 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3058208677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.750980098 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 83799983055 ps |
| CPU time | 1261.81 seconds |
| Started | Aug 25 05:30:51 PM UTC 24 |
| Finished | Aug 25 05:52:10 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750980098 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.750980098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.230569210 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 39830128148 ps |
| CPU time | 858.74 seconds |
| Started | Aug 25 05:30:49 PM UTC 24 |
| Finished | Aug 25 05:45:20 PM UTC 24 |
| Peak memory | 599404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230569210 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.230569210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_zero_delays.2129734419 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 511203378 ps |
| CPU time | 71.47 seconds |
| Started | Aug 25 05:30:47 PM UTC 24 |
| Finished | Aug 25 05:32:01 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129734419 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_delays.2129734419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_same_source.2233753315 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 338999683 ps |
| CPU time | 20.26 seconds |
| Started | Aug 25 05:30:53 PM UTC 24 |
| Finished | Aug 25 05:31:15 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233753315 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2233753315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke.2717846599 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 257647133 ps |
| CPU time | 17.17 seconds |
| Started | Aug 25 05:30:09 PM UTC 24 |
| Finished | Aug 25 05:30:28 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717846599 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2717846599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_large_delays.3257632893 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 5900603830 ps |
| CPU time | 101.7 seconds |
| Started | Aug 25 05:30:18 PM UTC 24 |
| Finished | Aug 25 05:32:02 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257632893 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3257632893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1468723799 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 6560304269 ps |
| CPU time | 146.58 seconds |
| Started | Aug 25 05:30:25 PM UTC 24 |
| Finished | Aug 25 05:32:55 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468723799 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1468723799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1176468954 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 51171655 ps |
| CPU time | 8.75 seconds |
| Started | Aug 25 05:30:17 PM UTC 24 |
| Finished | Aug 25 05:30:26 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176468954 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays.1176468954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all.201861587 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 278546524 ps |
| CPU time | 49.23 seconds |
| Started | Aug 25 05:31:01 PM UTC 24 |
| Finished | Aug 25 05:31:52 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201861587 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.201861587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.3858177457 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 3865866557 ps |
| CPU time | 471.78 seconds |
| Started | Aug 25 05:31:10 PM UTC 24 |
| Finished | Aug 25 05:39:10 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858177457 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3858177457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2172878059 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 264478407 ps |
| CPU time | 124.1 seconds |
| Started | Aug 25 05:31:06 PM UTC 24 |
| Finished | Aug 25 05:33:13 PM UTC 24 |
| Peak memory | 599244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172878059 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_rand_reset.2172878059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1043165257 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 287754280 ps |
| CPU time | 143.08 seconds |
| Started | Aug 25 05:31:09 PM UTC 24 |
| Finished | Aug 25 05:33:36 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043165257 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_reset_error.1043165257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_unmapped_addr.204438313 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 1137838431 ps |
| CPU time | 74.43 seconds |
| Started | Aug 25 05:30:54 PM UTC 24 |
| Finished | Aug 25 05:32:11 PM UTC 24 |
| Peak memory | 599392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204438313 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.204438313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device.4030287831 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 362171336 ps |
| CPU time | 63.87 seconds |
| Started | Aug 25 05:31:35 PM UTC 24 |
| Finished | Aug 25 05:32:41 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030287831 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device.4030287831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3238835654 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 28371811601 ps |
| CPU time | 711.25 seconds |
| Started | Aug 25 05:31:39 PM UTC 24 |
| Finished | Aug 25 05:43:42 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238835654 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device_slow_rsp.3238835654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.125927429 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 1074873337 ps |
| CPU time | 49.64 seconds |
| Started | Aug 25 05:31:54 PM UTC 24 |
| Finished | Aug 25 05:32:46 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125927429 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr.125927429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_error_random.361129907 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 114527651 ps |
| CPU time | 14.33 seconds |
| Started | Aug 25 05:31:50 PM UTC 24 |
| Finished | Aug 25 05:32:05 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361129907 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.361129907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random.3617885629 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 2287005264 ps |
| CPU time | 120.06 seconds |
| Started | Aug 25 05:31:26 PM UTC 24 |
| Finished | Aug 25 05:33:29 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617885629 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.3617885629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_large_delays.4277826132 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 118490991165 ps |
| CPU time | 1826.12 seconds |
| Started | Aug 25 05:31:32 PM UTC 24 |
| Finished | Aug 25 06:02:25 PM UTC 24 |
| Peak memory | 599388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277826132 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.4277826132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.1257988506 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 20493466913 ps |
| CPU time | 426.29 seconds |
| Started | Aug 25 05:31:31 PM UTC 24 |
| Finished | Aug 25 05:38:44 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257988506 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.1257988506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_zero_delays.2930105805 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 444168826 ps |
| CPU time | 59.91 seconds |
| Started | Aug 25 05:31:28 PM UTC 24 |
| Finished | Aug 25 05:32:30 PM UTC 24 |
| Peak memory | 599220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930105805 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_delays.2930105805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_same_source.3114660212 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 1926973897 ps |
| CPU time | 70.98 seconds |
| Started | Aug 25 05:31:51 PM UTC 24 |
| Finished | Aug 25 05:33:04 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114660212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3114660212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke.3025167165 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 269006240 ps |
| CPU time | 16.61 seconds |
| Started | Aug 25 05:31:11 PM UTC 24 |
| Finished | Aug 25 05:31:29 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025167165 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.3025167165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_large_delays.3370160892 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 7305180322 ps |
| CPU time | 122.87 seconds |
| Started | Aug 25 05:31:19 PM UTC 24 |
| Finished | Aug 25 05:33:25 PM UTC 24 |
| Peak memory | 597460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370160892 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.3370160892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4003676813 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 6315512553 ps |
| CPU time | 135.4 seconds |
| Started | Aug 25 05:31:21 PM UTC 24 |
| Finished | Aug 25 05:33:39 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003676813 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.4003676813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_smoke_zero_delays.3134663250 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 48047595 ps |
| CPU time | 10.51 seconds |
| Started | Aug 25 05:31:16 PM UTC 24 |
| Finished | Aug 25 05:31:27 PM UTC 24 |
| Peak memory | 597148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134663250 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays.3134663250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1912058312 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 11930235930 ps |
| CPU time | 693.96 seconds |
| Started | Aug 25 05:32:05 PM UTC 24 |
| Finished | Aug 25 05:43:50 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912058312 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1912058312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_error.138732553 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 595682007 ps |
| CPU time | 85.67 seconds |
| Started | Aug 25 05:32:20 PM UTC 24 |
| Finished | Aug 25 05:33:48 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138732553 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.138732553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.4021492373 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 90813198 ps |
| CPU time | 54.91 seconds |
| Started | Aug 25 05:32:17 PM UTC 24 |
| Finished | Aug 25 05:33:13 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021492373 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_rand_reset.4021492373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.452648770 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 3003841906 ps |
| CPU time | 515.49 seconds |
| Started | Aug 25 05:32:20 PM UTC 24 |
| Finished | Aug 25 05:41:04 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452648770 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_reset_error.452648770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_unmapped_addr.3264750779 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 177933917 ps |
| CPU time | 34.08 seconds |
| Started | Aug 25 05:31:51 PM UTC 24 |
| Finished | Aug 25 05:32:27 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264750779 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3264750779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2095344242 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 3228128857 ps |
| CPU time | 200.11 seconds |
| Started | Aug 25 05:33:01 PM UTC 24 |
| Finished | Aug 25 05:36:26 PM UTC 24 |
| Peak memory | 599348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095344242 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device.2095344242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.240731712 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 12954085141 ps |
| CPU time | 296.95 seconds |
| Started | Aug 25 05:33:04 PM UTC 24 |
| Finished | Aug 25 05:38:06 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240731712 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device_slow_rsp.240731712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.331186229 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 160999820 ps |
| CPU time | 23.55 seconds |
| Started | Aug 25 05:33:11 PM UTC 24 |
| Finished | Aug 25 05:33:35 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331186229 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr.331186229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_error_random.1984149970 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 507339851 ps |
| CPU time | 48.16 seconds |
| Started | Aug 25 05:33:06 PM UTC 24 |
| Finished | Aug 25 05:33:56 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984149970 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.1984149970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random.2900402727 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 896157855 ps |
| CPU time | 49.58 seconds |
| Started | Aug 25 05:32:48 PM UTC 24 |
| Finished | Aug 25 05:33:40 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900402727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2900402727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.3963820883 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 27712032470 ps |
| CPU time | 439.71 seconds |
| Started | Aug 25 05:33:01 PM UTC 24 |
| Finished | Aug 25 05:40:27 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963820883 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3963820883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.915751984 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 29462032398 ps |
| CPU time | 702.11 seconds |
| Started | Aug 25 05:33:00 PM UTC 24 |
| Finished | Aug 25 05:44:53 PM UTC 24 |
| Peak memory | 599392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915751984 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.915751984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_zero_delays.2470598404 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 369448279 ps |
| CPU time | 51.07 seconds |
| Started | Aug 25 05:32:55 PM UTC 24 |
| Finished | Aug 25 05:33:48 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470598404 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delays.2470598404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_same_source.376513763 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 601324467 ps |
| CPU time | 33.21 seconds |
| Started | Aug 25 05:33:03 PM UTC 24 |
| Finished | Aug 25 05:33:38 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376513763 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.376513763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke.2851580278 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 217524706 ps |
| CPU time | 11.32 seconds |
| Started | Aug 25 05:32:24 PM UTC 24 |
| Finished | Aug 25 05:32:36 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851580278 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2851580278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_large_delays.2372662242 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 6456604974 ps |
| CPU time | 112.41 seconds |
| Started | Aug 25 05:32:30 PM UTC 24 |
| Finished | Aug 25 05:34:25 PM UTC 24 |
| Peak memory | 597580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372662242 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2372662242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.315410987 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 5227090745 ps |
| CPU time | 133.03 seconds |
| Started | Aug 25 05:32:35 PM UTC 24 |
| Finished | Aug 25 05:34:51 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315410987 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.315410987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3841295569 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 35904169 ps |
| CPU time | 9.62 seconds |
| Started | Aug 25 05:32:26 PM UTC 24 |
| Finished | Aug 25 05:32:36 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841295569 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays.3841295569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.933231203 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 4523679550 ps |
| CPU time | 244.4 seconds |
| Started | Aug 25 05:33:12 PM UTC 24 |
| Finished | Aug 25 05:37:20 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933231203 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.933231203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.742809701 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 4902441687 ps |
| CPU time | 273.64 seconds |
| Started | Aug 25 05:33:20 PM UTC 24 |
| Finished | Aug 25 05:37:59 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742809701 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.742809701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1526030340 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 325555252 ps |
| CPU time | 267.68 seconds |
| Started | Aug 25 05:33:19 PM UTC 24 |
| Finished | Aug 25 05:37:52 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526030340 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_rand_reset.1526030340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3340257502 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 3765976232 ps |
| CPU time | 495.65 seconds |
| Started | Aug 25 05:33:22 PM UTC 24 |
| Finished | Aug 25 05:41:46 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340257502 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_reset_error.3340257502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_unmapped_addr.2794592689 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 177597178 ps |
| CPU time | 15.82 seconds |
| Started | Aug 25 05:33:08 PM UTC 24 |
| Finished | Aug 25 05:33:26 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794592689 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2794592689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2868603494 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 6624520170 ps |
| CPU time | 789.01 seconds |
| Started | Aug 25 03:44:43 PM UTC 24 |
| Finished | Aug 25 03:58:04 PM UTC 24 |
| Peak memory | 663152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2868603494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 8.chip_csr_mem_rw_with_rand_reset.2868603494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1613325171 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 4594530986 ps |
| CPU time | 605.66 seconds |
| Started | Aug 25 03:44:35 PM UTC 24 |
| Finished | Aug 25 03:54:50 PM UTC 24 |
| Peak memory | 622324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613325171 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1613325171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_same_csr_outstanding.120533955 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 15546970214 ps |
| CPU time | 3276.02 seconds |
| Started | Aug 25 03:42:43 PM UTC 24 |
| Finished | Aug 25 04:38:08 PM UTC 24 |
| Peak memory | 611892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=120533955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.chip_same_csr_outstanding.120533955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.110462298 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2154737027 ps |
| CPU time | 104.54 seconds |
| Started | Aug 25 03:43:28 PM UTC 24 |
| Finished | Aug 25 03:45:15 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110462298 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.110462298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2711242943 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 68698527722 ps |
| CPU time | 1500.42 seconds |
| Started | Aug 25 03:43:29 PM UTC 24 |
| Finished | Aug 25 04:08:51 PM UTC 24 |
| Peak memory | 599388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711242943 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2711242943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3119823920 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 1316158944 ps |
| CPU time | 61.49 seconds |
| Started | Aug 25 03:44:05 PM UTC 24 |
| Finished | Aug 25 03:45:08 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119823920 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3119823920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2058383087 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 480109449 ps |
| CPU time | 60.95 seconds |
| Started | Aug 25 03:43:59 PM UTC 24 |
| Finished | Aug 25 03:45:02 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058383087 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2058383087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3713215133 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 214077642 ps |
| CPU time | 15.53 seconds |
| Started | Aug 25 03:43:18 PM UTC 24 |
| Finished | Aug 25 03:43:35 PM UTC 24 |
| Peak memory | 597252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713215133 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3713215133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1017326425 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 25471937826 ps |
| CPU time | 442.19 seconds |
| Started | Aug 25 03:43:27 PM UTC 24 |
| Finished | Aug 25 03:50:57 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017326425 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1017326425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3521649379 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 68633969599 ps |
| CPU time | 1632.28 seconds |
| Started | Aug 25 03:43:29 PM UTC 24 |
| Finished | Aug 25 04:11:05 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521649379 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3521649379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.437959654 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 446788517 ps |
| CPU time | 42.18 seconds |
| Started | Aug 25 03:43:24 PM UTC 24 |
| Finished | Aug 25 03:44:08 PM UTC 24 |
| Peak memory | 599404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437959654 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.437959654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1865987956 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2626218199 ps |
| CPU time | 120.17 seconds |
| Started | Aug 25 03:43:49 PM UTC 24 |
| Finished | Aug 25 03:45:52 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865987956 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1865987956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2187043335 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 46440229 ps |
| CPU time | 8.62 seconds |
| Started | Aug 25 03:42:52 PM UTC 24 |
| Finished | Aug 25 03:43:03 PM UTC 24 |
| Peak memory | 597400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187043335 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2187043335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.585523821 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 5505120235 ps |
| CPU time | 88.9 seconds |
| Started | Aug 25 03:42:54 PM UTC 24 |
| Finished | Aug 25 03:44:25 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585523821 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.585523821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3775376166 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 3806545816 ps |
| CPU time | 97.85 seconds |
| Started | Aug 25 03:43:12 PM UTC 24 |
| Finished | Aug 25 03:44:53 PM UTC 24 |
| Peak memory | 597080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775376166 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3775376166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.303168987 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 48031734 ps |
| CPU time | 10.33 seconds |
| Started | Aug 25 03:42:53 PM UTC 24 |
| Finished | Aug 25 03:43:06 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303168987 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.303168987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2923114369 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2323133047 ps |
| CPU time | 291.17 seconds |
| Started | Aug 25 03:44:06 PM UTC 24 |
| Finished | Aug 25 03:49:03 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923114369 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2923114369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3955736855 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 3687072330 ps |
| CPU time | 422.69 seconds |
| Started | Aug 25 03:44:24 PM UTC 24 |
| Finished | Aug 25 03:51:34 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955736855 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3955736855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2505154598 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 263409892 ps |
| CPU time | 194.69 seconds |
| Started | Aug 25 03:44:08 PM UTC 24 |
| Finished | Aug 25 03:47:27 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505154598 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2505154598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2644647691 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 139491532 ps |
| CPU time | 45.9 seconds |
| Started | Aug 25 03:44:33 PM UTC 24 |
| Finished | Aug 25 03:45:20 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644647691 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2644647691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1421865882 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1371729391 ps |
| CPU time | 75.94 seconds |
| Started | Aug 25 03:44:01 PM UTC 24 |
| Finished | Aug 25 03:45:19 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421865882 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1421865882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2220982423 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 2855570278 ps |
| CPU time | 145.61 seconds |
| Started | Aug 25 05:33:56 PM UTC 24 |
| Finished | Aug 25 05:36:25 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220982423 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.2220982423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.5136142 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 80686682537 ps |
| CPU time | 1820.25 seconds |
| Started | Aug 25 05:34:00 PM UTC 24 |
| Finished | Aug 25 06:04:47 PM UTC 24 |
| Peak memory | 599516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5136142 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device_slow_rsp.5136142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2028313387 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 669534866 ps |
| CPU time | 35.21 seconds |
| Started | Aug 25 05:34:03 PM UTC 24 |
| Finished | Aug 25 05:34:40 PM UTC 24 |
| Peak memory | 599292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028313387 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr.2028313387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_error_random.3860487205 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 193958505 ps |
| CPU time | 28.68 seconds |
| Started | Aug 25 05:34:00 PM UTC 24 |
| Finished | Aug 25 05:34:30 PM UTC 24 |
| Peak memory | 599480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860487205 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3860487205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random.1841386081 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 36824893 ps |
| CPU time | 10.45 seconds |
| Started | Aug 25 05:33:46 PM UTC 24 |
| Finished | Aug 25 05:33:57 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841386081 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1841386081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.820756656 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 16613472854 ps |
| CPU time | 286.43 seconds |
| Started | Aug 25 05:33:48 PM UTC 24 |
| Finished | Aug 25 05:38:39 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820756656 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.820756656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.4033499956 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 31587413132 ps |
| CPU time | 664.41 seconds |
| Started | Aug 25 05:33:53 PM UTC 24 |
| Finished | Aug 25 05:45:06 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033499956 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.4033499956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_zero_delays.3912111649 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 204711899 ps |
| CPU time | 32.5 seconds |
| Started | Aug 25 05:33:49 PM UTC 24 |
| Finished | Aug 25 05:34:23 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912111649 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_delays.3912111649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_same_source.4188195489 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 293659270 ps |
| CPU time | 30.95 seconds |
| Started | Aug 25 05:33:59 PM UTC 24 |
| Finished | Aug 25 05:34:31 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188195489 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.4188195489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke.285494298 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 198084199 ps |
| CPU time | 13.74 seconds |
| Started | Aug 25 05:33:27 PM UTC 24 |
| Finished | Aug 25 05:33:42 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285494298 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.285494298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_large_delays.2874525000 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 6627220436 ps |
| CPU time | 89.57 seconds |
| Started | Aug 25 05:33:36 PM UTC 24 |
| Finished | Aug 25 05:35:08 PM UTC 24 |
| Peak memory | 597208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874525000 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2874525000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3518064692 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 4371111794 ps |
| CPU time | 99.12 seconds |
| Started | Aug 25 05:33:42 PM UTC 24 |
| Finished | Aug 25 05:35:23 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518064692 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3518064692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2428491612 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 55304672 ps |
| CPU time | 11.01 seconds |
| Started | Aug 25 05:33:35 PM UTC 24 |
| Finished | Aug 25 05:33:47 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428491612 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays.2428491612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2552354777 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 2906312335 ps |
| CPU time | 249.56 seconds |
| Started | Aug 25 05:34:05 PM UTC 24 |
| Finished | Aug 25 05:38:19 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552354777 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2552354777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.4191124075 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 1268437417 ps |
| CPU time | 98.22 seconds |
| Started | Aug 25 05:34:07 PM UTC 24 |
| Finished | Aug 25 05:35:47 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191124075 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.4191124075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1589256395 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 6407335129 ps |
| CPU time | 908.7 seconds |
| Started | Aug 25 05:34:04 PM UTC 24 |
| Finished | Aug 25 05:49:26 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589256395 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_rand_reset.1589256395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.4107264772 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 9396874050 ps |
| CPU time | 692.44 seconds |
| Started | Aug 25 05:34:06 PM UTC 24 |
| Finished | Aug 25 05:45:49 PM UTC 24 |
| Peak memory | 599636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107264772 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_reset_error.4107264772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_unmapped_addr.2983476200 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 297524473 ps |
| CPU time | 25.91 seconds |
| Started | Aug 25 05:34:02 PM UTC 24 |
| Finished | Aug 25 05:34:29 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983476200 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2983476200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.200907196 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 470281159 ps |
| CPU time | 61.92 seconds |
| Started | Aug 25 05:34:46 PM UTC 24 |
| Finished | Aug 25 05:35:50 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200907196 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.200907196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2962853795 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 44966347806 ps |
| CPU time | 950.15 seconds |
| Started | Aug 25 05:34:47 PM UTC 24 |
| Finished | Aug 25 05:50:50 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962853795 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device_slow_rsp.2962853795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1410803713 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 798706335 ps |
| CPU time | 46.99 seconds |
| Started | Aug 25 05:34:53 PM UTC 24 |
| Finished | Aug 25 05:35:41 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410803713 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr.1410803713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2362745924 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 1356558073 ps |
| CPU time | 50.05 seconds |
| Started | Aug 25 05:34:51 PM UTC 24 |
| Finished | Aug 25 05:35:43 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362745924 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2362745924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random.3394247166 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 224801720 ps |
| CPU time | 32.5 seconds |
| Started | Aug 25 05:34:22 PM UTC 24 |
| Finished | Aug 25 05:34:56 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394247166 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3394247166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.15460832 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 3301507330 ps |
| CPU time | 56.12 seconds |
| Started | Aug 25 05:34:38 PM UTC 24 |
| Finished | Aug 25 05:35:36 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15460832 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.15460832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.467701627 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 33567412931 ps |
| CPU time | 659.06 seconds |
| Started | Aug 25 05:34:39 PM UTC 24 |
| Finished | Aug 25 05:45:47 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467701627 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.467701627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_zero_delays.1620858394 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 375106489 ps |
| CPU time | 51.4 seconds |
| Started | Aug 25 05:34:32 PM UTC 24 |
| Finished | Aug 25 05:35:25 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620858394 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_delays.1620858394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_same_source.1427713434 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 416455937 ps |
| CPU time | 24.06 seconds |
| Started | Aug 25 05:34:50 PM UTC 24 |
| Finished | Aug 25 05:35:15 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427713434 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1427713434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke.3477099347 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 205084574 ps |
| CPU time | 14.94 seconds |
| Started | Aug 25 05:34:12 PM UTC 24 |
| Finished | Aug 25 05:34:28 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477099347 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3477099347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1094617559 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 10289731205 ps |
| CPU time | 193.07 seconds |
| Started | Aug 25 05:34:12 PM UTC 24 |
| Finished | Aug 25 05:37:28 PM UTC 24 |
| Peak memory | 597388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094617559 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1094617559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.522132542 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 6413556911 ps |
| CPU time | 149.66 seconds |
| Started | Aug 25 05:34:19 PM UTC 24 |
| Finished | Aug 25 05:36:51 PM UTC 24 |
| Peak memory | 597136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522132542 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.522132542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1995469746 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 52235763 ps |
| CPU time | 9.25 seconds |
| Started | Aug 25 05:34:11 PM UTC 24 |
| Finished | Aug 25 05:34:22 PM UTC 24 |
| Peak memory | 597216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995469746 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays.1995469746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1703272486 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 1481708637 ps |
| CPU time | 186.28 seconds |
| Started | Aug 25 05:34:51 PM UTC 24 |
| Finished | Aug 25 05:38:01 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703272486 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1703272486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2885208518 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 9691521109 ps |
| CPU time | 633.28 seconds |
| Started | Aug 25 05:35:02 PM UTC 24 |
| Finished | Aug 25 05:45:45 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885208518 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_rand_reset.2885208518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.477896784 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 4359521636 ps |
| CPU time | 844.52 seconds |
| Started | Aug 25 05:35:18 PM UTC 24 |
| Finished | Aug 25 05:49:36 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477896784 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_reset_error.477896784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.3633502704 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 573819210 ps |
| CPU time | 40.5 seconds |
| Started | Aug 25 05:34:51 PM UTC 24 |
| Finished | Aug 25 05:35:33 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633502704 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3633502704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.455413934 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 392502278 ps |
| CPU time | 32.33 seconds |
| Started | Aug 25 05:36:00 PM UTC 24 |
| Finished | Aug 25 05:36:34 PM UTC 24 |
| Peak memory | 599568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455413934 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device.455413934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2162661144 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 69352001184 ps |
| CPU time | 1546.97 seconds |
| Started | Aug 25 05:36:04 PM UTC 24 |
| Finished | Aug 25 06:02:13 PM UTC 24 |
| Peak memory | 599408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162661144 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device_slow_rsp.2162661144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.4259222035 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 308240353 ps |
| CPU time | 46.72 seconds |
| Started | Aug 25 05:36:13 PM UTC 24 |
| Finished | Aug 25 05:37:01 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259222035 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_addr.4259222035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.4249992537 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 480913566 ps |
| CPU time | 58.07 seconds |
| Started | Aug 25 05:36:07 PM UTC 24 |
| Finished | Aug 25 05:37:07 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249992537 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.4249992537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1774943117 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2571341622 ps |
| CPU time | 144.85 seconds |
| Started | Aug 25 05:35:47 PM UTC 24 |
| Finished | Aug 25 05:38:15 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774943117 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1774943117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_large_delays.461034851 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 90178201849 ps |
| CPU time | 1274.31 seconds |
| Started | Aug 25 05:35:56 PM UTC 24 |
| Finished | Aug 25 05:57:28 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461034851 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.461034851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.669445819 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 10162991599 ps |
| CPU time | 271.06 seconds |
| Started | Aug 25 05:35:58 PM UTC 24 |
| Finished | Aug 25 05:40:34 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669445819 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.669445819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.1667981062 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 406119458 ps |
| CPU time | 57.1 seconds |
| Started | Aug 25 05:35:51 PM UTC 24 |
| Finished | Aug 25 05:36:50 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667981062 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.1667981062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3221240471 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 208869868 ps |
| CPU time | 28.84 seconds |
| Started | Aug 25 05:36:07 PM UTC 24 |
| Finished | Aug 25 05:36:38 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221240471 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.3221240471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.520629265 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 247173796 ps |
| CPU time | 11.13 seconds |
| Started | Aug 25 05:35:20 PM UTC 24 |
| Finished | Aug 25 05:35:32 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520629265 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.520629265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1700559778 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 7676274593 ps |
| CPU time | 94.52 seconds |
| Started | Aug 25 05:35:34 PM UTC 24 |
| Finished | Aug 25 05:37:10 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700559778 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1700559778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2571331333 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 4699169287 ps |
| CPU time | 115.99 seconds |
| Started | Aug 25 05:35:39 PM UTC 24 |
| Finished | Aug 25 05:37:38 PM UTC 24 |
| Peak memory | 597404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571331333 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2571331333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.696131728 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 41029174 ps |
| CPU time | 9.83 seconds |
| Started | Aug 25 05:35:32 PM UTC 24 |
| Finished | Aug 25 05:35:43 PM UTC 24 |
| Peak memory | 597088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696131728 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays.696131728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1260272096 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 3257534972 ps |
| CPU time | 293.67 seconds |
| Started | Aug 25 05:36:25 PM UTC 24 |
| Finished | Aug 25 05:41:24 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260272096 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1260272096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.1309634098 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 3980291718 ps |
| CPU time | 189.67 seconds |
| Started | Aug 25 05:36:50 PM UTC 24 |
| Finished | Aug 25 05:40:03 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309634098 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1309634098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.683857552 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 8215106 ps |
| CPU time | 14.92 seconds |
| Started | Aug 25 05:36:35 PM UTC 24 |
| Finished | Aug 25 05:36:51 PM UTC 24 |
| Peak memory | 597016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683857552 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_rand_reset.683857552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1853133852 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 7056838373 ps |
| CPU time | 438.67 seconds |
| Started | Aug 25 05:36:51 PM UTC 24 |
| Finished | Aug 25 05:44:17 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853133852 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_reset_error.1853133852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.1101894187 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 155793253 ps |
| CPU time | 26.09 seconds |
| Started | Aug 25 05:36:12 PM UTC 24 |
| Finished | Aug 25 05:36:39 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101894187 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1101894187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2983450151 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 323530435 ps |
| CPU time | 32.51 seconds |
| Started | Aug 25 05:37:35 PM UTC 24 |
| Finished | Aug 25 05:38:09 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983450151 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device.2983450151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.366970267 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 62381065207 ps |
| CPU time | 1499.57 seconds |
| Started | Aug 25 05:37:35 PM UTC 24 |
| Finished | Aug 25 06:02:58 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366970267 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device_slow_rsp.366970267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2135387492 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 581863186 ps |
| CPU time | 38.08 seconds |
| Started | Aug 25 05:38:03 PM UTC 24 |
| Finished | Aug 25 05:38:43 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135387492 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.2135387492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3996829582 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 1385478635 ps |
| CPU time | 66.12 seconds |
| Started | Aug 25 05:37:45 PM UTC 24 |
| Finished | Aug 25 05:38:53 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996829582 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3996829582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1052544212 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 551031060 ps |
| CPU time | 60.48 seconds |
| Started | Aug 25 05:37:14 PM UTC 24 |
| Finished | Aug 25 05:38:16 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052544212 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1052544212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_large_delays.3193545113 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 95628823477 ps |
| CPU time | 1367.86 seconds |
| Started | Aug 25 05:37:26 PM UTC 24 |
| Finished | Aug 25 06:00:32 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193545113 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3193545113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.2680078155 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 16595365962 ps |
| CPU time | 426.29 seconds |
| Started | Aug 25 05:37:31 PM UTC 24 |
| Finished | Aug 25 05:44:44 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680078155 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.2680078155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.3879401934 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 168530319 ps |
| CPU time | 27.52 seconds |
| Started | Aug 25 05:37:17 PM UTC 24 |
| Finished | Aug 25 05:37:46 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879401934 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delays.3879401934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.345460713 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 790329141 ps |
| CPU time | 34.35 seconds |
| Started | Aug 25 05:37:39 PM UTC 24 |
| Finished | Aug 25 05:38:14 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345460713 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.345460713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1028060134 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 43915022 ps |
| CPU time | 10.17 seconds |
| Started | Aug 25 05:36:59 PM UTC 24 |
| Finished | Aug 25 05:37:10 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028060134 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1028060134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.275871756 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 7865799699 ps |
| CPU time | 122.17 seconds |
| Started | Aug 25 05:37:05 PM UTC 24 |
| Finished | Aug 25 05:39:10 PM UTC 24 |
| Peak memory | 597268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275871756 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.275871756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2512003812 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 4729933115 ps |
| CPU time | 115.69 seconds |
| Started | Aug 25 05:37:15 PM UTC 24 |
| Finished | Aug 25 05:39:13 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512003812 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2512003812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2310996392 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 40458713 ps |
| CPU time | 10.2 seconds |
| Started | Aug 25 05:37:02 PM UTC 24 |
| Finished | Aug 25 05:37:13 PM UTC 24 |
| Peak memory | 597248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310996392 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.2310996392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1598089822 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1086930909 ps |
| CPU time | 54.32 seconds |
| Started | Aug 25 05:38:11 PM UTC 24 |
| Finished | Aug 25 05:39:07 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598089822 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1598089822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.225812730 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 2145317787 ps |
| CPU time | 237.65 seconds |
| Started | Aug 25 05:38:24 PM UTC 24 |
| Finished | Aug 25 05:42:26 PM UTC 24 |
| Peak memory | 599140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225812730 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.225812730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3761105388 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 192203238 ps |
| CPU time | 155.84 seconds |
| Started | Aug 25 05:38:18 PM UTC 24 |
| Finished | Aug 25 05:40:57 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761105388 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_rand_reset.3761105388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.126477505 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 290632888 ps |
| CPU time | 141.38 seconds |
| Started | Aug 25 05:38:26 PM UTC 24 |
| Finished | Aug 25 05:40:50 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126477505 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_reset_error.126477505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1337083664 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 417314350 ps |
| CPU time | 25.97 seconds |
| Started | Aug 25 05:37:53 PM UTC 24 |
| Finished | Aug 25 05:38:20 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337083664 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.1337083664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.155863019 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 462407671 ps |
| CPU time | 48.87 seconds |
| Started | Aug 25 05:38:47 PM UTC 24 |
| Finished | Aug 25 05:39:38 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155863019 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.155863019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1541445833 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 128915698907 ps |
| CPU time | 2707.5 seconds |
| Started | Aug 25 05:39:03 PM UTC 24 |
| Finished | Aug 25 06:24:55 PM UTC 24 |
| Peak memory | 600032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541445833 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device_slow_rsp.1541445833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2118766571 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 786391973 ps |
| CPU time | 38.8 seconds |
| Started | Aug 25 05:39:07 PM UTC 24 |
| Finished | Aug 25 05:39:47 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118766571 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr.2118766571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.2519303541 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 497561087 ps |
| CPU time | 57.15 seconds |
| Started | Aug 25 05:39:07 PM UTC 24 |
| Finished | Aug 25 05:40:06 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519303541 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2519303541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.571696668 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 1109906336 ps |
| CPU time | 59 seconds |
| Started | Aug 25 05:38:38 PM UTC 24 |
| Finished | Aug 25 05:39:39 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571696668 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.571696668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.2634824562 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 18847098857 ps |
| CPU time | 298.65 seconds |
| Started | Aug 25 05:38:43 PM UTC 24 |
| Finished | Aug 25 05:43:46 PM UTC 24 |
| Peak memory | 599600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634824562 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.2634824562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_slow_rsp.554583920 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 54276598306 ps |
| CPU time | 1313.46 seconds |
| Started | Aug 25 05:38:45 PM UTC 24 |
| Finished | Aug 25 06:00:59 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554583920 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.554583920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1745235913 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 159639121 ps |
| CPU time | 25.5 seconds |
| Started | Aug 25 05:38:40 PM UTC 24 |
| Finished | Aug 25 05:39:07 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745235913 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_delays.1745235913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3147247606 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 2316047696 ps |
| CPU time | 107.55 seconds |
| Started | Aug 25 05:39:05 PM UTC 24 |
| Finished | Aug 25 05:40:55 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147247606 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3147247606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.2672061190 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 194300719 ps |
| CPU time | 14.15 seconds |
| Started | Aug 25 05:38:27 PM UTC 24 |
| Finished | Aug 25 05:38:42 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672061190 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2672061190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.3047188220 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 9651991377 ps |
| CPU time | 170.53 seconds |
| Started | Aug 25 05:38:34 PM UTC 24 |
| Finished | Aug 25 05:41:27 PM UTC 24 |
| Peak memory | 597456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047188220 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.3047188220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1865043459 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 5885301432 ps |
| CPU time | 135.54 seconds |
| Started | Aug 25 05:38:39 PM UTC 24 |
| Finished | Aug 25 05:40:57 PM UTC 24 |
| Peak memory | 597392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865043459 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1865043459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3469604909 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 45387217 ps |
| CPU time | 8.29 seconds |
| Started | Aug 25 05:38:31 PM UTC 24 |
| Finished | Aug 25 05:38:40 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469604909 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays.3469604909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2145077918 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 1351235059 ps |
| CPU time | 62.4 seconds |
| Started | Aug 25 05:39:09 PM UTC 24 |
| Finished | Aug 25 05:40:13 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145077918 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2145077918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.2459666369 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 14123555520 ps |
| CPU time | 620.61 seconds |
| Started | Aug 25 05:39:31 PM UTC 24 |
| Finished | Aug 25 05:50:02 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459666369 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2459666369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.758056409 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 3886424341 ps |
| CPU time | 414.71 seconds |
| Started | Aug 25 05:39:18 PM UTC 24 |
| Finished | Aug 25 05:46:20 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758056409 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_rand_reset.758056409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1479012633 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 5128463933 ps |
| CPU time | 508.62 seconds |
| Started | Aug 25 05:39:31 PM UTC 24 |
| Finished | Aug 25 05:48:10 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479012633 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_reset_error.1479012633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3717729044 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 392703892 ps |
| CPU time | 31.16 seconds |
| Started | Aug 25 05:39:08 PM UTC 24 |
| Finished | Aug 25 05:39:41 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717729044 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3717729044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.2360013697 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 437626140 ps |
| CPU time | 48 seconds |
| Started | Aug 25 05:40:12 PM UTC 24 |
| Finished | Aug 25 05:41:01 PM UTC 24 |
| Peak memory | 599504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360013697 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.2360013697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1766248763 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 148372337858 ps |
| CPU time | 2773.78 seconds |
| Started | Aug 25 05:40:28 PM UTC 24 |
| Finished | Aug 25 06:27:24 PM UTC 24 |
| Peak memory | 600032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766248763 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device_slow_rsp.1766248763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2507215869 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 161464019 ps |
| CPU time | 29.17 seconds |
| Started | Aug 25 05:40:45 PM UTC 24 |
| Finished | Aug 25 05:41:16 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507215869 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr.2507215869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.2415683095 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 1480226290 ps |
| CPU time | 74.21 seconds |
| Started | Aug 25 05:40:36 PM UTC 24 |
| Finished | Aug 25 05:41:52 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415683095 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2415683095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.3410515289 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 297095326 ps |
| CPU time | 19.52 seconds |
| Started | Aug 25 05:40:02 PM UTC 24 |
| Finished | Aug 25 05:40:23 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410515289 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3410515289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.707379609 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 11508207250 ps |
| CPU time | 180.37 seconds |
| Started | Aug 25 05:40:10 PM UTC 24 |
| Finished | Aug 25 05:43:14 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707379609 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.707379609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3898802213 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 8136134967 ps |
| CPU time | 185.33 seconds |
| Started | Aug 25 05:40:11 PM UTC 24 |
| Finished | Aug 25 05:43:20 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898802213 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3898802213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3261571838 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 126545081 ps |
| CPU time | 21.07 seconds |
| Started | Aug 25 05:40:05 PM UTC 24 |
| Finished | Aug 25 05:40:27 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261571838 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delays.3261571838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.350736527 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 2177528178 ps |
| CPU time | 100.69 seconds |
| Started | Aug 25 05:40:30 PM UTC 24 |
| Finished | Aug 25 05:42:14 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350736527 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.350736527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.1013853007 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 45571217 ps |
| CPU time | 10.09 seconds |
| Started | Aug 25 05:39:34 PM UTC 24 |
| Finished | Aug 25 05:39:46 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013853007 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1013853007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2504228411 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 8163681441 ps |
| CPU time | 139.32 seconds |
| Started | Aug 25 05:39:38 PM UTC 24 |
| Finished | Aug 25 05:42:00 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504228411 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2504228411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.341509478 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 4517259848 ps |
| CPU time | 126.4 seconds |
| Started | Aug 25 05:40:03 PM UTC 24 |
| Finished | Aug 25 05:42:12 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341509478 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.341509478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2875852566 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 47709083 ps |
| CPU time | 10.49 seconds |
| Started | Aug 25 05:39:34 PM UTC 24 |
| Finished | Aug 25 05:39:46 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875852566 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays.2875852566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.299730634 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 1976129851 ps |
| CPU time | 242.15 seconds |
| Started | Aug 25 05:40:51 PM UTC 24 |
| Finished | Aug 25 05:44:58 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299730634 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.299730634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_error.1437274513 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 17415531262 ps |
| CPU time | 951.41 seconds |
| Started | Aug 25 05:40:57 PM UTC 24 |
| Finished | Aug 25 05:57:04 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437274513 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1437274513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.285511469 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 2250092398 ps |
| CPU time | 545.39 seconds |
| Started | Aug 25 05:40:52 PM UTC 24 |
| Finished | Aug 25 05:50:06 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285511469 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_rand_reset.285511469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2143136089 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 143163078 ps |
| CPU time | 88.67 seconds |
| Started | Aug 25 05:41:06 PM UTC 24 |
| Finished | Aug 25 05:42:37 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143136089 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_reset_error.2143136089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.212886554 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 172439335 ps |
| CPU time | 30.66 seconds |
| Started | Aug 25 05:40:45 PM UTC 24 |
| Finished | Aug 25 05:41:18 PM UTC 24 |
| Peak memory | 599488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212886554 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.212886554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.2921386587 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 149921747 ps |
| CPU time | 13.92 seconds |
| Started | Aug 25 05:41:41 PM UTC 24 |
| Finished | Aug 25 05:41:56 PM UTC 24 |
| Peak memory | 597352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921386587 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.2921386587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.696865117 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 20364687088 ps |
| CPU time | 493.01 seconds |
| Started | Aug 25 05:41:42 PM UTC 24 |
| Finished | Aug 25 05:50:02 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696865117 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device_slow_rsp.696865117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2299796229 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 20634391 ps |
| CPU time | 8.31 seconds |
| Started | Aug 25 05:41:52 PM UTC 24 |
| Finished | Aug 25 05:42:01 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299796229 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr.2299796229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.364655682 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 2642448403 ps |
| CPU time | 98.06 seconds |
| Started | Aug 25 05:41:49 PM UTC 24 |
| Finished | Aug 25 05:43:29 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364655682 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.364655682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1503500190 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 137120223 ps |
| CPU time | 11.27 seconds |
| Started | Aug 25 05:41:20 PM UTC 24 |
| Finished | Aug 25 05:41:32 PM UTC 24 |
| Peak memory | 597204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503500190 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1503500190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_large_delays.2811215041 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 104335316090 ps |
| CPU time | 1451.61 seconds |
| Started | Aug 25 05:41:29 PM UTC 24 |
| Finished | Aug 25 06:06:01 PM UTC 24 |
| Peak memory | 599668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811215041 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.2811215041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_slow_rsp.4261160400 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 28945350305 ps |
| CPU time | 710.86 seconds |
| Started | Aug 25 05:41:42 PM UTC 24 |
| Finished | Aug 25 05:53:44 PM UTC 24 |
| Peak memory | 599616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261160400 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.4261160400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3843073389 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 106026135 ps |
| CPU time | 19.85 seconds |
| Started | Aug 25 05:41:26 PM UTC 24 |
| Finished | Aug 25 05:41:47 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843073389 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.3843073389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.4071957216 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 553387025 ps |
| CPU time | 23.57 seconds |
| Started | Aug 25 05:41:45 PM UTC 24 |
| Finished | Aug 25 05:42:10 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071957216 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.4071957216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.1820815352 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 44054443 ps |
| CPU time | 10.38 seconds |
| Started | Aug 25 05:41:12 PM UTC 24 |
| Finished | Aug 25 05:41:23 PM UTC 24 |
| Peak memory | 596996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820815352 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1820815352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.2013071046 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 7425947850 ps |
| CPU time | 131.34 seconds |
| Started | Aug 25 05:41:20 PM UTC 24 |
| Finished | Aug 25 05:43:34 PM UTC 24 |
| Peak memory | 597580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013071046 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2013071046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3309656645 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 5267767902 ps |
| CPU time | 138.78 seconds |
| Started | Aug 25 05:41:21 PM UTC 24 |
| Finished | Aug 25 05:43:43 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309656645 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3309656645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.622268447 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 47605214 ps |
| CPU time | 10.14 seconds |
| Started | Aug 25 05:41:17 PM UTC 24 |
| Finished | Aug 25 05:41:28 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622268447 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays.622268447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3443351660 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 1207582552 ps |
| CPU time | 157.79 seconds |
| Started | Aug 25 05:41:53 PM UTC 24 |
| Finished | Aug 25 05:44:34 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443351660 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3443351660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.844540785 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 5004669238 ps |
| CPU time | 237.6 seconds |
| Started | Aug 25 05:42:12 PM UTC 24 |
| Finished | Aug 25 05:46:14 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844540785 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.844540785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.551764075 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 7138060136 ps |
| CPU time | 678.87 seconds |
| Started | Aug 25 05:41:55 PM UTC 24 |
| Finished | Aug 25 05:53:24 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551764075 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_rand_reset.551764075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3401930525 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 7905523 ps |
| CPU time | 23.35 seconds |
| Started | Aug 25 05:42:12 PM UTC 24 |
| Finished | Aug 25 05:42:37 PM UTC 24 |
| Peak memory | 597156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401930525 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_reset_error.3401930525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3161664007 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 428675111 ps |
| CPU time | 31.68 seconds |
| Started | Aug 25 05:41:51 PM UTC 24 |
| Finished | Aug 25 05:42:24 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161664007 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3161664007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1437157235 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 996546666 ps |
| CPU time | 108.74 seconds |
| Started | Aug 25 05:42:50 PM UTC 24 |
| Finished | Aug 25 05:44:41 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437157235 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.1437157235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.856019496 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 15990953376 ps |
| CPU time | 351.64 seconds |
| Started | Aug 25 05:42:50 PM UTC 24 |
| Finished | Aug 25 05:48:48 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856019496 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device_slow_rsp.856019496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.940213713 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 668290074 ps |
| CPU time | 42.24 seconds |
| Started | Aug 25 05:43:01 PM UTC 24 |
| Finished | Aug 25 05:43:45 PM UTC 24 |
| Peak memory | 599244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940213713 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr.940213713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3047482434 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 639818585 ps |
| CPU time | 36.58 seconds |
| Started | Aug 25 05:42:52 PM UTC 24 |
| Finished | Aug 25 05:43:30 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047482434 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3047482434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2783710861 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 1161543189 ps |
| CPU time | 62.93 seconds |
| Started | Aug 25 05:42:32 PM UTC 24 |
| Finished | Aug 25 05:43:37 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783710861 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2783710861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3888520122 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 18465303787 ps |
| CPU time | 313.37 seconds |
| Started | Aug 25 05:42:37 PM UTC 24 |
| Finished | Aug 25 05:47:56 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888520122 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3888520122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.2576406497 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 19048052033 ps |
| CPU time | 491.86 seconds |
| Started | Aug 25 05:42:39 PM UTC 24 |
| Finished | Aug 25 05:50:59 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576406497 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2576406497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.867537784 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 243214259 ps |
| CPU time | 37.5 seconds |
| Started | Aug 25 05:42:35 PM UTC 24 |
| Finished | Aug 25 05:43:15 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867537784 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_delays.867537784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.134563154 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 1293909371 ps |
| CPU time | 65.24 seconds |
| Started | Aug 25 05:42:52 PM UTC 24 |
| Finished | Aug 25 05:43:59 PM UTC 24 |
| Peak memory | 599324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134563154 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.134563154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.440039462 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 230685135 ps |
| CPU time | 14.59 seconds |
| Started | Aug 25 05:42:14 PM UTC 24 |
| Finished | Aug 25 05:42:30 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440039462 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.440039462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.3597924918 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 7353054550 ps |
| CPU time | 115.97 seconds |
| Started | Aug 25 05:42:25 PM UTC 24 |
| Finished | Aug 25 05:44:24 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597924918 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3597924918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1826868166 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 5533635056 ps |
| CPU time | 124.76 seconds |
| Started | Aug 25 05:42:24 PM UTC 24 |
| Finished | Aug 25 05:44:31 PM UTC 24 |
| Peak memory | 597392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826868166 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1826868166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3755255428 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 38709954 ps |
| CPU time | 9.41 seconds |
| Started | Aug 25 05:42:16 PM UTC 24 |
| Finished | Aug 25 05:42:27 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755255428 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays.3755255428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3100653472 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 2562483309 ps |
| CPU time | 270.91 seconds |
| Started | Aug 25 05:43:01 PM UTC 24 |
| Finished | Aug 25 05:47:37 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100653472 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3100653472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1582413518 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 2765274781 ps |
| CPU time | 146.24 seconds |
| Started | Aug 25 05:43:38 PM UTC 24 |
| Finished | Aug 25 05:46:08 PM UTC 24 |
| Peak memory | 599540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582413518 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1582413518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3089782258 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 7446961926 ps |
| CPU time | 573.16 seconds |
| Started | Aug 25 05:43:27 PM UTC 24 |
| Finished | Aug 25 05:53:09 PM UTC 24 |
| Peak memory | 599624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089782258 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_rand_reset.3089782258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3320041300 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 5488170940 ps |
| CPU time | 620.28 seconds |
| Started | Aug 25 05:43:39 PM UTC 24 |
| Finished | Aug 25 05:54:08 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320041300 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_reset_error.3320041300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1619012867 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 983764772 ps |
| CPU time | 55.6 seconds |
| Started | Aug 25 05:42:55 PM UTC 24 |
| Finished | Aug 25 05:43:52 PM UTC 24 |
| Peak memory | 599316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619012867 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1619012867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.2866686400 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 855875335 ps |
| CPU time | 58.09 seconds |
| Started | Aug 25 05:44:07 PM UTC 24 |
| Finished | Aug 25 05:45:07 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866686400 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.2866686400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1404466059 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 121463078317 ps |
| CPU time | 2384.2 seconds |
| Started | Aug 25 05:44:09 PM UTC 24 |
| Finished | Aug 25 06:24:33 PM UTC 24 |
| Peak memory | 600224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404466059 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device_slow_rsp.1404466059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1638667386 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 116359885 ps |
| CPU time | 10.39 seconds |
| Started | Aug 25 05:44:21 PM UTC 24 |
| Finished | Aug 25 05:44:32 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638667386 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr.1638667386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3732511080 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 36096528 ps |
| CPU time | 8.52 seconds |
| Started | Aug 25 05:44:15 PM UTC 24 |
| Finished | Aug 25 05:44:25 PM UTC 24 |
| Peak memory | 597188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732511080 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3732511080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.287162161 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 2579745136 ps |
| CPU time | 135.19 seconds |
| Started | Aug 25 05:43:58 PM UTC 24 |
| Finished | Aug 25 05:46:16 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287162161 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.287162161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_large_delays.1811420612 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 33178640993 ps |
| CPU time | 491.57 seconds |
| Started | Aug 25 05:44:01 PM UTC 24 |
| Finished | Aug 25 05:52:20 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811420612 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1811420612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1325372300 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 14659138368 ps |
| CPU time | 374.13 seconds |
| Started | Aug 25 05:44:06 PM UTC 24 |
| Finished | Aug 25 05:50:26 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325372300 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1325372300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.3331003254 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 485565631 ps |
| CPU time | 70.17 seconds |
| Started | Aug 25 05:44:00 PM UTC 24 |
| Finished | Aug 25 05:45:12 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331003254 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_delays.3331003254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.379195381 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 133853898 ps |
| CPU time | 19.24 seconds |
| Started | Aug 25 05:44:10 PM UTC 24 |
| Finished | Aug 25 05:44:30 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379195381 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.379195381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.2550294388 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 211695380 ps |
| CPU time | 14.99 seconds |
| Started | Aug 25 05:43:44 PM UTC 24 |
| Finished | Aug 25 05:44:00 PM UTC 24 |
| Peak memory | 597268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550294388 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2550294388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2399681578 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 6828632776 ps |
| CPU time | 104.5 seconds |
| Started | Aug 25 05:43:55 PM UTC 24 |
| Finished | Aug 25 05:45:42 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399681578 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2399681578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1302482496 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 6321006194 ps |
| CPU time | 154.79 seconds |
| Started | Aug 25 05:43:55 PM UTC 24 |
| Finished | Aug 25 05:46:33 PM UTC 24 |
| Peak memory | 597464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302482496 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1302482496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2026389107 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 57561455 ps |
| CPU time | 10.82 seconds |
| Started | Aug 25 05:43:48 PM UTC 24 |
| Finished | Aug 25 05:44:00 PM UTC 24 |
| Peak memory | 597192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026389107 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.2026389107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.688068459 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 7660268836 ps |
| CPU time | 443.55 seconds |
| Started | Aug 25 05:44:24 PM UTC 24 |
| Finished | Aug 25 05:51:55 PM UTC 24 |
| Peak memory | 599336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688068459 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.688068459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_error.1628290089 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 16528191008 ps |
| CPU time | 941.26 seconds |
| Started | Aug 25 05:44:26 PM UTC 24 |
| Finished | Aug 25 06:00:23 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628290089 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1628290089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.123156449 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 13816136752 ps |
| CPU time | 977.73 seconds |
| Started | Aug 25 05:44:25 PM UTC 24 |
| Finished | Aug 25 06:01:00 PM UTC 24 |
| Peak memory | 599416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123156449 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_rand_reset.123156449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3175016840 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 1157065367 ps |
| CPU time | 370.22 seconds |
| Started | Aug 25 05:44:41 PM UTC 24 |
| Finished | Aug 25 05:50:58 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175016840 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_reset_error.3175016840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.610286386 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 169458143 ps |
| CPU time | 18.12 seconds |
| Started | Aug 25 05:44:17 PM UTC 24 |
| Finished | Aug 25 05:44:36 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610286386 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.610286386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2999425025 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 2197228122 ps |
| CPU time | 114.31 seconds |
| Started | Aug 25 05:45:06 PM UTC 24 |
| Finished | Aug 25 05:47:03 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999425025 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device.2999425025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3356194438 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 131307153419 ps |
| CPU time | 2700.1 seconds |
| Started | Aug 25 05:45:10 PM UTC 24 |
| Finished | Aug 25 06:30:51 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356194438 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device_slow_rsp.3356194438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3251776678 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 151356088 ps |
| CPU time | 14.45 seconds |
| Started | Aug 25 05:45:26 PM UTC 24 |
| Finished | Aug 25 05:45:41 PM UTC 24 |
| Peak memory | 597080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251776678 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr.3251776678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1933242965 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 461362159 ps |
| CPU time | 24.49 seconds |
| Started | Aug 25 05:45:23 PM UTC 24 |
| Finished | Aug 25 05:45:49 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933242965 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1933242965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.1981346100 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 1511260504 ps |
| CPU time | 83.71 seconds |
| Started | Aug 25 05:44:57 PM UTC 24 |
| Finished | Aug 25 05:46:23 PM UTC 24 |
| Peak memory | 599392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981346100 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1981346100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_large_delays.3671141313 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 41609140263 ps |
| CPU time | 703.79 seconds |
| Started | Aug 25 05:45:00 PM UTC 24 |
| Finished | Aug 25 05:56:55 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671141313 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3671141313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.88987810 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 14177156530 ps |
| CPU time | 358.59 seconds |
| Started | Aug 25 05:45:02 PM UTC 24 |
| Finished | Aug 25 05:51:07 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88987810 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.88987810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.2121843643 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 78593225 ps |
| CPU time | 15.77 seconds |
| Started | Aug 25 05:44:56 PM UTC 24 |
| Finished | Aug 25 05:45:13 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121843643 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_delays.2121843643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.3518366518 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 1493199867 ps |
| CPU time | 64.02 seconds |
| Started | Aug 25 05:45:18 PM UTC 24 |
| Finished | Aug 25 05:46:24 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518366518 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3518366518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1997249697 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 201256885 ps |
| CPU time | 14.27 seconds |
| Started | Aug 25 05:44:49 PM UTC 24 |
| Finished | Aug 25 05:45:04 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997249697 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1997249697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2322523640 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 6162942416 ps |
| CPU time | 101.86 seconds |
| Started | Aug 25 05:44:52 PM UTC 24 |
| Finished | Aug 25 05:46:36 PM UTC 24 |
| Peak memory | 597580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322523640 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.2322523640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.364190004 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 6394510996 ps |
| CPU time | 150.1 seconds |
| Started | Aug 25 05:44:55 PM UTC 24 |
| Finished | Aug 25 05:47:28 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364190004 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.364190004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.719379019 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 40476798 ps |
| CPU time | 9.73 seconds |
| Started | Aug 25 05:44:49 PM UTC 24 |
| Finished | Aug 25 05:45:00 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719379019 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays.719379019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all.1491569478 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 11019388807 ps |
| CPU time | 490.69 seconds |
| Started | Aug 25 05:45:28 PM UTC 24 |
| Finished | Aug 25 05:53:46 PM UTC 24 |
| Peak memory | 599492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491569478 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.1491569478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_error.2893975338 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 4098561355 ps |
| CPU time | 460.98 seconds |
| Started | Aug 25 05:45:32 PM UTC 24 |
| Finished | Aug 25 05:53:21 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893975338 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2893975338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.124582669 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 1554498220 ps |
| CPU time | 555.02 seconds |
| Started | Aug 25 05:45:28 PM UTC 24 |
| Finished | Aug 25 05:54:52 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124582669 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_rand_reset.124582669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.917861123 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 405545084 ps |
| CPU time | 250.38 seconds |
| Started | Aug 25 05:45:31 PM UTC 24 |
| Finished | Aug 25 05:49:47 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917861123 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_reset_error.917861123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1403981905 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 676969208 ps |
| CPU time | 41.88 seconds |
| Started | Aug 25 05:45:25 PM UTC 24 |
| Finished | Aug 25 05:46:09 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403981905 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1403981905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2580483706 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 8373682349 ps |
| CPU time | 1571.35 seconds |
| Started | Aug 25 03:46:25 PM UTC 24 |
| Finished | Aug 25 04:13:00 PM UTC 24 |
| Peak memory | 673724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000 000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2580483706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 9.chip_csr_mem_rw_with_rand_reset.2580483706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.2515046995 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3881651187 ps |
| CPU time | 604.2 seconds |
| Started | Aug 25 03:46:22 PM UTC 24 |
| Finished | Aug 25 03:56:37 PM UTC 24 |
| Peak memory | 620244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515046995 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2515046995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_same_csr_outstanding.1995441033 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 29248621137 ps |
| CPU time | 5802.43 seconds |
| Started | Aug 25 03:44:50 PM UTC 24 |
| Finished | Aug 25 05:22:53 PM UTC 24 |
| Peak memory | 614780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1995441033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.chip_same_csr_outstanding.1995441033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3755839933 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3606611990 ps |
| CPU time | 428.89 seconds |
| Started | Aug 25 03:45:06 PM UTC 24 |
| Finished | Aug 25 03:52:22 PM UTC 24 |
| Peak memory | 624328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755839933 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3755839933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1054176327 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 27296881 ps |
| CPU time | 13.03 seconds |
| Started | Aug 25 03:45:43 PM UTC 24 |
| Finished | Aug 25 03:45:57 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054176327 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1054176327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3844345387 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 662419776 ps |
| CPU time | 34.65 seconds |
| Started | Aug 25 03:46:06 PM UTC 24 |
| Finished | Aug 25 03:46:43 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844345387 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3844345387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.3360385111 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 1376401169 ps |
| CPU time | 63.8 seconds |
| Started | Aug 25 03:45:55 PM UTC 24 |
| Finished | Aug 25 03:47:00 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360385111 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3360385111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1876887974 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 102903920 ps |
| CPU time | 19.4 seconds |
| Started | Aug 25 03:45:29 PM UTC 24 |
| Finished | Aug 25 03:45:50 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876887974 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1876887974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.143229880 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 53597040944 ps |
| CPU time | 927.84 seconds |
| Started | Aug 25 03:45:35 PM UTC 24 |
| Finished | Aug 25 04:01:16 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143229880 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.143229880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.504989532 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 49195861018 ps |
| CPU time | 1025.65 seconds |
| Started | Aug 25 03:45:43 PM UTC 24 |
| Finished | Aug 25 04:03:02 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504989532 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.504989532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.442543068 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 231955779 ps |
| CPU time | 30.31 seconds |
| Started | Aug 25 03:45:31 PM UTC 24 |
| Finished | Aug 25 03:46:03 PM UTC 24 |
| Peak memory | 599280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442543068 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.442543068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2828172460 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1488765038 ps |
| CPU time | 68.88 seconds |
| Started | Aug 25 03:45:52 PM UTC 24 |
| Finished | Aug 25 03:47:03 PM UTC 24 |
| Peak memory | 599232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828172460 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2828172460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.4229713534 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 176643269 ps |
| CPU time | 10.74 seconds |
| Started | Aug 25 03:45:16 PM UTC 24 |
| Finished | Aug 25 03:45:28 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229713534 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4229713534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2811363400 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 9021385251 ps |
| CPU time | 167.25 seconds |
| Started | Aug 25 03:45:27 PM UTC 24 |
| Finished | Aug 25 03:48:18 PM UTC 24 |
| Peak memory | 597380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811363400 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2811363400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2581386901 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4781164078 ps |
| CPU time | 100.29 seconds |
| Started | Aug 25 03:45:27 PM UTC 24 |
| Finished | Aug 25 03:47:10 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581386901 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2581386901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2118779120 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 40753618 ps |
| CPU time | 9.27 seconds |
| Started | Aug 25 03:45:21 PM UTC 24 |
| Finished | Aug 25 03:45:31 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118779120 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2118779120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2719274567 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 12978080837 ps |
| CPU time | 753.14 seconds |
| Started | Aug 25 03:46:07 PM UTC 24 |
| Finished | Aug 25 03:58:53 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719274567 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2719274567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.800479630 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1876842288 ps |
| CPU time | 180.79 seconds |
| Started | Aug 25 03:46:15 PM UTC 24 |
| Finished | Aug 25 03:49:20 PM UTC 24 |
| Peak memory | 599236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800479630 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.800479630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3895762697 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 490643912 ps |
| CPU time | 382.52 seconds |
| Started | Aug 25 03:46:14 PM UTC 24 |
| Finished | Aug 25 03:52:43 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895762697 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.3895762697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1883078032 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2886511074 ps |
| CPU time | 436.49 seconds |
| Started | Aug 25 03:46:16 PM UTC 24 |
| Finished | Aug 25 03:53:40 PM UTC 24 |
| Peak memory | 599128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883078032 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.1883078032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.564765764 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 889893367 ps |
| CPU time | 52.3 seconds |
| Started | Aug 25 03:46:05 PM UTC 24 |
| Finished | Aug 25 03:46:59 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564765764 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.564765764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.3714841107 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 2127001176 ps |
| CPU time | 137 seconds |
| Started | Aug 25 05:46:09 PM UTC 24 |
| Finished | Aug 25 05:48:29 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714841107 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.3714841107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.525574511 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 59336927342 ps |
| CPU time | 1139.48 seconds |
| Started | Aug 25 05:46:12 PM UTC 24 |
| Finished | Aug 25 06:05:29 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525574511 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device_slow_rsp.525574511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1111903449 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 167119865 ps |
| CPU time | 24.33 seconds |
| Started | Aug 25 05:46:32 PM UTC 24 |
| Finished | Aug 25 05:46:57 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111903449 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_addr.1111903449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.315614095 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 1873951690 ps |
| CPU time | 74.08 seconds |
| Started | Aug 25 05:46:10 PM UTC 24 |
| Finished | Aug 25 05:47:26 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315614095 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.315614095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1323990776 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 2336902368 ps |
| CPU time | 141 seconds |
| Started | Aug 25 05:46:01 PM UTC 24 |
| Finished | Aug 25 05:48:25 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323990776 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1323990776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_large_delays.52509920 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 77023893942 ps |
| CPU time | 994.9 seconds |
| Started | Aug 25 05:46:09 PM UTC 24 |
| Finished | Aug 25 06:02:58 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52509920 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.52509920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_slow_rsp.2021595881 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 58157185489 ps |
| CPU time | 1161.88 seconds |
| Started | Aug 25 05:46:08 PM UTC 24 |
| Finished | Aug 25 06:05:47 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021595881 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2021595881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1649075098 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 87339014 ps |
| CPU time | 17.08 seconds |
| Started | Aug 25 05:46:05 PM UTC 24 |
| Finished | Aug 25 05:46:23 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649075098 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_delays.1649075098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.943275609 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 226839369 ps |
| CPU time | 15.58 seconds |
| Started | Aug 25 05:46:14 PM UTC 24 |
| Finished | Aug 25 05:46:31 PM UTC 24 |
| Peak memory | 597256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943275609 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.943275609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1808262727 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 172120450 ps |
| CPU time | 12.43 seconds |
| Started | Aug 25 05:45:36 PM UTC 24 |
| Finished | Aug 25 05:45:50 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808262727 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1808262727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.282375261 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 5337044785 ps |
| CPU time | 85.26 seconds |
| Started | Aug 25 05:45:45 PM UTC 24 |
| Finished | Aug 25 05:47:12 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282375261 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.282375261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2398582490 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 6400842315 ps |
| CPU time | 148.87 seconds |
| Started | Aug 25 05:45:48 PM UTC 24 |
| Finished | Aug 25 05:48:20 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398582490 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2398582490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1008136296 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 46073223 ps |
| CPU time | 10.08 seconds |
| Started | Aug 25 05:45:37 PM UTC 24 |
| Finished | Aug 25 05:45:49 PM UTC 24 |
| Peak memory | 597152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008136296 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays.1008136296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all.2001620313 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 17266221972 ps |
| CPU time | 823.44 seconds |
| Started | Aug 25 05:46:32 PM UTC 24 |
| Finished | Aug 25 06:00:29 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001620313 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2001620313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_error.2240240285 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 7997753976 ps |
| CPU time | 334.92 seconds |
| Started | Aug 25 05:46:41 PM UTC 24 |
| Finished | Aug 25 05:52:22 PM UTC 24 |
| Peak memory | 599384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240240285 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2240240285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2757999241 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 311039555 ps |
| CPU time | 210.94 seconds |
| Started | Aug 25 05:46:35 PM UTC 24 |
| Finished | Aug 25 05:50:11 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757999241 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_rand_reset.2757999241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2550241857 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 276593628 ps |
| CPU time | 138.82 seconds |
| Started | Aug 25 05:46:41 PM UTC 24 |
| Finished | Aug 25 05:49:03 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550241857 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_reset_error.2550241857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2361177197 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 514474133 ps |
| CPU time | 37.19 seconds |
| Started | Aug 25 05:46:14 PM UTC 24 |
| Finished | Aug 25 05:46:52 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361177197 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2361177197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2719705188 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 2006958808 ps |
| CPU time | 105.57 seconds |
| Started | Aug 25 05:47:20 PM UTC 24 |
| Finished | Aug 25 05:49:08 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719705188 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.2719705188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4155027883 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 32365388068 ps |
| CPU time | 686.66 seconds |
| Started | Aug 25 05:47:21 PM UTC 24 |
| Finished | Aug 25 05:58:58 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155027883 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device_slow_rsp.4155027883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2577668816 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 465933022 ps |
| CPU time | 25.76 seconds |
| Started | Aug 25 05:47:31 PM UTC 24 |
| Finished | Aug 25 05:47:58 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577668816 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr.2577668816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3658561248 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 842719753 ps |
| CPU time | 39.59 seconds |
| Started | Aug 25 05:47:22 PM UTC 24 |
| Finished | Aug 25 05:48:03 PM UTC 24 |
| Peak memory | 599428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658561248 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3658561248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2277218962 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 23345925 ps |
| CPU time | 8.99 seconds |
| Started | Aug 25 05:46:57 PM UTC 24 |
| Finished | Aug 25 05:47:07 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277218962 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2277218962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_large_delays.3662171368 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 23223473398 ps |
| CPU time | 396.39 seconds |
| Started | Aug 25 05:47:11 PM UTC 24 |
| Finished | Aug 25 05:53:54 PM UTC 24 |
| Peak memory | 599672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662171368 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3662171368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.3486052841 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 12201713588 ps |
| CPU time | 286.74 seconds |
| Started | Aug 25 05:47:17 PM UTC 24 |
| Finished | Aug 25 05:52:08 PM UTC 24 |
| Peak memory | 599184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486052841 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3486052841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1234010292 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 161486261 ps |
| CPU time | 21.57 seconds |
| Started | Aug 25 05:47:00 PM UTC 24 |
| Finished | Aug 25 05:47:23 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234010292 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delays.1234010292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1208487805 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 445034239 ps |
| CPU time | 24.65 seconds |
| Started | Aug 25 05:47:22 PM UTC 24 |
| Finished | Aug 25 05:47:48 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208487805 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1208487805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1806465902 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 41785753 ps |
| CPU time | 10.13 seconds |
| Started | Aug 25 05:46:46 PM UTC 24 |
| Finished | Aug 25 05:46:58 PM UTC 24 |
| Peak memory | 597312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806465902 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1806465902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.4036373375 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 5403715113 ps |
| CPU time | 102.3 seconds |
| Started | Aug 25 05:46:48 PM UTC 24 |
| Finished | Aug 25 05:48:33 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036373375 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.4036373375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1616524959 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 5752961102 ps |
| CPU time | 141.94 seconds |
| Started | Aug 25 05:46:55 PM UTC 24 |
| Finished | Aug 25 05:49:21 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616524959 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1616524959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2901820884 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 57873467 ps |
| CPU time | 9.6 seconds |
| Started | Aug 25 05:46:46 PM UTC 24 |
| Finished | Aug 25 05:46:56 PM UTC 24 |
| Peak memory | 597444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901820884 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays.2901820884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all.690954871 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 5170039633 ps |
| CPU time | 658.31 seconds |
| Started | Aug 25 05:47:36 PM UTC 24 |
| Finished | Aug 25 05:58:47 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690954871 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.690954871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_error.2380783231 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 8907231521 ps |
| CPU time | 488.49 seconds |
| Started | Aug 25 05:47:50 PM UTC 24 |
| Finished | Aug 25 05:56:07 PM UTC 24 |
| Peak memory | 599400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380783231 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.2380783231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3498979902 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 8361642 ps |
| CPU time | 7.05 seconds |
| Started | Aug 25 05:47:46 PM UTC 24 |
| Finished | Aug 25 05:47:54 PM UTC 24 |
| Peak memory | 596208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498979902 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_rand_reset.3498979902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1500483642 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 158773629 ps |
| CPU time | 27.18 seconds |
| Started | Aug 25 05:47:26 PM UTC 24 |
| Finished | Aug 25 05:47:55 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500483642 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1500483642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.774708388 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 214101861 ps |
| CPU time | 33.25 seconds |
| Started | Aug 25 05:48:34 PM UTC 24 |
| Finished | Aug 25 05:49:09 PM UTC 24 |
| Peak memory | 599512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774708388 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device.774708388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3423229360 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 24184303616 ps |
| CPU time | 609.72 seconds |
| Started | Aug 25 05:48:34 PM UTC 24 |
| Finished | Aug 25 05:58:55 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423229360 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device_slow_rsp.3423229360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.371244924 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 922571784 ps |
| CPU time | 47.17 seconds |
| Started | Aug 25 05:48:40 PM UTC 24 |
| Finished | Aug 25 05:49:29 PM UTC 24 |
| Peak memory | 599452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371244924 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.371244924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.459075321 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 544250649 ps |
| CPU time | 29.83 seconds |
| Started | Aug 25 05:48:39 PM UTC 24 |
| Finished | Aug 25 05:49:10 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459075321 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.459075321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.4058368801 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 253560730 ps |
| CPU time | 33.7 seconds |
| Started | Aug 25 05:48:20 PM UTC 24 |
| Finished | Aug 25 05:48:55 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058368801 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.4058368801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_large_delays.103700914 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 22117907714 ps |
| CPU time | 375.44 seconds |
| Started | Aug 25 05:48:21 PM UTC 24 |
| Finished | Aug 25 05:54:43 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103700914 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.103700914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_slow_rsp.2603428738 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 14931341627 ps |
| CPU time | 373.09 seconds |
| Started | Aug 25 05:48:24 PM UTC 24 |
| Finished | Aug 25 05:54:44 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603428738 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2603428738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3469725920 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 432858912 ps |
| CPU time | 61.52 seconds |
| Started | Aug 25 05:48:20 PM UTC 24 |
| Finished | Aug 25 05:49:23 PM UTC 24 |
| Peak memory | 599204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469725920 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_delays.3469725920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.3303277979 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 713117756 ps |
| CPU time | 36.62 seconds |
| Started | Aug 25 05:48:37 PM UTC 24 |
| Finished | Aug 25 05:49:16 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303277979 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3303277979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.929967837 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 272530022 ps |
| CPU time | 17.53 seconds |
| Started | Aug 25 05:47:57 PM UTC 24 |
| Finished | Aug 25 05:48:16 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929967837 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.929967837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2069739335 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 10190606754 ps |
| CPU time | 154.67 seconds |
| Started | Aug 25 05:48:11 PM UTC 24 |
| Finished | Aug 25 05:50:49 PM UTC 24 |
| Peak memory | 597320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069739335 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2069739335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3455339286 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 4805630874 ps |
| CPU time | 124.1 seconds |
| Started | Aug 25 05:48:18 PM UTC 24 |
| Finished | Aug 25 05:50:25 PM UTC 24 |
| Peak memory | 597276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455339286 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3455339286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1347309052 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 50949146 ps |
| CPU time | 10.89 seconds |
| Started | Aug 25 05:48:01 PM UTC 24 |
| Finished | Aug 25 05:48:13 PM UTC 24 |
| Peak memory | 597420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347309052 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays.1347309052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all.1963557611 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 11053314784 ps |
| CPU time | 494.9 seconds |
| Started | Aug 25 05:48:48 PM UTC 24 |
| Finished | Aug 25 05:57:11 PM UTC 24 |
| Peak memory | 599532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963557611 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1963557611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_error.3673668622 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 2949286962 ps |
| CPU time | 254.53 seconds |
| Started | Aug 25 05:48:55 PM UTC 24 |
| Finished | Aug 25 05:53:14 PM UTC 24 |
| Peak memory | 599284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673668622 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.3673668622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1919985696 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 3547683932 ps |
| CPU time | 324.6 seconds |
| Started | Aug 25 05:48:52 PM UTC 24 |
| Finished | Aug 25 05:54:22 PM UTC 24 |
| Peak memory | 599296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919985696 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_rand_reset.1919985696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.355692213 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 4362153519 ps |
| CPU time | 591.84 seconds |
| Started | Aug 25 05:49:10 PM UTC 24 |
| Finished | Aug 25 05:59:12 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355692213 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_reset_error.355692213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.904476881 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 272600982 ps |
| CPU time | 18.14 seconds |
| Started | Aug 25 05:48:39 PM UTC 24 |
| Finished | Aug 25 05:48:59 PM UTC 24 |
| Peak memory | 599048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904476881 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.904476881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1184851501 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 1648858513 ps |
| CPU time | 79.41 seconds |
| Started | Aug 25 05:49:40 PM UTC 24 |
| Finished | Aug 25 05:51:02 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184851501 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device.1184851501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3618286858 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 10916627075 ps |
| CPU time | 237.6 seconds |
| Started | Aug 25 05:49:44 PM UTC 24 |
| Finished | Aug 25 05:53:45 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618286858 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device_slow_rsp.3618286858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1056274703 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 488780548 ps |
| CPU time | 27.32 seconds |
| Started | Aug 25 05:49:52 PM UTC 24 |
| Finished | Aug 25 05:50:20 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056274703 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr.1056274703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.2606038971 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 2442150718 ps |
| CPU time | 128.16 seconds |
| Started | Aug 25 05:49:48 PM UTC 24 |
| Finished | Aug 25 05:51:59 PM UTC 24 |
| Peak memory | 599272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606038971 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2606038971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.2926923659 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 231897684 ps |
| CPU time | 14.84 seconds |
| Started | Aug 25 05:49:31 PM UTC 24 |
| Finished | Aug 25 05:49:47 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926923659 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2926923659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_large_delays.2055934497 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 22101535717 ps |
| CPU time | 389.79 seconds |
| Started | Aug 25 05:49:35 PM UTC 24 |
| Finished | Aug 25 05:56:11 PM UTC 24 |
| Peak memory | 599412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055934497 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2055934497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_slow_rsp.2323019903 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 56973208333 ps |
| CPU time | 1077.52 seconds |
| Started | Aug 25 05:49:37 PM UTC 24 |
| Finished | Aug 25 06:07:51 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323019903 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2323019903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1540770800 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 299676240 ps |
| CPU time | 42.45 seconds |
| Started | Aug 25 05:49:34 PM UTC 24 |
| Finished | Aug 25 05:50:18 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540770800 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_delays.1540770800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.3728366912 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 1156704429 ps |
| CPU time | 57 seconds |
| Started | Aug 25 05:49:46 PM UTC 24 |
| Finished | Aug 25 05:50:45 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728366912 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3728366912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2633975036 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 45324509 ps |
| CPU time | 10.27 seconds |
| Started | Aug 25 05:49:15 PM UTC 24 |
| Finished | Aug 25 05:49:27 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633975036 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.2633975036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.3762578878 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 6928035891 ps |
| CPU time | 116.64 seconds |
| Started | Aug 25 05:49:19 PM UTC 24 |
| Finished | Aug 25 05:51:18 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762578878 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3762578878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1690001738 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 5743366378 ps |
| CPU time | 133.14 seconds |
| Started | Aug 25 05:49:28 PM UTC 24 |
| Finished | Aug 25 05:51:44 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690001738 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1690001738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2838110138 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 48727280 ps |
| CPU time | 8.73 seconds |
| Started | Aug 25 05:49:19 PM UTC 24 |
| Finished | Aug 25 05:49:29 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838110138 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays.2838110138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.2218064227 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 963584779 ps |
| CPU time | 122.21 seconds |
| Started | Aug 25 05:49:52 PM UTC 24 |
| Finished | Aug 25 05:51:57 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218064227 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2218064227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4273208803 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 526927788 ps |
| CPU time | 64.6 seconds |
| Started | Aug 25 05:50:00 PM UTC 24 |
| Finished | Aug 25 05:51:06 PM UTC 24 |
| Peak memory | 599268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273208803 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.4273208803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1511218555 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 314774726 ps |
| CPU time | 199.29 seconds |
| Started | Aug 25 05:49:52 PM UTC 24 |
| Finished | Aug 25 05:53:15 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511218555 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_rand_reset.1511218555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2535309826 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 110777383 ps |
| CPU time | 30.85 seconds |
| Started | Aug 25 05:50:11 PM UTC 24 |
| Finished | Aug 25 05:50:43 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535309826 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_reset_error.2535309826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.1435874824 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 1266431333 ps |
| CPU time | 84.05 seconds |
| Started | Aug 25 05:49:49 PM UTC 24 |
| Finished | Aug 25 05:51:15 PM UTC 24 |
| Peak memory | 599140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435874824 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1435874824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device.2187836745 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 2312878764 ps |
| CPU time | 132.83 seconds |
| Started | Aug 25 05:50:45 PM UTC 24 |
| Finished | Aug 25 05:53:01 PM UTC 24 |
| Peak memory | 599124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187836745 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.2187836745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1814437512 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 94355286100 ps |
| CPU time | 1738.55 seconds |
| Started | Aug 25 05:50:51 PM UTC 24 |
| Finished | Aug 25 06:20:16 PM UTC 24 |
| Peak memory | 600164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814437512 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device_slow_rsp.1814437512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.4220190800 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 25037683 ps |
| CPU time | 7.95 seconds |
| Started | Aug 25 05:51:09 PM UTC 24 |
| Finished | Aug 25 05:51:18 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220190800 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.4220190800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.344224642 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 427124784 ps |
| CPU time | 51.83 seconds |
| Started | Aug 25 05:51:00 PM UTC 24 |
| Finished | Aug 25 05:51:53 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344224642 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.344224642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.3280802217 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 260253009 ps |
| CPU time | 39.3 seconds |
| Started | Aug 25 05:50:36 PM UTC 24 |
| Finished | Aug 25 05:51:16 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280802217 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3280802217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_large_delays.2145452865 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 35020075652 ps |
| CPU time | 479.39 seconds |
| Started | Aug 25 05:50:45 PM UTC 24 |
| Finished | Aug 25 05:58:52 PM UTC 24 |
| Peak memory | 599412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145452865 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.2145452865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_slow_rsp.3269492782 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 20472172502 ps |
| CPU time | 450.88 seconds |
| Started | Aug 25 05:50:47 PM UTC 24 |
| Finished | Aug 25 05:58:26 PM UTC 24 |
| Peak memory | 599632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269492782 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3269492782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.1390041541 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 460633113 ps |
| CPU time | 59.26 seconds |
| Started | Aug 25 05:50:43 PM UTC 24 |
| Finished | Aug 25 05:51:44 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390041541 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_delays.1390041541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.417796282 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 348602110 ps |
| CPU time | 41.86 seconds |
| Started | Aug 25 05:50:50 PM UTC 24 |
| Finished | Aug 25 05:51:33 PM UTC 24 |
| Peak memory | 599196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417796282 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.417796282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.524675633 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 153902697 ps |
| CPU time | 12.43 seconds |
| Started | Aug 25 05:50:12 PM UTC 24 |
| Finished | Aug 25 05:50:25 PM UTC 24 |
| Peak memory | 597336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524675633 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.524675633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_large_delays.3451747899 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 8310558640 ps |
| CPU time | 141.78 seconds |
| Started | Aug 25 05:50:26 PM UTC 24 |
| Finished | Aug 25 05:52:51 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451747899 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3451747899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.47099753 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 5494557906 ps |
| CPU time | 125.85 seconds |
| Started | Aug 25 05:50:32 PM UTC 24 |
| Finished | Aug 25 05:52:40 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47099753 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.47099753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.469882835 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 37381435 ps |
| CPU time | 9.59 seconds |
| Started | Aug 25 05:50:26 PM UTC 24 |
| Finished | Aug 25 05:50:37 PM UTC 24 |
| Peak memory | 597008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469882835 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays.469882835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all.309820826 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 14784332278 ps |
| CPU time | 615.77 seconds |
| Started | Aug 25 05:51:12 PM UTC 24 |
| Finished | Aug 25 06:01:38 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309820826 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.309820826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_error.3329644457 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 10003334490 ps |
| CPU time | 520.31 seconds |
| Started | Aug 25 05:51:22 PM UTC 24 |
| Finished | Aug 25 06:00:12 PM UTC 24 |
| Peak memory | 599440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329644457 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3329644457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3504126955 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 69496141 ps |
| CPU time | 46.79 seconds |
| Started | Aug 25 05:51:15 PM UTC 24 |
| Finished | Aug 25 05:52:03 PM UTC 24 |
| Peak memory | 597252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504126955 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_rand_reset.3504126955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2571407590 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 798822600 ps |
| CPU time | 455.65 seconds |
| Started | Aug 25 05:51:24 PM UTC 24 |
| Finished | Aug 25 05:59:09 PM UTC 24 |
| Peak memory | 599260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571407590 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_reset_error.2571407590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1723558838 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 227860028 ps |
| CPU time | 18.91 seconds |
| Started | Aug 25 05:51:08 PM UTC 24 |
| Finished | Aug 25 05:51:29 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723558838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1723558838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device.1960730695 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 3213639575 ps |
| CPU time | 193.52 seconds |
| Started | Aug 25 05:51:58 PM UTC 24 |
| Finished | Aug 25 05:55:15 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960730695 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.1960730695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1805465571 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 111668015285 ps |
| CPU time | 2342.05 seconds |
| Started | Aug 25 05:52:03 PM UTC 24 |
| Finished | Aug 25 06:31:43 PM UTC 24 |
| Peak memory | 600028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805465571 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device_slow_rsp.1805465571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2350800449 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 848878392 ps |
| CPU time | 45.64 seconds |
| Started | Aug 25 05:52:19 PM UTC 24 |
| Finished | Aug 25 05:53:06 PM UTC 24 |
| Peak memory | 599464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350800449 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.2350800449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_error_random.1938122737 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 1086788129 ps |
| CPU time | 50.89 seconds |
| Started | Aug 25 05:52:10 PM UTC 24 |
| Finished | Aug 25 05:53:02 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938122737 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1938122737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random.3317887409 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1448147594 ps |
| CPU time | 74.62 seconds |
| Started | Aug 25 05:51:41 PM UTC 24 |
| Finished | Aug 25 05:52:58 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317887409 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3317887409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_large_delays.686830460 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 5552359507 ps |
| CPU time | 97.36 seconds |
| Started | Aug 25 05:51:44 PM UTC 24 |
| Finished | Aug 25 05:53:24 PM UTC 24 |
| Peak memory | 597324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686830460 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.686830460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_slow_rsp.3528308449 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 48258321765 ps |
| CPU time | 827.98 seconds |
| Started | Aug 25 05:51:54 PM UTC 24 |
| Finished | Aug 25 06:05:53 PM UTC 24 |
| Peak memory | 599636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528308449 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3528308449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_random_zero_delays.3031594807 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 547477542 ps |
| CPU time | 77.02 seconds |
| Started | Aug 25 05:51:43 PM UTC 24 |
| Finished | Aug 25 05:53:03 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031594807 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delays.3031594807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_same_source.905478612 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 236358972 ps |
| CPU time | 26.56 seconds |
| Started | Aug 25 05:52:07 PM UTC 24 |
| Finished | Aug 25 05:52:35 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905478612 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.905478612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.952342535 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 130942608 ps |
| CPU time | 12.27 seconds |
| Started | Aug 25 05:51:26 PM UTC 24 |
| Finished | Aug 25 05:51:40 PM UTC 24 |
| Peak memory | 597232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952342535 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.952342535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_large_delays.4090915717 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 7909753465 ps |
| CPU time | 127.73 seconds |
| Started | Aug 25 05:51:31 PM UTC 24 |
| Finished | Aug 25 05:53:41 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090915717 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.4090915717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2307305755 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 5471345185 ps |
| CPU time | 137.59 seconds |
| Started | Aug 25 05:51:37 PM UTC 24 |
| Finished | Aug 25 05:53:58 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307305755 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2307305755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3290645449 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 47672189 ps |
| CPU time | 10.18 seconds |
| Started | Aug 25 05:51:32 PM UTC 24 |
| Finished | Aug 25 05:51:43 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290645449 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays.3290645449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all.213720636 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 5340254532 ps |
| CPU time | 299.38 seconds |
| Started | Aug 25 05:52:20 PM UTC 24 |
| Finished | Aug 25 05:57:25 PM UTC 24 |
| Peak memory | 599424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213720636 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.213720636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_error.3297565179 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 1423490815 ps |
| CPU time | 176.58 seconds |
| Started | Aug 25 05:52:24 PM UTC 24 |
| Finished | Aug 25 05:55:25 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297565179 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3297565179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2715269859 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 289261433 ps |
| CPU time | 156.81 seconds |
| Started | Aug 25 05:52:23 PM UTC 24 |
| Finished | Aug 25 05:55:03 PM UTC 24 |
| Peak memory | 599264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715269859 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_rand_reset.2715269859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3573954765 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 253542773 ps |
| CPU time | 145.73 seconds |
| Started | Aug 25 05:52:27 PM UTC 24 |
| Finished | Aug 25 05:54:56 PM UTC 24 |
| Peak memory | 599144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573954765 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_reset_error.3573954765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_unmapped_addr.1094647814 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 217495173 ps |
| CPU time | 43.83 seconds |
| Started | Aug 25 05:52:07 PM UTC 24 |
| Finished | Aug 25 05:52:52 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094647814 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1094647814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device.2920792750 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1016072649 ps |
| CPU time | 83.27 seconds |
| Started | Aug 25 05:53:14 PM UTC 24 |
| Finished | Aug 25 05:54:39 PM UTC 24 |
| Peak memory | 599252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920792750 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.2920792750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2818021825 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 3005282545 ps |
| CPU time | 71.93 seconds |
| Started | Aug 25 05:53:13 PM UTC 24 |
| Finished | Aug 25 05:54:27 PM UTC 24 |
| Peak memory | 597272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818021825 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device_slow_rsp.2818021825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1198853679 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 1365341348 ps |
| CPU time | 65.19 seconds |
| Started | Aug 25 05:53:26 PM UTC 24 |
| Finished | Aug 25 05:54:33 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198853679 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr.1198853679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_error_random.3164694182 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 462991040 ps |
| CPU time | 45.03 seconds |
| Started | Aug 25 05:53:22 PM UTC 24 |
| Finished | Aug 25 05:54:09 PM UTC 24 |
| Peak memory | 599572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164694182 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3164694182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random.776387640 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 1166055680 ps |
| CPU time | 56.37 seconds |
| Started | Aug 25 05:52:46 PM UTC 24 |
| Finished | Aug 25 05:53:44 PM UTC 24 |
| Peak memory | 599056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776387640 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.776387640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_large_delays.2532823713 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 50170991435 ps |
| CPU time | 637.48 seconds |
| Started | Aug 25 05:53:04 PM UTC 24 |
| Finished | Aug 25 06:03:51 PM UTC 24 |
| Peak memory | 599380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532823713 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2532823713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_slow_rsp.1489763916 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 46387112044 ps |
| CPU time | 851.1 seconds |
| Started | Aug 25 05:53:10 PM UTC 24 |
| Finished | Aug 25 06:07:34 PM UTC 24 |
| Peak memory | 599496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489763916 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1489763916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_random_zero_delays.2106271835 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 331847669 ps |
| CPU time | 45.95 seconds |
| Started | Aug 25 05:52:59 PM UTC 24 |
| Finished | Aug 25 05:53:47 PM UTC 24 |
| Peak memory | 599304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106271835 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_delays.2106271835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_same_source.691825065 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 2008965343 ps |
| CPU time | 96.4 seconds |
| Started | Aug 25 05:53:16 PM UTC 24 |
| Finished | Aug 25 05:54:56 PM UTC 24 |
| Peak memory | 599300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691825065 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.691825065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke.882465553 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 225484215 ps |
| CPU time | 14 seconds |
| Started | Aug 25 05:52:34 PM UTC 24 |
| Finished | Aug 25 05:52:50 PM UTC 24 |
| Peak memory | 597140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882465553 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.882465553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_large_delays.2946448984 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 6885153703 ps |
| CPU time | 104.39 seconds |
| Started | Aug 25 05:52:44 PM UTC 24 |
| Finished | Aug 25 05:54:31 PM UTC 24 |
| Peak memory | 597564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946448984 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2946448984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1702091336 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 4890213863 ps |
| CPU time | 132.96 seconds |
| Started | Aug 25 05:52:45 PM UTC 24 |
| Finished | Aug 25 05:55:01 PM UTC 24 |
| Peak memory | 597132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702091336 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.1702091336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2928745594 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 48915850 ps |
| CPU time | 10.47 seconds |
| Started | Aug 25 05:52:34 PM UTC 24 |
| Finished | Aug 25 05:52:46 PM UTC 24 |
| Peak memory | 597068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928745594 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays.2928745594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all.3368488061 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 9213238706 ps |
| CPU time | 491.29 seconds |
| Started | Aug 25 05:53:26 PM UTC 24 |
| Finished | Aug 25 06:01:48 PM UTC 24 |
| Peak memory | 598948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368488061 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3368488061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_error.1033200575 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 1854049247 ps |
| CPU time | 205.78 seconds |
| Started | Aug 25 05:53:34 PM UTC 24 |
| Finished | Aug 25 05:57:04 PM UTC 24 |
| Peak memory | 599308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033200575 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.1033200575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2322774498 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 8638997497 ps |
| CPU time | 586.66 seconds |
| Started | Aug 25 05:53:30 PM UTC 24 |
| Finished | Aug 25 06:03:25 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322774498 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_rand_reset.2322774498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2897281236 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 13805127456 ps |
| CPU time | 658.36 seconds |
| Started | Aug 25 05:53:38 PM UTC 24 |
| Finished | Aug 25 06:04:46 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897281236 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_reset_error.2897281236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_unmapped_addr.2471929512 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 275829087 ps |
| CPU time | 23.77 seconds |
| Started | Aug 25 05:53:26 PM UTC 24 |
| Finished | Aug 25 05:53:51 PM UTC 24 |
| Peak memory | 599200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471929512 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2471929512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device.1781804816 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 2714292090 ps |
| CPU time | 153.65 seconds |
| Started | Aug 25 05:54:09 PM UTC 24 |
| Finished | Aug 25 05:56:46 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781804816 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.1781804816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3287076458 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 46717587320 ps |
| CPU time | 814.68 seconds |
| Started | Aug 25 05:54:10 PM UTC 24 |
| Finished | Aug 25 06:07:56 PM UTC 24 |
| Peak memory | 599448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287076458 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device_slow_rsp.3287076458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1089209594 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 201187584 ps |
| CPU time | 13.96 seconds |
| Started | Aug 25 05:54:15 PM UTC 24 |
| Finished | Aug 25 05:54:30 PM UTC 24 |
| Peak memory | 599288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089209594 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr.1089209594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_error_random.1861501602 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 1619771615 ps |
| CPU time | 70.73 seconds |
| Started | Aug 25 05:54:11 PM UTC 24 |
| Finished | Aug 25 05:55:23 PM UTC 24 |
| Peak memory | 598888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861501602 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1861501602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random.3505475896 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 560210396 ps |
| CPU time | 74.69 seconds |
| Started | Aug 25 05:53:48 PM UTC 24 |
| Finished | Aug 25 05:55:05 PM UTC 24 |
| Peak memory | 599212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505475896 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3505475896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_large_delays.3932410264 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 56577731891 ps |
| CPU time | 633.34 seconds |
| Started | Aug 25 05:54:08 PM UTC 24 |
| Finished | Aug 25 06:04:50 PM UTC 24 |
| Peak memory | 599188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932410264 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3932410264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_slow_rsp.3634009642 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 24453564213 ps |
| CPU time | 486.7 seconds |
| Started | Aug 25 05:54:09 PM UTC 24 |
| Finished | Aug 25 06:02:25 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634009642 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.3634009642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.3593703498 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 539040057 ps |
| CPU time | 67.37 seconds |
| Started | Aug 25 05:54:06 PM UTC 24 |
| Finished | Aug 25 05:55:15 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593703498 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_delays.3593703498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_same_source.1001729338 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 545437006 ps |
| CPU time | 49.84 seconds |
| Started | Aug 25 05:54:11 PM UTC 24 |
| Finished | Aug 25 05:55:02 PM UTC 24 |
| Peak memory | 598524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001729338 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1001729338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke.147193253 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 204365423 ps |
| CPU time | 10.75 seconds |
| Started | Aug 25 05:53:39 PM UTC 24 |
| Finished | Aug 25 05:53:51 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147193253 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.147193253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_large_delays.3678105457 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 9175828513 ps |
| CPU time | 136.28 seconds |
| Started | Aug 25 05:53:45 PM UTC 24 |
| Finished | Aug 25 05:56:04 PM UTC 24 |
| Peak memory | 597128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678105457 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3678105457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.881559262 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 4554447955 ps |
| CPU time | 119.97 seconds |
| Started | Aug 25 05:53:49 PM UTC 24 |
| Finished | Aug 25 05:55:52 PM UTC 24 |
| Peak memory | 597352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881559262 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.881559262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2650066645 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 50356664 ps |
| CPU time | 9.46 seconds |
| Started | Aug 25 05:53:41 PM UTC 24 |
| Finished | Aug 25 05:53:51 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650066645 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays.2650066645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all.3851349305 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 1650945730 ps |
| CPU time | 152.88 seconds |
| Started | Aug 25 05:54:16 PM UTC 24 |
| Finished | Aug 25 05:56:52 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851349305 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3851349305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_error.2273351054 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 11493461988 ps |
| CPU time | 432.25 seconds |
| Started | Aug 25 05:54:22 PM UTC 24 |
| Finished | Aug 25 06:01:42 PM UTC 24 |
| Peak memory | 599628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273351054 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2273351054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.303995603 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 8152286880 ps |
| CPU time | 506.67 seconds |
| Started | Aug 25 05:54:18 PM UTC 24 |
| Finished | Aug 25 06:02:55 PM UTC 24 |
| Peak memory | 599444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303995603 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_rand_reset.303995603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1697089981 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 7720829836 ps |
| CPU time | 421.15 seconds |
| Started | Aug 25 05:54:32 PM UTC 24 |
| Finished | Aug 25 06:01:41 PM UTC 24 |
| Peak memory | 599192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697089981 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_reset_error.1697089981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_unmapped_addr.42026692 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 751939740 ps |
| CPU time | 41.45 seconds |
| Started | Aug 25 05:54:14 PM UTC 24 |
| Finished | Aug 25 05:54:57 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42026692 -assert nopostproc +UVM_TESTNAME= xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.42026692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device.3794950838 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2330415419 ps |
| CPU time | 150.58 seconds |
| Started | Aug 25 05:55:08 PM UTC 24 |
| Finished | Aug 25 05:57:42 PM UTC 24 |
| Peak memory | 599376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794950838 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.3794950838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2886029513 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 143329304977 ps |
| CPU time | 2742.4 seconds |
| Started | Aug 25 05:55:06 PM UTC 24 |
| Finished | Aug 25 06:41:32 PM UTC 24 |
| Peak memory | 600288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886029513 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device_slow_rsp.2886029513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2860609849 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 399735597 ps |
| CPU time | 21.28 seconds |
| Started | Aug 25 05:55:20 PM UTC 24 |
| Finished | Aug 25 05:55:43 PM UTC 24 |
| Peak memory | 599116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860609849 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr.2860609849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_error_random.3873105543 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 25774677 ps |
| CPU time | 7.4 seconds |
| Started | Aug 25 05:55:16 PM UTC 24 |
| Finished | Aug 25 05:55:24 PM UTC 24 |
| Peak memory | 597012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873105543 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3873105543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random.1184594669 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 465575199 ps |
| CPU time | 66.7 seconds |
| Started | Aug 25 05:54:55 PM UTC 24 |
| Finished | Aug 25 05:56:04 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184594669 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1184594669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_large_delays.1403796064 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 112200947265 ps |
| CPU time | 1279.77 seconds |
| Started | Aug 25 05:55:01 PM UTC 24 |
| Finished | Aug 25 06:16:40 PM UTC 24 |
| Peak memory | 599656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403796064 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1403796064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_slow_rsp.575221248 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 5334894679 ps |
| CPU time | 148.85 seconds |
| Started | Aug 25 05:55:05 PM UTC 24 |
| Finished | Aug 25 05:57:38 PM UTC 24 |
| Peak memory | 597372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575221248 -assert nopostproc +UVM_TE STNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.575221248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_random_zero_delays.3252640129 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 516116921 ps |
| CPU time | 52.49 seconds |
| Started | Aug 25 05:54:55 PM UTC 24 |
| Finished | Aug 25 05:55:50 PM UTC 24 |
| Peak memory | 599064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252640129 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delays.3252640129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_same_source.2396916036 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 445511734 ps |
| CPU time | 55.59 seconds |
| Started | Aug 25 05:55:10 PM UTC 24 |
| Finished | Aug 25 05:56:08 PM UTC 24 |
| Peak memory | 599320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396916036 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2396916036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke.921139409 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 42659035 ps |
| CPU time | 9.33 seconds |
| Started | Aug 25 05:54:33 PM UTC 24 |
| Finished | Aug 25 05:54:43 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921139409 -assert nopostproc +UVM_TESTNAME =xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.921139409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_large_delays.583949335 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 11214519297 ps |
| CPU time | 200.55 seconds |
| Started | Aug 25 05:54:51 PM UTC 24 |
| Finished | Aug 25 05:58:16 PM UTC 24 |
| Peak memory | 597384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583949335 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.583949335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2452017640 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 5077740838 ps |
| CPU time | 105.39 seconds |
| Started | Aug 25 05:54:54 PM UTC 24 |
| Finished | Aug 25 05:56:42 PM UTC 24 |
| Peak memory | 597144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452017640 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2452017640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1374033360 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 60564650 ps |
| CPU time | 10.63 seconds |
| Started | Aug 25 05:54:44 PM UTC 24 |
| Finished | Aug 25 05:54:56 PM UTC 24 |
| Peak memory | 597340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374033360 -assert nopostpr oc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays.1374033360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all.3050203337 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 3070413927 ps |
| CPU time | 144.06 seconds |
| Started | Aug 25 05:55:19 PM UTC 24 |
| Finished | Aug 25 05:57:47 PM UTC 24 |
| Peak memory | 599460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050203337 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.3050203337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_error.3648347073 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 2657306160 ps |
| CPU time | 310.45 seconds |
| Started | Aug 25 05:55:23 PM UTC 24 |
| Finished | Aug 25 06:00:41 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648347073 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3648347073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2944806414 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 9226332530 ps |
| CPU time | 607.55 seconds |
| Started | Aug 25 05:55:20 PM UTC 24 |
| Finished | Aug 25 06:05:38 PM UTC 24 |
| Peak memory | 599432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944806414 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_rand_reset.2944806414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.3044573358 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 2219561421 ps |
| CPU time | 412.28 seconds |
| Started | Aug 25 05:55:25 PM UTC 24 |
| Finished | Aug 25 06:02:25 PM UTC 24 |
| Peak memory | 599132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044573358 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_reset_error.3044573358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/98.xbar_unmapped_addr.2635437799 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 388848186 ps |
| CPU time | 28.07 seconds |
| Started | Aug 25 05:55:19 PM UTC 24 |
| Finished | Aug 25 05:55:49 PM UTC 24 |
| Peak memory | 599456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635437799 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2635437799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device.2037395389 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 1934868322 ps |
| CPU time | 108.56 seconds |
| Started | Aug 25 05:55:48 PM UTC 24 |
| Finished | Aug 25 05:57:39 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037395389 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.2037395389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2405561935 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 33358632421 ps |
| CPU time | 538.35 seconds |
| Started | Aug 25 05:56:00 PM UTC 24 |
| Finished | Aug 25 06:05:06 PM UTC 24 |
| Peak memory | 599640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405561935 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device_slow_rsp.2405561935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.374285158 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1057380672 ps |
| CPU time | 66.57 seconds |
| Started | Aug 25 05:56:13 PM UTC 24 |
| Finished | Aug 25 05:57:22 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374285158 -assert nopostproc +UVM_TESTNAME =xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr.374285158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_error_random.2550750443 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 1178395605 ps |
| CPU time | 54.59 seconds |
| Started | Aug 25 05:56:06 PM UTC 24 |
| Finished | Aug 25 05:57:02 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550750443 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2550750443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random.4107359941 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 1709561870 ps |
| CPU time | 77.21 seconds |
| Started | Aug 25 05:55:47 PM UTC 24 |
| Finished | Aug 25 05:57:06 PM UTC 24 |
| Peak memory | 599208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107359941 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.4107359941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_large_delays.411861717 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 34794719499 ps |
| CPU time | 433.05 seconds |
| Started | Aug 25 05:55:49 PM UTC 24 |
| Finished | Aug 25 06:03:09 PM UTC 24 |
| Peak memory | 599588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411861717 -assert nopostproc +UV M_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.411861717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_slow_rsp.2496253506 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 24258296034 ps |
| CPU time | 469.3 seconds |
| Started | Aug 25 05:55:51 PM UTC 24 |
| Finished | Aug 25 06:03:48 PM UTC 24 |
| Peak memory | 599436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496253506 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2496253506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_random_zero_delays.132447254 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 206764367 ps |
| CPU time | 25.6 seconds |
| Started | Aug 25 05:55:48 PM UTC 24 |
| Finished | Aug 25 05:56:15 PM UTC 24 |
| Peak memory | 599072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132447254 -assert nopostpro c +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delays.132447254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_same_source.1280040834 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 1915865014 ps |
| CPU time | 89.5 seconds |
| Started | Aug 25 05:56:03 PM UTC 24 |
| Finished | Aug 25 05:57:35 PM UTC 24 |
| Peak memory | 599312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280040834 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1280040834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke.3947190822 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 42836345 ps |
| CPU time | 8.54 seconds |
| Started | Aug 25 05:55:27 PM UTC 24 |
| Finished | Aug 25 05:55:37 PM UTC 24 |
| Peak memory | 597000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947190822 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3947190822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_large_delays.1269034227 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 9344114794 ps |
| CPU time | 158.6 seconds |
| Started | Aug 25 05:55:39 PM UTC 24 |
| Finished | Aug 25 05:58:21 PM UTC 24 |
| Peak memory | 597576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max _device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269034227 -assert nopostproc +U VM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1269034227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3594367890 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 5931142600 ps |
| CPU time | 132.26 seconds |
| Started | Aug 25 05:55:39 PM UTC 24 |
| Finished | Aug 25 05:57:54 PM UTC 24 |
| Peak memory | 597528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_d evice_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594367890 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3594367890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_smoke_zero_delays.52737101 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 52210299 ps |
| CPU time | 10.59 seconds |
| Started | Aug 25 05:55:30 PM UTC 24 |
| Finished | Aug 25 05:55:41 PM UTC 24 |
| Peak memory | 597004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52737101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.52737101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all.3011110213 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 14079489118 ps |
| CPU time | 502.28 seconds |
| Started | Aug 25 05:56:15 PM UTC 24 |
| Finished | Aug 25 06:04:45 PM UTC 24 |
| Peak memory | 599420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011110213 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3011110213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_error.3789054304 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2441020662 ps |
| CPU time | 207.56 seconds |
| Started | Aug 25 05:56:27 PM UTC 24 |
| Finished | Aug 25 05:59:59 PM UTC 24 |
| Peak memory | 599256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789054304 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3789054304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4014355512 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 649433701 ps |
| CPU time | 363.23 seconds |
| Started | Aug 25 05:56:26 PM UTC 24 |
| Finished | Aug 25 06:02:37 PM UTC 24 |
| Peak memory | 599068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014355512 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_rand_reset.4014355512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.4121936182 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 70928014 ps |
| CPU time | 35.4 seconds |
| Started | Aug 25 05:56:32 PM UTC 24 |
| Finished | Aug 25 05:57:08 PM UTC 24 |
| Peak memory | 599060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121936182 -assert nopostproc +UVM_TESTNAM E=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_reset_error.4121936182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/99.xbar_unmapped_addr.2094101057 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 68157486 ps |
| CPU time | 16.71 seconds |
| Started | Aug 25 05:56:13 PM UTC 24 |
| Finished | Aug 25 05:56:31 PM UTC 24 |
| Peak memory | 599396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094101057 -assert nopostproc +UVM_TESTNAM E=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.2094101057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.2173505798 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 14052536185 ps |
| CPU time | 1614.47 seconds |
| Started | Aug 25 06:35:06 PM UTC 24 |
| Finished | Aug 25 07:02:28 PM UTC 24 |
| Peak memory | 623252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173505798 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2173505798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.3616259083 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4822880660 ps |
| CPU time | 588.84 seconds |
| Started | Aug 25 06:39:00 PM UTC 24 |
| Finished | Aug 25 06:49:02 PM UTC 24 |
| Peak memory | 636080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616259083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3616259083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.2553494860 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3002877588 ps |
| CPU time | 279.35 seconds |
| Started | Aug 25 06:08:22 PM UTC 24 |
| Finished | Aug 25 06:13:06 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553494860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2553494860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3176216841 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2990301632 ps |
| CPU time | 362.53 seconds |
| Started | Aug 25 06:18:43 PM UTC 24 |
| Finished | Aug 25 06:24:53 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176216841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3176216841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.1939566394 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3671591551 ps |
| CPU time | 401.32 seconds |
| Started | Aug 25 06:19:05 PM UTC 24 |
| Finished | Aug 25 06:25:55 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939566394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1939566394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2681193149 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2645725507 ps |
| CPU time | 271.84 seconds |
| Started | Aug 25 06:48:02 PM UTC 24 |
| Finished | Aug 25 06:52:40 PM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681193149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2681193149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.576315242 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3440507328 ps |
| CPU time | 366.86 seconds |
| Started | Aug 25 06:21:42 PM UTC 24 |
| Finished | Aug 25 06:27:56 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576315242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_aes_entropy.576315242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.2087198358 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3595993940 ps |
| CPU time | 381.34 seconds |
| Started | Aug 25 06:19:12 PM UTC 24 |
| Finished | Aug 25 06:25:42 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087198358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2087198358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.1020358399 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2507430854 ps |
| CPU time | 451.15 seconds |
| Started | Aug 25 06:19:21 PM UTC 24 |
| Finished | Aug 25 06:27:02 PM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020358399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_aes_masking_off.1020358399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.544119154 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3414293408 ps |
| CPU time | 345.05 seconds |
| Started | Aug 25 07:00:19 PM UTC 24 |
| Finished | Aug 25 07:06:10 PM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=544119154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ae s_smoketest.544119154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1824136187 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2522990726 ps |
| CPU time | 346.5 seconds |
| Started | Aug 25 06:21:19 PM UTC 24 |
| Finished | Aug 25 06:27:14 PM UTC 24 |
| Peak memory | 623756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824136187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1824136187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.954697475 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5237096152 ps |
| CPU time | 753.08 seconds |
| Started | Aug 25 06:21:08 PM UTC 24 |
| Finished | Aug 25 06:33:56 PM UTC 24 |
| Peak memory | 635964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954697475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_e arlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.954697475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.403891867 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 8157855380 ps |
| CPU time | 2408.36 seconds |
| Started | Aug 25 06:21:28 PM UTC 24 |
| Finished | Aug 25 07:02:18 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403891867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.403891867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1797105208 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 8401626868 ps |
| CPU time | 2013.32 seconds |
| Started | Aug 25 06:19:49 PM UTC 24 |
| Finished | Aug 25 06:54:00 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797105208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.1797105208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1541982472 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4963689318 ps |
| CPU time | 635.68 seconds |
| Started | Aug 25 06:20:13 PM UTC 24 |
| Finished | Aug 25 06:31:00 PM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541982472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1541982472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1720873924 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4346385580 ps |
| CPU time | 458.49 seconds |
| Started | Aug 25 06:15:15 PM UTC 24 |
| Finished | Aug 25 06:23:03 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720873924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1720873924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2122882955 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 8102020720 ps |
| CPU time | 599.84 seconds |
| Started | Aug 25 06:15:36 PM UTC 24 |
| Finished | Aug 25 06:25:48 PM UTC 24 |
| Peak memory | 623860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122882955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2122882955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.483466908 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2605305400 ps |
| CPU time | 338.2 seconds |
| Started | Aug 25 07:01:39 PM UTC 24 |
| Finished | Aug 25 07:07:23 PM UTC 24 |
| Peak memory | 623692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483466908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_aon_timer_smoketest.483466908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1342248665 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 9721044120 ps |
| CPU time | 1038.55 seconds |
| Started | Aug 25 06:15:39 PM UTC 24 |
| Finished | Aug 25 06:33:16 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342248665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1342248665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3706266460 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4898101338 ps |
| CPU time | 709.37 seconds |
| Started | Aug 25 06:16:15 PM UTC 24 |
| Finished | Aug 25 06:28:18 PM UTC 24 |
| Peak memory | 623856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706266460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3706266460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1345839928 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 7815524984 ps |
| CPU time | 1153.1 seconds |
| Started | Aug 25 06:37:04 PM UTC 24 |
| Finished | Aug 25 06:56:39 PM UTC 24 |
| Peak memory | 632012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=1345839928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1345839928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2941006609 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 7652971949 ps |
| CPU time | 681.5 seconds |
| Started | Aug 25 06:33:29 PM UTC 24 |
| Finished | Aug 25 06:45:04 PM UTC 24 |
| Peak memory | 638324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941006609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2941006609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1304221346 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4204500128 ps |
| CPU time | 947.21 seconds |
| Started | Aug 25 06:34:37 PM UTC 24 |
| Finished | Aug 25 06:50:45 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304221346 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.1304221346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2748589378 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3509798200 ps |
| CPU time | 915.8 seconds |
| Started | Aug 25 06:33:58 PM UTC 24 |
| Finished | Aug 25 06:49:30 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274 8589378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2748589378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4001632834 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 4809763148 ps |
| CPU time | 842.24 seconds |
| Started | Aug 25 06:35:06 PM UTC 24 |
| Finished | Aug 25 06:49:26 PM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001632834 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.4001632834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2900246115 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5375208700 ps |
| CPU time | 832.56 seconds |
| Started | Aug 25 06:35:07 PM UTC 24 |
| Finished | Aug 25 06:49:17 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900246115 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_rma.2900246115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2445777989 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4624517200 ps |
| CPU time | 892.92 seconds |
| Started | Aug 25 06:33:36 PM UTC 24 |
| Finished | Aug 25 06:48:48 PM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244 5777989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.2445777989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.3940543300 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3185759943 ps |
| CPU time | 348.27 seconds |
| Started | Aug 25 06:35:16 PM UTC 24 |
| Finished | Aug 25 06:41:12 PM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3940543300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_clkmgr_jitter.3940543300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3163622603 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3587442296 ps |
| CPU time | 553.31 seconds |
| Started | Aug 25 06:35:08 PM UTC 24 |
| Finished | Aug 25 06:44:35 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=3163622603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_clkmgr_jitter_frequency.3163622603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1782199616 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3663066175 ps |
| CPU time | 319.6 seconds |
| Started | Aug 25 06:43:27 PM UTC 24 |
| Finished | Aug 25 06:48:54 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1782199616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1782199616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1737544405 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4275791882 ps |
| CPU time | 736.57 seconds |
| Started | Aug 25 06:32:31 PM UTC 24 |
| Finished | Aug 25 06:45:01 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1737544405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1737544405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.814539449 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 3505480904 ps |
| CPU time | 608.35 seconds |
| Started | Aug 25 06:31:47 PM UTC 24 |
| Finished | Aug 25 06:42:08 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=814539449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.814539449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2737014246 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4617590280 ps |
| CPU time | 776.97 seconds |
| Started | Aug 25 06:32:33 PM UTC 24 |
| Finished | Aug 25 06:45:45 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2737014246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_clkmgr_off_kmac_trans.2737014246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.927437270 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 7764131822 ps |
| CPU time | 1128.38 seconds |
| Started | Aug 25 06:32:32 PM UTC 24 |
| Finished | Aug 25 06:51:44 PM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927437270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.927437270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.91152876 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3490057032 ps |
| CPU time | 679.13 seconds |
| Started | Aug 25 06:34:41 PM UTC 24 |
| Finished | Aug 25 06:46:14 PM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91152876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.91152876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3366463327 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4390816050 ps |
| CPU time | 732.32 seconds |
| Started | Aug 25 06:35:18 PM UTC 24 |
| Finished | Aug 25 06:47:43 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366463327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3366463327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.4180737039 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2650907300 ps |
| CPU time | 246.77 seconds |
| Started | Aug 25 07:05:14 PM UTC 24 |
| Finished | Aug 25 07:09:27 PM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=4180737039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_clkmgr_smoketest.4180737039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.2931146698 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20477109220 ps |
| CPU time | 7431.75 seconds |
| Started | Aug 25 06:27:48 PM UTC 24 |
| Finished | Aug 25 08:33:54 PM UTC 24 |
| Peak memory | 628984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2931146698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_csrng_edn_concurrency.2931146698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1565758405 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3872226826 ps |
| CPU time | 573.96 seconds |
| Started | Aug 25 06:24:58 PM UTC 24 |
| Finished | Aug 25 06:34:43 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565758405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1565758405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.755177556 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2554358392 ps |
| CPU time | 370.49 seconds |
| Started | Aug 25 06:30:49 PM UTC 24 |
| Finished | Aug 25 06:37:08 PM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=755177556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.755177556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.1875901248 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 2479019240 ps |
| CPU time | 404.37 seconds |
| Started | Aug 25 07:05:15 PM UTC 24 |
| Finished | Aug 25 07:12:08 PM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1875901248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_smoketest.1875901248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.2459821043 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 6349146520 ps |
| CPU time | 1151.97 seconds |
| Started | Aug 25 06:24:57 PM UTC 24 |
| Finished | Aug 25 06:44:31 PM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459821043 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2459821043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.207111778 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5219709908 ps |
| CPU time | 1110.05 seconds |
| Started | Aug 25 06:25:56 PM UTC 24 |
| Finished | Aug 25 06:44:47 PM UTC 24 |
| Peak memory | 626088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207111778 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.207111778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.1410692357 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3757353600 ps |
| CPU time | 818.23 seconds |
| Started | Aug 25 06:22:31 PM UTC 24 |
| Finished | Aug 25 06:36:25 PM UTC 24 |
| Peak memory | 629932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=1410692357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_edn_kat.1410692357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.125036302 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5476036830 ps |
| CPU time | 1579.47 seconds |
| Started | Aug 25 06:22:55 PM UTC 24 |
| Finished | Aug 25 06:49:45 PM UTC 24 |
| Peak memory | 623880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=125036302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_edn_sw_mode.125036302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1347984931 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3116585682 ps |
| CPU time | 391.86 seconds |
| Started | Aug 25 06:26:31 PM UTC 24 |
| Finished | Aug 25 06:33:10 PM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347984931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1347984931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3947813578 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3139270010 ps |
| CPU time | 317.27 seconds |
| Started | Aug 25 06:21:41 PM UTC 24 |
| Finished | Aug 25 06:27:05 PM UTC 24 |
| Peak memory | 623744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947813578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3947813578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_smoketest.2660506571 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3240077320 ps |
| CPU time | 673.48 seconds |
| Started | Aug 25 07:04:47 PM UTC 24 |
| Finished | Aug 25 07:16:14 PM UTC 24 |
| Peak memory | 623744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660506571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2660506571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.3162045773 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2337832328 ps |
| CPU time | 210.82 seconds |
| Started | Aug 25 06:08:30 PM UTC 24 |
| Finished | Aug 25 06:12:05 PM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3162045773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.3162045773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.3365553798 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2599225114 ps |
| CPU time | 142.5 seconds |
| Started | Aug 25 06:05:37 PM UTC 24 |
| Finished | Aug 25 06:08:02 PM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3365553798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_example_flash.3365553798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.3730886038 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3042680192 ps |
| CPU time | 207.03 seconds |
| Started | Aug 25 06:03:50 PM UTC 24 |
| Finished | Aug 25 06:07:20 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3730886038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ex ample_manufacturer.3730886038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.2537489666 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2601683552 ps |
| CPU time | 98.55 seconds |
| Started | Aug 25 06:08:24 PM UTC 24 |
| Finished | Aug 25 06:10:04 PM UTC 24 |
| Peak memory | 623356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2537489666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_example_rom.2537489666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.1705855364 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5368128424 ps |
| CPU time | 757.93 seconds |
| Started | Aug 25 06:43:10 PM UTC 24 |
| Finished | Aug 25 06:56:01 PM UTC 24 |
| Peak memory | 626144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705855364 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1705855364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.1937387787 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 6001093460 ps |
| CPU time | 1349.63 seconds |
| Started | Aug 25 06:11:43 PM UTC 24 |
| Finished | Aug 25 06:34:38 PM UTC 24 |
| Peak memory | 623908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1937387787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _flash_ctrl_access.1937387787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.95430845 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 5814549897 ps |
| CPU time | 1374.27 seconds |
| Started | Aug 25 06:10:00 PM UTC 24 |
| Finished | Aug 25 06:33:20 PM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=95430845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_flash_ctrl_access_jitter_en.95430845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3211023599 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 7546657341 ps |
| CPU time | 944.16 seconds |
| Started | Aug 25 06:44:34 PM UTC 24 |
| Finished | Aug 25 07:00:33 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211023599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3211023599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.840079906 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6197630996 ps |
| CPU time | 1266.06 seconds |
| Started | Aug 25 06:07:32 PM UTC 24 |
| Finished | Aug 25 06:29:00 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=840079906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.chip_sw_flash_ctrl_clock_freqs.840079906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1010719140 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5201884438 ps |
| CPU time | 1250.38 seconds |
| Started | Aug 25 06:55:45 PM UTC 24 |
| Finished | Aug 25 07:16:55 PM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1010719140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_flash_ctrl_mem_protection.1010719140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.3295778872 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4089879700 ps |
| CPU time | 704 seconds |
| Started | Aug 25 06:11:29 PM UTC 24 |
| Finished | Aug 25 06:23:26 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295778872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3295778872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801740084 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4329777184 ps |
| CPU time | 712.54 seconds |
| Started | Aug 25 06:44:28 PM UTC 24 |
| Finished | Aug 25 06:56:34 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801740084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801740084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.4173686332 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3356473590 ps |
| CPU time | 471.76 seconds |
| Started | Aug 25 06:43:21 PM UTC 24 |
| Finished | Aug 25 06:51:23 PM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173686332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.4173686332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.657964419 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 20193868890 ps |
| CPU time | 2784.2 seconds |
| Started | Aug 25 06:08:22 PM UTC 24 |
| Finished | Aug 25 06:55:36 PM UTC 24 |
| Peak memory | 632844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657964419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.657964419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.2168938696 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2767280480 ps |
| CPU time | 191.17 seconds |
| Started | Aug 25 06:53:41 PM UTC 24 |
| Finished | Aug 25 06:56:55 PM UTC 24 |
| Peak memory | 623636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168938696 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2168938696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.1528843403 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2524520162 ps |
| CPU time | 360.2 seconds |
| Started | Aug 25 07:04:45 PM UTC 24 |
| Finished | Aug 25 07:10:54 PM UTC 24 |
| Peak memory | 623816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1528843403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_gpio_smoketest.1528843403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.3059945147 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2338803600 ps |
| CPU time | 362.52 seconds |
| Started | Aug 25 06:31:44 PM UTC 24 |
| Finished | Aug 25 06:37:53 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3059945147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_hmac_enc_idle.3059945147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.510758666 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2466407156 ps |
| CPU time | 312.48 seconds |
| Started | Aug 25 06:30:32 PM UTC 24 |
| Finished | Aug 25 06:35:51 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=510758666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.510758666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1429231574 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2660089718 ps |
| CPU time | 271.28 seconds |
| Started | Aug 25 06:48:57 PM UTC 24 |
| Finished | Aug 25 06:53:33 PM UTC 24 |
| Peak memory | 623596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429231574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1429231574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.704660720 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 7534415436 ps |
| CPU time | 1731.96 seconds |
| Started | Aug 25 06:31:03 PM UTC 24 |
| Finished | Aug 25 07:00:25 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=704660720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_multistream.704660720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.2654585639 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3284578368 ps |
| CPU time | 375.99 seconds |
| Started | Aug 25 06:27:57 PM UTC 24 |
| Finished | Aug 25 06:34:20 PM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2654585639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_h mac_oneshot.2654585639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.4162448289 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3362889608 ps |
| CPU time | 520.14 seconds |
| Started | Aug 25 07:04:35 PM UTC 24 |
| Finished | Aug 25 07:13:27 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4162448289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ hmac_smoketest.4162448289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.308504684 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4208786704 ps |
| CPU time | 802.59 seconds |
| Started | Aug 25 06:09:08 PM UTC 24 |
| Finished | Aug 25 06:22:47 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=308504684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_i2c_device_tx_rx.308504684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2998507605 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 12688992181 ps |
| CPU time | 3129.07 seconds |
| Started | Aug 25 06:30:51 PM UTC 24 |
| Finished | Aug 25 07:23:55 PM UTC 24 |
| Peak memory | 634168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998507605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2998507605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1487819063 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 9246772648 ps |
| CPU time | 1158.63 seconds |
| Started | Aug 25 06:48:06 PM UTC 24 |
| Finished | Aug 25 07:07:42 PM UTC 24 |
| Peak memory | 631992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487819063 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1487819063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2329162222 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9080464932 ps |
| CPU time | 2431.58 seconds |
| Started | Aug 25 06:30:32 PM UTC 24 |
| Finished | Aug 25 07:11:45 PM UTC 24 |
| Peak memory | 632032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329162222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.2329162222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.2589378200 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2865286350 ps |
| CPU time | 281.41 seconds |
| Started | Aug 25 06:31:28 PM UTC 24 |
| Finished | Aug 25 06:36:16 PM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=2589378200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_kmac_app_rom.2589378200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.3006984927 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2380373342 ps |
| CPU time | 412.75 seconds |
| Started | Aug 25 06:12:18 PM UTC 24 |
| Finished | Aug 25 06:19:19 PM UTC 24 |
| Peak memory | 623872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=3006984927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_kmac_entropy.3006984927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.1716680487 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2640475320 ps |
| CPU time | 440.2 seconds |
| Started | Aug 25 06:30:37 PM UTC 24 |
| Finished | Aug 25 06:38:07 PM UTC 24 |
| Peak memory | 623812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1716680487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_idle.1716680487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2991446232 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2422926856 ps |
| CPU time | 237.18 seconds |
| Started | Aug 25 06:28:31 PM UTC 24 |
| Finished | Aug 25 06:32:33 PM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2991446232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_kmac_mode_cshake.2991446232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.2335361008 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2453379800 ps |
| CPU time | 440.54 seconds |
| Started | Aug 25 06:32:03 PM UTC 24 |
| Finished | Aug 25 06:39:34 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335361008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_kmac_mode_kmac.2335361008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.396088048 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 3133361254 ps |
| CPU time | 534.77 seconds |
| Started | Aug 25 06:30:37 PM UTC 24 |
| Finished | Aug 25 06:39:43 PM UTC 24 |
| Peak memory | 623568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=396088048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_kmac_mode_kmac_jitter_en.396088048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3519806683 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3037140283 ps |
| CPU time | 314.41 seconds |
| Started | Aug 25 06:47:33 PM UTC 24 |
| Finished | Aug 25 06:52:54 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519806683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3519806683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.3196553767 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2742248440 ps |
| CPU time | 546.49 seconds |
| Started | Aug 25 07:07:16 PM UTC 24 |
| Finished | Aug 25 07:16:33 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3196553767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ kmac_smoketest.3196553767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3709610446 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2545692770 ps |
| CPU time | 357.12 seconds |
| Started | Aug 25 06:09:09 PM UTC 24 |
| Finished | Aug 25 06:15:13 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3709610446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3709610446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2115187097 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3840384384 ps |
| CPU time | 178.32 seconds |
| Started | Aug 25 06:11:26 PM UTC 24 |
| Finished | Aug 25 06:14:28 PM UTC 24 |
| Peak memory | 637476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115187097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2115187097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4039947983 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3969073866 ps |
| CPU time | 212.4 seconds |
| Started | Aug 25 06:10:43 PM UTC 24 |
| Finished | Aug 25 06:14:20 PM UTC 24 |
| Peak memory | 635356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039947983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.4039947983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.351661825 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3490823540 ps |
| CPU time | 246.14 seconds |
| Started | Aug 25 06:12:30 PM UTC 24 |
| Finished | Aug 25 06:16:41 PM UTC 24 |
| Peak memory | 637576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTes tLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351661825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip _earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.351661825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.452347765 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7418912805 ps |
| CPU time | 618.62 seconds |
| Started | Aug 25 06:08:30 PM UTC 24 |
| Finished | Aug 25 06:18:59 PM UTC 24 |
| Peak memory | 636036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=452347765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_lc_ctrl_transition.452347765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.360910287 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2661535711 ps |
| CPU time | 149.61 seconds |
| Started | Aug 25 06:10:15 PM UTC 24 |
| Finished | Aug 25 06:12:48 PM UTC 24 |
| Peak memory | 635372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360910287 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.360910287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3750896884 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2204730762 ps |
| CPU time | 138.95 seconds |
| Started | Aug 25 06:10:57 PM UTC 24 |
| Finished | Aug 25 06:13:19 PM UTC 24 |
| Peak memory | 633508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37508968 84 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.3750896884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2881358270 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 22187543516 ps |
| CPU time | 2739.06 seconds |
| Started | Aug 25 06:11:30 PM UTC 24 |
| Finished | Aug 25 06:57:58 PM UTC 24 |
| Peak memory | 640260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881358270 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunlocks.2881358270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2577150999 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 18895990179 ps |
| CPU time | 6283.01 seconds |
| Started | Aug 25 06:17:32 PM UTC 24 |
| Finished | Aug 25 08:04:03 PM UTC 24 |
| Peak memory | 629052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577150999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2577150999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2336623397 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 24893175572 ps |
| CPU time | 6573.12 seconds |
| Started | Aug 25 06:47:26 PM UTC 24 |
| Finished | Aug 25 08:38:56 PM UTC 24 |
| Peak memory | 628912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336623397 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2336623397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1903321410 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3593104168 ps |
| CPU time | 593.75 seconds |
| Started | Aug 25 06:17:30 PM UTC 24 |
| Finished | Aug 25 06:27:36 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903321410 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1903321410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.1812938676 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 6437731736 ps |
| CPU time | 1360.77 seconds |
| Started | Aug 25 06:17:06 PM UTC 24 |
| Finished | Aug 25 06:40:13 PM UTC 24 |
| Peak memory | 626060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812938676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1812938676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_smoketest.4137616582 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 5865310440 ps |
| CPU time | 1479.13 seconds |
| Started | Aug 25 07:07:31 PM UTC 24 |
| Finished | Aug 25 07:32:38 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4137616582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ otbn_smoketest.4137616582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4100753750 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2525407053 ps |
| CPU time | 272.61 seconds |
| Started | Aug 25 06:09:19 PM UTC 24 |
| Finished | Aug 25 06:13:56 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4100753750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.4100753750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3858018675 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8259887228 ps |
| CPU time | 1461.6 seconds |
| Started | Aug 25 06:08:51 PM UTC 24 |
| Finished | Aug 25 06:33:40 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858018675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3858018675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.913297575 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 9755574932 ps |
| CPU time | 1997.44 seconds |
| Started | Aug 25 06:08:51 PM UTC 24 |
| Finished | Aug 25 06:42:46 PM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913297575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.913297575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1103939660 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 8157306712 ps |
| CPU time | 1203.61 seconds |
| Started | Aug 25 06:09:05 PM UTC 24 |
| Finished | Aug 25 06:29:29 PM UTC 24 |
| Peak memory | 623812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103939660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1103939660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.122927949 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4295610720 ps |
| CPU time | 751.15 seconds |
| Started | Aug 25 06:10:01 PM UTC 24 |
| Finished | Aug 25 06:22:45 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122927949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.122927949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.2542886 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 3214388392 ps |
| CPU time | 461.24 seconds |
| Started | Aug 25 07:07:35 PM UTC 24 |
| Finished | Aug 25 07:15:24 PM UTC 24 |
| Peak memory | 623580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2542886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _otp_ctrl_smoketest.2542886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.2676624877 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2694853676 ps |
| CPU time | 211.96 seconds |
| Started | Aug 25 06:08:35 PM UTC 24 |
| Finished | Aug 25 06:12:11 PM UTC 24 |
| Peak memory | 623788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676624877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2676624877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.382322495 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2405475840 ps |
| CPU time | 364.85 seconds |
| Started | Aug 25 06:32:31 PM UTC 24 |
| Finished | Aug 25 06:38:44 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=382322495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _plic_sw_irq.382322495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.1283683415 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 4166239528 ps |
| CPU time | 637.91 seconds |
| Started | Aug 25 06:48:02 PM UTC 24 |
| Finished | Aug 25 06:58:50 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283683415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_power_idle_load.1283683415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.909905999 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4061128264 ps |
| CPU time | 378.89 seconds |
| Started | Aug 25 06:47:36 PM UTC 24 |
| Finished | Aug 25 06:54:02 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=909905999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_power_sleep_load.909905999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2801993995 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9707623814 ps |
| CPU time | 2224.89 seconds |
| Started | Aug 25 06:10:44 PM UTC 24 |
| Finished | Aug 25 06:48:32 PM UTC 24 |
| Peak memory | 625960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801993995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2801993995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.679264223 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 31896289000 ps |
| CPU time | 3448.84 seconds |
| Started | Aug 25 06:31:07 PM UTC 24 |
| Finished | Aug 25 07:29:36 PM UTC 24 |
| Peak memory | 626092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679264223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_res et_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.679264223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2431896060 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 18406649533 ps |
| CPU time | 2152.06 seconds |
| Started | Aug 25 06:10:58 PM UTC 24 |
| Finished | Aug 25 06:47:31 PM UTC 24 |
| Peak memory | 626044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431896060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2431896060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3977382105 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7542631464 ps |
| CPU time | 820.85 seconds |
| Started | Aug 25 06:12:40 PM UTC 24 |
| Finished | Aug 25 06:26:38 PM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3977382105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.3977382105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3010032078 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4079216010 ps |
| CPU time | 636.61 seconds |
| Started | Aug 25 06:12:40 PM UTC 24 |
| Finished | Aug 25 06:23:29 PM UTC 24 |
| Peak memory | 631740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010032078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3010032078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3072324973 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 13493185965 ps |
| CPU time | 2122.79 seconds |
| Started | Aug 25 06:12:47 PM UTC 24 |
| Finished | Aug 25 06:48:51 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3072324973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3072324973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3374140407 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6777832766 ps |
| CPU time | 499.99 seconds |
| Started | Aug 25 06:37:13 PM UTC 24 |
| Finished | Aug 25 06:45:44 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3374140407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3374140407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3193436176 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 27039201065 ps |
| CPU time | 2535.96 seconds |
| Started | Aug 25 06:10:29 PM UTC 24 |
| Finished | Aug 25 06:53:31 PM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193436176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3193436176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3531441722 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 23489008856 ps |
| CPU time | 1612.53 seconds |
| Started | Aug 25 06:38:03 PM UTC 24 |
| Finished | Aug 25 07:05:23 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531441722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3531441722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.101327675 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3227892512 ps |
| CPU time | 452.95 seconds |
| Started | Aug 25 06:15:19 PM UTC 24 |
| Finished | Aug 25 06:23:01 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=101327675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.101327675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.451672076 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 6824851218 ps |
| CPU time | 734.89 seconds |
| Started | Aug 25 06:38:58 PM UTC 24 |
| Finished | Aug 25 06:51:29 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451672076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.451672076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_smoketest.3965376108 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4831056850 ps |
| CPU time | 648.46 seconds |
| Started | Aug 25 07:08:30 PM UTC 24 |
| Finished | Aug 25 07:19:32 PM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965376108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3965376108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.966490341 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 7003226716 ps |
| CPU time | 1368.8 seconds |
| Started | Aug 25 06:14:35 PM UTC 24 |
| Finished | Aug 25 06:37:51 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=966490341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.966490341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.401375727 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4868740494 ps |
| CPU time | 815.16 seconds |
| Started | Aug 25 06:15:16 PM UTC 24 |
| Finished | Aug 25 06:29:07 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=401375727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.401375727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3038141165 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4979229352 ps |
| CPU time | 588.5 seconds |
| Started | Aug 25 07:08:41 PM UTC 24 |
| Finished | Aug 25 07:18:41 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3038141165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_pwrmgr_usbdev_smoketest.3038141165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.367360176 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5159114230 ps |
| CPU time | 748.78 seconds |
| Started | Aug 25 06:16:02 PM UTC 24 |
| Finished | Aug 25 06:28:45 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367360176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.367360176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.285309992 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 9245622251 ps |
| CPU time | 654.72 seconds |
| Started | Aug 25 06:30:38 PM UTC 24 |
| Finished | Aug 25 06:41:46 PM UTC 24 |
| Peak memory | 640236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=285309992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.285309992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.563852690 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 5074717376 ps |
| CPU time | 971.98 seconds |
| Started | Aug 25 06:09:10 PM UTC 24 |
| Finished | Aug 25 06:25:42 PM UTC 24 |
| Peak memory | 668160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563852690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_ cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.563852690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_smoketest.2429991949 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3283133800 ps |
| CPU time | 359.01 seconds |
| Started | Aug 25 07:10:08 PM UTC 24 |
| Finished | Aug 25 07:16:13 PM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2429991949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rstmgr_smoketest.2429991949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.3769520202 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4019088150 ps |
| CPU time | 446.46 seconds |
| Started | Aug 25 06:08:31 PM UTC 24 |
| Finished | Aug 25 06:16:06 PM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3769520202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rstmgr_sw_req.3769520202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.354009593 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3337014390 ps |
| CPU time | 414.24 seconds |
| Started | Aug 25 06:10:54 PM UTC 24 |
| Finished | Aug 25 06:17:57 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=354009593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_rstmgr_sw_rst.354009593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3509191171 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3447125849 ps |
| CPU time | 317.59 seconds |
| Started | Aug 25 06:42:33 PM UTC 24 |
| Finished | Aug 25 06:47:58 PM UTC 24 |
| Peak memory | 623764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3509191171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3509191171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.2737851731 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5497501644 ps |
| CPU time | 1190.93 seconds |
| Started | Aug 25 06:19:08 PM UTC 24 |
| Finished | Aug 25 06:39:21 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737851731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2737851731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.936067535 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 6620518020 ps |
| CPU time | 711.61 seconds |
| Started | Aug 25 06:39:35 PM UTC 24 |
| Finished | Aug 25 06:51:42 PM UTC 24 |
| Peak memory | 635880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=936067535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wake up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.936067535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_plic_smoketest.877086129 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3247638408 ps |
| CPU time | 293.36 seconds |
| Started | Aug 25 07:08:40 PM UTC 24 |
| Finished | Aug 25 07:13:40 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=877086129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_rv_plic_smoketest.877086129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.637683704 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3457642610 ps |
| CPU time | 398.93 seconds |
| Started | Aug 25 06:13:03 PM UTC 24 |
| Finished | Aug 25 06:19:50 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=637683704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_rv_timer_irq.637683704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.2173808893 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2716151512 ps |
| CPU time | 261.27 seconds |
| Started | Aug 25 07:09:23 PM UTC 24 |
| Finished | Aug 25 07:13:51 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2173808893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_rv_timer_smoketest.2173808893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.2107218446 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2514671241 ps |
| CPU time | 286.55 seconds |
| Started | Aug 25 06:31:06 PM UTC 24 |
| Finished | Aug 25 06:36:00 PM UTC 24 |
| Peak memory | 623912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107218446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2107218446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.2538424424 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9772060440 ps |
| CPU time | 1515.03 seconds |
| Started | Aug 25 06:08:32 PM UTC 24 |
| Finished | Aug 25 06:34:14 PM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2538424424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sleep_pwm_pulses.2538424424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3321228066 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 7984440016 ps |
| CPU time | 1089.33 seconds |
| Started | Aug 25 06:30:53 PM UTC 24 |
| Finished | Aug 25 06:49:23 PM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321228066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents _no_scramble.3321228066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.887384001 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 6322934418 ps |
| CPU time | 918.27 seconds |
| Started | Aug 25 06:31:02 PM UTC 24 |
| Finished | Aug 25 06:46:40 PM UTC 24 |
| Peak memory | 623888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887384001 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_sram_ret_contents_scramble.887384001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.3852236992 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7227727575 ps |
| CPU time | 899.88 seconds |
| Started | Aug 25 06:08:48 PM UTC 24 |
| Finished | Aug 25 06:24:04 PM UTC 24 |
| Peak memory | 640376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852236992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_spi_device_pass_through.3852236992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.2765025986 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4139087932 ps |
| CPU time | 561.66 seconds |
| Started | Aug 25 06:08:57 PM UTC 24 |
| Finished | Aug 25 06:18:29 PM UTC 24 |
| Peak memory | 640392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765025986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2765025986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.3898816874 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3029060586 ps |
| CPU time | 399.42 seconds |
| Started | Aug 25 06:09:02 PM UTC 24 |
| Finished | Aug 25 06:15:49 PM UTC 24 |
| Peak memory | 636212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3898816874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_spi_device_tpm.3898816874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.4026580818 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 7998759857 ps |
| CPU time | 1265.49 seconds |
| Started | Aug 25 06:32:29 PM UTC 24 |
| Finished | Aug 25 06:53:59 PM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4026580818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.4026580818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3632964476 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 4206054734 ps |
| CPU time | 762.09 seconds |
| Started | Aug 25 06:30:40 PM UTC 24 |
| Finished | Aug 25 06:43:37 PM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632964476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_ access.3632964476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3474464551 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4817455595 ps |
| CPU time | 910.49 seconds |
| Started | Aug 25 07:02:01 PM UTC 24 |
| Finished | Aug 25 07:17:29 PM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474464551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3474464551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.2201804381 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3276459154 ps |
| CPU time | 429.88 seconds |
| Started | Aug 25 07:11:35 PM UTC 24 |
| Finished | Aug 25 07:18:55 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201804381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_sram_ctrl_smoketest.2201804381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.335711986 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2971707607 ps |
| CPU time | 451.5 seconds |
| Started | Aug 25 06:14:31 PM UTC 24 |
| Finished | Aug 25 06:22:13 PM UTC 24 |
| Peak memory | 628016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=335711986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_sysrst_ctrl_inputs.335711986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.955776 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3670385500 ps |
| CPU time | 512.09 seconds |
| Started | Aug 25 06:15:16 PM UTC 24 |
| Finished | Aug 25 06:24:00 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=955776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_sysrst_ctrl_outputs.955776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.2767667020 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 24186745988 ps |
| CPU time | 2031.59 seconds |
| Started | Aug 25 06:15:30 PM UTC 24 |
| Finished | Aug 25 06:49:59 PM UTC 24 |
| Peak memory | 629992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767667020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2767667020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.1346993881 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 3527904504 ps |
| CPU time | 465.02 seconds |
| Started | Aug 25 07:11:59 PM UTC 24 |
| Finished | Aug 25 07:19:55 PM UTC 24 |
| Peak memory | 629836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1346993881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_sw_uart_smoketest.1346993881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3761294035 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4510070568 ps |
| CPU time | 887.18 seconds |
| Started | Aug 25 06:09:21 PM UTC 24 |
| Finished | Aug 25 06:24:27 PM UTC 24 |
| Peak memory | 640056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761294035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3761294035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3025128254 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8912329845 ps |
| CPU time | 2019.19 seconds |
| Started | Aug 25 06:08:05 PM UTC 24 |
| Finished | Aug 25 06:42:21 PM UTC 24 |
| Peak memory | 639268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025128254 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq.3025128254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1587070760 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4758696886 ps |
| CPU time | 532.78 seconds |
| Started | Aug 25 06:08:46 PM UTC 24 |
| Finished | Aug 25 06:17:48 PM UTC 24 |
| Peak memory | 634224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587070760 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1587070760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2946252452 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 79179177269 ps |
| CPU time | 23252.5 seconds |
| Started | Aug 25 06:08:33 PM UTC 24 |
| Finished | Aug 26 12:42:45 AM UTC 24 |
| Peak memory | 657668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946252452 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2946252452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.118334456 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4071760280 ps |
| CPU time | 630.6 seconds |
| Started | Aug 25 06:08:49 PM UTC 24 |
| Finished | Aug 25 06:19:31 PM UTC 24 |
| Peak memory | 640156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118334456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.118334456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.975225488 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3241970806 ps |
| CPU time | 439.87 seconds |
| Started | Aug 25 06:43:07 PM UTC 24 |
| Finished | Aug 25 06:50:37 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw _images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975225488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.975225488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.3284388207 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11365465360 ps |
| CPU time | 3934.76 seconds |
| Started | Aug 25 06:12:27 PM UTC 24 |
| Finished | Aug 25 07:19:10 PM UTC 24 |
| Peak memory | 626740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284388207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3284388207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.2869548539 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 31391668234 ps |
| CPU time | 11366.3 seconds |
| Started | Aug 25 06:01:30 PM UTC 24 |
| Finished | Aug 25 09:14:16 PM UTC 24 |
| Peak memory | 626768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000 _000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869548539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2869548539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.2378361320 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3583396324 ps |
| CPU time | 370.12 seconds |
| Started | Aug 25 06:08:14 PM UTC 24 |
| Finished | Aug 25 06:14:31 PM UTC 24 |
| Peak memory | 625724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378361320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2378361320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.2458058728 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3774106452 ps |
| CPU time | 670.46 seconds |
| Started | Aug 25 06:10:24 PM UTC 24 |
| Finished | Aug 25 06:21:49 PM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458058728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2458058728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.772722278 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 18564819720 ps |
| CPU time | 5751.73 seconds |
| Started | Aug 25 06:09:07 PM UTC 24 |
| Finished | Aug 25 07:46:38 PM UTC 24 |
| Peak memory | 628864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_ 000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772722278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.772722278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_stream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.3704549885 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2462862644 ps |
| CPU time | 346.53 seconds |
| Started | Aug 25 06:11:03 PM UTC 24 |
| Finished | Aug 25 06:16:56 PM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704549885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3704549885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.3938982361 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 17708417183 ps |
| CPU time | 2231.84 seconds |
| Started | Aug 25 06:40:14 PM UTC 24 |
| Finished | Aug 25 07:18:03 PM UTC 24 |
| Peak memory | 650936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938982361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3938982361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.2403285259 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2434175751 ps |
| CPU time | 271.55 seconds |
| Started | Aug 25 06:40:53 PM UTC 24 |
| Finished | Aug 25 06:45:30 PM UTC 24 |
| Peak memory | 639908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403285259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2403285259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_dev.2097861259 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 15023148315 ps |
| CPU time | 6450.99 seconds |
| Started | Aug 25 06:59:31 PM UTC 24 |
| Finished | Aug 25 08:49:01 PM UTC 24 |
| Peak memory | 627032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097861259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2097861259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod.1308798866 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 15209123360 ps |
| CPU time | 5471.32 seconds |
| Started | Aug 25 06:57:34 PM UTC 24 |
| Finished | Aug 25 08:30:23 PM UTC 24 |
| Peak memory | 626908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308798866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1308798866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_prod_end.1850137980 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 15456910524 ps |
| CPU time | 5400.67 seconds |
| Started | Aug 25 07:05:24 PM UTC 24 |
| Finished | Aug 25 08:37:02 PM UTC 24 |
| Peak memory | 626172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185013 7980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_in it_prod_end.1850137980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_rma.3540991268 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 15199680088 ps |
| CPU time | 5970.74 seconds |
| Started | Aug 25 07:04:42 PM UTC 24 |
| Finished | Aug 25 08:46:02 PM UTC 24 |
| Peak memory | 626300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540991268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3540991268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4162190865 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 12042641268 ps |
| CPU time | 4493.2 seconds |
| Started | Aug 25 07:05:08 PM UTC 24 |
| Finished | Aug 25 08:21:26 PM UTC 24 |
| Peak memory | 626140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4162190865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e 2e_asm_init_test_unlocked0.4162190865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.294943950 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 24096739816 ps |
| CPU time | 10737.6 seconds |
| Started | Aug 25 07:07:06 PM UTC 24 |
| Finished | Aug 25 10:09:16 PM UTC 24 |
| Peak memory | 626812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294943950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.294943950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.788281028 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 23883802152 ps |
| CPU time | 9946.22 seconds |
| Started | Aug 25 07:05:47 PM UTC 24 |
| Finished | Aug 25 09:54:37 PM UTC 24 |
| Peak memory | 629012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788281028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.788281028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.40784675 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 23394878124 ps |
| CPU time | 9260.8 seconds |
| Started | Aug 25 07:06:00 PM UTC 24 |
| Finished | Aug 25 09:43:14 PM UTC 24 |
| Peak memory | 629092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40784675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.40784675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.106843537 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 18240837710 ps |
| CPU time | 6954.5 seconds |
| Started | Aug 25 07:05:47 PM UTC 24 |
| Finished | Aug 25 09:03:51 PM UTC 24 |
| Peak memory | 624004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_k ey_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106843537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.106843537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2175038548 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 15109298694 ps |
| CPU time | 5917.17 seconds |
| Started | Aug 25 07:06:17 PM UTC 24 |
| Finished | Aug 25 08:46:45 PM UTC 24 |
| Peak memory | 625840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175038548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2175038548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.536429898 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 15253187000 ps |
| CPU time | 5607.44 seconds |
| Started | Aug 25 07:00:52 PM UTC 24 |
| Finished | Aug 25 08:36:02 PM UTC 24 |
| Peak memory | 623884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536429898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.536429898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3513160419 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 15282959250 ps |
| CPU time | 5778.18 seconds |
| Started | Aug 25 07:07:26 PM UTC 24 |
| Finished | Aug 25 08:45:30 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513160419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3513160419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3799006437 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 14680859640 ps |
| CPU time | 5134.94 seconds |
| Started | Aug 25 07:00:36 PM UTC 24 |
| Finished | Aug 25 08:27:44 PM UTC 24 |
| Peak memory | 624000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed :fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799006437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3799006437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.38343078 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 15017067448 ps |
| CPU time | 5218.9 seconds |
| Started | Aug 25 06:56:32 PM UTC 24 |
| Finished | Aug 25 08:25:08 PM UTC 24 |
| Peak memory | 629056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38343078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.38343078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2199670769 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 15570530452 ps |
| CPU time | 5363.07 seconds |
| Started | Aug 25 07:03:17 PM UTC 24 |
| Finished | Aug 25 08:34:20 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199670769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2199670769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4229927279 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 15124804190 ps |
| CPU time | 5601.08 seconds |
| Started | Aug 25 07:01:02 PM UTC 24 |
| Finished | Aug 25 08:36:03 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229927279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4229927279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4257663334 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 14399401130 ps |
| CPU time | 5205.98 seconds |
| Started | Aug 25 07:00:37 PM UTC 24 |
| Finished | Aug 25 08:28:58 PM UTC 24 |
| Peak memory | 626096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257663334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4257663334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1531365190 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 11858837470 ps |
| CPU time | 4551.93 seconds |
| Started | Aug 25 07:01:37 PM UTC 24 |
| Finished | Aug 25 08:18:48 PM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_b inary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531365190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1531365190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2163393914 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 11653629378 ps |
| CPU time | 2467.55 seconds |
| Started | Aug 25 07:03:53 PM UTC 24 |
| Finished | Aug 25 07:45:45 PM UTC 24 |
| Peak memory | 640300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163393914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2163393914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.2459293168 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 12244253453 ps |
| CPU time | 2518.42 seconds |
| Started | Aug 25 06:59:09 PM UTC 24 |
| Finished | Aug 25 07:41:54 PM UTC 24 |
| Peak memory | 640304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459293168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jta g_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2459293168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.604588225 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11470481658 ps |
| CPU time | 2577.73 seconds |
| Started | Aug 25 06:57:15 PM UTC 24 |
| Finished | Aug 25 07:40:57 PM UTC 24 |
| Peak memory | 636320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_devic e=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604588225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_r om_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.604588225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_dev.3625501879 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 42088539350 ps |
| CPU time | 5515.09 seconds |
| Started | Aug 25 06:59:03 PM UTC 24 |
| Finished | Aug 25 08:32:36 PM UTC 24 |
| Peak memory | 638952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625501879 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3625501879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_rma.4174014414 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 33094155366 ps |
| CPU time | 6266.13 seconds |
| Started | Aug 25 06:59:33 PM UTC 24 |
| Finished | Aug 25 08:45:54 PM UTC 24 |
| Peak memory | 638668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174014414 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.4174014414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4107198542 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 34829888270 ps |
| CPU time | 5717.84 seconds |
| Started | Aug 25 06:59:47 PM UTC 24 |
| Finished | Aug 25 08:36:51 PM UTC 24 |
| Peak memory | 640696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_imag e=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107198542 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_test_unlocked0.4107198542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.964908704 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 15024373080 ps |
| CPU time | 5409.63 seconds |
| Started | Aug 25 07:02:05 PM UTC 24 |
| Finished | Aug 25 08:33:53 PM UTC 24 |
| Peak memory | 626084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964908704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.964908704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1094522729 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 15067108016 ps |
| CPU time | 5928.31 seconds |
| Started | Aug 25 06:59:05 PM UTC 24 |
| Finished | Aug 25 08:39:39 PM UTC 24 |
| Peak memory | 626788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094522729 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1094522729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2697410161 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 15540644000 ps |
| CPU time | 6472.53 seconds |
| Started | Aug 25 07:00:26 PM UTC 24 |
| Finished | Aug 25 08:50:16 PM UTC 24 |
| Peak memory | 626968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697410161 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_no_meas.2697410161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3486280420 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 27292263800 ps |
| CPU time | 10569.6 seconds |
| Started | Aug 25 07:05:08 PM UTC 24 |
| Finished | Aug 25 10:04:35 PM UTC 24 |
| Peak memory | 626912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486280420 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3486280420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.723200948 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 14776451508 ps |
| CPU time | 5875.26 seconds |
| Started | Aug 25 07:03:22 PM UTC 24 |
| Finished | Aug 25 08:43:06 PM UTC 24 |
| Peak memory | 626844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723200948 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.723200948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3927404815 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 23994404440 ps |
| CPU time | 8909.13 seconds |
| Started | Aug 25 07:08:38 PM UTC 24 |
| Finished | Aug 25 09:39:47 PM UTC 24 |
| Peak memory | 627160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_fla sh_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927404815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3927404815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3088593544 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 24055253118 ps |
| CPU time | 10308.3 seconds |
| Started | Aug 25 07:05:04 PM UTC 24 |
| Finished | Aug 25 10:00:06 PM UTC 24 |
| Peak memory | 626836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088593544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3088593544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1636182612 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 23894360504 ps |
| CPU time | 9833.6 seconds |
| Started | Aug 25 07:04:42 PM UTC 24 |
| Finished | Aug 25 09:51:35 PM UTC 24 |
| Peak memory | 626844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636182612 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1636182612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1323135703 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 22754359852 ps |
| CPU time | 9356.38 seconds |
| Started | Aug 25 07:05:07 PM UTC 24 |
| Finished | Aug 25 09:43:53 PM UTC 24 |
| Peak memory | 626984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323135703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1323135703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2516804789 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 17333301208 ps |
| CPU time | 7248 seconds |
| Started | Aug 25 07:07:05 PM UTC 24 |
| Finished | Aug 25 09:10:09 PM UTC 24 |
| Peak memory | 624088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_fl ash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516804789 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2516804789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2682094821 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 14975246860 ps |
| CPU time | 6091.36 seconds |
| Started | Aug 25 07:07:37 PM UTC 24 |
| Finished | Aug 25 08:51:01 PM UTC 24 |
| Peak memory | 624056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2682094821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2682094821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3275610572 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 15122983380 ps |
| CPU time | 5757.05 seconds |
| Started | Aug 25 07:03:20 PM UTC 24 |
| Finished | Aug 25 08:41:00 PM UTC 24 |
| Peak memory | 624780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3275610572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3275610572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2791179149 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 15006718079 ps |
| CPU time | 5716.96 seconds |
| Started | Aug 25 07:03:21 PM UTC 24 |
| Finished | Aug 25 08:40:21 PM UTC 24 |
| Peak memory | 623984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2791179149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2791179149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2699888402 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 14561437889 ps |
| CPU time | 5711.33 seconds |
| Started | Aug 25 06:58:49 PM UTC 24 |
| Finished | Aug 25 08:35:43 PM UTC 24 |
| Peak memory | 629028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2699888402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2699888402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1685561768 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 10843562281 ps |
| CPU time | 3632.84 seconds |
| Started | Aug 25 06:58:20 PM UTC 24 |
| Finished | Aug 25 07:59:57 PM UTC 24 |
| Peak memory | 624092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_ test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1685561768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1685561768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3644587672 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 14761484278 ps |
| CPU time | 5087 seconds |
| Started | Aug 25 07:07:30 PM UTC 24 |
| Finished | Aug 25 08:33:50 PM UTC 24 |
| Peak memory | 626100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3644587672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3644587672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1668077876 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 14482610552 ps |
| CPU time | 6073.17 seconds |
| Started | Aug 25 07:00:34 PM UTC 24 |
| Finished | Aug 25 08:43:39 PM UTC 24 |
| Peak memory | 629072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mas k_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1668077876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1668077876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2094789571 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 14449826684 ps |
| CPU time | 5103.83 seconds |
| Started | Aug 25 07:05:15 PM UTC 24 |
| Finished | Aug 25 08:31:52 PM UTC 24 |
| Peak memory | 624024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4 ,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2094789571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2094789571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2605611843 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 14076879542 ps |
| CPU time | 5340.32 seconds |
| Started | Aug 25 06:58:09 PM UTC 24 |
| Finished | Aug 25 08:28:41 PM UTC 24 |
| Peak memory | 627080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2605611843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2605611843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1388390870 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 11216364116 ps |
| CPU time | 4387.06 seconds |
| Started | Aug 25 06:57:31 PM UTC 24 |
| Finished | Aug 25 08:11:53 PM UTC 24 |
| Peak memory | 626976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unloc ked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388390870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1388390870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.3070382226 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 15315301328 ps |
| CPU time | 5422.78 seconds |
| Started | Aug 25 06:55:22 PM UTC 24 |
| Finished | Aug 25 08:27:23 PM UTC 24 |
| Peak memory | 626776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070382226 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3070382226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.3764972146 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 16661637446 ps |
| CPU time | 7074.56 seconds |
| Started | Aug 25 07:04:43 PM UTC 24 |
| Finished | Aug 25 09:04:47 PM UTC 24 |
| Peak memory | 628832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764972146 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3764972146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.7935329 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 5491617028 ps |
| CPU time | 647.51 seconds |
| Started | Aug 25 07:00:17 PM UTC 24 |
| Finished | Aug 25 07:11:17 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7935329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.7935329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3752894016 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4144505232 ps |
| CPU time | 300.47 seconds |
| Started | Aug 25 07:03:35 PM UTC 24 |
| Finished | Aug 25 07:08:41 PM UTC 24 |
| Peak memory | 637764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752894016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3752894016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_jtag_mem_access.416247101 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14348402380 ps |
| CPU time | 2493.9 seconds |
| Started | Aug 25 08:45:05 PM UTC 24 |
| Finished | Aug 25 09:27:24 PM UTC 24 |
| Peak memory | 623332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416247101 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.416247101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_rv_dm_ndm_reset_req.2463138216 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4640919408 ps |
| CPU time | 611.33 seconds |
| Started | Aug 25 08:48:27 PM UTC 24 |
| Finished | Aug 25 08:58:52 PM UTC 24 |
| Peak memory | 636060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463138216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2463138216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.1627997457 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3814767912 ps |
| CPU time | 427.32 seconds |
| Started | Aug 25 07:14:38 PM UTC 24 |
| Finished | Aug 25 07:21:54 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627997457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1627997457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3042865217 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 19999975380 ps |
| CPU time | 676.81 seconds |
| Started | Aug 25 08:13:05 PM UTC 24 |
| Finished | Aug 25 08:24:36 PM UTC 24 |
| Peak memory | 636072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042865217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3042865217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc.1351123742 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2351021700 ps |
| CPU time | 404.62 seconds |
| Started | Aug 25 08:17:14 PM UTC 24 |
| Finished | Aug 25 08:24:06 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351123742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1351123742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.942787514 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2467456958 ps |
| CPU time | 386.68 seconds |
| Started | Aug 25 08:17:14 PM UTC 24 |
| Finished | Aug 25 08:23:50 PM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942787514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.942787514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.100333636 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2486705285 ps |
| CPU time | 352.54 seconds |
| Started | Aug 25 08:53:44 PM UTC 24 |
| Finished | Aug 25 08:59:45 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100333636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.100333636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_entropy.893013700 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2942595940 ps |
| CPU time | 369.68 seconds |
| Started | Aug 25 08:24:54 PM UTC 24 |
| Finished | Aug 25 08:31:12 PM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893013700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_aes_entropy.893013700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.436675862 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2716613080 ps |
| CPU time | 328.23 seconds |
| Started | Aug 25 08:17:48 PM UTC 24 |
| Finished | Aug 25 08:23:25 PM UTC 24 |
| Peak memory | 625564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=436675862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.436675862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_masking_off.635678309 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3348108064 ps |
| CPU time | 463.53 seconds |
| Started | Aug 25 08:19:29 PM UTC 24 |
| Finished | Aug 25 08:27:23 PM UTC 24 |
| Peak memory | 623580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635678309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_aes_masking_off.635678309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_smoketest.2139249578 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 3238441684 ps |
| CPU time | 522.09 seconds |
| Started | Aug 25 09:05:52 PM UTC 24 |
| Finished | Aug 25 09:14:45 PM UTC 24 |
| Peak memory | 625720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2139249578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_a es_smoketest.2139249578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_entropy.3668274839 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3644322411 ps |
| CPU time | 490.37 seconds |
| Started | Aug 25 08:25:14 PM UTC 24 |
| Finished | Aug 25 08:33:36 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668274839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgr ey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3668274839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_escalation.2665637697 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 4500429888 ps |
| CPU time | 635.67 seconds |
| Started | Aug 25 08:20:45 PM UTC 24 |
| Finished | Aug 25 08:31:33 PM UTC 24 |
| Peak memory | 636056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665637697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2665637697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2743236411 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 7167372866 ps |
| CPU time | 1741.65 seconds |
| Started | Aug 25 08:24:25 PM UTC 24 |
| Finished | Aug 25 08:54:04 PM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743236411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2743236411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2644658435 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 7109621164 ps |
| CPU time | 1827.14 seconds |
| Started | Aug 25 08:24:30 PM UTC 24 |
| Finished | Aug 25 08:55:35 PM UTC 24 |
| Peak memory | 625936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644658435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.2644658435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960322058 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3665066768 ps |
| CPU time | 586.44 seconds |
| Started | Aug 25 08:23:15 PM UTC 24 |
| Finished | Aug 25 08:33:14 PM UTC 24 |
| Peak memory | 672248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960322058 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_s leep_mode_alerts.2960322058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1842159947 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 12843092410 ps |
| CPU time | 1902.25 seconds |
| Started | Aug 25 08:24:52 PM UTC 24 |
| Finished | Aug 25 08:57:14 PM UTC 24 |
| Peak memory | 625992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842159947 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_hand ler_lpg_sleep_mode_pings.1842159947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_ok.3417851865 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 7764429692 ps |
| CPU time | 1821.59 seconds |
| Started | Aug 25 08:22:07 PM UTC 24 |
| Finished | Aug 25 08:53:04 PM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417851865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3417851865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_handler_ping_timeout.3446254900 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5412911110 ps |
| CPU time | 787.5 seconds |
| Started | Aug 25 08:20:40 PM UTC 24 |
| Finished | Aug 25 08:34:03 PM UTC 24 |
| Peak memory | 625740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446254900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3446254900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_alert_test.1208281802 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3574109162 ps |
| CPU time | 578.82 seconds |
| Started | Aug 25 08:20:46 PM UTC 24 |
| Finished | Aug 25 08:30:36 PM UTC 24 |
| Peak memory | 623876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=1208281802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aler t_test.1208281802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3043698452 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3816708776 ps |
| CPU time | 668.91 seconds |
| Started | Aug 25 08:10:41 PM UTC 24 |
| Finished | Aug 25 08:22:03 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043698452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3043698452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3818666068 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 8149420646 ps |
| CPU time | 731.85 seconds |
| Started | Aug 25 08:10:42 PM UTC 24 |
| Finished | Aug 25 08:23:09 PM UTC 24 |
| Peak memory | 623956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818666068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3818666068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_smoketest.3096635319 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3550369560 ps |
| CPU time | 413.18 seconds |
| Started | Aug 25 09:04:01 PM UTC 24 |
| Finished | Aug 25 09:11:03 PM UTC 24 |
| Peak memory | 623684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096635319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_aon_timer_smoketest.3096635319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.771614213 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 8338763004 ps |
| CPU time | 1193.18 seconds |
| Started | Aug 25 08:11:58 PM UTC 24 |
| Finished | Aug 25 08:32:13 PM UTC 24 |
| Peak memory | 625944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771614213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.771614213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2392421660 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 5233692876 ps |
| CPU time | 870.23 seconds |
| Started | Aug 25 08:13:07 PM UTC 24 |
| Finished | Aug 25 08:27:55 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392421660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2392421660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_outputs.3367500890 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 7743582568 ps |
| CPU time | 1485.87 seconds |
| Started | Aug 25 08:46:49 PM UTC 24 |
| Finished | Aug 25 09:12:04 PM UTC 24 |
| Peak memory | 632092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=3367500890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3367500890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1647182316 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 14694022416 ps |
| CPU time | 2081.53 seconds |
| Started | Aug 25 08:57:57 PM UTC 24 |
| Finished | Aug 25 09:33:19 PM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647182316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1647182316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2328554639 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 6825963496 ps |
| CPU time | 727.33 seconds |
| Started | Aug 25 08:41:18 PM UTC 24 |
| Finished | Aug 25 08:53:41 PM UTC 24 |
| Peak memory | 638316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328554639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2328554639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2604697805 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 4037184220 ps |
| CPU time | 804.51 seconds |
| Started | Aug 25 08:42:24 PM UTC 24 |
| Finished | Aug 25 08:56:06 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604697805 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.2604697805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3973135112 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 3833075098 ps |
| CPU time | 753.45 seconds |
| Started | Aug 25 08:44:55 PM UTC 24 |
| Finished | Aug 25 08:57:45 PM UTC 24 |
| Peak memory | 625612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973135112 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.3973135112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.801019700 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 4101357968 ps |
| CPU time | 972.06 seconds |
| Started | Aug 25 08:41:52 PM UTC 24 |
| Finished | Aug 25 08:58:26 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801 019700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_extern al_clk_src_for_sw_fast_test_unlocked0.801019700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1972700545 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 4046709160 ps |
| CPU time | 754.79 seconds |
| Started | Aug 25 08:43:23 PM UTC 24 |
| Finished | Aug 25 08:56:14 PM UTC 24 |
| Peak memory | 625880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972700545 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.1972700545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.784207042 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 5037156600 ps |
| CPU time | 776.58 seconds |
| Started | Aug 25 08:44:44 PM UTC 24 |
| Finished | Aug 25 08:57:56 PM UTC 24 |
| Peak memory | 626004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784207042 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src _for_sw_slow_rma.784207042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2191877810 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4703990796 ps |
| CPU time | 868.4 seconds |
| Started | Aug 25 08:41:53 PM UTC 24 |
| Finished | Aug 25 08:56:40 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219 1877810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.2191877810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter.2445880791 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2841474318 ps |
| CPU time | 375.98 seconds |
| Started | Aug 25 08:44:55 PM UTC 24 |
| Finished | Aug 25 08:51:18 PM UTC 24 |
| Peak memory | 623824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2445880791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_clkmgr_jitter.2445880791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1556670014 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 4140013916 ps |
| CPU time | 591.63 seconds |
| Started | Aug 25 08:44:57 PM UTC 24 |
| Finished | Aug 25 08:55:01 PM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=1556670014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_clkmgr_jitter_frequency.1556670014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1556538087 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2911454503 ps |
| CPU time | 348.98 seconds |
| Started | Aug 25 08:52:56 PM UTC 24 |
| Finished | Aug 25 08:58:53 PM UTC 24 |
| Peak memory | 625752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1556538087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1556538087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2863697475 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4294496580 ps |
| CPU time | 688.73 seconds |
| Started | Aug 25 08:40:31 PM UTC 24 |
| Finished | Aug 25 08:52:14 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2863697475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2863697475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1603197164 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4022073648 ps |
| CPU time | 686 seconds |
| Started | Aug 25 08:41:04 PM UTC 24 |
| Finished | Aug 25 08:52:45 PM UTC 24 |
| Peak memory | 625748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1603197164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_hmac_trans.1603197164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.444045953 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 4711703610 ps |
| CPU time | 794.99 seconds |
| Started | Aug 25 08:41:19 PM UTC 24 |
| Finished | Aug 25 08:54:51 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=444045953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.444045953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4140818840 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 4220926952 ps |
| CPU time | 614.82 seconds |
| Started | Aug 25 08:41:20 PM UTC 24 |
| Finished | Aug 25 08:51:47 PM UTC 24 |
| Peak memory | 625836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4140818840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_clkmgr_off_otbn_trans.4140818840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_off_peri.2192330057 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 9250188900 ps |
| CPU time | 1417.06 seconds |
| Started | Aug 25 08:40:22 PM UTC 24 |
| Finished | Aug 25 09:04:26 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192330057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2192330057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_reset_frequency.3372000982 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3119633196 ps |
| CPU time | 467.34 seconds |
| Started | Aug 25 08:44:42 PM UTC 24 |
| Finished | Aug 25 08:52:40 PM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372000982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3372000982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1486829472 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 4249443288 ps |
| CPU time | 778.64 seconds |
| Started | Aug 25 08:44:58 PM UTC 24 |
| Finished | Aug 25 08:58:13 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486829472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1486829472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_clkmgr_smoketest.478164562 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2797288088 ps |
| CPU time | 386.94 seconds |
| Started | Aug 25 09:04:21 PM UTC 24 |
| Finished | Aug 25 09:10:56 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=478164562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _clkmgr_smoketest.478164562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.1033643653 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 26277778010 ps |
| CPU time | 9693.49 seconds |
| Started | Aug 25 08:29:17 PM UTC 24 |
| Finished | Aug 25 11:13:55 PM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1033643653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_csrng_edn_concurrency.1033643653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2561182696 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 25365200959 ps |
| CPU time | 7254.95 seconds |
| Started | Aug 25 08:55:50 PM UTC 24 |
| Finished | Aug 25 10:58:56 PM UTC 24 |
| Peak memory | 628844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561182696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2561182696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3353480906 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4453846072 ps |
| CPU time | 826.06 seconds |
| Started | Aug 25 08:29:49 PM UTC 24 |
| Finished | Aug 25 08:43:53 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353480906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3353480906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_kat_test.1293355097 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2750607440 ps |
| CPU time | 427.13 seconds |
| Started | Aug 25 08:28:50 PM UTC 24 |
| Finished | Aug 25 08:36:07 PM UTC 24 |
| Peak memory | 623760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293355097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_csrng_kat_test.1293355097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1667456201 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 6544847147 ps |
| CPU time | 879.06 seconds |
| Started | Aug 25 08:29:46 PM UTC 24 |
| Finished | Aug 25 08:44:43 PM UTC 24 |
| Peak memory | 623888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667456201 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_lc_hw_debug_en_test.1667456201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_smoketest.1072728187 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2129965880 ps |
| CPU time | 259.9 seconds |
| Started | Aug 25 09:05:23 PM UTC 24 |
| Finished | Aug 25 09:09:48 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1072728187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_smoketest.1072728187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.3008454857 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5034382520 ps |
| CPU time | 1200.54 seconds |
| Started | Aug 25 07:17:52 PM UTC 24 |
| Finished | Aug 25 07:38:15 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008454857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3008454857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_auto_mode.803312666 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4120443570 ps |
| CPU time | 1523.96 seconds |
| Started | Aug 25 08:25:19 PM UTC 24 |
| Finished | Aug 25 08:51:14 PM UTC 24 |
| Peak memory | 623944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803312666 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_auto_mode.803312666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_boot_mode.1601571986 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3270209800 ps |
| CPU time | 770.85 seconds |
| Started | Aug 25 08:25:48 PM UTC 24 |
| Finished | Aug 25 08:38:55 PM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601571986 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_boot_mode.1601571986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs.2595573140 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 5484809482 ps |
| CPU time | 1213.95 seconds |
| Started | Aug 25 08:29:55 PM UTC 24 |
| Finished | Aug 25 08:50:35 PM UTC 24 |
| Peak memory | 625828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595573140 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2595573140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3615764634 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 6628762423 ps |
| CPU time | 1712.74 seconds |
| Started | Aug 25 08:31:22 PM UTC 24 |
| Finished | Aug 25 09:00:30 PM UTC 24 |
| Peak memory | 625980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615764634 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3615764634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_kat.4183181686 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3371013248 ps |
| CPU time | 846.76 seconds |
| Started | Aug 25 08:27:19 PM UTC 24 |
| Finished | Aug 25 08:41:43 PM UTC 24 |
| Peak memory | 631980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=4183181686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_edn_kat.4183181686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_edn_sw_mode.886473814 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 6421390760 ps |
| CPU time | 2100.93 seconds |
| Started | Aug 25 08:29:05 PM UTC 24 |
| Finished | Aug 25 09:04:45 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=886473814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_edn_sw_mode.886473814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2257977263 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2136175990 ps |
| CPU time | 330.73 seconds |
| Started | Aug 25 08:29:43 PM UTC 24 |
| Finished | Aug 25 08:35:21 PM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257977263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2257977263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_csrng.421345633 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8107071244 ps |
| CPU time | 2137.97 seconds |
| Started | Aug 25 08:29:51 PM UTC 24 |
| Finished | Aug 25 09:06:11 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421345633 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.421345633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_kat_test.1192821979 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2613593706 ps |
| CPU time | 408.28 seconds |
| Started | Aug 25 08:25:13 PM UTC 24 |
| Finished | Aug 25 08:32:11 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192821979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1192821979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_entropy_src_smoketest.2806263884 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 2909140144 ps |
| CPU time | 558.54 seconds |
| Started | Aug 25 09:06:16 PM UTC 24 |
| Finished | Aug 25 09:15:46 PM UTC 24 |
| Peak memory | 623644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806263884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2806263884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.2058792231 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2962851480 ps |
| CPU time | 285.67 seconds |
| Started | Aug 25 07:14:38 PM UTC 24 |
| Finished | Aug 25 07:19:30 PM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2058792231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.2058792231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2907680737 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2145479990 ps |
| CPU time | 253.97 seconds |
| Started | Aug 25 07:12:26 PM UTC 24 |
| Finished | Aug 25 07:16:46 PM UTC 24 |
| Peak memory | 623452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2907680737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_example_flash.2907680737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.398578810 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2592588530 ps |
| CPU time | 325.62 seconds |
| Started | Aug 25 07:14:33 PM UTC 24 |
| Finished | Aug 25 07:20:08 PM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=398578810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exa mple_manufacturer.398578810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.2732888947 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3001572280 ps |
| CPU time | 193.16 seconds |
| Started | Aug 25 07:12:40 PM UTC 24 |
| Finished | Aug 25 07:15:57 PM UTC 24 |
| Peak memory | 623480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2732888947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_example_rom.2732888947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_crash_alert.2894683162 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 5807824142 ps |
| CPU time | 886.18 seconds |
| Started | Aug 25 08:52:51 PM UTC 24 |
| Finished | Aug 25 09:07:54 PM UTC 24 |
| Peak memory | 626160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894683162 -assert nopostproc +UVM_TESTNAME=chip_base_test + UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2894683162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.4292342229 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5810384592 ps |
| CPU time | 1268.23 seconds |
| Started | Aug 25 07:36:09 PM UTC 24 |
| Finished | Aug 25 07:57:40 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4292342229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _flash_ctrl_access.4292342229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2401736949 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5642251194 ps |
| CPU time | 1514.63 seconds |
| Started | Aug 25 07:36:10 PM UTC 24 |
| Finished | Aug 25 08:01:54 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2401736949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_flash_ctrl_access_jitter_en.2401736949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2969178764 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 7367692387 ps |
| CPU time | 1458.75 seconds |
| Started | Aug 25 08:53:00 PM UTC 24 |
| Finished | Aug 25 09:17:45 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969178764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2969178764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.871850269 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 6009180902 ps |
| CPU time | 1390.72 seconds |
| Started | Aug 25 07:38:55 PM UTC 24 |
| Finished | Aug 25 08:02:31 PM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=871850269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_flash_ctrl_clock_freqs.871850269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1696059005 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3712422954 ps |
| CPU time | 528.69 seconds |
| Started | Aug 25 07:36:38 PM UTC 24 |
| Finished | Aug 25 07:45:37 PM UTC 24 |
| Peak memory | 625932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1696059005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_flash_ctrl_idle_low_power.1696059005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1763329380 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5339938232 ps |
| CPU time | 677.87 seconds |
| Started | Aug 25 07:35:15 PM UTC 24 |
| Finished | Aug 25 07:46:46 PM UTC 24 |
| Peak memory | 625812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763329380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1763329380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_mem_protection.960849647 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 6146989618 ps |
| CPU time | 1463.63 seconds |
| Started | Aug 25 08:58:49 PM UTC 24 |
| Finished | Aug 25 09:23:40 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=960849647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_flash_ctrl_mem_protection.960849647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.4259112610 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3884697632 ps |
| CPU time | 940.56 seconds |
| Started | Aug 25 07:33:40 PM UTC 24 |
| Finished | Aug 25 07:49:38 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259112610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.4259112610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.712210756 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4282463052 ps |
| CPU time | 1078.88 seconds |
| Started | Aug 25 07:35:14 PM UTC 24 |
| Finished | Aug 25 07:53:33 PM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712210756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.712210756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_write_clear.2865868777 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3159262542 ps |
| CPU time | 476.71 seconds |
| Started | Aug 25 08:52:54 PM UTC 24 |
| Finished | Aug 25 09:01:01 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865868777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2865868777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.1752834867 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 22382015921 ps |
| CPU time | 2743.5 seconds |
| Started | Aug 25 07:36:33 PM UTC 24 |
| Finished | Aug 25 08:23:07 PM UTC 24 |
| Peak memory | 627868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752834867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1752834867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2275878494 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 25338877617 ps |
| CPU time | 2517.6 seconds |
| Started | Aug 25 08:55:27 PM UTC 24 |
| Finished | Aug 25 09:38:12 PM UTC 24 |
| Peak memory | 629996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275878494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2275878494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_scrambling_smoketest.2220142045 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2787162552 ps |
| CPU time | 223.62 seconds |
| Started | Aug 25 08:59:20 PM UTC 24 |
| Finished | Aug 25 09:03:08 PM UTC 24 |
| Peak memory | 625820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220142045 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2220142045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_gpio_smoketest.1072030582 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 3090556119 ps |
| CPU time | 375.15 seconds |
| Started | Aug 25 09:04:04 PM UTC 24 |
| Finished | Aug 25 09:10:26 PM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1072030582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_gpio_smoketest.1072030582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc.3659009596 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 3261893156 ps |
| CPU time | 370.49 seconds |
| Started | Aug 25 08:31:24 PM UTC 24 |
| Finished | Aug 25 08:37:44 PM UTC 24 |
| Peak memory | 623772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3659009596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_enc.3659009596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_idle.597256479 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 3619513000 ps |
| CPU time | 462 seconds |
| Started | Aug 25 08:32:15 PM UTC 24 |
| Finished | Aug 25 08:40:07 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=597256479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_hmac_enc_idle.597256479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en.1109578348 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3728566847 ps |
| CPU time | 406.98 seconds |
| Started | Aug 25 08:31:55 PM UTC 24 |
| Finished | Aug 25 08:38:50 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1109578348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_hmac_enc_jitter_en.1109578348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1484381546 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 2629641493 ps |
| CPU time | 293.25 seconds |
| Started | Aug 25 08:53:51 PM UTC 24 |
| Finished | Aug 25 08:58:51 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484381546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1484381546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_multistream.2361155529 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 7879214200 ps |
| CPU time | 2666.02 seconds |
| Started | Aug 25 08:33:42 PM UTC 24 |
| Finished | Aug 25 09:19:00 PM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2361155529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_multistream.2361155529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.3550209138 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 3424548194 ps |
| CPU time | 456.97 seconds |
| Started | Aug 25 08:32:34 PM UTC 24 |
| Finished | Aug 25 08:40:20 PM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=3550209138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_h mac_oneshot.3550209138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_smoketest.2200486950 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 3541162108 ps |
| CPU time | 489.44 seconds |
| Started | Aug 25 09:06:04 PM UTC 24 |
| Finished | Aug 25 09:14:24 PM UTC 24 |
| Peak memory | 623728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2200486950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ hmac_smoketest.2200486950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.2373799284 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4739999196 ps |
| CPU time | 929.84 seconds |
| Started | Aug 25 07:25:34 PM UTC 24 |
| Finished | Aug 25 07:41:20 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2373799284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2373799284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.2176997449 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4836938500 ps |
| CPU time | 991.52 seconds |
| Started | Aug 25 07:25:03 PM UTC 24 |
| Finished | Aug 25 07:41:51 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2176997449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx.2176997449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1245124694 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4602682856 ps |
| CPU time | 1138.19 seconds |
| Started | Aug 25 07:25:06 PM UTC 24 |
| Finished | Aug 25 07:44:25 PM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1245124694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1245124694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1088607175 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5704029672 ps |
| CPU time | 1049.68 seconds |
| Started | Aug 25 07:25:07 PM UTC 24 |
| Finished | Aug 25 07:42:55 PM UTC 24 |
| Peak memory | 623860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1088607175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1088607175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation.895855215 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 10713278608 ps |
| CPU time | 2485.79 seconds |
| Started | Aug 25 08:33:28 PM UTC 24 |
| Finished | Aug 25 09:15:43 PM UTC 24 |
| Peak memory | 632132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895855215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_ derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.895855215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1820143695 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 10895168505 ps |
| CPU time | 2507.15 seconds |
| Started | Aug 25 08:35:05 PM UTC 24 |
| Finished | Aug 25 09:17:39 PM UTC 24 |
| Peak memory | 632088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820143695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1820143695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.636942033 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 12090494727 ps |
| CPU time | 2477.05 seconds |
| Started | Aug 25 08:54:25 PM UTC 24 |
| Finished | Aug 25 09:36:31 PM UTC 24 |
| Peak memory | 634220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636942033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.636942033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_prod.951369076 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 11011366452 ps |
| CPU time | 2706.99 seconds |
| Started | Aug 25 08:34:32 PM UTC 24 |
| Finished | Aug 25 09:20:32 PM UTC 24 |
| Peak memory | 632104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951369076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.951369076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_kmac.2223252925 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 9366625760 ps |
| CPU time | 2041.34 seconds |
| Started | Aug 25 08:35:44 PM UTC 24 |
| Finished | Aug 25 09:10:24 PM UTC 24 |
| Peak memory | 623880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223252925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2223252925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.952575233 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 14856418120 ps |
| CPU time | 5507.36 seconds |
| Started | Aug 25 08:35:41 PM UTC 24 |
| Finished | Aug 25 10:09:12 PM UTC 24 |
| Peak memory | 628968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952575233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.952575233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_app_rom.614696986 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2486655164 ps |
| CPU time | 355.54 seconds |
| Started | Aug 25 08:36:36 PM UTC 24 |
| Finished | Aug 25 08:42:39 PM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=614696986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_kmac_app_rom.614696986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.1890577701 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2516029136 ps |
| CPU time | 421.94 seconds |
| Started | Aug 25 07:39:59 PM UTC 24 |
| Finished | Aug 25 07:47:09 PM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=1890577701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_kmac_entropy.1890577701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_idle.4024053539 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 3000827204 ps |
| CPU time | 441.07 seconds |
| Started | Aug 25 08:35:43 PM UTC 24 |
| Finished | Aug 25 08:43:14 PM UTC 24 |
| Peak memory | 623748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4024053539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_idle.4024053539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_cshake.2232429641 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3004801544 ps |
| CPU time | 393.04 seconds |
| Started | Aug 25 08:36:23 PM UTC 24 |
| Finished | Aug 25 08:43:06 PM UTC 24 |
| Peak memory | 623612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2232429641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_kmac_mode_cshake.2232429641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac.4061295957 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2716789500 ps |
| CPU time | 550.55 seconds |
| Started | Aug 25 08:35:57 PM UTC 24 |
| Finished | Aug 25 08:45:20 PM UTC 24 |
| Peak memory | 623524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061295957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_kmac_mode_kmac.4061295957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.451081388 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3140301900 ps |
| CPU time | 405.06 seconds |
| Started | Aug 25 08:36:06 PM UTC 24 |
| Finished | Aug 25 08:43:00 PM UTC 24 |
| Peak memory | 623764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=451081388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_kmac_mode_kmac_jitter_en.451081388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1990750946 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3475778959 ps |
| CPU time | 480.38 seconds |
| Started | Aug 25 08:54:46 PM UTC 24 |
| Finished | Aug 25 09:02:56 PM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990750946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1990750946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_smoketest.1354333994 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3190722112 ps |
| CPU time | 440.27 seconds |
| Started | Aug 25 09:05:55 PM UTC 24 |
| Finished | Aug 25 09:13:24 PM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1354333994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ kmac_smoketest.1354333994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1017195687 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3069273900 ps |
| CPU time | 459.26 seconds |
| Started | Aug 25 07:41:37 PM UTC 24 |
| Finished | Aug 25 07:49:25 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1017195687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1017195687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_program_error.2310633117 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4728087370 ps |
| CPU time | 656.3 seconds |
| Started | Aug 25 08:47:22 PM UTC 24 |
| Finished | Aug 25 08:58:33 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310633117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2310633117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3430451874 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2950553738 ps |
| CPU time | 461.26 seconds |
| Started | Aug 25 07:46:29 PM UTC 24 |
| Finished | Aug 25 07:54:20 PM UTC 24 |
| Peak memory | 638012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430451874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3430451874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.2902749544 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 12562689113 ps |
| CPU time | 1305.55 seconds |
| Started | Aug 25 07:45:07 PM UTC 24 |
| Finished | Aug 25 08:07:14 PM UTC 24 |
| Peak memory | 636216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2902749544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_lc_ctrl_transition.2902749544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.754485126 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2466234535 ps |
| CPU time | 172.83 seconds |
| Started | Aug 25 07:47:50 PM UTC 24 |
| Finished | Aug 25 07:50:46 PM UTC 24 |
| Peak memory | 635536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754485126 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.754485126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2372469606 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2246492231 ps |
| CPU time | 157.74 seconds |
| Started | Aug 25 07:49:27 PM UTC 24 |
| Finished | Aug 25 07:52:09 PM UTC 24 |
| Peak memory | 633352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23724696 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.2372469606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3020130562 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 46035343898 ps |
| CPU time | 10475.6 seconds |
| Started | Aug 25 07:46:31 PM UTC 24 |
| Finished | Aug 25 10:44:21 PM UTC 24 |
| Peak memory | 643488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020130562 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_dev.3020130562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.1779623438 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 48251990692 ps |
| CPU time | 9716.24 seconds |
| Started | Aug 25 07:47:32 PM UTC 24 |
| Finished | Aug 25 10:32:31 PM UTC 24 |
| Peak memory | 643376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779623438 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prod.1779623438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.1726324457 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 9616599272 ps |
| CPU time | 1447.03 seconds |
| Started | Aug 25 07:47:33 PM UTC 24 |
| Finished | Aug 25 08:12:06 PM UTC 24 |
| Peak memory | 640188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726324457 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1726324457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3656033233 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 47433522335 ps |
| CPU time | 8544.72 seconds |
| Started | Aug 25 07:49:44 PM UTC 24 |
| Finished | Aug 25 10:14:51 PM UTC 24 |
| Peak memory | 643236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656033233 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_rma.3656033233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3357599115 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 16558202560 ps |
| CPU time | 5445.1 seconds |
| Started | Aug 25 08:14:45 PM UTC 24 |
| Finished | Aug 25 09:47:14 PM UTC 24 |
| Peak memory | 626692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357599115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3357599115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.612864384 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 18684515954 ps |
| CPU time | 6342.52 seconds |
| Started | Aug 25 08:14:46 PM UTC 24 |
| Finished | Aug 25 10:02:28 PM UTC 24 |
| Peak memory | 629020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612864384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.612864384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4104920920 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 24173246076 ps |
| CPU time | 5907.33 seconds |
| Started | Aug 25 08:53:45 PM UTC 24 |
| Finished | Aug 25 10:34:04 PM UTC 24 |
| Peak memory | 628836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104920920 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4104920920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_mem_scramble.4192164526 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3939318748 ps |
| CPU time | 790.14 seconds |
| Started | Aug 25 08:15:04 PM UTC 24 |
| Finished | Aug 25 08:28:30 PM UTC 24 |
| Peak memory | 625576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn_mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192164526 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.4192164526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_randomness.1159359176 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6000436200 ps |
| CPU time | 1419.87 seconds |
| Started | Aug 25 08:14:44 PM UTC 24 |
| Finished | Aug 25 08:38:50 PM UTC 24 |
| Peak memory | 626188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159359176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1159359176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.462995268 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 7133021520 ps |
| CPU time | 2163.6 seconds |
| Started | Aug 25 09:06:05 PM UTC 24 |
| Finished | Aug 25 09:42:50 PM UTC 24 |
| Peak memory | 625972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=462995268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_o tbn_smoketest.462995268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2984915877 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3251128481 ps |
| CPU time | 455.43 seconds |
| Started | Aug 25 07:43:35 PM UTC 24 |
| Finished | Aug 25 07:51:20 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2984915877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2984915877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3171831456 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7236913864 ps |
| CPU time | 1457.12 seconds |
| Started | Aug 25 07:42:14 PM UTC 24 |
| Finished | Aug 25 08:06:59 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171831456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3171831456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3682304512 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 9682116450 ps |
| CPU time | 1971.04 seconds |
| Started | Aug 25 07:42:54 PM UTC 24 |
| Finished | Aug 25 08:16:22 PM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682304512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3682304512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2640387453 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 9137782688 ps |
| CPU time | 1887.23 seconds |
| Started | Aug 25 07:42:56 PM UTC 24 |
| Finished | Aug 25 08:15:00 PM UTC 24 |
| Peak memory | 623816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640387453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2640387453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1778220530 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4964078728 ps |
| CPU time | 878.34 seconds |
| Started | Aug 25 07:42:14 PM UTC 24 |
| Finished | Aug 25 07:57:10 PM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778220530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1778220530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_smoketest.3859444682 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 3208069160 ps |
| CPU time | 400.96 seconds |
| Started | Aug 25 09:04:44 PM UTC 24 |
| Finished | Aug 25 09:11:34 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3859444682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_otp_ctrl_smoketest.3859444682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.3657609510 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2663449368 ps |
| CPU time | 416.53 seconds |
| Started | Aug 25 07:18:17 PM UTC 24 |
| Finished | Aug 25 07:25:24 PM UTC 24 |
| Peak memory | 623656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657609510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3657609510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_plic_sw_irq.569242766 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2689360340 ps |
| CPU time | 352.92 seconds |
| Started | Aug 25 08:40:27 PM UTC 24 |
| Finished | Aug 25 08:46:28 PM UTC 24 |
| Peak memory | 623900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=569242766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _plic_sw_irq.569242766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_idle_load.2471035209 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4566179700 ps |
| CPU time | 836.85 seconds |
| Started | Aug 25 08:55:51 PM UTC 24 |
| Finished | Aug 25 09:10:03 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471035209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_power_idle_load.2471035209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_sleep_load.182087328 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4767978054 ps |
| CPU time | 527.08 seconds |
| Started | Aug 25 08:57:39 PM UTC 24 |
| Finished | Aug 25 09:06:36 PM UTC 24 |
| Peak memory | 625772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=182087328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_power_sleep_load.182087328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.2945388818 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5444298682 ps |
| CPU time | 1867.18 seconds |
| Started | Aug 25 08:59:22 PM UTC 24 |
| Finished | Aug 25 09:31:03 PM UTC 24 |
| Peak memory | 640636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945388818 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2945388818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.140469562 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9713934180 ps |
| CPU time | 1797.68 seconds |
| Started | Aug 25 07:57:00 PM UTC 24 |
| Finished | Aug 25 08:27:32 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140469562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_ all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.140469562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1847082961 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 23089205953 ps |
| CPU time | 3668.6 seconds |
| Started | Aug 25 08:38:30 PM UTC 24 |
| Finished | Aug 25 09:40:46 PM UTC 24 |
| Peak memory | 626068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847082961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1847082961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1523193147 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 14202249949 ps |
| CPU time | 2294.75 seconds |
| Started | Aug 25 07:58:37 PM UTC 24 |
| Finished | Aug 25 08:37:34 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523193147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1523193147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.348700301 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 22869631680 ps |
| CPU time | 3098.88 seconds |
| Started | Aug 25 08:47:34 PM UTC 24 |
| Finished | Aug 25 09:40:09 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348700301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_ deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.348700301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1139881888 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 6882223814 ps |
| CPU time | 891.93 seconds |
| Started | Aug 25 07:58:41 PM UTC 24 |
| Finished | Aug 25 08:13:50 PM UTC 24 |
| Peak memory | 623872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1139881888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1139881888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1003237871 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 6855094908 ps |
| CPU time | 815.95 seconds |
| Started | Aug 25 08:02:35 PM UTC 24 |
| Finished | Aug 25 08:16:28 PM UTC 24 |
| Peak memory | 631872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003237871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1003237871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3541676032 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 8930823056 ps |
| CPU time | 695.52 seconds |
| Started | Aug 25 07:53:09 PM UTC 24 |
| Finished | Aug 25 08:04:58 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3541676032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_full_aon_reset.3541676032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.427203555 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4272186998 ps |
| CPU time | 699.59 seconds |
| Started | Aug 25 08:48:24 PM UTC 24 |
| Finished | Aug 25 09:00:19 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=427203555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_lowpower_cancel.427203555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1989871570 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 4036705616 ps |
| CPU time | 690.5 seconds |
| Started | Aug 25 07:54:16 PM UTC 24 |
| Finished | Aug 25 08:05:59 PM UTC 24 |
| Peak memory | 631740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989871570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1989871570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2835505555 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 11377610269 ps |
| CPU time | 2028.98 seconds |
| Started | Aug 25 07:58:36 PM UTC 24 |
| Finished | Aug 25 08:33:04 PM UTC 24 |
| Peak memory | 625788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2835505555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2835505555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4160082828 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 7574049170 ps |
| CPU time | 476.35 seconds |
| Started | Aug 25 08:47:21 PM UTC 24 |
| Finished | Aug 25 08:55:29 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4160082828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4160082828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1991075271 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 6031853408 ps |
| CPU time | 764.35 seconds |
| Started | Aug 25 08:00:34 PM UTC 24 |
| Finished | Aug 25 08:13:33 PM UTC 24 |
| Peak memory | 625908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1991075271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1991075271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.5525749 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 23144563094 ps |
| CPU time | 3642.38 seconds |
| Started | Aug 25 07:57:51 PM UTC 24 |
| Finished | Aug 25 08:59:43 PM UTC 24 |
| Peak memory | 625996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5525749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.5525749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4115990661 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 24130592424 ps |
| CPU time | 2570.13 seconds |
| Started | Aug 25 08:48:26 PM UTC 24 |
| Finished | Aug 25 09:32:03 PM UTC 24 |
| Peak memory | 625904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115990661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4115990661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1756069114 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4830068120 ps |
| CPU time | 640.32 seconds |
| Started | Aug 25 08:48:25 PM UTC 24 |
| Finished | Aug 25 08:59:18 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756069114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1756069114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3151049090 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3006664428 ps |
| CPU time | 350.9 seconds |
| Started | Aug 25 08:03:51 PM UTC 24 |
| Finished | Aug 25 08:09:49 PM UTC 24 |
| Peak memory | 623532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3151049090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.chip_sw_pwrmgr_sleep_disabled.3151049090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1253797061 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4774427000 ps |
| CPU time | 552.69 seconds |
| Started | Aug 25 08:37:45 PM UTC 24 |
| Finished | Aug 25 08:47:10 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253797061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1253797061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1247501112 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 6235019084 ps |
| CPU time | 768.01 seconds |
| Started | Aug 25 08:48:20 PM UTC 24 |
| Finished | Aug 25 09:01:24 PM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247501112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1247501112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_smoketest.1538983563 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5567131920 ps |
| CPU time | 611.69 seconds |
| Started | Aug 25 09:05:25 PM UTC 24 |
| Finished | Aug 25 09:15:49 PM UTC 24 |
| Peak memory | 623808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538983563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1538983563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1634856239 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 7850239066 ps |
| CPU time | 1446.51 seconds |
| Started | Aug 25 07:55:02 PM UTC 24 |
| Finished | Aug 25 08:19:36 PM UTC 24 |
| Peak memory | 625888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1634856239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1634856239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2309200696 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4984332110 ps |
| CPU time | 713.85 seconds |
| Started | Aug 25 08:05:01 PM UTC 24 |
| Finished | Aug 25 08:17:08 PM UTC 24 |
| Peak memory | 625928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2309200696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2309200696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.440437517 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 6457216380 ps |
| CPU time | 623.72 seconds |
| Started | Aug 25 09:04:14 PM UTC 24 |
| Finished | Aug 25 09:14:50 PM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=440437517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_pwrmgr_usbdev_smoketest.440437517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.217899647 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 5188855884 ps |
| CPU time | 625.29 seconds |
| Started | Aug 25 08:13:01 PM UTC 24 |
| Finished | Aug 25 08:23:38 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217899647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.217899647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3510130536 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 9712903996 ps |
| CPU time | 678.3 seconds |
| Started | Aug 25 08:36:05 PM UTC 24 |
| Finished | Aug 25 08:47:38 PM UTC 24 |
| Peak memory | 625924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3510130536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3510130536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.3793539700 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 10682681292 ps |
| CPU time | 2039.99 seconds |
| Started | Aug 25 07:52:01 PM UTC 24 |
| Finished | Aug 25 08:26:38 PM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793539700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3793539700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.465198833 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5950062136 ps |
| CPU time | 995.14 seconds |
| Started | Aug 25 07:53:03 PM UTC 24 |
| Finished | Aug 25 08:09:58 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465198833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_rstmgr_cpu_info.465198833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.972967087 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4813110132 ps |
| CPU time | 1152.75 seconds |
| Started | Aug 25 07:17:01 PM UTC 24 |
| Finished | Aug 25 07:36:36 PM UTC 24 |
| Peak memory | 670072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972967087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_ cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.972967087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_smoketest.3552694582 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 2684494760 ps |
| CPU time | 301.44 seconds |
| Started | Aug 25 09:06:24 PM UTC 24 |
| Finished | Aug 25 09:11:33 PM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3552694582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rstmgr_smoketest.3552694582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.2574458388 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3375616332 ps |
| CPU time | 550.56 seconds |
| Started | Aug 25 07:50:22 PM UTC 24 |
| Finished | Aug 25 07:59:42 PM UTC 24 |
| Peak memory | 625580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2574458388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rstmgr_sw_req.2574458388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.1876657887 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2994313602 ps |
| CPU time | 369.04 seconds |
| Started | Aug 25 07:51:27 PM UTC 24 |
| Finished | Aug 25 07:57:43 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1876657887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_rstmgr_sw_rst.1876657887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4253069283 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3296837034 ps |
| CPU time | 388.34 seconds |
| Started | Aug 25 08:50:56 PM UTC 24 |
| Finished | Aug 25 08:57:32 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253069283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.4253069283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1732596405 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3287270879 ps |
| CPU time | 394.92 seconds |
| Started | Aug 25 08:52:12 PM UTC 24 |
| Finished | Aug 25 08:58:57 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1732596405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1732596405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1726948974 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5182736232 ps |
| CPU time | 1326.87 seconds |
| Started | Aug 25 08:16:07 PM UTC 24 |
| Finished | Aug 25 08:38:40 PM UTC 24 |
| Peak memory | 623712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726948974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1726948974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.3441052823 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 5404668696 ps |
| CPU time | 1497.62 seconds |
| Started | Aug 25 08:15:41 PM UTC 24 |
| Finished | Aug 25 08:41:09 PM UTC 24 |
| Peak memory | 623584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441052823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3441052823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.217187687 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5174201410 ps |
| CPU time | 584.08 seconds |
| Started | Aug 25 08:48:48 PM UTC 24 |
| Finished | Aug 25 08:58:45 PM UTC 24 |
| Peak memory | 635948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=217187687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esca lation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.217187687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2422915352 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5434226810 ps |
| CPU time | 605.58 seconds |
| Started | Aug 25 08:48:44 PM UTC 24 |
| Finished | Aug 25 08:59:05 PM UTC 24 |
| Peak memory | 636108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422915352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wak eup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.2422915352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2751310623 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5228648632 ps |
| CPU time | 735.8 seconds |
| Started | Aug 25 08:48:30 PM UTC 24 |
| Finished | Aug 25 09:01:02 PM UTC 24 |
| Peak memory | 638244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751310623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2751310623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_plic_smoketest.351097415 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 2573990600 ps |
| CPU time | 257.65 seconds |
| Started | Aug 25 09:06:14 PM UTC 24 |
| Finished | Aug 25 09:10:38 PM UTC 24 |
| Peak memory | 625960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=351097415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_rv_plic_smoketest.351097415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.1719434594 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3430754180 ps |
| CPU time | 369.97 seconds |
| Started | Aug 25 08:04:58 PM UTC 24 |
| Finished | Aug 25 08:11:16 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1719434594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_irq.1719434594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_smoketest.3950434033 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2578209170 ps |
| CPU time | 372.67 seconds |
| Started | Aug 25 09:06:26 PM UTC 24 |
| Finished | Aug 25 09:12:46 PM UTC 24 |
| Peak memory | 625804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3950434033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_rv_timer_smoketest.3950434033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_alert.1707201429 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5012470250 ps |
| CPU time | 833.38 seconds |
| Started | Aug 25 08:37:14 PM UTC 24 |
| Finished | Aug 25 08:51:25 PM UTC 24 |
| Peak memory | 623884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707201429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1707201429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sensor_ctrl_status.3294347904 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2997925681 ps |
| CPU time | 374.52 seconds |
| Started | Aug 25 08:37:41 PM UTC 24 |
| Finished | Aug 25 08:44:03 PM UTC 24 |
| Peak memory | 626092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294347904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3294347904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.2953861360 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3292126180 ps |
| CPU time | 363.61 seconds |
| Started | Aug 25 07:17:51 PM UTC 24 |
| Finished | Aug 25 07:24:02 PM UTC 24 |
| Peak memory | 623880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2953861360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sleep_pin_retention.2953861360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.3186684522 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 8934722760 ps |
| CPU time | 2018.17 seconds |
| Started | Aug 25 07:18:10 PM UTC 24 |
| Finished | Aug 25 07:52:24 PM UTC 24 |
| Peak memory | 625948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3186684522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sleep_pwm_pulses.3186684522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3756605565 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 6962410440 ps |
| CPU time | 644.76 seconds |
| Started | Aug 25 08:37:08 PM UTC 24 |
| Finished | Aug 25 08:48:07 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756605565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents _no_scramble.3756605565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.127819077 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7192697262 ps |
| CPU time | 704.74 seconds |
| Started | Aug 25 08:37:13 PM UTC 24 |
| Finished | Aug 25 08:49:13 PM UTC 24 |
| Peak memory | 625780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127819077 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_sram_ret_contents_scramble.127819077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2426103254 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6636475786 ps |
| CPU time | 1073.96 seconds |
| Started | Aug 25 07:30:33 PM UTC 24 |
| Finished | Aug 25 07:48:47 PM UTC 24 |
| Peak memory | 640248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426103254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_spi_device_pass_through.2426103254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.1274959566 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3916132763 ps |
| CPU time | 595.98 seconds |
| Started | Aug 25 07:31:17 PM UTC 24 |
| Finished | Aug 25 07:41:24 PM UTC 24 |
| Peak memory | 640252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274959566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1274959566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3402805565 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3832370382 ps |
| CPU time | 517.02 seconds |
| Started | Aug 25 07:30:33 PM UTC 24 |
| Finished | Aug 25 07:39:20 PM UTC 24 |
| Peak memory | 636356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3402805565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3402805565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_tpm.3003524998 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3577234160 ps |
| CPU time | 537.52 seconds |
| Started | Aug 25 07:26:07 PM UTC 24 |
| Finished | Aug 25 07:35:14 PM UTC 24 |
| Peak memory | 636380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3003524998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_spi_device_tpm.3003524998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_host_tx_rx.3471333046 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3360357710 ps |
| CPU time | 480.89 seconds |
| Started | Aug 25 07:27:39 PM UTC 24 |
| Finished | Aug 25 07:35:50 PM UTC 24 |
| Peak memory | 624036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471333046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_spi_host_tx_rx.3471333046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_execution_main.2425493820 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 9166197063 ps |
| CPU time | 1343.58 seconds |
| Started | Aug 25 08:37:05 PM UTC 24 |
| Finished | Aug 25 08:59:55 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2425493820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2425493820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2499457804 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4696570168 ps |
| CPU time | 804.06 seconds |
| Started | Aug 25 08:36:18 PM UTC 24 |
| Finished | Aug 25 08:50:00 PM UTC 24 |
| Peak memory | 625968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499457804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_ access.2499457804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3894846327 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4047925867 ps |
| CPU time | 632.41 seconds |
| Started | Aug 25 08:36:37 PM UTC 24 |
| Finished | Aug 25 08:47:24 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894846327 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ct rl_scrambled_access_jitter_en.3894846327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3297168239 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4278641541 ps |
| CPU time | 790.95 seconds |
| Started | Aug 25 08:55:06 PM UTC 24 |
| Finished | Aug 25 09:08:33 PM UTC 24 |
| Peak memory | 625672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297168239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3297168239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sram_ctrl_smoketest.3736459351 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2417521318 ps |
| CPU time | 231.87 seconds |
| Started | Aug 25 09:06:25 PM UTC 24 |
| Finished | Aug 25 09:10:23 PM UTC 24 |
| Peak memory | 623588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736459351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_sram_ctrl_smoketest.3736459351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3293458420 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 20671860437 ps |
| CPU time | 4930.6 seconds |
| Started | Aug 25 08:09:40 PM UTC 24 |
| Finished | Aug 25 09:33:25 PM UTC 24 |
| Peak memory | 625948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3293458420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3293458420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1417462021 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4591955720 ps |
| CPU time | 934.97 seconds |
| Started | Aug 25 08:06:38 PM UTC 24 |
| Finished | Aug 25 08:22:33 PM UTC 24 |
| Peak memory | 626076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1417462021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1417462021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2517819727 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3022687117 ps |
| CPU time | 512.57 seconds |
| Started | Aug 25 08:05:39 PM UTC 24 |
| Finished | Aug 25 08:14:22 PM UTC 24 |
| Peak memory | 627868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2517819727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_sysrst_ctrl_inputs.2517819727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1844050945 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 4164449160 ps |
| CPU time | 633.28 seconds |
| Started | Aug 25 08:08:53 PM UTC 24 |
| Finished | Aug 25 08:19:38 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1844050945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1844050945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2363626715 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 25463333182 ps |
| CPU time | 2283.32 seconds |
| Started | Aug 25 08:07:58 PM UTC 24 |
| Finished | Aug 25 08:46:45 PM UTC 24 |
| Peak memory | 630124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363626715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2363626715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.19791930 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5710275040 ps |
| CPU time | 706.09 seconds |
| Started | Aug 25 08:07:51 PM UTC 24 |
| Finished | Aug 25 08:19:51 PM UTC 24 |
| Peak memory | 625988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=19791930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.19791930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.3358669961 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 8711861080 ps |
| CPU time | 2527.48 seconds |
| Started | Aug 25 07:21:05 PM UTC 24 |
| Finished | Aug 25 08:03:58 PM UTC 24 |
| Peak memory | 636196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358669961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.3358669961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_smoketest.3129083209 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2600063478 ps |
| CPU time | 316.09 seconds |
| Started | Aug 25 09:06:23 PM UTC 24 |
| Finished | Aug 25 09:11:45 PM UTC 24 |
| Peak memory | 629796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3129083209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_sw_uart_smoketest.3129083209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1585760316 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4057911236 ps |
| CPU time | 925.34 seconds |
| Started | Aug 25 07:18:46 PM UTC 24 |
| Finished | Aug 25 07:34:28 PM UTC 24 |
| Peak memory | 640232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585760316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1585760316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1532814917 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 8983944599 ps |
| CPU time | 2423.47 seconds |
| Started | Aug 25 07:22:44 PM UTC 24 |
| Finished | Aug 25 08:03:51 PM UTC 24 |
| Peak memory | 636244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532814917 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq.1532814917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4288540191 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3845506641 ps |
| CPU time | 603.15 seconds |
| Started | Aug 25 07:22:45 PM UTC 24 |
| Finished | Aug 25 07:32:59 PM UTC 24 |
| Peak memory | 636172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288540191 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4288540191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.1296644954 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4520523392 ps |
| CPU time | 912.92 seconds |
| Started | Aug 25 07:19:49 PM UTC 24 |
| Finished | Aug 25 07:35:19 PM UTC 24 |
| Peak memory | 640216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296644954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1296644954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.336832730 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 4263429188 ps |
| CPU time | 913.97 seconds |
| Started | Aug 25 07:20:20 PM UTC 24 |
| Finished | Aug 25 07:35:50 PM UTC 24 |
| Peak memory | 640212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336832730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.336832730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.4195447417 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3968775766 ps |
| CPU time | 799.86 seconds |
| Started | Aug 25 07:20:43 PM UTC 24 |
| Finished | Aug 25 07:34:18 PM UTC 24 |
| Peak memory | 640068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195447417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.4195447417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_prod.4079292997 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 2358713014 ps |
| CPU time | 228.87 seconds |
| Started | Aug 25 08:50:31 PM UTC 24 |
| Finished | Aug 25 08:54:26 PM UTC 24 |
| Peak memory | 637480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079292997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4079292997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_rma.1637729538 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 7128457406 ps |
| CPU time | 734.95 seconds |
| Started | Aug 25 08:49:58 PM UTC 24 |
| Finished | Aug 25 09:02:28 PM UTC 24 |
| Peak memory | 648620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637729538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1637729538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.2466010443 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 5539783965 ps |
| CPU time | 772.37 seconds |
| Started | Aug 25 08:49:44 PM UTC 24 |
| Finished | Aug 25 09:02:52 PM UTC 24 |
| Peak memory | 650868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466010443 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2466010443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.2158232639 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 15652616347 ps |
| CPU time | 6034.8 seconds |
| Started | Aug 25 09:05:00 PM UTC 24 |
| Finished | Aug 25 10:47:27 PM UTC 24 |
| Peak memory | 626904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158232639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.2158232639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.3295852415 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 15770220406 ps |
| CPU time | 6346.15 seconds |
| Started | Aug 25 09:04:47 PM UTC 24 |
| Finished | Aug 25 10:52:30 PM UTC 24 |
| Peak memory | 628956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295852415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3295852415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2699226344 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 15218019861 ps |
| CPU time | 5614.2 seconds |
| Started | Aug 25 09:05:22 PM UTC 24 |
| Finished | Aug 25 10:40:40 PM UTC 24 |
| Peak memory | 627136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269922 6344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_in it_prod_end.2699226344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.1350949007 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 14883557539 ps |
| CPU time | 4932.17 seconds |
| Started | Aug 25 09:04:22 PM UTC 24 |
| Finished | Aug 25 10:28:08 PM UTC 24 |
| Peak memory | 629184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350949007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1350949007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.789396659 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 11071469869 ps |
| CPU time | 4833.49 seconds |
| Started | Aug 25 09:03:52 PM UTC 24 |
| Finished | Aug 25 10:25:57 PM UTC 24 |
| Peak memory | 627092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=789396659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2 e_asm_init_test_unlocked0.789396659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.128252758 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 14665937510 ps |
| CPU time | 6359.91 seconds |
| Started | Aug 25 09:05:55 PM UTC 24 |
| Finished | Aug 25 10:53:53 PM UTC 24 |
| Peak memory | 629004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128252758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.128252758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1448594694 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 14963662104 ps |
| CPU time | 5511.19 seconds |
| Started | Aug 25 09:06:01 PM UTC 24 |
| Finished | Aug 25 10:39:35 PM UTC 24 |
| Peak memory | 624028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448594694 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1448594694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3134998171 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 15219822268 ps |
| CPU time | 6479.41 seconds |
| Started | Aug 25 09:04:45 PM UTC 24 |
| Finished | Aug 25 10:54:43 PM UTC 24 |
| Peak memory | 628832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134998171 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_no_meas.3134998171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2523572426 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 26914429180 ps |
| CPU time | 10461.8 seconds |
| Started | Aug 25 09:06:07 PM UTC 24 |
| Finished | Aug 26 12:03:43 AM UTC 24 |
| Peak memory | 629024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523572426 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2523572426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.1680327618 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 14858916420 ps |
| CPU time | 5576.47 seconds |
| Started | Aug 25 09:01:26 PM UTC 24 |
| Finished | Aug 25 10:36:05 PM UTC 24 |
| Peak memory | 629024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680327618 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.1680327618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2449234126 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 27192963475 ps |
| CPU time | 5587.49 seconds |
| Started | Aug 25 09:04:21 PM UTC 24 |
| Finished | Aug 25 10:39:12 PM UTC 24 |
| Peak memory | 628888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449234126 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2449234126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2347199982 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 15105660478 ps |
| CPU time | 5855.4 seconds |
| Started | Aug 25 09:00:02 PM UTC 24 |
| Finished | Aug 25 10:39:26 PM UTC 24 |
| Peak memory | 628952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347199982 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2347199982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1064007788 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 17143916936 ps |
| CPU time | 6128.64 seconds |
| Started | Aug 25 09:06:05 PM UTC 24 |
| Finished | Aug 25 10:50:15 PM UTC 24 |
| Peak memory | 626900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064007788 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1064007788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_keymgr_functest.2063841466 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4302404330 ps |
| CPU time | 644.1 seconds |
| Started | Aug 25 09:03:26 PM UTC 24 |
| Finished | Aug 25 09:14:23 PM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063841466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.rom_keymgr_functest.2063841466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_raw_unlock.2251656150 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 6570016861 ps |
| CPU time | 396.1 seconds |
| Started | Aug 25 09:03:28 PM UTC 24 |
| Finished | Aug 25 09:10:12 PM UTC 24 |
| Peak memory | 637712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251656150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2251656150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_volatile_raw_unlock.2666204078 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2176349737 ps |
| CPU time | 169.4 seconds |
| Started | Aug 25 09:06:19 PM UTC 24 |
| Finished | Aug 25 09:09:13 PM UTC 24 |
| Peak memory | 633460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2666204078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.2666204078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.1313700268 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 11029835491 ps |
| CPU time | 1114.72 seconds |
| Started | Aug 25 10:56:49 PM UTC 24 |
| Finished | Aug 25 11:15:46 PM UTC 24 |
| Peak memory | 636192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1313700268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.chip_sw_lc_ctrl_transition.1313700268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.372459445 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 8168228360 ps |
| CPU time | 2097.09 seconds |
| Started | Aug 25 10:58:10 PM UTC 24 |
| Finished | Aug 25 11:33:50 PM UTC 24 |
| Peak memory | 636020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372459445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.372459445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2752004281 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 6245628882 ps |
| CPU time | 730.41 seconds |
| Started | Aug 25 10:58:58 PM UTC 24 |
| Finished | Aug 25 11:11:23 PM UTC 24 |
| Peak memory | 636200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2752004281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.chip_sw_lc_ctrl_transition.2752004281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3778340019 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 8315669600 ps |
| CPU time | 1817.16 seconds |
| Started | Aug 25 10:58:08 PM UTC 24 |
| Finished | Aug 25 11:29:00 PM UTC 24 |
| Peak memory | 635956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778340019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.3778340019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.2443740457 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 6440063237 ps |
| CPU time | 702.07 seconds |
| Started | Aug 25 10:59:54 PM UTC 24 |
| Finished | Aug 25 11:11:51 PM UTC 24 |
| Peak memory | 636256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2443740457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.chip_sw_lc_ctrl_transition.2443740457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.314528462 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 8074061288 ps |
| CPU time | 2247.26 seconds |
| Started | Aug 25 10:59:49 PM UTC 24 |
| Finished | Aug 25 11:37:56 PM UTC 24 |
| Peak memory | 636188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314528462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.314528462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.94376705 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 5052751086 ps |
| CPU time | 636.56 seconds |
| Started | Aug 25 11:01:31 PM UTC 24 |
| Finished | Aug 25 11:12:19 PM UTC 24 |
| Peak memory | 638132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=94376705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.chip_sw_lc_ctrl_transition.94376705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4261967980 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5127218248 ps |
| CPU time | 803.73 seconds |
| Started | Aug 25 11:01:36 PM UTC 24 |
| Finished | Aug 25 11:15:16 PM UTC 24 |
| Peak memory | 636108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261967980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.4261967980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.429743255 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 11570348826 ps |
| CPU time | 1098.98 seconds |
| Started | Aug 25 11:04:12 PM UTC 24 |
| Finished | Aug 25 11:22:54 PM UTC 24 |
| Peak memory | 636156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=429743255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.chip_sw_lc_ctrl_transition.429743255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2825592963 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3637572200 ps |
| CPU time | 737.98 seconds |
| Started | Aug 25 11:02:19 PM UTC 24 |
| Finished | Aug 25 11:14:50 PM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825592963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2825592963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.3867351827 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4960835092 ps |
| CPU time | 860.32 seconds |
| Started | Aug 25 11:05:32 PM UTC 24 |
| Finished | Aug 25 11:20:09 PM UTC 24 |
| Peak memory | 636472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867351827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3867351827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.4077616521 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 7694694486 ps |
| CPU time | 2010.16 seconds |
| Started | Aug 25 11:05:33 PM UTC 24 |
| Finished | Aug 25 11:39:41 PM UTC 24 |
| Peak memory | 636228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077616521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.4077616521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.790291035 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 4643603130 ps |
| CPU time | 809.83 seconds |
| Started | Aug 25 11:06:58 PM UTC 24 |
| Finished | Aug 25 11:20:43 PM UTC 24 |
| Peak memory | 635956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790291035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.790291035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.387273801 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 8336863604 ps |
| CPU time | 2331.34 seconds |
| Started | Aug 25 11:09:37 PM UTC 24 |
| Finished | Aug 25 11:49:11 PM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387273801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.387273801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2872633733 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4156108192 ps |
| CPU time | 698.98 seconds |
| Started | Aug 25 11:09:47 PM UTC 24 |
| Finished | Aug 25 11:21:40 PM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872633733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2872633733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1856197795 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 13354838330 ps |
| CPU time | 3209.47 seconds |
| Started | Aug 25 11:09:53 PM UTC 24 |
| Finished | Aug 26 12:04:18 AM UTC 24 |
| Peak memory | 636084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856197795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1856197795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.4059134728 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5990559450 ps |
| CPU time | 1005.51 seconds |
| Started | Aug 25 11:09:52 PM UTC 24 |
| Finished | Aug 25 11:26:57 PM UTC 24 |
| Peak memory | 674540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059134728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.4059134728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3210889103 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 3201329690 ps |
| CPU time | 715.76 seconds |
| Started | Aug 25 11:10:49 PM UTC 24 |
| Finished | Aug 25 11:22:58 PM UTC 24 |
| Peak memory | 636036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210889103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3210889103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.481883730 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13326624672 ps |
| CPU time | 2076.97 seconds |
| Started | Aug 25 10:12:43 PM UTC 24 |
| Finished | Aug 25 10:47:59 PM UTC 24 |
| Peak memory | 623076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481883730 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.481883730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_jtag_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2074710793 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3585172160 ps |
| CPU time | 433.43 seconds |
| Started | Aug 25 10:18:11 PM UTC 24 |
| Finished | Aug 25 10:25:34 PM UTC 24 |
| Peak memory | 635932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074710793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_ reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2074710793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sival_flash_info_access.866192057 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3117499784 ps |
| CPU time | 421.9 seconds |
| Started | Aug 25 09:08:08 PM UTC 24 |
| Finished | Aug 25 09:15:18 PM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim _dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866192057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_bas e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.866192057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sival_flash_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2910809335 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 18308645452 ps |
| CPU time | 761.95 seconds |
| Started | Aug 25 09:41:44 PM UTC 24 |
| Finished | Aug 25 09:54:41 PM UTC 24 |
| Peak memory | 635952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910809335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/c hip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2910809335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1653622340 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 2833406928 ps |
| CPU time | 315.73 seconds |
| Started | Aug 25 09:45:06 PM UTC 24 |
| Finished | Aug 25 09:50:29 PM UTC 24 |
| Peak memory | 623816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_i mages=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653622340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1653622340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.1572245638 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 2848054183 ps |
| CPU time | 371.94 seconds |
| Started | Aug 25 09:44:50 PM UTC 24 |
| Finished | Aug 25 09:51:10 PM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572245638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1572245638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3111124343 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2409568437 ps |
| CPU time | 312.56 seconds |
| Started | Aug 25 10:23:49 PM UTC 24 |
| Finished | Aug 25 10:29:08 PM UTC 24 |
| Peak memory | 623852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111124343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3111124343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3248979768 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2741527896 ps |
| CPU time | 273.22 seconds |
| Started | Aug 25 09:49:45 PM UTC 24 |
| Finished | Aug 25 09:54:26 PM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248979768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_aes_entropy.3248979768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1634748327 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 2921521738 ps |
| CPU time | 364.84 seconds |
| Started | Aug 25 09:44:39 PM UTC 24 |
| Finished | Aug 25 09:50:52 PM UTC 24 |
| Peak memory | 625560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/ repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634748327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1634748327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2105373906 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2721550814 ps |
| CPU time | 395.09 seconds |
| Started | Aug 25 09:45:06 PM UTC 24 |
| Finished | Aug 25 09:51:48 PM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105373906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_aes_masking_off.2105373906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_masking_off/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2771353805 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 2427090930 ps |
| CPU time | 329.04 seconds |
| Started | Aug 25 10:32:28 PM UTC 24 |
| Finished | Aug 25 10:38:04 PM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2771353805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_a es_smoketest.2771353805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aes_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.392623567 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2811178794 ps |
| CPU time | 552.22 seconds |
| Started | Aug 25 09:49:25 PM UTC 24 |
| Finished | Aug 25 09:58:49 PM UTC 24 |
| Peak memory | 625868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392623567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.392623567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.4164771121 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4345604632 ps |
| CPU time | 752.43 seconds |
| Started | Aug 25 09:45:05 PM UTC 24 |
| Finished | Aug 25 09:57:54 PM UTC 24 |
| Peak memory | 636072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164771121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.4164771121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3499686488 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 8078586288 ps |
| CPU time | 2761.34 seconds |
| Started | Aug 25 09:48:48 PM UTC 24 |
| Finished | Aug 25 10:35:41 PM UTC 24 |
| Peak memory | 625632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499686488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_ea rlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3499686488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.162306000 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 8106906096 ps |
| CPU time | 2578.78 seconds |
| Started | Aug 25 09:49:24 PM UTC 24 |
| Finished | Aug 25 10:33:12 PM UTC 24 |
| Peak memory | 625636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device= sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162306000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.162306000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2521581101 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 11188249928 ps |
| CPU time | 2078.67 seconds |
| Started | Aug 25 09:47:56 PM UTC 24 |
| Finished | Aug 25 10:23:14 PM UTC 24 |
| Peak memory | 626080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521581101 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_hand ler_lpg_sleep_mode_pings.2521581101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2683051156 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 7856345554 ps |
| CPU time | 1618.18 seconds |
| Started | Aug 25 09:46:29 PM UTC 24 |
| Finished | Aug 25 10:14:00 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683051156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ba se_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2683051156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3074800664 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 4819190616 ps |
| CPU time | 894.54 seconds |
| Started | Aug 25 09:46:31 PM UTC 24 |
| Finished | Aug 25 10:01:45 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_ dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074800664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3074800664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.1405585634 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3324556560 ps |
| CPU time | 349.13 seconds |
| Started | Aug 25 09:45:03 PM UTC 24 |
| Finished | Aug 25 09:51:00 PM UTC 24 |
| Peak memory | 623680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rand om_seed=1405585634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aler t_test.1405585634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_all_escalation_resets.1535464744 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4531335240 ps |
| CPU time | 984.09 seconds |
| Started | Aug 25 09:08:36 PM UTC 24 |
| Finished | Aug 25 09:25:20 PM UTC 24 |
| Peak memory | 674416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535464744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1535464744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.790154134 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 4059338568 ps |
| CPU time | 656.52 seconds |
| Started | Aug 25 09:39:05 PM UTC 24 |
| Finished | Aug 25 09:50:15 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790154134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_aon_timer_irq.790154134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.663873745 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 6960401568 ps |
| CPU time | 779.73 seconds |
| Started | Aug 25 09:40:29 PM UTC 24 |
| Finished | Aug 25 09:53:44 PM UTC 24 |
| Peak memory | 625696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663873745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.663873745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.2601915396 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 2649682550 ps |
| CPU time | 371.74 seconds |
| Started | Aug 25 10:35:47 PM UTC 24 |
| Finished | Aug 25 10:42:07 PM UTC 24 |
| Peak memory | 623748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601915396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_aon_timer_smoketest.2601915396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.930802305 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 8994462288 ps |
| CPU time | 1297.07 seconds |
| Started | Aug 25 09:41:46 PM UTC 24 |
| Finished | Aug 25 10:03:49 PM UTC 24 |
| Peak memory | 623956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930802305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.930802305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3732244290 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4147093352 ps |
| CPU time | 726.53 seconds |
| Started | Aug 25 09:41:45 PM UTC 24 |
| Finished | Aug 25 09:54:06 PM UTC 24 |
| Peak memory | 625584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucl i -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732244290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3732244290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.1389291858 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 6533354350 ps |
| CPU time | 1249.3 seconds |
| Started | Aug 25 10:13:18 PM UTC 24 |
| Finished | Aug 25 10:34:29 PM UTC 24 |
| Peak memory | 632096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_ clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h w/dv/tools/sim.tcl +ntb_random_seed=1389291858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1389291858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1665478612 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 21201235054 ps |
| CPU time | 5047.72 seconds |
| Started | Aug 25 10:27:37 PM UTC 24 |
| Finished | Aug 25 11:53:13 PM UTC 24 |
| Peak memory | 628700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_ images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665478612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_input s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1665478612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1818812925 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 10449944964 ps |
| CPU time | 1126.93 seconds |
| Started | Aug 25 10:06:50 PM UTC 24 |
| Finished | Aug 25 10:25:59 PM UTC 24 |
| Peak memory | 638080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_de vice=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818812925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1818812925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3032672825 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3850981496 ps |
| CPU time | 761.55 seconds |
| Started | Aug 25 10:08:20 PM UTC 24 |
| Finished | Aug 25 10:21:17 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032672825 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_dev.3032672825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2333744364 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 4412130248 ps |
| CPU time | 975.78 seconds |
| Started | Aug 25 10:08:05 PM UTC 24 |
| Finished | Aug 25 10:24:40 PM UTC 24 |
| Peak memory | 625968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333744364 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_fast_rma.2333744364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2923556373 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 3560030536 ps |
| CPU time | 1010.35 seconds |
| Started | Aug 25 10:07:36 PM UTC 24 |
| Finished | Aug 25 10:24:46 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292 3556373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_fast_test_unlocked0.2923556373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1884723319 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 5393235776 ps |
| CPU time | 985.62 seconds |
| Started | Aug 25 10:08:24 PM UTC 24 |
| Finished | Aug 25 10:25:08 PM UTC 24 |
| Peak memory | 627932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884723319 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_sr c_for_sw_slow_dev.1884723319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.8021669 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 4678987236 ps |
| CPU time | 801.66 seconds |
| Started | Aug 25 10:08:23 PM UTC 24 |
| Finished | Aug 25 10:21:59 PM UTC 24 |
| Peak memory | 625944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8021669 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_f or_sw_slow_rma.8021669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3917665984 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 4351903836 ps |
| CPU time | 925.65 seconds |
| Started | Aug 25 10:08:15 PM UTC 24 |
| Finished | Aug 25 10:23:59 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_u sb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391 7665984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_exter nal_clk_src_for_sw_slow_test_unlocked0.3917665984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2980669657 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2425456547 ps |
| CPU time | 418.3 seconds |
| Started | Aug 25 10:11:09 PM UTC 24 |
| Finished | Aug 25 10:18:17 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2980669657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_clkmgr_jitter.2980669657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2473091531 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3290202966 ps |
| CPU time | 653.77 seconds |
| Started | Aug 25 10:10:03 PM UTC 24 |
| Finished | Aug 25 10:21:10 PM UTC 24 |
| Peak memory | 623848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2473091531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_clkmgr_jitter_frequency.2473091531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1275858009 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2714300022 ps |
| CPU time | 274.69 seconds |
| Started | Aug 25 10:22:09 PM UTC 24 |
| Finished | Aug 25 10:26:49 PM UTC 24 |
| Peak memory | 625876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkm gr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1275858009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.1275858009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.441971396 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4788170248 ps |
| CPU time | 590.66 seconds |
| Started | Aug 25 10:06:43 PM UTC 24 |
| Finished | Aug 25 10:16:46 PM UTC 24 |
| Peak memory | 625964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=441971396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.441971396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3969391853 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4630076540 ps |
| CPU time | 724.77 seconds |
| Started | Aug 25 10:06:51 PM UTC 24 |
| Finished | Aug 25 10:19:09 PM UTC 24 |
| Peak memory | 623740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3969391853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_hmac_trans.3969391853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1252956497 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 5542342680 ps |
| CPU time | 758.74 seconds |
| Started | Aug 25 10:06:54 PM UTC 24 |
| Finished | Aug 25 10:19:47 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1252956497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_kmac_trans.1252956497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1933852142 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 4314358384 ps |
| CPU time | 802.31 seconds |
| Started | Aug 25 10:08:23 PM UTC 24 |
| Finished | Aug 25 10:22:00 PM UTC 24 |
| Peak memory | 625760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1933852142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_clkmgr_off_otbn_trans.1933852142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.4088902828 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 11956345256 ps |
| CPU time | 1689.15 seconds |
| Started | Aug 25 10:06:44 PM UTC 24 |
| Finished | Aug 25 10:35:24 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_i mages=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088902828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.4088902828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1120729015 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3389620520 ps |
| CPU time | 605.09 seconds |
| Started | Aug 25 10:10:03 PM UTC 24 |
| Finished | Aug 25 10:20:20 PM UTC 24 |
| Peak memory | 623640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120729015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1120729015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.884089624 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 4499734086 ps |
| CPU time | 816.65 seconds |
| Started | Aug 25 10:12:24 PM UTC 24 |
| Finished | Aug 25 10:26:17 PM UTC 24 |
| Peak memory | 625936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkm gr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884089624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.884089624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2024613598 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 2506593752 ps |
| CPU time | 380.48 seconds |
| Started | Aug 25 10:31:29 PM UTC 24 |
| Finished | Aug 25 10:37:57 PM UTC 24 |
| Peak memory | 625572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2024613598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_clkmgr_smoketest.2024613598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.881697642 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 15934144610 ps |
| CPU time | 6096.8 seconds |
| Started | Aug 25 09:53:18 PM UTC 24 |
| Finished | Aug 25 11:36:46 PM UTC 24 |
| Peak memory | 626792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=881697642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_csrng_edn_concurrency.881697642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4012880269 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 9338813240 ps |
| CPU time | 2738.97 seconds |
| Started | Aug 25 10:27:10 PM UTC 24 |
| Finished | Aug 25 11:13:40 PM UTC 24 |
| Peak memory | 624072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accele rate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012880269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.4012880269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1294416606 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 5139276152 ps |
| CPU time | 653.76 seconds |
| Started | Aug 25 09:53:27 PM UTC 24 |
| Finished | Aug 25 10:04:35 PM UTC 24 |
| Peak memory | 623776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294416606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src _fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1294416606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.1107360167 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 2150582358 ps |
| CPU time | 331.44 seconds |
| Started | Aug 25 09:52:34 PM UTC 24 |
| Finished | Aug 25 09:58:13 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107360167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_csrng_kat_test.1107360167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1061762216 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 5907569232 ps |
| CPU time | 798.54 seconds |
| Started | Aug 25 09:53:01 PM UTC 24 |
| Finished | Aug 25 10:06:37 PM UTC 24 |
| Peak memory | 626092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_ otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061762216 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_lc_hw_debug_en_test.1061762216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2777339005 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 2842722332 ps |
| CPU time | 347.95 seconds |
| Started | Aug 25 10:34:46 PM UTC 24 |
| Finished | Aug 25 10:40:40 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2777339005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_smoketest.2777339005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.296383966 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 4340083032 ps |
| CPU time | 1464.38 seconds |
| Started | Aug 25 09:51:53 PM UTC 24 |
| Finished | Aug 25 10:16:46 PM UTC 24 |
| Peak memory | 625912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296383966 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_auto_mode.296383966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1591801594 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2895667528 ps |
| CPU time | 859.88 seconds |
| Started | Aug 25 09:52:09 PM UTC 24 |
| Finished | Aug 25 10:06:47 PM UTC 24 |
| Peak memory | 623860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_ device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591801594 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_boot_mode.1591801594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.4117558774 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 6701459788 ps |
| CPU time | 1259.47 seconds |
| Started | Aug 25 09:53:32 PM UTC 24 |
| Finished | Aug 25 10:14:57 PM UTC 24 |
| Peak memory | 626076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117558774 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.4117558774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1983320741 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 5961679574 ps |
| CPU time | 1577.77 seconds |
| Started | Aug 25 09:53:56 PM UTC 24 |
| Finished | Aug 25 10:20:44 PM UTC 24 |
| Peak memory | 626072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_sr ate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=entropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983320741 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.1983320741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3741542395 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3693997568 ps |
| CPU time | 817.89 seconds |
| Started | Aug 25 09:52:41 PM UTC 24 |
| Finished | Aug 25 10:06:37 PM UTC 24 |
| Peak memory | 629772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_a ssert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3741542395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_edn_kat.3741542395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_kat/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.17828742 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 5780149464 ps |
| CPU time | 1706.82 seconds |
| Started | Aug 25 09:52:56 PM UTC 24 |
| Finished | Aug 25 10:21:57 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=17828742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_edn_sw_mode.17828742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2025643042 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2695553400 ps |
| CPU time | 275.47 seconds |
| Started | Aug 25 09:53:34 PM UTC 24 |
| Finished | Aug 25 09:58:15 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025643042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2025643042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3817200333 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 7556893854 ps |
| CPU time | 2291.22 seconds |
| Started | Aug 25 09:53:26 PM UTC 24 |
| Finished | Aug 25 10:32:21 PM UTC 24 |
| Peak memory | 623780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_ srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817200333 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 4/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3817200333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.109051257 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2570744960 ps |
| CPU time | 366.78 seconds |
| Started | Aug 25 09:51:15 PM UTC 24 |
| Finished | Aug 25 09:57:31 PM UTC 24 |
| Peak memory | 623696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109051257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.109051257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.3131034869 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3911703100 ps |
| CPU time | 698.56 seconds |
| Started | Aug 25 10:34:00 PM UTC 24 |
| Finished | Aug 25 10:45:51 PM UTC 24 |
| Peak memory | 623716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_de vice=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131034869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3131034869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_concurrency.1088354165 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 2831969400 ps |
| CPU time | 291.55 seconds |
| Started | Aug 25 09:08:00 PM UTC 24 |
| Finished | Aug 25 09:12:58 PM UTC 24 |
| Peak memory | 623676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1088354165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.1088354165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_flash.3722124896 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3209750512 ps |
| CPU time | 424.56 seconds |
| Started | Aug 25 09:06:51 PM UTC 24 |
| Finished | Aug 25 09:14:05 PM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3722124896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_example_flash.3722124896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_manufacturer.4096672528 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 2375758142 ps |
| CPU time | 301.41 seconds |
| Started | Aug 25 09:08:01 PM UTC 24 |
| Finished | Aug 25 09:13:09 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4096672528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ex ample_manufacturer.4096672528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_manufacturer/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_example_rom.223512751 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2432217866 ps |
| CPU time | 222.75 seconds |
| Started | Aug 25 09:07:08 PM UTC 24 |
| Finished | Aug 25 09:10:56 PM UTC 24 |
| Peak memory | 625404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:t est_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=223512751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_example_rom.223512751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_example_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.354002765 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4841262000 ps |
| CPU time | 858.9 seconds |
| Started | Aug 25 10:22:11 PM UTC 24 |
| Finished | Aug 25 10:36:46 PM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check= 1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354002765 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.354002765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2149757370 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 5425161928 ps |
| CPU time | 1427.25 seconds |
| Started | Aug 25 09:17:11 PM UTC 24 |
| Finished | Aug 25 09:41:27 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2149757370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _flash_ctrl_access.2149757370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2575854482 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 6383081941 ps |
| CPU time | 1693.85 seconds |
| Started | Aug 25 09:17:20 PM UTC 24 |
| Finished | Aug 25 09:46:06 PM UTC 24 |
| Peak memory | 623836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_t est:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools /sim.tcl +ntb_random_seed=2575854482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_flash_ctrl_access_jitter_en.2575854482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4249092836 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 6948723234 ps |
| CPU time | 1637.05 seconds |
| Started | Aug 25 10:24:18 PM UTC 24 |
| Finished | Aug 25 10:52:06 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp aces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249092836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4249092836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3213063442 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 5447725236 ps |
| CPU time | 1362.33 seconds |
| Started | Aug 25 09:19:40 PM UTC 24 |
| Finished | Aug 25 09:42:50 PM UTC 24 |
| Peak memory | 623660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=3213063442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_flash_ctrl_clock_freqs.3213063442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3839009033 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3628115128 ps |
| CPU time | 579.21 seconds |
| Started | Aug 25 09:18:37 PM UTC 24 |
| Finished | Aug 25 09:28:28 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3839009033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_idle_low_power.3839009033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3560079514 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4874104044 ps |
| CPU time | 796.98 seconds |
| Started | Aug 25 09:17:14 PM UTC 24 |
| Finished | Aug 25 09:30:44 PM UTC 24 |
| Peak memory | 623644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560079514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ct rl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3560079514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3189528005 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 5309559400 ps |
| CPU time | 1347.19 seconds |
| Started | Aug 25 10:29:46 PM UTC 24 |
| Finished | Aug 25 10:52:40 PM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3189528005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_flash_ctrl_mem_protection.3189528005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.3165817294 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4223556302 ps |
| CPU time | 1014.55 seconds |
| Started | Aug 25 09:17:00 PM UTC 24 |
| Finished | Aug 25 09:34:15 PM UTC 24 |
| Peak memory | 625824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165817294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3165817294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4053378226 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4234309388 ps |
| CPU time | 887.68 seconds |
| Started | Aug 25 09:16:58 PM UTC 24 |
| Finished | Aug 25 09:32:03 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053378226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.4053378226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3885652016 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4611383575 ps |
| CPU time | 761.29 seconds |
| Started | Aug 25 10:23:27 PM UTC 24 |
| Finished | Aug 25 10:36:22 PM UTC 24 |
| Peak memory | 623700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885652016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_a sic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3885652016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.284951202 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 3445807192 ps |
| CPU time | 556.56 seconds |
| Started | Aug 25 10:22:10 PM UTC 24 |
| Finished | Aug 25 10:31:36 PM UTC 24 |
| Peak memory | 623752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_image s=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284951202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.284951202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2762058733 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 22865710088 ps |
| CPU time | 3184.62 seconds |
| Started | Aug 25 09:18:31 PM UTC 24 |
| Finished | Aug 25 10:12:37 PM UTC 24 |
| Peak memory | 627944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_i mages=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762058733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_flash_init.2762058733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.2135729743 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 18287204864 ps |
| CPU time | 2542.05 seconds |
| Started | Aug 25 10:24:33 PM UTC 24 |
| Finished | Aug 25 11:07:41 PM UTC 24 |
| Peak memory | 629996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_buil d_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135729743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw _flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2135729743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4039713619 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3151222942 ps |
| CPU time | 332.17 seconds |
| Started | Aug 25 10:32:13 PM UTC 24 |
| Finished | Aug 25 10:37:52 PM UTC 24 |
| Peak memory | 623652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_ima ges=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoketest_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039713619 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chi p_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.4039713619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3030197286 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3028349151 ps |
| CPU time | 388.05 seconds |
| Started | Aug 25 10:34:12 PM UTC 24 |
| Finished | Aug 25 10:40:48 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=3030197286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_gpio_smoketest.3030197286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.2813447038 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 3056471180 ps |
| CPU time | 398.51 seconds |
| Started | Aug 25 09:54:27 PM UTC 24 |
| Finished | Aug 25 10:01:14 PM UTC 24 |
| Peak memory | 623768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=2813447038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_h mac_enc.2813447038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2963913680 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3140786400 ps |
| CPU time | 515.59 seconds |
| Started | Aug 25 09:56:05 PM UTC 24 |
| Finished | Aug 25 10:04:50 PM UTC 24 |
| Peak memory | 623672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2963913680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_hmac_enc_idle.2963913680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.506241184 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 3522237711 ps |
| CPU time | 448.19 seconds |
| Started | Aug 25 09:54:48 PM UTC 24 |
| Finished | Aug 25 10:02:25 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=506241184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.506241184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2237333049 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3315807935 ps |
| CPU time | 302.55 seconds |
| Started | Aug 25 10:24:11 PM UTC 24 |
| Finished | Aug 25 10:29:19 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237333049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2237333049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1553994612 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 7723329636 ps |
| CPU time | 1988.09 seconds |
| Started | Aug 25 09:56:38 PM UTC 24 |
| Finished | Aug 25 10:30:23 PM UTC 24 |
| Peak memory | 623668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1553994612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_multistream.1553994612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.681186113 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 3010910160 ps |
| CPU time | 428.06 seconds |
| Started | Aug 25 09:56:12 PM UTC 24 |
| Finished | Aug 25 10:03:31 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r andom_seed=681186113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hm ac_oneshot.681186113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.4279044496 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2853069452 ps |
| CPU time | 532.81 seconds |
| Started | Aug 25 10:31:18 PM UTC 24 |
| Finished | Aug 25 10:40:23 PM UTC 24 |
| Peak memory | 625648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4279044496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ hmac_smoketest.4279044496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_device_tx_rx.2614965543 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 3751802256 ps |
| CPU time | 690.21 seconds |
| Started | Aug 25 09:15:00 PM UTC 24 |
| Finished | Aug 25 09:26:44 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2614965543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2614965543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3141382682 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4509471900 ps |
| CPU time | 1083.4 seconds |
| Started | Aug 25 09:15:27 PM UTC 24 |
| Finished | Aug 25 09:33:50 PM UTC 24 |
| Peak memory | 623720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3141382682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx.3141382682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3222163409 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4709682464 ps |
| CPU time | 1122.82 seconds |
| Started | Aug 25 09:14:17 PM UTC 24 |
| Finished | Aug 25 09:33:22 PM UTC 24 |
| Peak memory | 625932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=3222163409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3222163409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1773568137 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4622419224 ps |
| CPU time | 1109.37 seconds |
| Started | Aug 25 09:15:40 PM UTC 24 |
| Finished | Aug 25 09:34:31 PM UTC 24 |
| Peak memory | 626012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=1773568137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1773568137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2679774619 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 66847323197 ps |
| CPU time | 15680.4 seconds |
| Started | Aug 25 09:13:15 PM UTC 24 |
| Finished | Aug 26 01:38:27 AM UTC 24 |
| Peak memory | 643424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=1 50_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679774619 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2679774619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.794874463 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 8711925972 ps |
| CPU time | 2225.44 seconds |
| Started | Aug 25 09:56:31 PM UTC 24 |
| Finished | Aug 25 10:34:17 PM UTC 24 |
| Peak memory | 632116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device =sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794874463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_s w_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.794874463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.923121056 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 10858219835 ps |
| CPU time | 1946.94 seconds |
| Started | Aug 25 10:23:50 PM UTC 24 |
| Finished | Aug 25 10:56:53 PM UTC 24 |
| Peak memory | 632116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70m hz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923121056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.923121056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.783747585 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 8183848120 ps |
| CPU time | 1816.05 seconds |
| Started | Aug 25 09:56:36 PM UTC 24 |
| Finished | Aug 25 10:27:27 PM UTC 24 |
| Peak memory | 631880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_devic e=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783747585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.783747585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.2971861902 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 6771226072 ps |
| CPU time | 1522.26 seconds |
| Started | Aug 25 09:57:12 PM UTC 24 |
| Finished | Aug 25 10:23:05 PM UTC 24 |
| Peak memory | 625984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971861902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sidel oad_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2971861902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.4157859014 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 6934933640 ps |
| CPU time | 1774.84 seconds |
| Started | Aug 25 09:56:37 PM UTC 24 |
| Finished | Aug 25 10:26:44 PM UTC 24 |
| Peak memory | 625952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157859014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_side load_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.4157859014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.4093635871 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 12396568564 ps |
| CPU time | 5376.9 seconds |
| Started | Aug 25 09:58:14 PM UTC 24 |
| Finished | Aug 25 11:29:27 PM UTC 24 |
| Peak memory | 626724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093635871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.4093635871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.31560970 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2137835836 ps |
| CPU time | 317.05 seconds |
| Started | Aug 25 09:59:29 PM UTC 24 |
| Finished | Aug 25 10:04:54 PM UTC 24 |
| Peak memory | 623456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=31560970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _kmac_app_rom.31560970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_entropy.4023042180 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 3326798686 ps |
| CPU time | 373.73 seconds |
| Started | Aug 25 09:20:10 PM UTC 24 |
| Finished | Aug 25 09:26:31 PM UTC 24 |
| Peak memory | 625908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=4023042180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_kmac_entropy.4023042180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.4043417044 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3131162608 ps |
| CPU time | 283.54 seconds |
| Started | Aug 25 10:00:25 PM UTC 24 |
| Finished | Aug 25 10:05:17 PM UTC 24 |
| Peak memory | 625568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=4043417044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_idle.4043417044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.3998623992 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2846546416 ps |
| CPU time | 310.1 seconds |
| Started | Aug 25 09:58:34 PM UTC 24 |
| Finished | Aug 25 10:03:52 PM UTC 24 |
| Peak memory | 623664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3998623992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_sw_kmac_mode_cshake.3998623992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.2095395473 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3128897548 ps |
| CPU time | 385.16 seconds |
| Started | Aug 25 09:59:05 PM UTC 24 |
| Finished | Aug 25 10:05:39 PM UTC 24 |
| Peak memory | 623528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095395473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_kmac_mode_kmac.2095395473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1178324922 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3124010515 ps |
| CPU time | 389.19 seconds |
| Started | Aug 25 09:59:06 PM UTC 24 |
| Finished | Aug 25 10:05:45 PM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_km ac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1178324922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1178324922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1796843644 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 3040861583 ps |
| CPU time | 380.12 seconds |
| Started | Aug 25 10:26:20 PM UTC 24 |
| Finished | Aug 25 10:32:47 PM UTC 24 |
| Peak memory | 625656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +s w_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796843644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1796843644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.2704289848 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2857154940 ps |
| CPU time | 329.99 seconds |
| Started | Aug 25 10:31:28 PM UTC 24 |
| Finished | Aug 25 10:37:05 PM UTC 24 |
| Peak memory | 625716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2704289848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ kmac_smoketest.2704289848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1958627673 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2828096216 ps |
| CPU time | 463.5 seconds |
| Started | Aug 25 09:21:12 PM UTC 24 |
| Finished | Aug 25 09:29:06 PM UTC 24 |
| Peak memory | 623520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1958627673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1958627673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2616020721 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4875751090 ps |
| CPU time | 634.42 seconds |
| Started | Aug 25 10:14:53 PM UTC 24 |
| Finished | Aug 25 10:25:41 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_devic e=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616020721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_l c_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2616020721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2411895714 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3998632041 ps |
| CPU time | 391.27 seconds |
| Started | Aug 25 09:26:07 PM UTC 24 |
| Finished | Aug 25 09:32:46 PM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411895714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2411895714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.1552883009 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 6682094970 ps |
| CPU time | 708.58 seconds |
| Started | Aug 25 09:26:09 PM UTC 24 |
| Finished | Aug 25 09:38:11 PM UTC 24 |
| Peak memory | 636148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1552883009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_lc_ctrl_transition.1552883009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1139542204 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2889636025 ps |
| CPU time | 204.26 seconds |
| Started | Aug 25 09:28:18 PM UTC 24 |
| Finished | Aug 25 09:31:47 PM UTC 24 |
| Peak memory | 633432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139542204 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1139542204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2519592331 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2271389080 ps |
| CPU time | 155.16 seconds |
| Started | Aug 25 09:28:35 PM UTC 24 |
| Finished | Aug 25 09:31:14 PM UTC 24 |
| Peak memory | 633256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSo urceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25195923 31 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc _ctrl_volatile_raw_unlock_ext_clk_48mhz.2519592331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2872274868 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 50882213507 ps |
| CPU time | 9718.42 seconds |
| Started | Aug 25 09:26:09 PM UTC 24 |
| Finished | Aug 26 12:10:54 AM UTC 24 |
| Peak memory | 643416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872274868 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_dev.2872274868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.2853121755 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 49187893629 ps |
| CPU time | 8911.77 seconds |
| Started | Aug 25 09:27:52 PM UTC 24 |
| Finished | Aug 25 11:59:06 PM UTC 24 |
| Peak memory | 643492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853121755 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prod.2853121755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.3603801200 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 11265658696 ps |
| CPU time | 1604.04 seconds |
| Started | Aug 25 09:28:26 PM UTC 24 |
| Finished | Aug 25 09:55:42 PM UTC 24 |
| Peak memory | 640048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest _dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603801200 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3603801200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.2427280847 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 45202373730 ps |
| CPU time | 9117.28 seconds |
| Started | Aug 25 09:28:33 PM UTC 24 |
| Finished | Aug 26 12:03:11 AM UTC 24 |
| Peak memory | 643232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +fl ash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427280847 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_rma.2427280847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.303417301 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 34226060021 ps |
| CPU time | 3189.65 seconds |
| Started | Aug 25 09:28:27 PM UTC 24 |
| Finished | Aug 25 10:22:38 PM UTC 24 |
| Peak memory | 640256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnl ock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303417301 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunlocks.303417301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1346782644 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 17689323944 ps |
| CPU time | 5691.63 seconds |
| Started | Aug 25 09:42:10 PM UTC 24 |
| Finished | Aug 25 11:18:48 PM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346782644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1346782644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3229798706 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 19349940928 ps |
| CPU time | 6414.75 seconds |
| Started | Aug 25 09:42:43 PM UTC 24 |
| Finished | Aug 25 11:31:34 PM UTC 24 |
| Peak memory | 629088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229798706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3229798706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2043482760 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 24261383575 ps |
| CPU time | 5602.8 seconds |
| Started | Aug 25 10:24:32 PM UTC 24 |
| Finished | Aug 25 11:59:33 PM UTC 24 |
| Peak memory | 628976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitte r=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043482760 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2043482760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3036541306 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 5825191528 ps |
| CPU time | 1201.69 seconds |
| Started | Aug 25 09:41:51 PM UTC 24 |
| Finished | Aug 25 10:02:18 PM UTC 24 |
| Peak memory | 626056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build _device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036541306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3036541306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_randomness/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.1309248431 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 9693704770 ps |
| CPU time | 2767.18 seconds |
| Started | Aug 25 10:32:37 PM UTC 24 |
| Finished | Aug 25 11:19:36 PM UTC 24 |
| Peak memory | 623964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=1309248431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ otbn_smoketest.1309248431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3533303366 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 2797280589 ps |
| CPU time | 292.16 seconds |
| Started | Aug 25 09:24:45 PM UTC 24 |
| Finished | Aug 25 09:29:44 PM UTC 24 |
| Peak memory | 623592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_ error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3533303366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3533303366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2561773371 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 8732533472 ps |
| CPU time | 1967.81 seconds |
| Started | Aug 25 09:23:06 PM UTC 24 |
| Finished | Aug 25 09:56:31 PM UTC 24 |
| Peak memory | 625844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561773371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2561773371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.632825032 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 6897243002 ps |
| CPU time | 1602.49 seconds |
| Started | Aug 25 09:23:24 PM UTC 24 |
| Finished | Aug 25 09:50:36 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_buil d_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632825032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.632825032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2783327533 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 8112480678 ps |
| CPU time | 1634.75 seconds |
| Started | Aug 25 09:24:43 PM UTC 24 |
| Finished | Aug 25 09:52:30 PM UTC 24 |
| Peak memory | 623840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build _device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783327533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2783327533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2405772886 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 4129674824 ps |
| CPU time | 1046.63 seconds |
| Started | Aug 25 09:22:43 PM UTC 24 |
| Finished | Aug 25 09:40:29 PM UTC 24 |
| Peak memory | 625816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405772886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_ asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2405772886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2924816874 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3193711198 ps |
| CPU time | 336.23 seconds |
| Started | Aug 25 10:32:53 PM UTC 24 |
| Finished | Aug 25 10:38:36 PM UTC 24 |
| Peak memory | 625684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2924816874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_otp_ctrl_smoketest.2924816874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pattgen_ios.2978761620 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2970679122 ps |
| CPU time | 391.17 seconds |
| Started | Aug 25 09:12:50 PM UTC 24 |
| Finished | Aug 25 09:19:29 PM UTC 24 |
| Peak memory | 625800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_im ages=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978761620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2978761620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pattgen_ios/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.1091741364 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2650107836 ps |
| CPU time | 447.73 seconds |
| Started | Aug 25 10:06:40 PM UTC 24 |
| Finished | Aug 25 10:14:17 PM UTC 24 |
| Peak memory | 625644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1091741364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_plic_sw_irq.1091741364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.4261331163 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 4399969448 ps |
| CPU time | 768.18 seconds |
| Started | Aug 25 10:30:31 PM UTC 24 |
| Finished | Aug 25 10:43:33 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261331163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_power_idle_load.4261331163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.3991295894 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 11657924132 ps |
| CPU time | 801.54 seconds |
| Started | Aug 25 10:26:17 PM UTC 24 |
| Finished | Aug 25 10:39:53 PM UTC 24 |
| Peak memory | 625984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3991295894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3991295894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.451523607 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5537860848 ps |
| CPU time | 1714.37 seconds |
| Started | Aug 25 10:34:55 PM UTC 24 |
| Finished | Aug 25 11:04:01 PM UTC 24 |
| Peak memory | 640656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_tim eout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_ img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451523607 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.451523607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3231390559 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 8669974273 ps |
| CPU time | 1656.14 seconds |
| Started | Aug 25 09:32:27 PM UTC 24 |
| Finished | Aug 25 10:00:37 PM UTC 24 |
| Peak memory | 625916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231390559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep _all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3231390559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2597730784 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 26817177420 ps |
| CPU time | 3728.85 seconds |
| Started | Aug 25 10:06:41 PM UTC 24 |
| Finished | Aug 25 11:09:53 PM UTC 24 |
| Peak memory | 623972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597730784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_re set_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2597730784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.212529950 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 16874050780 ps |
| CPU time | 2271.28 seconds |
| Started | Aug 25 09:33:06 PM UTC 24 |
| Finished | Aug 25 10:11:42 PM UTC 24 |
| Peak memory | 625784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212529950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.212529950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1118237708 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 21413360412 ps |
| CPU time | 2202.87 seconds |
| Started | Aug 25 10:15:57 PM UTC 24 |
| Finished | Aug 25 10:53:21 PM UTC 24 |
| Peak memory | 625848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118237708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr _deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgre y_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1118237708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2497819803 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 8917584918 ps |
| CPU time | 882.83 seconds |
| Started | Aug 25 09:33:35 PM UTC 24 |
| Finished | Aug 25 09:48:34 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_res et_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2497819803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2497819803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1618413683 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 6643894600 ps |
| CPU time | 560.45 seconds |
| Started | Aug 25 09:35:53 PM UTC 24 |
| Finished | Aug 25 09:45:25 PM UTC 24 |
| Peak memory | 632072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618413683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_as ic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1618413683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1837913859 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 7333108544 ps |
| CPU time | 678.98 seconds |
| Started | Aug 25 09:30:24 PM UTC 24 |
| Finished | Aug 25 09:41:57 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1837913859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_full_aon_reset.1837913859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2846133849 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3549623232 ps |
| CPU time | 512.91 seconds |
| Started | Aug 25 10:15:56 PM UTC 24 |
| Finished | Aug 25 10:24:41 PM UTC 24 |
| Peak memory | 623792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_te st:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/ sim.tcl +ntb_random_seed=2846133849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_pwrmgr_lowpower_cancel.2846133849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1919703599 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3310175207 ps |
| CPU time | 687.5 seconds |
| Started | Aug 25 09:31:25 PM UTC 24 |
| Finished | Aug 25 09:43:07 PM UTC 24 |
| Peak memory | 631988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919703599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_mai n_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1919703599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.306383467 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 9482721276 ps |
| CPU time | 1588.88 seconds |
| Started | Aug 25 09:33:59 PM UTC 24 |
| Finished | Aug 25 10:00:59 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_r eset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=306383467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.306383467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2091362127 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 8054206600 ps |
| CPU time | 675.67 seconds |
| Started | Aug 25 10:15:00 PM UTC 24 |
| Finished | Aug 25 10:26:30 PM UTC 24 |
| Peak memory | 625920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_w ake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2091362127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2091362127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3264077777 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 5896719920 ps |
| CPU time | 853.17 seconds |
| Started | Aug 25 09:33:36 PM UTC 24 |
| Finished | Aug 25 09:48:06 PM UTC 24 |
| Peak memory | 625768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_r eset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3264077777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3264077777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2343957634 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 20708395980 ps |
| CPU time | 2897.37 seconds |
| Started | Aug 25 09:32:48 PM UTC 24 |
| Finished | Aug 25 10:22:03 PM UTC 24 |
| Peak memory | 625872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343957634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey _asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2343957634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2271086928 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 18582593250 ps |
| CPU time | 1615.79 seconds |
| Started | Aug 25 10:16:02 PM UTC 24 |
| Finished | Aug 25 10:43:28 PM UTC 24 |
| Peak memory | 625708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271086928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2271086928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3372274171 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5586560952 ps |
| CPU time | 698.04 seconds |
| Started | Aug 25 10:16:58 PM UTC 24 |
| Finished | Aug 25 10:28:50 PM UTC 24 |
| Peak memory | 625776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372274171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3372274171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1062531766 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3304175114 ps |
| CPU time | 408.87 seconds |
| Started | Aug 25 09:36:00 PM UTC 24 |
| Finished | Aug 25 09:42:58 PM UTC 24 |
| Peak memory | 625808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1062531766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.chip_sw_pwrmgr_sleep_disabled.1062531766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4113775737 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5104936652 ps |
| CPU time | 716.88 seconds |
| Started | Aug 25 10:04:49 PM UTC 24 |
| Finished | Aug 25 10:16:59 PM UTC 24 |
| Peak memory | 623868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_im ages=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113775737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4113775737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3116335941 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 6382106688 ps |
| CPU time | 682.22 seconds |
| Started | Aug 25 10:16:52 PM UTC 24 |
| Finished | Aug 25 10:28:28 PM UTC 24 |
| Peak memory | 625700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device =sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116335941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3116335941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.1236339972 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 6702071720 ps |
| CPU time | 837.82 seconds |
| Started | Aug 25 10:33:07 PM UTC 24 |
| Finished | Aug 25 10:47:21 PM UTC 24 |
| Peak memory | 625764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_ima ges=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236339972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1236339972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1623735061 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 7041031700 ps |
| CPU time | 1245.21 seconds |
| Started | Aug 25 09:32:07 PM UTC 24 |
| Finished | Aug 25 09:53:17 PM UTC 24 |
| Peak memory | 625864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1623735061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1623735061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2297212404 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 5595030980 ps |
| CPU time | 821.1 seconds |
| Started | Aug 25 09:35:08 PM UTC 24 |
| Finished | Aug 25 09:49:05 PM UTC 24 |
| Peak memory | 623844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_w hen_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2297212404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2297212404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1788384459 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6294399922 ps |
| CPU time | 865.93 seconds |
| Started | Aug 25 10:35:19 PM UTC 24 |
| Finished | Aug 25 10:50:01 PM UTC 24 |
| Peak memory | 623724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1788384459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_pwrmgr_usbdev_smoketest.1788384459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.952396795 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4422140328 ps |
| CPU time | 809.5 seconds |
| Started | Aug 25 09:41:38 PM UTC 24 |
| Finished | Aug 25 09:55:23 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952396795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.952396795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3045361392 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9029763848 ps |
| CPU time | 678.96 seconds |
| Started | Aug 25 10:00:48 PM UTC 24 |
| Finished | Aug 25 10:12:21 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3045361392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3045361392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2014124341 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 10669519394 ps |
| CPU time | 2468.63 seconds |
| Started | Aug 25 09:30:02 PM UTC 24 |
| Finished | Aug 25 10:11:57 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_buil d_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014124341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2014124341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.1884714105 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5340222064 ps |
| CPU time | 1084.99 seconds |
| Started | Aug 25 09:30:04 PM UTC 24 |
| Finished | Aug 25 09:48:28 PM UTC 24 |
| Peak memory | 623608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884714105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_rstmgr_cpu_info.1884714105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2910714652 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 4923650666 ps |
| CPU time | 913.28 seconds |
| Started | Aug 25 09:09:32 PM UTC 24 |
| Finished | Aug 25 09:25:03 PM UTC 24 |
| Peak memory | 668088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910714652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr _cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2910714652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3955680848 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2702297760 ps |
| CPU time | 292.57 seconds |
| Started | Aug 25 10:35:22 PM UTC 24 |
| Finished | Aug 25 10:40:21 PM UTC 24 |
| Peak memory | 623736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3955680848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_rstmgr_smoketest.3955680848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.3456796016 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 4948320188 ps |
| CPU time | 832.86 seconds |
| Started | Aug 25 09:28:36 PM UTC 24 |
| Finished | Aug 25 09:42:45 PM UTC 24 |
| Peak memory | 623908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3456796016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rstmgr_sw_req.3456796016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.1136260163 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 2349652152 ps |
| CPU time | 328.5 seconds |
| Started | Aug 25 09:29:09 PM UTC 24 |
| Finished | Aug 25 09:34:45 PM UTC 24 |
| Peak memory | 623796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1136260163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_rstmgr_sw_rst.1136260163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2359946978 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2630506460 ps |
| CPU time | 380.09 seconds |
| Started | Aug 25 10:20:38 PM UTC 24 |
| Finished | Aug 25 10:27:06 PM UTC 24 |
| Peak memory | 623516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_im ages=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359946978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2359946978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4263941484 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3375158924 ps |
| CPU time | 351.85 seconds |
| Started | Aug 25 10:21:25 PM UTC 24 |
| Finished | Aug 25 10:27:24 PM UTC 24 |
| Peak memory | 623748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_inval idate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4263941484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.4263941484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1804175292 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 2487808720 ps |
| CPU time | 299.06 seconds |
| Started | Aug 25 10:21:01 PM UTC 24 |
| Finished | Aug 25 10:26:07 PM UTC 24 |
| Peak memory | 662032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_ima ges=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1804175292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_gli tch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1804175292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4129018566 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4549169222 ps |
| CPU time | 1233.57 seconds |
| Started | Aug 25 09:44:40 PM UTC 24 |
| Finished | Aug 25 10:05:39 PM UTC 24 |
| Peak memory | 623812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129018566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4129018566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.3668370958 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 5324528194 ps |
| CPU time | 1313.23 seconds |
| Started | Aug 25 09:44:41 PM UTC 24 |
| Finished | Aug 25 10:07:01 PM UTC 24 |
| Peak memory | 623684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_b uild_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668370958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3668370958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4286565983 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5055786357 ps |
| CPU time | 542.66 seconds |
| Started | Aug 25 10:18:10 PM UTC 24 |
| Finished | Aug 25 10:27:25 PM UTC 24 |
| Peak memory | 635884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_han dler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286565983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_esc alation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.4286565983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.322737164 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 6606698750 ps |
| CPU time | 835.77 seconds |
| Started | Aug 25 10:18:05 PM UTC 24 |
| Finished | Aug 25 10:32:15 PM UTC 24 |
| Peak memory | 636096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_acc ess_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces /repo/hw/dv/tools/sim.tcl +ntb_random_seed=322737164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wake up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.322737164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3654402174 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 5205529270 ps |
| CPU time | 717.58 seconds |
| Started | Aug 25 10:18:02 PM UTC 24 |
| Finished | Aug 25 10:30:14 PM UTC 24 |
| Peak memory | 638080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm _reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654402174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_re set_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asi c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3654402174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.22973220 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2661446456 ps |
| CPU time | 319.23 seconds |
| Started | Aug 25 10:33:21 PM UTC 24 |
| Finished | Aug 25 10:38:48 PM UTC 24 |
| Peak memory | 623704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +n tb_random_seed=22973220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _rv_plic_smoketest.22973220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3707201443 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2630695080 ps |
| CPU time | 317.13 seconds |
| Started | Aug 25 09:35:20 PM UTC 24 |
| Finished | Aug 25 09:40:43 PM UTC 24 |
| Peak memory | 625736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3707201443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_irq.3707201443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.3723416448 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 2825557786 ps |
| CPU time | 362.73 seconds |
| Started | Aug 25 10:34:14 PM UTC 24 |
| Finished | Aug 25 10:40:24 PM UTC 24 |
| Peak memory | 625688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3723416448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_rv_timer_smoketest.3723416448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.2183931535 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 3556522506 ps |
| CPU time | 411.13 seconds |
| Started | Aug 25 10:03:29 PM UTC 24 |
| Finished | Aug 25 10:10:29 PM UTC 24 |
| Peak memory | 623784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183931535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_s tatus_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2183931535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_retention.1125259109 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3473896462 ps |
| CPU time | 520.76 seconds |
| Started | Aug 25 09:13:52 PM UTC 24 |
| Finished | Aug 25 09:22:43 PM UTC 24 |
| Peak memory | 623884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1125259109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sleep_pin_retention.1125259109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2691056156 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 8483591304 ps |
| CPU time | 1704.03 seconds |
| Started | Aug 25 09:14:16 PM UTC 24 |
| Finished | Aug 25 09:43:11 PM UTC 24 |
| Peak memory | 625884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2691056156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sleep_pwm_pulses.2691056156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.356322575 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 8010914770 ps |
| CPU time | 796.78 seconds |
| Started | Aug 25 10:02:26 PM UTC 24 |
| Finished | Aug 25 10:15:59 PM UTC 24 |
| Peak memory | 625704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356322575 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_ no_scramble.356322575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.220523326 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 9053544918 ps |
| CPU time | 1220.48 seconds |
| Started | Aug 25 10:03:23 PM UTC 24 |
| Finished | Aug 25 10:24:08 PM UTC 24 |
| Peak memory | 625792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220523326 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_sram_ret_contents_scramble.220523326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.4135653088 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5861963719 ps |
| CPU time | 942.57 seconds |
| Started | Aug 25 09:17:09 PM UTC 24 |
| Finished | Aug 25 09:33:11 PM UTC 24 |
| Peak memory | 640564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135653088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_spi_device_pass_through.4135653088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.1370812605 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4480551891 ps |
| CPU time | 924.73 seconds |
| Started | Aug 25 09:17:00 PM UTC 24 |
| Finished | Aug 25 09:32:43 PM UTC 24 |
| Peak memory | 640248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370812605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1370812605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3429208483 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3299351341 ps |
| CPU time | 365.99 seconds |
| Started | Aug 25 09:17:19 PM UTC 24 |
| Finished | Aug 25 09:23:33 PM UTC 24 |
| Peak memory | 636256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3429208483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3429208483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_tpm.3781196179 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2779731580 ps |
| CPU time | 379.96 seconds |
| Started | Aug 25 09:17:08 PM UTC 24 |
| Finished | Aug 25 09:23:37 PM UTC 24 |
| Peak memory | 636268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3781196179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_spi_device_tpm.3781196179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.1741926498 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 6620331792 ps |
| CPU time | 1057.91 seconds |
| Started | Aug 25 10:01:56 PM UTC 24 |
| Finished | Aug 25 10:19:55 PM UTC 24 |
| Peak memory | 625640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_ test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1741926498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1741926498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3390769307 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 5198596552 ps |
| CPU time | 821.94 seconds |
| Started | Aug 25 10:01:19 PM UTC 24 |
| Finished | Aug 25 10:15:17 PM UTC 24 |
| Peak memory | 625900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_ alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390769307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_ access.3390769307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3435667230 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 4355818717 ps |
| CPU time | 916.29 seconds |
| Started | Aug 25 10:01:49 PM UTC 24 |
| Finished | Aug 25 10:17:23 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_ch eck=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435667230 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ct rl_scrambled_access_jitter_en.3435667230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4048347025 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 4374599675 ps |
| CPU time | 547.2 seconds |
| Started | Aug 25 10:24:45 PM UTC 24 |
| Finished | Aug 25 10:34:02 PM UTC 24 |
| Peak memory | 625912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_r eady_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048347025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4048347025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.4042236593 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2760709980 ps |
| CPU time | 414.8 seconds |
| Started | Aug 25 10:35:48 PM UTC 24 |
| Finished | Aug 25 10:42:51 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042236593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_sram_ctrl_smoketest.4042236593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2709469081 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 20420013362 ps |
| CPU time | 5665.62 seconds |
| Started | Aug 25 09:39:06 PM UTC 24 |
| Finished | Aug 25 11:15:16 PM UTC 24 |
| Peak memory | 625952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2709469081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2709469081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3211297990 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 4804412453 ps |
| CPU time | 892.7 seconds |
| Started | Aug 25 09:35:27 PM UTC 24 |
| Finished | Aug 25 09:50:40 PM UTC 24 |
| Peak memory | 628188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3211297990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3211297990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3746098788 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3537352583 ps |
| CPU time | 576.76 seconds |
| Started | Aug 25 09:35:30 PM UTC 24 |
| Finished | Aug 25 09:45:20 PM UTC 24 |
| Peak memory | 626004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3746098788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_sysrst_ctrl_inputs.3746098788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2540525467 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3212503000 ps |
| CPU time | 481.02 seconds |
| Started | Aug 25 09:37:13 PM UTC 24 |
| Finished | Aug 25 09:45:24 PM UTC 24 |
| Peak memory | 625896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test: 1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2540525467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2540525467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.51458608 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 24467668040 ps |
| CPU time | 2750.21 seconds |
| Started | Aug 25 09:35:51 PM UTC 24 |
| Finished | Aug 25 10:22:35 PM UTC 24 |
| Peak memory | 630056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_i mages=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51458608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.51458608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2465873181 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5336042236 ps |
| CPU time | 836.27 seconds |
| Started | Aug 25 09:35:46 PM UTC 24 |
| Finished | Aug 25 09:50:00 PM UTC 24 |
| Peak memory | 623904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/too ls/sim.tcl +ntb_random_seed=2465873181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2465873181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.1612149494 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 13668280176 ps |
| CPU time | 3989.18 seconds |
| Started | Aug 25 09:16:51 PM UTC 24 |
| Finished | Aug 25 10:24:39 PM UTC 24 |
| Peak memory | 636028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612149494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1612149494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.2541986617 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2846821624 ps |
| CPU time | 313.4 seconds |
| Started | Aug 25 10:36:12 PM UTC 24 |
| Finished | Aug 25 10:41:32 PM UTC 24 |
| Peak memory | 629836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rule s,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ random_seed=2541986617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_sw_uart_smoketest.2541986617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_smoketest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.942255431 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4898617192 ps |
| CPU time | 961.4 seconds |
| Started | Aug 25 09:15:38 PM UTC 24 |
| Finished | Aug 25 09:31:58 PM UTC 24 |
| Peak memory | 640112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942255431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.942255431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4158490085 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 8829857697 ps |
| CPU time | 2684.51 seconds |
| Started | Aug 25 09:14:10 PM UTC 24 |
| Finished | Aug 25 09:59:44 PM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158490085 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq.4158490085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3008709370 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4377433707 ps |
| CPU time | 694.89 seconds |
| Started | Aug 25 09:13:17 PM UTC 24 |
| Finished | Aug 25 09:25:06 PM UTC 24 |
| Peak memory | 634224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008709370 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3008709370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1231758872 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 78782475080 ps |
| CPU time | 17384.3 seconds |
| Started | Aug 25 09:13:11 PM UTC 24 |
| Finished | Aug 26 02:06:59 AM UTC 24 |
| Peak memory | 657696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout _ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231758872 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ch ip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1231758872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx1.1898276160 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3985659600 ps |
| CPU time | 736.27 seconds |
| Started | Aug 25 09:14:17 PM UTC 24 |
| Finished | Aug 25 09:26:47 PM UTC 24 |
| Peak memory | 640200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898276160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1898276160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx2.2363359065 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4441674056 ps |
| CPU time | 807.19 seconds |
| Started | Aug 25 09:13:18 PM UTC 24 |
| Finished | Aug 25 09:27:00 PM UTC 24 |
| Peak memory | 640252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363359065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2363359065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_idx3.861780448 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4533066984 ps |
| CPU time | 773.51 seconds |
| Started | Aug 25 09:13:55 PM UTC 24 |
| Finished | Aug 25 09:27:04 PM UTC 24 |
| Peak memory | 640056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861780448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.861780448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2389618558 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 3091102045 ps |
| CPU time | 299.07 seconds |
| Started | Aug 25 10:18:47 PM UTC 24 |
| Finished | Aug 25 10:23:53 PM UTC 24 |
| Peak memory | 640116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389618558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2389618558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2313733906 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 3028438177 ps |
| CPU time | 217.13 seconds |
| Started | Aug 25 10:20:31 PM UTC 24 |
| Finished | Aug 25 10:24:15 PM UTC 24 |
| Peak memory | 640124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313733906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2313733906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2607416552 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2477702202 ps |
| CPU time | 210.28 seconds |
| Started | Aug 25 10:19:41 PM UTC 24 |
| Finished | Aug 25 10:23:16 PM UTC 24 |
| Peak memory | 642160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607416552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2607416552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.798408416 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4446480755 ps |
| CPU time | 585.13 seconds |
| Started | Aug 25 10:19:31 PM UTC 24 |
| Finished | Aug 25 10:29:28 PM UTC 24 |
| Peak memory | 650884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798408416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.798408416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1835388760 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 15709720016 ps |
| CPU time | 5318.96 seconds |
| Started | Aug 25 10:34:08 PM UTC 24 |
| Finished | Aug 26 12:04:22 AM UTC 24 |
| Peak memory | 624724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835388760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1835388760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.1842873683 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 15021630419 ps |
| CPU time | 5177.12 seconds |
| Started | Aug 25 10:31:18 PM UTC 24 |
| Finished | Aug 25 11:59:07 PM UTC 24 |
| Peak memory | 627108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842873683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1842873683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2602343308 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 16054255714 ps |
| CPU time | 5398.16 seconds |
| Started | Aug 25 10:32:52 PM UTC 24 |
| Finished | Aug 26 12:04:24 AM UTC 24 |
| Peak memory | 626904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260234 3308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_in it_prod_end.2602343308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2032299894 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 14793716924 ps |
| CPU time | 5386.43 seconds |
| Started | Aug 25 10:36:28 PM UTC 24 |
| Finished | Aug 26 12:07:47 AM UTC 24 |
| Peak memory | 629204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +s w_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032299894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2032299894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1351115998 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 11486699757 ps |
| CPU time | 4498.96 seconds |
| Started | Aug 25 10:30:54 PM UTC 24 |
| Finished | Aug 25 11:47:13 PM UTC 24 |
| Peak memory | 627136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1351115998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e 2e_asm_init_test_unlocked0.1351115998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3042554808 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 14626714188 ps |
| CPU time | 5605.29 seconds |
| Started | Aug 25 10:36:44 PM UTC 24 |
| Finished | Aug 26 12:11:44 AM UTC 24 |
| Peak memory | 626992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid_meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042554808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3042554808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.850848784 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 14571525116 ps |
| CPU time | 5251.76 seconds |
| Started | Aug 25 10:30:01 PM UTC 24 |
| Finished | Aug 25 11:59:08 PM UTC 24 |
| Peak memory | 625088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1:new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850848784 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.850848784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2995747327 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 15143524450 ps |
| CPU time | 5244.41 seconds |
| Started | Aug 25 10:31:30 PM UTC 24 |
| Finished | Aug 26 12:00:30 AM UTC 24 |
| Peak memory | 626988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas:1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995747327 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_no_meas.2995747327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1293601739 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 27115637960 ps |
| CPU time | 7116.03 seconds |
| Started | Aug 25 10:32:51 PM UTC 24 |
| Finished | Aug 26 12:33:20 AM UTC 24 |
| Peak memory | 627028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_rules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293601739 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1293601739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.2906570800 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 14341585652 ps |
| CPU time | 5394.41 seconds |
| Started | Aug 25 10:32:20 PM UTC 24 |
| Finished | Aug 26 12:03:47 AM UTC 24 |
| Peak memory | 625036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906570800 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.2906570800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.4066126590 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 24004593725 ps |
| CPU time | 4884.67 seconds |
| Started | Aug 25 10:34:55 PM UTC 24 |
| Finished | Aug 25 11:57:49 PM UTC 24 |
| Peak memory | 625892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_flash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066126590 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.4066126590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3560896930 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 14923259744 ps |
| CPU time | 5087.06 seconds |
| Started | Aug 25 10:36:28 PM UTC 24 |
| Finished | Aug 26 12:02:47 AM UTC 24 |
| Peak memory | 625992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560896930 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24 /chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3560896930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3589834965 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 16339446504 ps |
| CPU time | 5876.98 seconds |
| Started | Aug 25 10:32:29 PM UTC 24 |
| Finished | Aug 26 12:12:03 AM UTC 24 |
| Peak memory | 626784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +s w_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589834965 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3589834965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.55749811 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4745623744 ps |
| CPU time | 695.42 seconds |
| Started | Aug 25 10:34:11 PM UTC 24 |
| Finished | Aug 25 10:46:02 PM UTC 24 |
| Peak memory | 625796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_i mages=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace s/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55749811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.55749811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.4206727033 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5365932423 ps |
| CPU time | 373.63 seconds |
| Started | Aug 25 10:31:49 PM UTC 24 |
| Finished | Aug 25 10:38:10 PM UTC 24 |
| Peak memory | 637732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images =empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206727033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.4206727033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2110952793 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 1774678419 ps |
| CPU time | 132.55 seconds |
| Started | Aug 25 10:29:06 PM UTC 24 |
| Finished | Aug 25 10:31:22 PM UTC 24 |
| Peak memory | 633328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRa w +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot _flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2110952793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2110952793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1360280877 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4023601950 ps |
| CPU time | 528.51 seconds |
| Started | Aug 25 11:13:00 PM UTC 24 |
| Finished | Aug 25 11:21:59 PM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360280877 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1360280877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.131947514 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 5289436040 ps |
| CPU time | 704.34 seconds |
| Started | Aug 25 11:12:38 PM UTC 24 |
| Finished | Aug 25 11:24:37 PM UTC 24 |
| Peak memory | 674280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131947514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.131947514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2765359442 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5710154760 ps |
| CPU time | 942.32 seconds |
| Started | Aug 25 11:15:26 PM UTC 24 |
| Finished | Aug 25 11:31:27 PM UTC 24 |
| Peak memory | 674404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765359442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2765359442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2209258487 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 5324544072 ps |
| CPU time | 736.51 seconds |
| Started | Aug 25 11:18:06 PM UTC 24 |
| Finished | Aug 25 11:30:38 PM UTC 24 |
| Peak memory | 674540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209258487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2209258487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958035402 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4004998584 ps |
| CPU time | 546.56 seconds |
| Started | Aug 25 11:17:46 PM UTC 24 |
| Finished | Aug 25 11:27:04 PM UTC 24 |
| Peak memory | 672472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958035402 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2958035402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2785766761 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5036258656 ps |
| CPU time | 944.3 seconds |
| Started | Aug 25 11:17:59 PM UTC 24 |
| Finished | Aug 25 11:34:02 PM UTC 24 |
| Peak memory | 674268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785766761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.2785766761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278740850 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4001663916 ps |
| CPU time | 675.85 seconds |
| Started | Aug 25 11:18:11 PM UTC 24 |
| Finished | Aug 25 11:29:41 PM UTC 24 |
| Peak memory | 672236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278740850 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2278740850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.611628385 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5126864720 ps |
| CPU time | 921.96 seconds |
| Started | Aug 25 10:37:29 PM UTC 24 |
| Finished | Aug 25 10:53:08 PM UTC 24 |
| Peak memory | 674404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611628385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.611628385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.20493187 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 6824071248 ps |
| CPU time | 865.93 seconds |
| Started | Aug 25 10:39:28 PM UTC 24 |
| Finished | Aug 25 10:54:10 PM UTC 24 |
| Peak memory | 623732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20493187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_b ase_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.20493187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3108409170 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 20090831200 ps |
| CPU time | 6632.15 seconds |
| Started | Aug 25 10:39:48 PM UTC 24 |
| Finished | Aug 26 12:32:00 AM UTC 24 |
| Peak memory | 626864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3108409170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.chip_sw_csrng_edn_concurrency.3108409170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.828862120 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 6388055856 ps |
| CPU time | 1007.17 seconds |
| Started | Aug 25 10:36:06 PM UTC 24 |
| Finished | Aug 25 10:53:13 PM UTC 24 |
| Peak memory | 625912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828862120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.828862120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.170930016 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 10468235280 ps |
| CPU time | 1251.75 seconds |
| Started | Aug 25 10:39:25 PM UTC 24 |
| Finished | Aug 25 11:00:41 PM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=170930016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.chip_sw_lc_ctrl_transition.170930016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3082800198 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 7169867594 ps |
| CPU time | 872.8 seconds |
| Started | Aug 25 10:39:46 PM UTC 24 |
| Finished | Aug 25 10:54:36 PM UTC 24 |
| Peak memory | 623788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082800198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3082800198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.837294115 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 9518159932 ps |
| CPU time | 2593.54 seconds |
| Started | Aug 25 10:37:52 PM UTC 24 |
| Finished | Aug 25 11:21:53 PM UTC 24 |
| Peak memory | 636216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837294115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.837294115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2861429054 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4813678988 ps |
| CPU time | 864.67 seconds |
| Started | Aug 25 10:37:07 PM UTC 24 |
| Finished | Aug 25 10:51:50 PM UTC 24 |
| Peak memory | 640232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861429054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2861429054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3164965469 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 8614138701 ps |
| CPU time | 2187.96 seconds |
| Started | Aug 25 10:37:44 PM UTC 24 |
| Finished | Aug 25 11:14:54 PM UTC 24 |
| Peak memory | 636156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164965469 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq.3164965469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1022024720 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 8981059027 ps |
| CPU time | 1327.95 seconds |
| Started | Aug 25 10:37:53 PM UTC 24 |
| Finished | Aug 25 11:00:25 PM UTC 24 |
| Peak memory | 636332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022024720 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1022024720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2147634007 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 4019811560 ps |
| CPU time | 848.56 seconds |
| Started | Aug 25 10:37:21 PM UTC 24 |
| Finished | Aug 25 10:51:47 PM UTC 24 |
| Peak memory | 640100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147634007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2147634007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.929761755 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4210615792 ps |
| CPU time | 800.6 seconds |
| Started | Aug 25 10:37:43 PM UTC 24 |
| Finished | Aug 25 10:51:19 PM UTC 24 |
| Peak memory | 640100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929761755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.929761755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1609026229 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4390221250 ps |
| CPU time | 870.11 seconds |
| Started | Aug 25 10:37:07 PM UTC 24 |
| Finished | Aug 25 10:51:54 PM UTC 24 |
| Peak memory | 639980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609026229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1609026229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.4018485258 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3378107528 ps |
| CPU time | 366.88 seconds |
| Started | Aug 25 10:39:32 PM UTC 24 |
| Finished | Aug 25 10:45:48 PM UTC 24 |
| Peak memory | 638304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018485258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.4018485258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.4096166278 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 7724214287 ps |
| CPU time | 905.16 seconds |
| Started | Aug 25 10:40:06 PM UTC 24 |
| Finished | Aug 25 10:55:28 PM UTC 24 |
| Peak memory | 640436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096166278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.4096166278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.1935053639 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5835090808 ps |
| CPU time | 863.01 seconds |
| Started | Aug 25 10:39:57 PM UTC 24 |
| Finished | Aug 25 10:54:36 PM UTC 24 |
| Peak memory | 638704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935053639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1935053639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.578993661 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3567594151 ps |
| CPU time | 422.83 seconds |
| Started | Aug 25 10:39:49 PM UTC 24 |
| Finished | Aug 25 10:47:01 PM UTC 24 |
| Peak memory | 640448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578993661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlg rey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.578993661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.452288355 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3499496114 ps |
| CPU time | 580.15 seconds |
| Started | Aug 25 11:18:16 PM UTC 24 |
| Finished | Aug 25 11:28:08 PM UTC 24 |
| Peak memory | 672476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452288355 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_alert_handler_lpg_s leep_mode_alerts.452288355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3276290939 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3962043536 ps |
| CPU time | 642.75 seconds |
| Started | Aug 25 11:19:58 PM UTC 24 |
| Finished | Aug 25 11:30:55 PM UTC 24 |
| Peak memory | 672480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276290939 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3276290939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1876304722 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3557033300 ps |
| CPU time | 510.93 seconds |
| Started | Aug 25 11:20:43 PM UTC 24 |
| Finished | Aug 25 11:29:26 PM UTC 24 |
| Peak memory | 668300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876304722 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1876304722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.300234320 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3540975616 ps |
| CPU time | 572.82 seconds |
| Started | Aug 25 11:21:57 PM UTC 24 |
| Finished | Aug 25 11:31:42 PM UTC 24 |
| Peak memory | 672424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300234320 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_alert_handler_lpg_s leep_mode_alerts.300234320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718429255 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3767957512 ps |
| CPU time | 619.77 seconds |
| Started | Aug 25 11:22:37 PM UTC 24 |
| Finished | Aug 25 11:33:09 PM UTC 24 |
| Peak memory | 672232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718429255 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1718429255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1879858279 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 5530491508 ps |
| CPU time | 909.11 seconds |
| Started | Aug 25 11:23:14 PM UTC 24 |
| Finished | Aug 25 11:38:40 PM UTC 24 |
| Peak memory | 636356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879858279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1879858279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4216494515 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4521000280 ps |
| CPU time | 678.46 seconds |
| Started | Aug 25 11:23:18 PM UTC 24 |
| Finished | Aug 25 11:34:51 PM UTC 24 |
| Peak memory | 672540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216494515 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_alert_handler_lpg_ sleep_mode_alerts.4216494515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3462765186 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3983832152 ps |
| CPU time | 533.58 seconds |
| Started | Aug 25 11:22:53 PM UTC 24 |
| Finished | Aug 25 11:31:57 PM UTC 24 |
| Peak memory | 672556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462765186 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3462765186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.717759492 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4059446160 ps |
| CPU time | 550.97 seconds |
| Started | Aug 25 11:22:40 PM UTC 24 |
| Finished | Aug 25 11:32:03 PM UTC 24 |
| Peak memory | 672500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717759492 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_alert_handler_lpg_s leep_mode_alerts.717759492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2236015170 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 4697368740 ps |
| CPU time | 817.55 seconds |
| Started | Aug 25 11:23:18 PM UTC 24 |
| Finished | Aug 25 11:37:10 PM UTC 24 |
| Peak memory | 672372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236015170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2236015170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1853084163 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5692769400 ps |
| CPU time | 815.33 seconds |
| Started | Aug 25 11:23:45 PM UTC 24 |
| Finished | Aug 25 11:37:36 PM UTC 24 |
| Peak memory | 674508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853084163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1853084163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3831458468 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 4107174520 ps |
| CPU time | 596.59 seconds |
| Started | Aug 25 10:44:24 PM UTC 24 |
| Finished | Aug 25 10:54:33 PM UTC 24 |
| Peak memory | 636284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831458468 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_alert_handler_lpg_s leep_mode_alerts.3831458468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.4197978070 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5042787068 ps |
| CPU time | 1043.85 seconds |
| Started | Aug 25 10:40:34 PM UTC 24 |
| Finished | Aug 25 10:58:19 PM UTC 24 |
| Peak memory | 625856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197978070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4197978070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.465056621 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 7238791108 ps |
| CPU time | 589.31 seconds |
| Started | Aug 25 10:44:23 PM UTC 24 |
| Finished | Aug 25 10:54:24 PM UTC 24 |
| Peak memory | 625992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_i mages=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465056621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.465056621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.932434427 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 26257701500 ps |
| CPU time | 7426.82 seconds |
| Started | Aug 25 10:45:03 PM UTC 24 |
| Finished | Aug 26 12:50:35 AM UTC 24 |
| Peak memory | 628840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=932434427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 4.chip_sw_csrng_edn_concurrency.932434427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.2296179755 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4735551752 ps |
| CPU time | 814.96 seconds |
| Started | Aug 25 10:42:13 PM UTC 24 |
| Finished | Aug 25 10:56:04 PM UTC 24 |
| Peak memory | 625880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296179755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2296179755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.184696627 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 6217151860 ps |
| CPU time | 682 seconds |
| Started | Aug 25 10:43:32 PM UTC 24 |
| Finished | Aug 25 10:55:08 PM UTC 24 |
| Peak memory | 635960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=184696627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.chip_sw_lc_ctrl_transition.184696627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.4029870159 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 4868063742 ps |
| CPU time | 792.76 seconds |
| Started | Aug 25 10:46:42 PM UTC 24 |
| Finished | Aug 25 11:00:10 PM UTC 24 |
| Peak memory | 625860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_i mages=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029870159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4029870159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.4253841839 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 9211612040 ps |
| CPU time | 2577.22 seconds |
| Started | Aug 25 10:42:12 PM UTC 24 |
| Finished | Aug 25 11:25:57 PM UTC 24 |
| Peak memory | 636164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253841839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.4253841839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2223602000 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 4420433384 ps |
| CPU time | 882.04 seconds |
| Started | Aug 25 10:42:14 PM UTC 24 |
| Finished | Aug 25 10:57:13 PM UTC 24 |
| Peak memory | 639980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223602000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2223602000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3241864973 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 7827099304 ps |
| CPU time | 1995.96 seconds |
| Started | Aug 25 10:42:49 PM UTC 24 |
| Finished | Aug 25 11:16:42 PM UTC 24 |
| Peak memory | 636184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockS ourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241864973 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq.3241864973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1109093723 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 4271090566 ps |
| CPU time | 719.57 seconds |
| Started | Aug 25 10:42:54 PM UTC 24 |
| Finished | Aug 25 10:55:08 PM UTC 24 |
| Peak memory | 636024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_cl ock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109093723 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1109093723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.1909373518 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4953589200 ps |
| CPU time | 881.68 seconds |
| Started | Aug 25 10:42:47 PM UTC 24 |
| Finished | Aug 25 10:57:45 PM UTC 24 |
| Peak memory | 640216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909373518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1909373518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.4229534156 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4427566500 ps |
| CPU time | 873.48 seconds |
| Started | Aug 25 10:42:15 PM UTC 24 |
| Finished | Aug 25 10:57:05 PM UTC 24 |
| Peak memory | 640368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229534156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.4229534156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.302161211 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4633212168 ps |
| CPU time | 765.22 seconds |
| Started | Aug 25 10:42:29 PM UTC 24 |
| Finished | Aug 25 10:55:31 PM UTC 24 |
| Peak memory | 640180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw _images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302161211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.302161211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.3363769337 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 4144828865 ps |
| CPU time | 395.51 seconds |
| Started | Aug 25 10:46:38 PM UTC 24 |
| Finished | Aug 25 10:53:21 PM UTC 24 |
| Peak memory | 650292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_b uild_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363769337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3363769337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_dev/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.3663373974 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 11522954434 ps |
| CPU time | 1936.81 seconds |
| Started | Aug 25 10:48:06 PM UTC 24 |
| Finished | Aug 25 11:20:56 PM UTC 24 |
| Peak memory | 642480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_ build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663373974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3663373974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_prod/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.1141051493 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3689993941 ps |
| CPU time | 381.33 seconds |
| Started | Aug 25 10:47:35 PM UTC 24 |
| Finished | Aug 25 10:54:04 PM UTC 24 |
| Peak memory | 652976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images= example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac es/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141051493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1141051493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3949417156 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 11226457038 ps |
| CPU time | 1590.67 seconds |
| Started | Aug 25 10:46:36 PM UTC 24 |
| Finished | Aug 25 11:13:36 PM UTC 24 |
| Peak memory | 640640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_m ap=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949417156 -assert nopostproc +UVM_TESTNAME=chip_base_test +U VM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earl grey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3949417156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.660904262 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3541976212 ps |
| CPU time | 483.5 seconds |
| Started | Aug 25 11:24:18 PM UTC 24 |
| Finished | Aug 25 11:32:32 PM UTC 24 |
| Peak memory | 672388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660904262 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_alert_handler_lpg_s leep_mode_alerts.660904262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.1809668681 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 6650972968 ps |
| CPU time | 986.97 seconds |
| Started | Aug 25 11:23:55 PM UTC 24 |
| Finished | Aug 25 11:40:41 PM UTC 24 |
| Peak memory | 674648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809668681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1809668681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1513522699 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4449531590 ps |
| CPU time | 493.5 seconds |
| Started | Aug 25 11:26:09 PM UTC 24 |
| Finished | Aug 25 11:34:33 PM UTC 24 |
| Peak memory | 672300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513522699 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1513522699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.1434582419 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6394421368 ps |
| CPU time | 883.93 seconds |
| Started | Aug 25 11:26:40 PM UTC 24 |
| Finished | Aug 25 11:41:40 PM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434582419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1434582419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2428559500 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3413852964 ps |
| CPU time | 596.5 seconds |
| Started | Aug 25 11:29:42 PM UTC 24 |
| Finished | Aug 25 11:39:49 PM UTC 24 |
| Peak memory | 672388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428559500 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2428559500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3995974027 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6147821074 ps |
| CPU time | 878.58 seconds |
| Started | Aug 25 11:29:44 PM UTC 24 |
| Finished | Aug 25 11:44:39 PM UTC 24 |
| Peak memory | 674592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995974027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3995974027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1731381014 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3266265152 ps |
| CPU time | 461.02 seconds |
| Started | Aug 25 11:30:27 PM UTC 24 |
| Finished | Aug 25 11:38:17 PM UTC 24 |
| Peak memory | 672496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731381014 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1731381014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.448362515 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4469573400 ps |
| CPU time | 578.22 seconds |
| Started | Aug 25 11:36:12 PM UTC 24 |
| Finished | Aug 25 11:46:02 PM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448362515 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_alert_handler_lpg_s leep_mode_alerts.448362515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.2342310303 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4905909082 ps |
| CPU time | 969.29 seconds |
| Started | Aug 25 11:30:27 PM UTC 24 |
| Finished | Aug 25 11:46:54 PM UTC 24 |
| Peak memory | 674436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342310303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2342310303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2486011781 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3392340024 ps |
| CPU time | 583.25 seconds |
| Started | Aug 25 11:31:01 PM UTC 24 |
| Finished | Aug 25 11:40:54 PM UTC 24 |
| Peak memory | 672348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486011781 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2486011781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1369599894 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5006968872 ps |
| CPU time | 1050.54 seconds |
| Started | Aug 25 11:30:26 PM UTC 24 |
| Finished | Aug 25 11:48:15 PM UTC 24 |
| Peak memory | 674540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369599894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.1369599894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1475073508 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4445806740 ps |
| CPU time | 787.86 seconds |
| Started | Aug 25 10:48:12 PM UTC 24 |
| Finished | Aug 25 11:01:36 PM UTC 24 |
| Peak memory | 674288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475073508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1475073508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2903229734 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 18604170712 ps |
| CPU time | 5996.68 seconds |
| Started | Aug 25 10:51:00 PM UTC 24 |
| Finished | Aug 26 12:32:28 AM UTC 24 |
| Peak memory | 628836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2903229734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.chip_sw_csrng_edn_concurrency.2903229734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1929057055 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4773321100 ps |
| CPU time | 851.83 seconds |
| Started | Aug 25 10:49:03 PM UTC 24 |
| Finished | Aug 25 11:03:31 PM UTC 24 |
| Peak memory | 625712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=data_integrity_escalation_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929057055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1929057055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1030971528 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 11265162880 ps |
| CPU time | 1155.17 seconds |
| Started | Aug 25 10:49:10 PM UTC 24 |
| Finished | Aug 25 11:08:47 PM UTC 24 |
| Peak memory | 638012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1030971528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.chip_sw_lc_ctrl_transition.1030971528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.269781395 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 8566791292 ps |
| CPU time | 2094.61 seconds |
| Started | Aug 25 10:49:10 PM UTC 24 |
| Finished | Aug 25 11:24:45 PM UTC 24 |
| Peak memory | 635956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269781395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_u art_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.269781395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.452404514 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4183661050 ps |
| CPU time | 716.01 seconds |
| Started | Aug 25 11:33:23 PM UTC 24 |
| Finished | Aug 25 11:45:32 PM UTC 24 |
| Peak memory | 672500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452404514 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_alert_handler_lpg_s leep_mode_alerts.452404514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2902770863 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4282111070 ps |
| CPU time | 617.26 seconds |
| Started | Aug 25 11:33:00 PM UTC 24 |
| Finished | Aug 25 11:43:28 PM UTC 24 |
| Peak memory | 672400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902770863 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2902770863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.3506806127 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4600890726 ps |
| CPU time | 766.39 seconds |
| Started | Aug 25 11:33:38 PM UTC 24 |
| Finished | Aug 25 11:46:40 PM UTC 24 |
| Peak memory | 674444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506806127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3506806127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2694216879 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4100686284 ps |
| CPU time | 576.14 seconds |
| Started | Aug 25 11:35:24 PM UTC 24 |
| Finished | Aug 25 11:45:12 PM UTC 24 |
| Peak memory | 672312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694216879 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2694216879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.2575126611 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5419417028 ps |
| CPU time | 824.93 seconds |
| Started | Aug 25 11:33:01 PM UTC 24 |
| Finished | Aug 25 11:47:01 PM UTC 24 |
| Peak memory | 674548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575126611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.2575126611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1838238589 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3768421544 ps |
| CPU time | 525.36 seconds |
| Started | Aug 25 11:35:26 PM UTC 24 |
| Finished | Aug 25 11:44:22 PM UTC 24 |
| Peak memory | 672452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838238589 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1838238589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3248269617 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 5757883936 ps |
| CPU time | 941.31 seconds |
| Started | Aug 25 11:36:59 PM UTC 24 |
| Finished | Aug 25 11:52:57 PM UTC 24 |
| Peak memory | 674328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248269617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3248269617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883412818 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3449698864 ps |
| CPU time | 554.2 seconds |
| Started | Aug 25 11:34:32 PM UTC 24 |
| Finished | Aug 25 11:43:57 PM UTC 24 |
| Peak memory | 672416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883412818 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3883412818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2609111095 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 5541158600 ps |
| CPU time | 825.58 seconds |
| Started | Aug 25 11:38:02 PM UTC 24 |
| Finished | Aug 25 11:52:04 PM UTC 24 |
| Peak memory | 674532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609111095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2609111095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3559113067 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3762299940 ps |
| CPU time | 647.71 seconds |
| Started | Aug 25 11:36:59 PM UTC 24 |
| Finished | Aug 25 11:48:00 PM UTC 24 |
| Peak memory | 672432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559113067 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3559113067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.351625086 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3658259776 ps |
| CPU time | 551.47 seconds |
| Started | Aug 25 11:36:20 PM UTC 24 |
| Finished | Aug 25 11:45:43 PM UTC 24 |
| Peak memory | 672492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351625086 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_alert_handler_lpg_s leep_mode_alerts.351625086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3815837638 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4522152560 ps |
| CPU time | 696.12 seconds |
| Started | Aug 25 11:38:50 PM UTC 24 |
| Finished | Aug 25 11:50:40 PM UTC 24 |
| Peak memory | 672484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815837638 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3815837638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.989812649 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 3185225160 ps |
| CPU time | 488.57 seconds |
| Started | Aug 25 11:40:04 PM UTC 24 |
| Finished | Aug 25 11:48:22 PM UTC 24 |
| Peak memory | 672316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989812649 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_alert_handler_lpg_s leep_mode_alerts.989812649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.3172712310 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 5768787306 ps |
| CPU time | 857.77 seconds |
| Started | Aug 25 11:35:37 PM UTC 24 |
| Finished | Aug 25 11:50:11 PM UTC 24 |
| Peak memory | 674548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172712310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3172712310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3646529686 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 6238146168 ps |
| CPU time | 936.7 seconds |
| Started | Aug 25 11:37:36 PM UTC 24 |
| Finished | Aug 25 11:53:29 PM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646529686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3646529686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127195425 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4532008756 ps |
| CPU time | 605.3 seconds |
| Started | Aug 25 10:55:16 PM UTC 24 |
| Finished | Aug 25 11:05:33 PM UTC 24 |
| Peak memory | 672452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127195425 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_alert_handler_lpg_s leep_mode_alerts.2127195425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.372790120 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5018141880 ps |
| CPU time | 926.15 seconds |
| Started | Aug 25 10:52:02 PM UTC 24 |
| Finished | Aug 25 11:07:46 PM UTC 24 |
| Peak memory | 674444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372790120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.372790120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.1548482360 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 22553392570 ps |
| CPU time | 6131.82 seconds |
| Started | Aug 25 10:56:51 PM UTC 24 |
| Finished | Aug 26 12:40:32 AM UTC 24 |
| Peak memory | 629056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1548482360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.chip_sw_csrng_edn_concurrency.1548482360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.2481265448 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 12218235315 ps |
| CPU time | 1474.75 seconds |
| Started | Aug 25 10:53:44 PM UTC 24 |
| Finished | Aug 25 11:18:46 PM UTC 24 |
| Peak memory | 636188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2481265448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.chip_sw_lc_ctrl_transition.2481265448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3943649563 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 4032595040 ps |
| CPU time | 848.06 seconds |
| Started | Aug 25 10:58:57 PM UTC 24 |
| Finished | Aug 25 11:13:23 PM UTC 24 |
| Peak memory | 635888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943649563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3943649563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1827458109 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4522008800 ps |
| CPU time | 743.35 seconds |
| Started | Aug 25 11:37:03 PM UTC 24 |
| Finished | Aug 25 11:49:39 PM UTC 24 |
| Peak memory | 674592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827458109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1827458109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708759546 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3640501944 ps |
| CPU time | 486.67 seconds |
| Started | Aug 25 11:37:01 PM UTC 24 |
| Finished | Aug 25 11:45:17 PM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708759546 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1708759546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.2670510452 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5906901432 ps |
| CPU time | 760.34 seconds |
| Started | Aug 25 11:37:06 PM UTC 24 |
| Finished | Aug 25 11:50:01 PM UTC 24 |
| Peak memory | 674476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670510452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2670510452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165632888 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3836060360 ps |
| CPU time | 593.73 seconds |
| Started | Aug 25 11:37:07 PM UTC 24 |
| Finished | Aug 25 11:47:12 PM UTC 24 |
| Peak memory | 672464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165632888 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3165632888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1264229372 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3147393472 ps |
| CPU time | 486.03 seconds |
| Started | Aug 25 11:38:30 PM UTC 24 |
| Finished | Aug 25 11:46:46 PM UTC 24 |
| Peak memory | 672296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264229372 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1264229372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.380426481 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 6439372798 ps |
| CPU time | 862.96 seconds |
| Started | Aug 25 11:38:18 PM UTC 24 |
| Finished | Aug 25 11:52:59 PM UTC 24 |
| Peak memory | 674484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380426481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.380426481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049634480 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3753932344 ps |
| CPU time | 686.46 seconds |
| Started | Aug 25 11:39:51 PM UTC 24 |
| Finished | Aug 25 11:51:30 PM UTC 24 |
| Peak memory | 672300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049634480 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3049634480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1165807673 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5146042856 ps |
| CPU time | 824.91 seconds |
| Started | Aug 25 11:38:02 PM UTC 24 |
| Finished | Aug 25 11:52:03 PM UTC 24 |
| Peak memory | 674528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165807673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1165807673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1831883541 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4213281436 ps |
| CPU time | 666.56 seconds |
| Started | Aug 25 11:40:19 PM UTC 24 |
| Finished | Aug 25 11:51:38 PM UTC 24 |
| Peak memory | 636392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831883541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1831883541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2664267744 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3083766516 ps |
| CPU time | 448.15 seconds |
| Started | Aug 25 11:41:03 PM UTC 24 |
| Finished | Aug 25 11:48:40 PM UTC 24 |
| Peak memory | 672608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664267744 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2664267744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2840589550 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4474381500 ps |
| CPU time | 966.51 seconds |
| Started | Aug 25 11:40:31 PM UTC 24 |
| Finished | Aug 25 11:56:54 PM UTC 24 |
| Peak memory | 674352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840589550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2840589550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564727227 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 3623037170 ps |
| CPU time | 508.12 seconds |
| Started | Aug 25 11:40:34 PM UTC 24 |
| Finished | Aug 25 11:49:13 PM UTC 24 |
| Peak memory | 672236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564727227 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3564727227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1041406097 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5290703800 ps |
| CPU time | 857.49 seconds |
| Started | Aug 25 11:40:49 PM UTC 24 |
| Finished | Aug 25 11:55:22 PM UTC 24 |
| Peak memory | 674564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041406097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1041406097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.1133168336 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 4787467878 ps |
| CPU time | 817.78 seconds |
| Started | Aug 25 11:40:48 PM UTC 24 |
| Finished | Aug 25 11:54:39 PM UTC 24 |
| Peak memory | 674524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133168336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1133168336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1806354926 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3495212472 ps |
| CPU time | 489.32 seconds |
| Started | Aug 25 11:41:03 PM UTC 24 |
| Finished | Aug 25 11:49:23 PM UTC 24 |
| Peak memory | 672236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806354926 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1806354926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1088198687 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3610424152 ps |
| CPU time | 531.93 seconds |
| Started | Aug 25 10:55:28 PM UTC 24 |
| Finished | Aug 25 11:04:31 PM UTC 24 |
| Peak memory | 672456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088198687 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_alert_handler_lpg_s leep_mode_alerts.1088198687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2111105051 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5045358720 ps |
| CPU time | 794.63 seconds |
| Started | Aug 25 10:54:11 PM UTC 24 |
| Finished | Aug 25 11:07:39 PM UTC 24 |
| Peak memory | 674292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111105051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2111105051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.897889676 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 17886632600 ps |
| CPU time | 5078.14 seconds |
| Started | Aug 25 10:58:54 PM UTC 24 |
| Finished | Aug 26 12:24:51 AM UTC 24 |
| Peak memory | 625832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=897889676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.chip_sw_csrng_edn_concurrency.897889676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1580881832 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 6418144351 ps |
| CPU time | 483.76 seconds |
| Started | Aug 25 10:56:03 PM UTC 24 |
| Finished | Aug 25 11:04:17 PM UTC 24 |
| Peak memory | 636084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1580881832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.chip_sw_lc_ctrl_transition.1580881832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2051618880 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 7556037284 ps |
| CPU time | 2005.47 seconds |
| Started | Aug 25 10:53:43 PM UTC 24 |
| Finished | Aug 25 11:27:48 PM UTC 24 |
| Peak memory | 636156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051618880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2051618880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1509265399 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 6017185938 ps |
| CPU time | 727.09 seconds |
| Started | Aug 25 11:41:16 PM UTC 24 |
| Finished | Aug 25 11:53:36 PM UTC 24 |
| Peak memory | 674536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509265399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1509265399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398599282 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2962987460 ps |
| CPU time | 409.44 seconds |
| Started | Aug 25 11:42:37 PM UTC 24 |
| Finished | Aug 25 11:49:34 PM UTC 24 |
| Peak memory | 672488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398599282 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2398599282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.3551747286 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 6531765082 ps |
| CPU time | 938.7 seconds |
| Started | Aug 25 11:41:43 PM UTC 24 |
| Finished | Aug 25 11:57:37 PM UTC 24 |
| Peak memory | 674432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551747286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3551747286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086400972 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3756203836 ps |
| CPU time | 465.12 seconds |
| Started | Aug 25 11:44:52 PM UTC 24 |
| Finished | Aug 25 11:52:46 PM UTC 24 |
| Peak memory | 672360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086400972 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3086400972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3107692986 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3930121514 ps |
| CPU time | 509.93 seconds |
| Started | Aug 25 11:45:19 PM UTC 24 |
| Finished | Aug 25 11:53:57 PM UTC 24 |
| Peak memory | 672512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107692986 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3107692986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.238333377 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5637193512 ps |
| CPU time | 829.32 seconds |
| Started | Aug 25 11:45:31 PM UTC 24 |
| Finished | Aug 25 11:59:34 PM UTC 24 |
| Peak memory | 674428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238333377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.238333377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2204118991 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3560171840 ps |
| CPU time | 616.02 seconds |
| Started | Aug 25 11:46:27 PM UTC 24 |
| Finished | Aug 25 11:56:53 PM UTC 24 |
| Peak memory | 672412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204118991 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2204118991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2766854284 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 4766100632 ps |
| CPU time | 682.51 seconds |
| Started | Aug 25 11:49:41 PM UTC 24 |
| Finished | Aug 26 12:01:14 AM UTC 24 |
| Peak memory | 674608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766854284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2766854284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2176555015 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4426347866 ps |
| CPU time | 602.58 seconds |
| Started | Aug 25 11:51:13 PM UTC 24 |
| Finished | Aug 26 12:01:24 AM UTC 24 |
| Peak memory | 672472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176555015 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2176555015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.2961670461 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 6185572802 ps |
| CPU time | 713.52 seconds |
| Started | Aug 25 11:47:35 PM UTC 24 |
| Finished | Aug 25 11:59:40 PM UTC 24 |
| Peak memory | 674592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961670461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2961670461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080638114 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3971444316 ps |
| CPU time | 573.96 seconds |
| Started | Aug 25 11:47:41 PM UTC 24 |
| Finished | Aug 25 11:57:24 PM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080638114 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2080638114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428849130 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3533170488 ps |
| CPU time | 488.52 seconds |
| Started | Aug 25 11:47:36 PM UTC 24 |
| Finished | Aug 25 11:55:53 PM UTC 24 |
| Peak memory | 672316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428849130 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3428849130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.804522997 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4906991756 ps |
| CPU time | 787.77 seconds |
| Started | Aug 25 11:48:26 PM UTC 24 |
| Finished | Aug 26 12:01:45 AM UTC 24 |
| Peak memory | 674436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804522997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.804522997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.3945772634 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5135347432 ps |
| CPU time | 868.07 seconds |
| Started | Aug 25 11:47:56 PM UTC 24 |
| Finished | Aug 26 12:02:37 AM UTC 24 |
| Peak memory | 674352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945772634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.3945772634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.444515888 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3714085048 ps |
| CPU time | 426.39 seconds |
| Started | Aug 25 11:47:44 PM UTC 24 |
| Finished | Aug 25 11:54:58 PM UTC 24 |
| Peak memory | 672388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444515888 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_alert_handler_lpg_s leep_mode_alerts.444515888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.164078114 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 6483985240 ps |
| CPU time | 709.03 seconds |
| Started | Aug 25 11:53:13 PM UTC 24 |
| Finished | Aug 26 12:05:12 AM UTC 24 |
| Peak memory | 674464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164078114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.164078114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.1758039021 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4429524448 ps |
| CPU time | 773.3 seconds |
| Started | Aug 25 10:56:36 PM UTC 24 |
| Finished | Aug 25 11:09:45 PM UTC 24 |
| Peak memory | 674436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758039021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1758039021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.2748700238 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 10577560500 ps |
| CPU time | 3367.56 seconds |
| Started | Aug 25 10:57:04 PM UTC 24 |
| Finished | Aug 25 11:54:12 PM UTC 24 |
| Peak memory | 626088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2748700238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.chip_sw_csrng_edn_concurrency.2748700238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.3821395129 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 11808245839 ps |
| CPU time | 1848.19 seconds |
| Started | Aug 25 10:58:58 PM UTC 24 |
| Finished | Aug 25 11:30:22 PM UTC 24 |
| Peak memory | 636212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3821395129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.chip_sw_lc_ctrl_transition.3821395129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1038004946 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3762555316 ps |
| CPU time | 531.16 seconds |
| Started | Aug 25 10:57:13 PM UTC 24 |
| Finished | Aug 25 11:06:15 PM UTC 24 |
| Peak memory | 636100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038004946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1038004946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556449025 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 3254611848 ps |
| CPU time | 539.62 seconds |
| Started | Aug 25 11:49:22 PM UTC 24 |
| Finished | Aug 25 11:58:31 PM UTC 24 |
| Peak memory | 672380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556449025 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_alert_handler_lpg_ sleep_mode_alerts.2556449025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2705624592 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 5111942720 ps |
| CPU time | 694.93 seconds |
| Started | Aug 25 11:54:30 PM UTC 24 |
| Finished | Aug 26 12:06:14 AM UTC 24 |
| Peak memory | 674408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705624592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2705624592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.962611592 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 3169353700 ps |
| CPU time | 464.8 seconds |
| Started | Aug 25 11:54:53 PM UTC 24 |
| Finished | Aug 26 12:02:44 AM UTC 24 |
| Peak memory | 672464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962611592 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_alert_handler_lpg_s leep_mode_alerts.962611592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2588709563 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5538474344 ps |
| CPU time | 703.49 seconds |
| Started | Aug 25 11:53:33 PM UTC 24 |
| Finished | Aug 26 12:05:26 AM UTC 24 |
| Peak memory | 674576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588709563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2588709563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.511815500 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 3153897048 ps |
| CPU time | 491.98 seconds |
| Started | Aug 25 11:55:00 PM UTC 24 |
| Finished | Aug 26 12:03:19 AM UTC 24 |
| Peak memory | 672468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511815500 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_alert_handler_lpg_s leep_mode_alerts.511815500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.480345458 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 5449915644 ps |
| CPU time | 680.9 seconds |
| Started | Aug 25 11:52:32 PM UTC 24 |
| Finished | Aug 26 12:04:02 AM UTC 24 |
| Peak memory | 674504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480345458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.480345458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3555202890 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 3802174296 ps |
| CPU time | 347.41 seconds |
| Started | Aug 25 11:55:03 PM UTC 24 |
| Finished | Aug 26 12:00:56 AM UTC 24 |
| Peak memory | 672508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555202890 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3555202890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3932535530 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5529436514 ps |
| CPU time | 828.19 seconds |
| Started | Aug 25 11:50:36 PM UTC 24 |
| Finished | Aug 26 12:04:35 AM UTC 24 |
| Peak memory | 674372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932535530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3932535530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3072103650 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 5769878984 ps |
| CPU time | 749.95 seconds |
| Started | Aug 25 11:54:19 PM UTC 24 |
| Finished | Aug 26 12:06:59 AM UTC 24 |
| Peak memory | 674404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072103650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3072103650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3257590750 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 6069577184 ps |
| CPU time | 844.74 seconds |
| Started | Aug 25 11:51:09 PM UTC 24 |
| Finished | Aug 26 12:05:26 AM UTC 24 |
| Peak memory | 636372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257590750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3257590750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1413791796 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3866007950 ps |
| CPU time | 461.23 seconds |
| Started | Aug 25 11:52:44 PM UTC 24 |
| Finished | Aug 26 12:00:33 AM UTC 24 |
| Peak memory | 672556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413791796 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1413791796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2355906093 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 5704911610 ps |
| CPU time | 644.37 seconds |
| Started | Aug 25 11:51:54 PM UTC 24 |
| Finished | Aug 26 12:02:47 AM UTC 24 |
| Peak memory | 674508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355906093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2355906093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776681747 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 3574960952 ps |
| CPU time | 429.32 seconds |
| Started | Aug 25 11:54:33 PM UTC 24 |
| Finished | Aug 26 12:01:49 AM UTC 24 |
| Peak memory | 672348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776681747 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_alert_handler_lpg_ sleep_mode_alerts.1776681747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.162255077 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5035018944 ps |
| CPU time | 586 seconds |
| Started | Aug 25 11:53:01 PM UTC 24 |
| Finished | Aug 26 12:02:56 AM UTC 24 |
| Peak memory | 674340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162255077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.162255077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3693835536 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4011771952 ps |
| CPU time | 531.75 seconds |
| Started | Aug 25 11:53:45 PM UTC 24 |
| Finished | Aug 26 12:02:44 AM UTC 24 |
| Peak memory | 672372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693835536 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_alert_handler_lpg_ sleep_mode_alerts.3693835536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978170389 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3626951084 ps |
| CPU time | 473.79 seconds |
| Started | Aug 25 10:56:34 PM UTC 24 |
| Finished | Aug 25 11:04:37 PM UTC 24 |
| Peak memory | 672464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_rea dy_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv _core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_handler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978170389 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_alert_handler_lpg_s leep_mode_alerts.2978170389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2685799710 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5314952996 ps |
| CPU time | 645.89 seconds |
| Started | Aug 25 10:59:12 PM UTC 24 |
| Finished | Aug 25 11:10:11 PM UTC 24 |
| Peak memory | 674512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685799710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2685799710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.524411852 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 26458746604 ps |
| CPU time | 7317.47 seconds |
| Started | Aug 25 10:59:41 PM UTC 24 |
| Finished | Aug 26 01:03:16 AM UTC 24 |
| Peak memory | 629000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng _srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +acceler ate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=524411852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.chip_sw_csrng_edn_concurrency.524411852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1581900958 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 6018989430 ps |
| CPU time | 909.09 seconds |
| Started | Aug 25 10:58:39 PM UTC 24 |
| Finished | Aug 25 11:14:06 PM UTC 24 |
| Peak memory | 636072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1 :new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1581900958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.chip_sw_lc_ctrl_transition.1581900958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2927494222 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 13141974848 ps |
| CPU time | 3280.86 seconds |
| Started | Aug 25 10:59:27 PM UTC 24 |
| Finished | Aug 25 11:55:09 PM UTC 24 |
| Peak memory | 636132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_buil d_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927494222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2927494222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2770844455 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5074861760 ps |
| CPU time | 684.09 seconds |
| Started | Aug 25 11:52:24 PM UTC 24 |
| Finished | Aug 26 12:03:59 AM UTC 24 |
| Peak memory | 674340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770844455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2770844455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.3438842184 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 5648352992 ps |
| CPU time | 689.04 seconds |
| Started | Aug 25 11:53:47 PM UTC 24 |
| Finished | Aug 26 12:05:25 AM UTC 24 |
| Peak memory | 625956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438842184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3438842184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3068101907 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 5776841500 ps |
| CPU time | 577.45 seconds |
| Started | Aug 25 11:54:35 PM UTC 24 |
| Finished | Aug 26 12:04:20 AM UTC 24 |
| Peak memory | 674504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068101907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3068101907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2998470774 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5463348124 ps |
| CPU time | 592.02 seconds |
| Started | Aug 25 11:54:03 PM UTC 24 |
| Finished | Aug 26 12:04:03 AM UTC 24 |
| Peak memory | 674344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998470774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2998470774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3650377893 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 4775588332 ps |
| CPU time | 629.77 seconds |
| Started | Aug 25 11:54:33 PM UTC 24 |
| Finished | Aug 26 12:05:12 AM UTC 24 |
| Peak memory | 674476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650377893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.3650377893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.4097662489 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5208067300 ps |
| CPU time | 639.81 seconds |
| Started | Aug 25 11:55:05 PM UTC 24 |
| Finished | Aug 26 12:05:54 AM UTC 24 |
| Peak memory | 674296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097662489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.4097662489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.1672823963 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 5971614384 ps |
| CPU time | 649.12 seconds |
| Started | Aug 25 11:53:26 PM UTC 24 |
| Finished | Aug 26 12:04:24 AM UTC 24 |
| Peak memory | 674408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672823963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1672823963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.940598535 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 5743486672 ps |
| CPU time | 715.56 seconds |
| Started | Aug 25 11:53:46 PM UTC 24 |
| Finished | Aug 26 12:05:52 AM UTC 24 |
| Peak memory | 674532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940598535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_esc alation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.940598535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.4179385115 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5333651130 ps |
| CPU time | 586 seconds |
| Started | Aug 25 11:54:59 PM UTC 24 |
| Finished | Aug 26 12:04:53 AM UTC 24 |
| Peak memory | 674460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179385115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.4179385115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.3287145556 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5431083848 ps |
| CPU time | 818.68 seconds |
| Started | Aug 25 11:54:02 PM UTC 24 |
| Finished | Aug 26 12:07:51 AM UTC 24 |
| Peak memory | 674388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv + sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287145556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3287145556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3106790346 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4167992244 ps |
| CPU time | 293.85 seconds |
| Started | Aug 25 05:56:33 PM UTC 24 |
| Finished | Aug 25 06:01:33 PM UTC 24 |
| Peak memory | 656176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106790 346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 0.chip_ padctrl_attributes.3106790346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/0.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3269230669 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4443229560 ps |
| CPU time | 290.09 seconds |
| Started | Aug 25 05:56:36 PM UTC 24 |
| Finished | Aug 25 06:01:32 PM UTC 24 |
| Peak memory | 656248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269230 669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 1.chip_ padctrl_attributes.3269230669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/1.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.140691267 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4332561222 ps |
| CPU time | 302.9 seconds |
| Started | Aug 25 05:56:38 PM UTC 24 |
| Finished | Aug 25 06:01:47 PM UTC 24 |
| Peak memory | 670580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406912 67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 2.chip_p adctrl_attributes.140691267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/2.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.529622900 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 5517829126 ps |
| CPU time | 332.68 seconds |
| Started | Aug 25 05:57:05 PM UTC 24 |
| Finished | Aug 25 06:02:44 PM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5296229 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 4.chip_p adctrl_attributes.529622900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/4.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2347496682 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 6245163880 ps |
| CPU time | 370.77 seconds |
| Started | Aug 25 05:57:11 PM UTC 24 |
| Finished | Aug 25 06:03:28 PM UTC 24 |
| Peak memory | 670520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347496 682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 5.chip_ padctrl_attributes.2347496682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2387588596 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4903345964 ps |
| CPU time | 311.83 seconds |
| Started | Aug 25 05:57:15 PM UTC 24 |
| Finished | Aug 25 06:02:33 PM UTC 24 |
| Peak memory | 672420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387588 596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 6.chip_ padctrl_attributes.2387588596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/6.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3969783387 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4833649463 ps |
| CPU time | 304.68 seconds |
| Started | Aug 25 05:57:19 PM UTC 24 |
| Finished | Aug 25 06:02:31 PM UTC 24 |
| Peak memory | 672564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969783 387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 7.chip_ padctrl_attributes.3969783387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/7.chip_padctrl_attributes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3221585720 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4118826577 ps |
| CPU time | 329.27 seconds |
| Started | Aug 25 05:57:28 PM UTC 24 |
| Finished | Aug 25 06:03:04 PM UTC 24 |
| Peak memory | 666420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221585 720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/null -cm_name 9.chip_ padctrl_attributes.3221585720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/9.chip_padctrl_attributes/latest |
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