| T2026 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1371547924 |
|
|
Aug 25 04:53:20 PM UTC 24 |
Aug 25 04:59:22 PM UTC 24 |
1523428752 ps |
| T2027 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke.3599416606 |
|
|
Aug 25 04:59:13 PM UTC 24 |
Aug 25 04:59:25 PM UTC 24 |
53888223 ps |
| T2028 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random.4034628014 |
|
|
Aug 25 04:58:42 PM UTC 24 |
Aug 25 04:59:26 PM UTC 24 |
942369075 ps |
| T2029 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2667397853 |
|
|
Aug 25 04:59:03 PM UTC 24 |
Aug 25 04:59:37 PM UTC 24 |
441115313 ps |
| T2030 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1620578458 |
|
|
Aug 25 04:59:27 PM UTC 24 |
Aug 25 04:59:39 PM UTC 24 |
51017630 ps |
| T2031 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_random_large_delays.3636916706 |
|
|
Aug 25 04:34:19 PM UTC 24 |
Aug 25 04:59:45 PM UTC 24 |
102827164044 ps |
| T2032 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_large_delays.2295098404 |
|
|
Aug 25 04:41:33 PM UTC 24 |
Aug 25 04:59:49 PM UTC 24 |
61436998520 ps |
| T2033 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_zero_delays.3219409222 |
|
|
Aug 25 04:58:40 PM UTC 24 |
Aug 25 04:59:50 PM UTC 24 |
491339770 ps |
| T2034 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random.608637585 |
|
|
Aug 25 04:59:42 PM UTC 24 |
Aug 25 04:59:56 PM UTC 24 |
51448968 ps |
| T2035 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_slow_rsp.3127664370 |
|
|
Aug 25 04:52:39 PM UTC 24 |
Aug 25 05:00:03 PM UTC 24 |
19764598519 ps |
| T2036 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_zero_delays.2666485622 |
|
|
Aug 25 04:59:43 PM UTC 24 |
Aug 25 05:00:05 PM UTC 24 |
153537258 ps |
| T2037 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_same_source.1960168705 |
|
|
Aug 25 04:58:57 PM UTC 24 |
Aug 25 05:00:21 PM UTC 24 |
2020202590 ps |
| T2038 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1867343875 |
|
|
Aug 25 04:58:19 PM UTC 24 |
Aug 25 05:00:28 PM UTC 24 |
5701121176 ps |
| T2039 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.425244892 |
|
|
Aug 25 04:54:26 PM UTC 24 |
Aug 25 05:00:36 PM UTC 24 |
418918726 ps |
| T2040 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all.939726499 |
|
|
Aug 25 04:57:54 PM UTC 24 |
Aug 25 05:00:39 PM UTC 24 |
1393418017 ps |
| T2041 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_unmapped_addr.3949576315 |
|
|
Aug 25 05:00:15 PM UTC 24 |
Aug 25 05:00:39 PM UTC 24 |
129072183 ps |
| T2042 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_same_source.3240698427 |
|
|
Aug 25 05:00:02 PM UTC 24 |
Aug 25 05:00:41 PM UTC 24 |
282944472 ps |
| T2043 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_error_random.2496371676 |
|
|
Aug 25 04:58:55 PM UTC 24 |
Aug 25 05:00:49 PM UTC 24 |
2123184525 ps |
| T2044 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_large_delays.2751734102 |
|
|
Aug 25 04:58:15 PM UTC 24 |
Aug 25 05:00:58 PM UTC 24 |
10476765490 ps |
| T2045 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke.792181270 |
|
|
Aug 25 05:00:52 PM UTC 24 |
Aug 25 05:01:03 PM UTC 24 |
47599044 ps |
| T2046 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1324801967 |
|
|
Aug 25 05:00:15 PM UTC 24 |
Aug 25 05:01:03 PM UTC 24 |
975109146 ps |
| T2047 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3311162642 |
|
|
Aug 25 05:01:00 PM UTC 24 |
Aug 25 05:01:09 PM UTC 24 |
36468960 ps |
| T2048 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device.1478584223 |
|
|
Aug 25 04:59:50 PM UTC 24 |
Aug 25 05:01:12 PM UTC 24 |
622479369 ps |
| T2049 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_access_same_device.1200117095 |
|
|
Aug 25 04:58:44 PM UTC 24 |
Aug 25 05:01:18 PM UTC 24 |
2613468546 ps |
| T2050 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random_zero_delays.2397728977 |
|
|
Aug 25 05:01:14 PM UTC 24 |
Aug 25 05:01:30 PM UTC 24 |
66683526 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2343074783 |
|
|
Aug 25 04:32:19 PM UTC 24 |
Aug 25 05:01:30 PM UTC 24 |
10173116782 ps |
| T2051 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_large_delays.2796975879 |
|
|
Aug 25 04:59:31 PM UTC 24 |
Aug 25 05:01:32 PM UTC 24 |
7886096405 ps |
| T2052 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2600545601 |
|
|
Aug 25 04:56:38 PM UTC 24 |
Aug 25 05:01:36 PM UTC 24 |
1993111047 ps |
| T2053 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1036531897 |
|
|
Aug 25 04:59:36 PM UTC 24 |
Aug 25 05:01:36 PM UTC 24 |
4980012922 ps |
| T2054 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_error_random.3006473354 |
|
|
Aug 25 05:00:09 PM UTC 24 |
Aug 25 05:01:43 PM UTC 24 |
1762721694 ps |
| T2055 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_error.624196941 |
|
|
Aug 25 04:54:27 PM UTC 24 |
Aug 25 05:01:51 PM UTC 24 |
8966524666 ps |
| T2056 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_access_same_device.4212349197 |
|
|
Aug 25 05:01:25 PM UTC 24 |
Aug 25 05:02:17 PM UTC 24 |
697758422 ps |
| T2057 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2445667781 |
|
|
Aug 25 05:02:00 PM UTC 24 |
Aug 25 05:02:19 PM UTC 24 |
7825780 ps |
| T2058 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke.2006792838 |
|
|
Aug 25 05:02:13 PM UTC 24 |
Aug 25 05:02:23 PM UTC 24 |
39868974 ps |
| T2059 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_error.3006503862 |
|
|
Aug 25 04:53:18 PM UTC 24 |
Aug 25 05:02:27 PM UTC 24 |
10412773335 ps |
| T2060 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_zero_delays.216868893 |
|
|
Aug 25 05:02:23 PM UTC 24 |
Aug 25 05:02:32 PM UTC 24 |
38266858 ps |
| T2061 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_error.2221558706 |
|
|
Aug 25 04:59:13 PM UTC 24 |
Aug 25 05:02:36 PM UTC 24 |
1414909725 ps |
| T2062 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_random.630749649 |
|
|
Aug 25 05:01:04 PM UTC 24 |
Aug 25 05:02:39 PM UTC 24 |
1866017561 ps |
| T2063 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2711542808 |
|
|
Aug 25 04:54:30 PM UTC 24 |
Aug 25 05:02:40 PM UTC 24 |
4264248260 ps |
| T2064 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_same_source.1331759909 |
|
|
Aug 25 05:01:37 PM UTC 24 |
Aug 25 05:02:40 PM UTC 24 |
1447815647 ps |
| T2065 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all.2536011476 |
|
|
Aug 25 04:53:11 PM UTC 24 |
Aug 25 05:02:46 PM UTC 24 |
10611341181 ps |
| T2066 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_error.4102483215 |
|
|
Aug 25 05:02:00 PM UTC 24 |
Aug 25 05:02:50 PM UTC 24 |
884180185 ps |
| T2067 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_large_delays.550797338 |
|
|
Aug 25 05:01:01 PM UTC 24 |
Aug 25 05:02:53 PM UTC 24 |
6799972747 ps |
| T2068 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_unmapped_addr.595370725 |
|
|
Aug 25 05:01:54 PM UTC 24 |
Aug 25 05:02:56 PM UTC 24 |
857035455 ps |
| T2069 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3075207791 |
|
|
Aug 25 05:01:04 PM UTC 24 |
Aug 25 05:03:09 PM UTC 24 |
4809582370 ps |
| T2070 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_random.1994258228 |
|
|
Aug 25 05:01:44 PM UTC 24 |
Aug 25 05:03:09 PM UTC 24 |
1873693975 ps |
| T2071 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.726817004 |
|
|
Aug 25 05:01:58 PM UTC 24 |
Aug 25 05:03:16 PM UTC 24 |
1134122784 ps |
| T2072 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_slow_rsp.3567212123 |
|
|
Aug 25 04:35:29 PM UTC 24 |
Aug 25 05:03:18 PM UTC 24 |
63585797693 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2311770359 |
|
|
Aug 25 05:02:07 PM UTC 24 |
Aug 25 05:03:33 PM UTC 24 |
250975925 ps |
| T2073 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random.329650790 |
|
|
Aug 25 05:02:43 PM UTC 24 |
Aug 25 05:03:42 PM UTC 24 |
1369210706 ps |
| T2074 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1227586816 |
|
|
Aug 25 05:03:14 PM UTC 24 |
Aug 25 05:03:49 PM UTC 24 |
237160823 ps |
| T2075 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_zero_delays.1396923814 |
|
|
Aug 25 05:02:47 PM UTC 24 |
Aug 25 05:03:51 PM UTC 24 |
443154155 ps |
| T2076 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke.2101888461 |
|
|
Aug 25 05:03:40 PM UTC 24 |
Aug 25 05:03:53 PM UTC 24 |
187260201 ps |
| T2077 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2046876609 |
|
|
Aug 25 05:03:42 PM UTC 24 |
Aug 25 05:03:54 PM UTC 24 |
50815265 ps |
| T2078 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_unmapped_addr.3734313743 |
|
|
Aug 25 05:03:09 PM UTC 24 |
Aug 25 05:04:00 PM UTC 24 |
633409764 ps |
| T2079 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device.362691479 |
|
|
Aug 25 05:03:00 PM UTC 24 |
Aug 25 05:04:03 PM UTC 24 |
572513450 ps |
| T2080 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_error_random.2458277135 |
|
|
Aug 25 05:03:05 PM UTC 24 |
Aug 25 05:04:20 PM UTC 24 |
1379292196 ps |
| T2081 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_slow_rsp.4253261426 |
|
|
Aug 25 04:51:02 PM UTC 24 |
Aug 25 05:04:48 PM UTC 24 |
30966633521 ps |
| T2082 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_same_source.4159945616 |
|
|
Aug 25 05:03:04 PM UTC 24 |
Aug 25 05:04:50 PM UTC 24 |
2185998448 ps |
| T2083 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2742604456 |
|
|
Aug 25 05:02:41 PM UTC 24 |
Aug 25 05:04:52 PM UTC 24 |
5030181332 ps |
| T2084 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random.522970123 |
|
|
Aug 25 05:04:13 PM UTC 24 |
Aug 25 05:04:53 PM UTC 24 |
315782911 ps |
| T2085 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_error.1795591501 |
|
|
Aug 25 04:57:59 PM UTC 24 |
Aug 25 05:04:53 PM UTC 24 |
7811228215 ps |
| T2086 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_same_source.2581499661 |
|
|
Aug 25 05:04:43 PM UTC 24 |
Aug 25 05:04:55 PM UTC 24 |
64362498 ps |
| T2087 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_error.3243819150 |
|
|
Aug 25 05:03:33 PM UTC 24 |
Aug 25 05:04:55 PM UTC 24 |
588951291 ps |
| T2088 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_smoke_large_delays.3177502866 |
|
|
Aug 25 05:02:41 PM UTC 24 |
Aug 25 05:05:03 PM UTC 24 |
8737729659 ps |
| T2089 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_error.2705060524 |
|
|
Aug 25 05:00:35 PM UTC 24 |
Aug 25 05:05:07 PM UTC 24 |
5924917669 ps |
| T2090 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/55.xbar_stress_all.3480303880 |
|
|
Aug 25 05:01:59 PM UTC 24 |
Aug 25 05:05:24 PM UTC 24 |
1800672556 ps |
| T2091 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_random.1947578930 |
|
|
Aug 25 05:05:13 PM UTC 24 |
Aug 25 05:05:25 PM UTC 24 |
39641369 ps |
| T2092 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_random_zero_delays.3543299552 |
|
|
Aug 25 05:04:14 PM UTC 24 |
Aug 25 05:05:32 PM UTC 24 |
675633783 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1439565754 |
|
|
Aug 25 04:13:44 PM UTC 24 |
Aug 25 05:05:33 PM UTC 24 |
125173813344 ps |
| T2093 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_unmapped_addr.124638978 |
|
|
Aug 25 05:05:14 PM UTC 24 |
Aug 25 05:05:34 PM UTC 24 |
77993179 ps |
| T2094 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3881030585 |
|
|
Aug 25 05:05:31 PM UTC 24 |
Aug 25 05:05:43 PM UTC 24 |
46418060 ps |
| T2095 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke.3224220094 |
|
|
Aug 25 05:05:28 PM UTC 24 |
Aug 25 05:05:43 PM UTC 24 |
185823857 ps |
| T2096 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all.1122889513 |
|
|
Aug 25 05:00:20 PM UTC 24 |
Aug 25 05:05:43 PM UTC 24 |
5484811179 ps |
| T2097 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2663270787 |
|
|
Aug 25 05:05:18 PM UTC 24 |
Aug 25 05:05:47 PM UTC 24 |
7375600 ps |
| T2098 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3212534438 |
|
|
Aug 25 05:00:34 PM UTC 24 |
Aug 25 05:05:49 PM UTC 24 |
1725027839 ps |
| T2099 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2474718289 |
|
|
Aug 25 05:04:04 PM UTC 24 |
Aug 25 05:05:50 PM UTC 24 |
4504698732 ps |
| T2100 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1835954682 |
|
|
Aug 25 04:52:44 PM UTC 24 |
Aug 25 05:05:56 PM UTC 24 |
30849918206 ps |
| T2101 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device.2373515706 |
|
|
Aug 25 05:04:23 PM UTC 24 |
Aug 25 05:05:58 PM UTC 24 |
1636259952 ps |
| T2102 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.4120772063 |
|
|
Aug 25 05:05:17 PM UTC 24 |
Aug 25 05:05:59 PM UTC 24 |
301965958 ps |
| T2103 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_same_source.4216284245 |
|
|
Aug 25 05:06:12 PM UTC 24 |
Aug 25 05:06:23 PM UTC 24 |
38801047 ps |
| T2104 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_smoke_large_delays.3095067433 |
|
|
Aug 25 05:03:56 PM UTC 24 |
Aug 25 05:06:25 PM UTC 24 |
8126810467 ps |
| T2105 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_access_same_device.1922244741 |
|
|
Aug 25 05:06:08 PM UTC 24 |
Aug 25 05:06:27 PM UTC 24 |
138369298 ps |
| T2106 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.66379985 |
|
|
Aug 25 05:06:13 PM UTC 24 |
Aug 25 05:06:34 PM UTC 24 |
351922413 ps |
| T2107 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random.4253944612 |
|
|
Aug 25 05:05:57 PM UTC 24 |
Aug 25 05:06:35 PM UTC 24 |
245194659 ps |
| T2108 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all.3220280350 |
|
|
Aug 25 04:56:25 PM UTC 24 |
Aug 25 05:06:36 PM UTC 24 |
12922643696 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.762122909 |
|
|
Aug 25 05:05:21 PM UTC 24 |
Aug 25 05:06:38 PM UTC 24 |
265132665 ps |
| T2109 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3951342557 |
|
|
Aug 25 05:06:21 PM UTC 24 |
Aug 25 05:06:42 PM UTC 24 |
95050909 ps |
| T2110 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4096622257 |
|
|
Aug 25 04:59:10 PM UTC 24 |
Aug 25 05:06:46 PM UTC 24 |
3041027014 ps |
| T2111 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3028566323 |
|
|
Aug 25 04:41:41 PM UTC 24 |
Aug 25 05:06:48 PM UTC 24 |
61365035464 ps |
| T2112 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_zero_delays.1050513460 |
|
|
Aug 25 05:05:56 PM UTC 24 |
Aug 25 05:06:58 PM UTC 24 |
537818669 ps |
| T2113 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2269449173 |
|
|
Aug 25 04:55:33 PM UTC 24 |
Aug 25 05:06:58 PM UTC 24 |
3187644099 ps |
| T2114 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke.3723955825 |
|
|
Aug 25 05:06:51 PM UTC 24 |
Aug 25 05:07:08 PM UTC 24 |
195909694 ps |
| T2115 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_slow_rsp.3825767152 |
|
|
Aug 25 04:38:33 PM UTC 24 |
Aug 25 05:07:10 PM UTC 24 |
67336290043 ps |
| T2116 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_zero_delays.741502975 |
|
|
Aug 25 05:06:59 PM UTC 24 |
Aug 25 05:07:11 PM UTC 24 |
54846775 ps |
| T2117 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2195066911 |
|
|
Aug 25 03:52:50 PM UTC 24 |
Aug 25 05:07:16 PM UTC 24 |
28921645528 ps |
| T2118 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_unmapped_addr.2731388492 |
|
|
Aug 25 05:06:14 PM UTC 24 |
Aug 25 05:07:19 PM UTC 24 |
951684785 ps |
| T2119 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1385698474 |
|
|
Aug 25 05:06:49 PM UTC 24 |
Aug 25 05:07:31 PM UTC 24 |
26366924 ps |
| T2120 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_random_large_delays.741433993 |
|
|
Aug 25 04:38:31 PM UTC 24 |
Aug 25 05:07:33 PM UTC 24 |
107623257364 ps |
| T2121 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_large_delays.2742667638 |
|
|
Aug 25 04:48:13 PM UTC 24 |
Aug 25 05:07:37 PM UTC 24 |
65501908295 ps |
| T2122 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random_zero_delays.2732460852 |
|
|
Aug 25 05:07:07 PM UTC 24 |
Aug 25 05:07:41 PM UTC 24 |
243028431 ps |
| T2123 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_same_source.1284667362 |
|
|
Aug 25 05:07:32 PM UTC 24 |
Aug 25 05:07:48 PM UTC 24 |
86125963 ps |
| T2124 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_same_csr_outstanding.2570179048 |
|
|
Aug 25 03:34:35 PM UTC 24 |
Aug 25 05:07:52 PM UTC 24 |
29645192008 ps |
| T2125 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_access_same_device.3581021878 |
|
|
Aug 25 05:07:21 PM UTC 24 |
Aug 25 05:07:54 PM UTC 24 |
364867235 ps |
| T2126 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_random.3191324116 |
|
|
Aug 25 05:07:01 PM UTC 24 |
Aug 25 05:08:01 PM UTC 24 |
413615659 ps |
| T2127 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2228492683 |
|
|
Aug 25 04:59:13 PM UTC 24 |
Aug 25 05:08:08 PM UTC 24 |
5470296720 ps |
| T2128 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3991823658 |
|
|
Aug 25 05:05:49 PM UTC 24 |
Aug 25 05:08:08 PM UTC 24 |
5130923743 ps |
| T2129 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_slow_rsp.3455512279 |
|
|
Aug 25 04:54:55 PM UTC 24 |
Aug 25 05:08:15 PM UTC 24 |
34744318450 ps |
| T2130 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_smoke_large_delays.1161369122 |
|
|
Aug 25 05:05:49 PM UTC 24 |
Aug 25 05:08:18 PM UTC 24 |
8143789095 ps |
| T2131 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_slow_rsp.593988314 |
|
|
Aug 25 04:56:13 PM UTC 24 |
Aug 25 05:08:18 PM UTC 24 |
29434636977 ps |
| T2132 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.696709615 |
|
|
Aug 25 04:19:41 PM UTC 24 |
Aug 25 05:08:21 PM UTC 24 |
116048772470 ps |
| T2133 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2413447075 |
|
|
Aug 25 05:08:12 PM UTC 24 |
Aug 25 05:08:24 PM UTC 24 |
48208323 ps |
| T2134 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3625051578 |
|
|
Aug 25 05:07:41 PM UTC 24 |
Aug 25 05:08:29 PM UTC 24 |
258666889 ps |
| T2135 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_stress_all_with_error.4084569655 |
|
|
Aug 25 05:05:20 PM UTC 24 |
Aug 25 05:08:33 PM UTC 24 |
3924738746 ps |
| T2136 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_unmapped_addr.980403685 |
|
|
Aug 25 05:07:36 PM UTC 24 |
Aug 25 05:08:33 PM UTC 24 |
785142442 ps |
| T2137 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2226849080 |
|
|
Aug 25 04:56:35 PM UTC 24 |
Aug 25 05:08:38 PM UTC 24 |
4147320089 ps |
| T2138 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_large_delays.101916222 |
|
|
Aug 25 04:49:36 PM UTC 24 |
Aug 25 05:08:50 PM UTC 24 |
67095899064 ps |
| T2139 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_slow_rsp.1646646001 |
|
|
Aug 25 04:48:15 PM UTC 24 |
Aug 25 05:08:54 PM UTC 24 |
49920645699 ps |
| T2140 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_error.1934782827 |
|
|
Aug 25 05:06:48 PM UTC 24 |
Aug 25 05:08:55 PM UTC 24 |
885189282 ps |
| T2141 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_slow_rsp.1880457233 |
|
|
Aug 25 04:45:09 PM UTC 24 |
Aug 25 05:08:58 PM UTC 24 |
54839204236 ps |
| T2142 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_error_random.201332341 |
|
|
Aug 25 05:07:34 PM UTC 24 |
Aug 25 05:08:59 PM UTC 24 |
1624429538 ps |
| T2143 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.2796954807 |
|
|
Aug 25 05:00:46 PM UTC 24 |
Aug 25 05:08:59 PM UTC 24 |
4281063768 ps |
| T2144 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_large_delays.100978283 |
|
|
Aug 25 04:53:56 PM UTC 24 |
Aug 25 05:09:04 PM UTC 24 |
52648208760 ps |
| T2145 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_large_delays.985772559 |
|
|
Aug 25 05:07:00 PM UTC 24 |
Aug 25 05:09:05 PM UTC 24 |
8109345268 ps |
| T2146 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_unmapped_addr.3991304397 |
|
|
Aug 25 05:08:48 PM UTC 24 |
Aug 25 05:09:07 PM UTC 24 |
74359205 ps |
| T2147 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_random.1999687689 |
|
|
Aug 25 05:08:46 PM UTC 24 |
Aug 25 05:09:18 PM UTC 24 |
614252399 ps |
| T2148 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4071548835 |
|
|
Aug 25 05:08:54 PM UTC 24 |
Aug 25 05:09:20 PM UTC 24 |
326719606 ps |
| T2149 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1698378020 |
|
|
Aug 25 05:06:23 PM UTC 24 |
Aug 25 05:09:25 PM UTC 24 |
1648707386 ps |
| T2150 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke.3148411344 |
|
|
Aug 25 05:09:19 PM UTC 24 |
Aug 25 05:09:29 PM UTC 24 |
45915226 ps |
| T2151 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_zero_delays.939145933 |
|
|
Aug 25 05:09:20 PM UTC 24 |
Aug 25 05:09:32 PM UTC 24 |
47934798 ps |
| T2152 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.4196188618 |
|
|
Aug 25 05:07:00 PM UTC 24 |
Aug 25 05:09:33 PM UTC 24 |
6042904280 ps |
| T2153 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_zero_delays.4030079729 |
|
|
Aug 25 05:08:32 PM UTC 24 |
Aug 25 05:09:33 PM UTC 24 |
418729973 ps |
| T2154 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random.604900506 |
|
|
Aug 25 05:08:26 PM UTC 24 |
Aug 25 05:09:34 PM UTC 24 |
1197706984 ps |
| T2155 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_stress_all.210894223 |
|
|
Aug 25 04:59:06 PM UTC 24 |
Aug 25 05:09:38 PM UTC 24 |
12940157952 ps |
| T2156 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random_zero_delays.575404838 |
|
|
Aug 25 05:09:29 PM UTC 24 |
Aug 25 05:09:46 PM UTC 24 |
85148350 ps |
| T2157 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_random_large_delays.4101983522 |
|
|
Aug 25 04:58:43 PM UTC 24 |
Aug 25 05:09:59 PM UTC 24 |
45558185930 ps |
| T2158 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all.717488129 |
|
|
Aug 25 05:03:17 PM UTC 24 |
Aug 25 05:10:05 PM UTC 24 |
2931093642 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1343132973 |
|
|
Aug 25 04:35:43 PM UTC 24 |
Aug 25 05:10:11 PM UTC 24 |
95216593203 ps |
| T2159 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_slow_rsp.3150968227 |
|
|
Aug 25 04:43:08 PM UTC 24 |
Aug 25 05:10:18 PM UTC 24 |
64314382693 ps |
| T2160 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_same_source.3144776009 |
|
|
Aug 25 05:09:50 PM UTC 24 |
Aug 25 05:10:20 PM UTC 24 |
642696646 ps |
| T2161 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3428861910 |
|
|
Aug 25 05:08:19 PM UTC 24 |
Aug 25 05:10:21 PM UTC 24 |
5052487046 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_random.1545236821 |
|
|
Aug 25 05:09:24 PM UTC 24 |
Aug 25 05:10:22 PM UTC 24 |
916730846 ps |
| T2162 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_large_delays.1203226698 |
|
|
Aug 25 05:02:51 PM UTC 24 |
Aug 25 05:10:25 PM UTC 24 |
28032960150 ps |
| T2163 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_same_source.2618088594 |
|
|
Aug 25 05:08:41 PM UTC 24 |
Aug 25 05:10:29 PM UTC 24 |
2344582352 ps |
| T2164 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_access_same_device.3923118117 |
|
|
Aug 25 05:08:40 PM UTC 24 |
Aug 25 05:10:30 PM UTC 24 |
897062331 ps |
| T2165 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_large_delays.2380919433 |
|
|
Aug 25 04:54:49 PM UTC 24 |
Aug 25 05:10:34 PM UTC 24 |
61434633266 ps |
| T2166 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke.724950261 |
|
|
Aug 25 05:10:23 PM UTC 24 |
Aug 25 05:10:35 PM UTC 24 |
54519234 ps |
| T2167 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_random.3925393786 |
|
|
Aug 25 05:09:54 PM UTC 24 |
Aug 25 05:10:41 PM UTC 24 |
788283040 ps |
| T2168 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3796115193 |
|
|
Aug 25 05:10:30 PM UTC 24 |
Aug 25 05:10:41 PM UTC 24 |
39472740 ps |
| T2169 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1275796294 |
|
|
Aug 25 04:55:06 PM UTC 24 |
Aug 25 05:10:42 PM UTC 24 |
40864703065 ps |
| T2170 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_large_delays.3499932194 |
|
|
Aug 25 04:56:10 PM UTC 24 |
Aug 25 05:10:46 PM UTC 24 |
54494276963 ps |
| T2171 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_unmapped_addr.143459121 |
|
|
Aug 25 05:09:57 PM UTC 24 |
Aug 25 05:10:59 PM UTC 24 |
332270872 ps |
| T2172 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke_large_delays.1294663805 |
|
|
Aug 25 05:08:15 PM UTC 24 |
Aug 25 05:11:02 PM UTC 24 |
9309260515 ps |
| T2173 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_access_same_device.2582477812 |
|
|
Aug 25 05:09:41 PM UTC 24 |
Aug 25 05:11:03 PM UTC 24 |
668390062 ps |
| T2174 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all.2791462801 |
|
|
Aug 25 05:08:58 PM UTC 24 |
Aug 25 05:11:05 PM UTC 24 |
2413847773 ps |
| T2175 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_large_delays.2016332008 |
|
|
Aug 25 05:09:22 PM UTC 24 |
Aug 25 05:11:10 PM UTC 24 |
5952776103 ps |
| T2176 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2028845889 |
|
|
Aug 25 05:09:57 PM UTC 24 |
Aug 25 05:11:16 PM UTC 24 |
1480192613 ps |
| T2177 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.824413443 |
|
|
Aug 25 05:11:06 PM UTC 24 |
Aug 25 05:11:28 PM UTC 24 |
135931483 ps |
| T2178 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2592694302 |
|
|
Aug 25 05:09:24 PM UTC 24 |
Aug 25 05:11:29 PM UTC 24 |
4695045021 ps |
| T2179 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1632251890 |
|
|
Aug 25 05:11:29 PM UTC 24 |
Aug 25 05:11:39 PM UTC 24 |
36140212 ps |
| T2180 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke.595603027 |
|
|
Aug 25 05:11:26 PM UTC 24 |
Aug 25 05:11:43 PM UTC 24 |
224114589 ps |
| T2181 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random.338048960 |
|
|
Aug 25 05:10:44 PM UTC 24 |
Aug 25 05:11:51 PM UTC 24 |
498402476 ps |
| T2182 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_random_zero_delays.486555719 |
|
|
Aug 25 05:10:45 PM UTC 24 |
Aug 25 05:11:56 PM UTC 24 |
479810615 ps |
| T2183 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_unmapped_addr.1956715405 |
|
|
Aug 25 05:11:04 PM UTC 24 |
Aug 25 05:11:57 PM UTC 24 |
692062799 ps |
| T2184 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_same_source.3250268265 |
|
|
Aug 25 05:10:58 PM UTC 24 |
Aug 25 05:12:01 PM UTC 24 |
1172548518 ps |
| T2185 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_access_same_device.648128580 |
|
|
Aug 25 05:10:53 PM UTC 24 |
Aug 25 05:12:01 PM UTC 24 |
787531163 ps |
| T2186 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random_zero_delays.326275835 |
|
|
Aug 25 05:11:51 PM UTC 24 |
Aug 25 05:12:03 PM UTC 24 |
32878352 ps |
| T2187 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.686839185 |
|
|
Aug 25 05:10:11 PM UTC 24 |
Aug 25 05:12:25 PM UTC 24 |
274039824 ps |
| T2188 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.450408166 |
|
|
Aug 25 05:12:25 PM UTC 24 |
Aug 25 05:12:38 PM UTC 24 |
39744771 ps |
| T2189 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_large_delays.740636809 |
|
|
Aug 25 05:10:35 PM UTC 24 |
Aug 25 05:12:44 PM UTC 24 |
7088238289 ps |
| T2190 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_same_source.1083318542 |
|
|
Aug 25 05:12:22 PM UTC 24 |
Aug 25 05:13:01 PM UTC 24 |
299498473 ps |
| T2191 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2836748593 |
|
|
Aug 25 05:11:34 PM UTC 24 |
Aug 25 05:13:04 PM UTC 24 |
3728220004 ps |
| T2192 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_random.3831623212 |
|
|
Aug 25 05:11:40 PM UTC 24 |
Aug 25 05:13:04 PM UTC 24 |
2077122603 ps |
| T2193 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_error_random.4043646936 |
|
|
Aug 25 05:11:00 PM UTC 24 |
Aug 25 05:13:13 PM UTC 24 |
2566498314 ps |
| T2194 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3748080987 |
|
|
Aug 25 05:10:43 PM UTC 24 |
Aug 25 05:13:23 PM UTC 24 |
5884744363 ps |
| T2195 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1478398101 |
|
|
Aug 25 04:57:59 PM UTC 24 |
Aug 25 05:13:24 PM UTC 24 |
8296767934 ps |
| T2196 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2324883651 |
|
|
Aug 25 05:11:27 PM UTC 24 |
Aug 25 05:13:29 PM UTC 24 |
253018070 ps |
| T2197 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_same_csr_outstanding.2812742392 |
|
|
Aug 25 03:55:13 PM UTC 24 |
Aug 25 05:13:38 PM UTC 24 |
28634774476 ps |
| T2198 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke.2810916891 |
|
|
Aug 25 05:13:20 PM UTC 24 |
Aug 25 05:13:38 PM UTC 24 |
260026344 ps |
| T2199 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_zero_delays.213029440 |
|
|
Aug 25 05:13:28 PM UTC 24 |
Aug 25 05:13:39 PM UTC 24 |
48685153 ps |
| T2200 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_unmapped_addr.3432532919 |
|
|
Aug 25 05:12:26 PM UTC 24 |
Aug 25 05:13:44 PM UTC 24 |
1176146015 ps |
| T2201 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_error.144174786 |
|
|
Aug 25 05:13:02 PM UTC 24 |
Aug 25 05:13:53 PM UTC 24 |
933242017 ps |
| T2202 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_error_random.305423360 |
|
|
Aug 25 05:12:23 PM UTC 24 |
Aug 25 05:13:55 PM UTC 24 |
1701202116 ps |
| T2203 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random.2706956573 |
|
|
Aug 25 05:13:47 PM UTC 24 |
Aug 25 05:13:59 PM UTC 24 |
42690816 ps |
| T2204 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_access_same_device.3345144888 |
|
|
Aug 25 05:12:07 PM UTC 24 |
Aug 25 05:14:01 PM UTC 24 |
980786451 ps |
| T2205 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_smoke_large_delays.3204673929 |
|
|
Aug 25 05:11:33 PM UTC 24 |
Aug 25 05:14:28 PM UTC 24 |
9317154823 ps |
| T2206 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_same_source.1082899588 |
|
|
Aug 25 05:14:07 PM UTC 24 |
Aug 25 05:14:32 PM UTC 24 |
414983866 ps |
| T2207 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.531467747 |
|
|
Aug 25 05:14:20 PM UTC 24 |
Aug 25 05:14:37 PM UTC 24 |
100099856 ps |
| T2208 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_unmapped_addr.516188468 |
|
|
Aug 25 05:14:17 PM UTC 24 |
Aug 25 05:14:47 PM UTC 24 |
427662479 ps |
| T2209 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_zero_delays.3665199922 |
|
|
Aug 25 05:13:50 PM UTC 24 |
Aug 25 05:14:54 PM UTC 24 |
441268531 ps |
| T2210 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_random_slow_rsp.100270294 |
|
|
Aug 25 05:02:57 PM UTC 24 |
Aug 25 05:14:55 PM UTC 24 |
30444520332 ps |
| T2211 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.26234118 |
|
|
Aug 25 05:03:20 PM UTC 24 |
Aug 25 05:15:07 PM UTC 24 |
6289538184 ps |
| T2212 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all.1772861747 |
|
|
Aug 25 05:06:22 PM UTC 24 |
Aug 25 05:15:07 PM UTC 24 |
11735888528 ps |
| T2213 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_error_random.830448785 |
|
|
Aug 25 05:14:17 PM UTC 24 |
Aug 25 05:15:08 PM UTC 24 |
396807516 ps |
| T2214 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.571285882 |
|
|
Aug 25 05:13:35 PM UTC 24 |
Aug 25 05:15:09 PM UTC 24 |
3966234816 ps |
| T2215 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_smoke_large_delays.2241126685 |
|
|
Aug 25 05:13:29 PM UTC 24 |
Aug 25 05:15:23 PM UTC 24 |
6470695237 ps |
| T2216 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke.2014867555 |
|
|
Aug 25 05:15:11 PM UTC 24 |
Aug 25 05:15:27 PM UTC 24 |
224320760 ps |
| T2217 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1039660714 |
|
|
Aug 25 05:15:19 PM UTC 24 |
Aug 25 05:15:30 PM UTC 24 |
43816363 ps |
| T2218 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.16683841 |
|
|
Aug 25 05:09:58 PM UTC 24 |
Aug 25 05:15:38 PM UTC 24 |
1062760052 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.836830336 |
|
|
Aug 25 04:51:12 PM UTC 24 |
Aug 25 05:15:48 PM UTC 24 |
58278816793 ps |
| T2219 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_access_same_device.934534190 |
|
|
Aug 25 05:14:03 PM UTC 24 |
Aug 25 05:16:07 PM UTC 24 |
934568923 ps |
| T2220 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_random.3767410958 |
|
|
Aug 25 05:16:12 PM UTC 24 |
Aug 25 05:16:26 PM UTC 24 |
130028883 ps |
| T2221 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random.454790030 |
|
|
Aug 25 05:15:32 PM UTC 24 |
Aug 25 05:16:34 PM UTC 24 |
508824925 ps |
| T2222 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2359779595 |
|
|
Aug 25 05:07:56 PM UTC 24 |
Aug 25 05:16:37 PM UTC 24 |
3560681681 ps |
| T2223 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_zero_delays.1964718283 |
|
|
Aug 25 05:15:34 PM UTC 24 |
Aug 25 05:16:42 PM UTC 24 |
468110474 ps |
| T2224 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_error.4196631770 |
|
|
Aug 25 05:07:58 PM UTC 24 |
Aug 25 05:16:54 PM UTC 24 |
10394876274 ps |
| T2225 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_same_csr_outstanding.721358887 |
|
|
Aug 25 03:59:17 PM UTC 24 |
Aug 25 05:17:03 PM UTC 24 |
32223017207 ps |
| T2226 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3257404288 |
|
|
Aug 25 05:12:49 PM UTC 24 |
Aug 25 05:17:04 PM UTC 24 |
281255700 ps |
| T2227 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_unmapped_addr.3818122754 |
|
|
Aug 25 05:16:31 PM UTC 24 |
Aug 25 05:17:07 PM UTC 24 |
170996749 ps |
| T2228 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/62.xbar_stress_all_with_error.2817969964 |
|
|
Aug 25 05:11:23 PM UTC 24 |
Aug 25 05:17:12 PM UTC 24 |
5629260853 ps |
| T2229 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_large_delays.396660646 |
|
|
Aug 25 05:15:20 PM UTC 24 |
Aug 25 05:17:22 PM UTC 24 |
6965873830 ps |
| T2230 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_access_same_device.3763891241 |
|
|
Aug 25 05:15:52 PM UTC 24 |
Aug 25 05:17:27 PM UTC 24 |
739942456 ps |
| T2231 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2129994373 |
|
|
Aug 25 05:16:49 PM UTC 24 |
Aug 25 05:17:36 PM UTC 24 |
813529241 ps |
| T2232 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke.2491947242 |
|
|
Aug 25 05:17:27 PM UTC 24 |
Aug 25 05:17:38 PM UTC 24 |
42135225 ps |
| T2233 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_zero_delays.4134745096 |
|
|
Aug 25 05:17:28 PM UTC 24 |
Aug 25 05:17:40 PM UTC 24 |
51912499 ps |
| T2234 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_same_source.886553242 |
|
|
Aug 25 05:16:03 PM UTC 24 |
Aug 25 05:17:40 PM UTC 24 |
1925696092 ps |
| T2235 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_random_slow_rsp.3498061078 |
|
|
Aug 25 05:06:07 PM UTC 24 |
Aug 25 05:17:44 PM UTC 24 |
31567421155 ps |
| T2236 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_stress_all.1892110398 |
|
|
Aug 25 05:14:23 PM UTC 24 |
Aug 25 05:17:45 PM UTC 24 |
1628210297 ps |
| T2237 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1057334097 |
|
|
Aug 25 05:09:03 PM UTC 24 |
Aug 25 05:17:53 PM UTC 24 |
4584161922 ps |
| T2238 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_slow_rsp.3974949192 |
|
|
Aug 25 04:57:19 PM UTC 24 |
Aug 25 05:17:56 PM UTC 24 |
56692792039 ps |
| T2239 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1617721603 |
|
|
Aug 25 05:03:33 PM UTC 24 |
Aug 25 05:18:06 PM UTC 24 |
10740581502 ps |
| T2240 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_slow_rsp.2130001342 |
|
|
Aug 25 04:59:49 PM UTC 24 |
Aug 25 05:18:10 PM UTC 24 |
48314256119 ps |
| T2241 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random_zero_delays.3790314335 |
|
|
Aug 25 05:17:52 PM UTC 24 |
Aug 25 05:18:15 PM UTC 24 |
122152227 ps |
| T2242 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.859681071 |
|
|
Aug 25 05:15:32 PM UTC 24 |
Aug 25 05:18:18 PM UTC 24 |
6317090464 ps |
| T2243 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1172508848 |
|
|
Aug 25 04:58:01 PM UTC 24 |
Aug 25 05:18:22 PM UTC 24 |
20627870253 ps |
| T2244 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_random.611166076 |
|
|
Aug 25 05:17:47 PM UTC 24 |
Aug 25 05:18:25 PM UTC 24 |
749862930 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all.1132449097 |
|
|
Aug 25 05:07:43 PM UTC 24 |
Aug 25 05:18:31 PM UTC 24 |
12481440446 ps |
| T2245 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_same_source.3364151621 |
|
|
Aug 25 05:18:08 PM UTC 24 |
Aug 25 05:18:36 PM UTC 24 |
454770419 ps |
| T2246 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_unmapped_addr.3775434558 |
|
|
Aug 25 05:18:17 PM UTC 24 |
Aug 25 05:18:44 PM UTC 24 |
116575327 ps |
| T2247 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke.1010456142 |
|
|
Aug 25 05:18:46 PM UTC 24 |
Aug 25 05:18:58 PM UTC 24 |
48853504 ps |
| T2248 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_smoke_zero_delays.4023864676 |
|
|
Aug 25 05:18:50 PM UTC 24 |
Aug 25 05:19:02 PM UTC 24 |
51952519 ps |
| T2249 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_large_delays.341288017 |
|
|
Aug 25 04:57:14 PM UTC 24 |
Aug 25 05:19:04 PM UTC 24 |
83482642538 ps |
| T2250 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device.2293652580 |
|
|
Aug 25 05:18:03 PM UTC 24 |
Aug 25 05:19:05 PM UTC 24 |
1149235547 ps |
| T2251 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_random_large_delays.2083255648 |
|
|
Aug 25 04:59:46 PM UTC 24 |
Aug 25 05:19:08 PM UTC 24 |
72055896673 ps |
| T2252 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_random.33537527 |
|
|
Aug 25 05:18:10 PM UTC 24 |
Aug 25 05:19:14 PM UTC 24 |
1087178531 ps |
| T2253 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3847952691 |
|
|
Aug 25 05:13:08 PM UTC 24 |
Aug 25 05:19:14 PM UTC 24 |
631535067 ps |
| T2254 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.411387400 |
|
|
Aug 25 05:18:20 PM UTC 24 |
Aug 25 05:19:24 PM UTC 24 |
1016949402 ps |
| T2255 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1576766294 |
|
|
Aug 25 05:08:01 PM UTC 24 |
Aug 25 05:19:26 PM UTC 24 |
6540537559 ps |
| T2256 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_stress_all.3158770643 |
|
|
Aug 25 05:18:31 PM UTC 24 |
Aug 25 05:19:28 PM UTC 24 |
1035188681 ps |
| T2257 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1918097562 |
|
|
Aug 25 05:17:36 PM UTC 24 |
Aug 25 05:19:29 PM UTC 24 |
4310083011 ps |
| T2258 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.656242506 |
|
|
Aug 25 03:28:42 PM UTC 24 |
Aug 25 05:19:34 PM UTC 24 |
30585925888 ps |
| T2259 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_access_same_device.268177928 |
|
|
Aug 25 05:19:29 PM UTC 24 |
Aug 25 05:19:39 PM UTC 24 |
108438782 ps |
| T2260 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1846822592 |
|
|
Aug 25 04:33:18 PM UTC 24 |
Aug 25 05:19:46 PM UTC 24 |
107483893604 ps |
| T2261 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_smoke_large_delays.1993220011 |
|
|
Aug 25 05:17:31 PM UTC 24 |
Aug 25 05:19:48 PM UTC 24 |
7782959188 ps |
| T2262 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_random_slow_rsp.143766735 |
|
|
Aug 25 05:08:39 PM UTC 24 |
Aug 25 05:19:52 PM UTC 24 |
33113641352 ps |
| T2263 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1677205068 |
|
|
Aug 25 04:24:46 PM UTC 24 |
Aug 25 05:20:00 PM UTC 24 |
143537049636 ps |
| T2264 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_zero_delays.2017795182 |
|
|
Aug 25 05:19:23 PM UTC 24 |
Aug 25 05:20:01 PM UTC 24 |
232990930 ps |
| T2265 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.459630609 |
|
|
Aug 25 05:19:51 PM UTC 24 |
Aug 25 05:20:06 PM UTC 24 |
52671748 ps |
| T2266 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_same_source.3185278260 |
|
|
Aug 25 05:19:38 PM UTC 24 |
Aug 25 05:20:17 PM UTC 24 |
395246184 ps |
| T2267 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_smoke.4285433896 |
|
|
Aug 25 05:20:09 PM UTC 24 |
Aug 25 05:20:20 PM UTC 24 |
40333937 ps |