| T43 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio.1914460928 |
|
|
Aug 25 09:16:58 PM UTC 24 |
Aug 25 09:29:18 PM UTC 24 |
3754816984 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3533303366 |
|
|
Aug 25 09:24:45 PM UTC 24 |
Aug 25 09:29:44 PM UTC 24 |
2797280589 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3560079514 |
|
|
Aug 25 09:17:14 PM UTC 24 |
Aug 25 09:30:44 PM UTC 24 |
4874104044 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_power_virus.2945388818 |
|
|
Aug 25 08:59:22 PM UTC 24 |
Aug 25 09:31:03 PM UTC 24 |
5444298682 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2519592331 |
|
|
Aug 25 09:28:35 PM UTC 24 |
Aug 25 09:31:14 PM UTC 24 |
2271389080 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1586730273 |
|
|
Aug 25 09:09:32 PM UTC 24 |
Aug 25 09:31:18 PM UTC 24 |
5747825544 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1139542204 |
|
|
Aug 25 09:28:18 PM UTC 24 |
Aug 25 09:31:47 PM UTC 24 |
2889636025 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx.942255431 |
|
|
Aug 25 09:15:38 PM UTC 24 |
Aug 25 09:31:58 PM UTC 24 |
4898617192 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4115990661 |
|
|
Aug 25 08:48:26 PM UTC 24 |
Aug 25 09:32:03 PM UTC 24 |
24130592424 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4053378226 |
|
|
Aug 25 09:16:58 PM UTC 24 |
Aug 25 09:32:03 PM UTC 24 |
4234309388 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through_collision.1370812605 |
|
|
Aug 25 09:17:00 PM UTC 24 |
Aug 25 09:32:43 PM UTC 24 |
4480551891 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2411895714 |
|
|
Aug 25 09:26:07 PM UTC 24 |
Aug 25 09:32:46 PM UTC 24 |
3998632041 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_spi_device_pass_through.4135653088 |
|
|
Aug 25 09:17:09 PM UTC 24 |
Aug 25 09:33:11 PM UTC 24 |
5861963719 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_ast_clk_rst_inputs.1647182316 |
|
|
Aug 25 08:57:57 PM UTC 24 |
Aug 25 09:33:19 PM UTC 24 |
14694022416 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3222163409 |
|
|
Aug 25 09:14:17 PM UTC 24 |
Aug 25 09:33:22 PM UTC 24 |
4709682464 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3293458420 |
|
|
Aug 25 08:09:40 PM UTC 24 |
Aug 25 09:33:25 PM UTC 24 |
20671860437 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx.3141382682 |
|
|
Aug 25 09:15:27 PM UTC 24 |
Aug 25 09:33:50 PM UTC 24 |
4509471900 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops.3165817294 |
|
|
Aug 25 09:17:00 PM UTC 24 |
Aug 25 09:34:15 PM UTC 24 |
4223556302 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1773568137 |
|
|
Aug 25 09:15:40 PM UTC 24 |
Aug 25 09:34:31 PM UTC 24 |
4622419224 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_rst.1136260163 |
|
|
Aug 25 09:29:09 PM UTC 24 |
Aug 25 09:34:45 PM UTC 24 |
2349652152 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.636942033 |
|
|
Aug 25 08:54:25 PM UTC 24 |
Aug 25 09:36:31 PM UTC 24 |
12090494727 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_transition.1552883009 |
|
|
Aug 25 09:26:09 PM UTC 24 |
Aug 25 09:38:11 PM UTC 24 |
6682094970 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init_reduced_freq.2275878494 |
|
|
Aug 25 08:55:27 PM UTC 24 |
Aug 25 09:38:12 PM UTC 24 |
25338877617 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3927404815 |
|
|
Aug 25 07:08:38 PM UTC 24 |
Aug 25 09:39:47 PM UTC 24 |
23994404440 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.348700301 |
|
|
Aug 25 08:47:34 PM UTC 24 |
Aug 25 09:40:09 PM UTC 24 |
22869631680 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2405772886 |
|
|
Aug 25 09:22:43 PM UTC 24 |
Aug 25 09:40:29 PM UTC 24 |
4129674824 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_irq.3707201443 |
|
|
Aug 25 09:35:20 PM UTC 24 |
Aug 25 09:40:43 PM UTC 24 |
2630695080 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1847082961 |
|
|
Aug 25 08:38:30 PM UTC 24 |
Aug 25 09:40:46 PM UTC 24 |
23089205953 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access.2149757370 |
|
|
Aug 25 09:17:11 PM UTC 24 |
Aug 25 09:41:27 PM UTC 24 |
5425161928 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1837913859 |
|
|
Aug 25 09:30:24 PM UTC 24 |
Aug 25 09:41:57 PM UTC 24 |
7333108544 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_sw_req.3456796016 |
|
|
Aug 25 09:28:36 PM UTC 24 |
Aug 25 09:42:45 PM UTC 24 |
4948320188 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3213063442 |
|
|
Aug 25 09:19:40 PM UTC 24 |
Aug 25 09:42:50 PM UTC 24 |
5447725236 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_smoketest.462995268 |
|
|
Aug 25 09:06:05 PM UTC 24 |
Aug 25 09:42:50 PM UTC 24 |
7133021520 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1062531766 |
|
|
Aug 25 09:36:00 PM UTC 24 |
Aug 25 09:42:58 PM UTC 24 |
3304175114 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1919703599 |
|
|
Aug 25 09:31:25 PM UTC 24 |
Aug 25 09:43:07 PM UTC 24 |
3310175207 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pwm_pulses.2691056156 |
|
|
Aug 25 09:14:16 PM UTC 24 |
Aug 25 09:43:11 PM UTC 24 |
8483591304 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.40784675 |
|
|
Aug 25 07:06:00 PM UTC 24 |
Aug 25 09:43:14 PM UTC 24 |
23394878124 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1323135703 |
|
|
Aug 25 07:05:07 PM UTC 24 |
Aug 25 09:43:53 PM UTC 24 |
22754359852 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3746098788 |
|
|
Aug 25 09:35:30 PM UTC 24 |
Aug 25 09:45:20 PM UTC 24 |
3537352583 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2540525467 |
|
|
Aug 25 09:37:13 PM UTC 24 |
Aug 25 09:45:24 PM UTC 24 |
3212503000 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1618413683 |
|
|
Aug 25 09:35:53 PM UTC 24 |
Aug 25 09:45:25 PM UTC 24 |
6643894600 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2575854482 |
|
|
Aug 25 09:17:20 PM UTC 24 |
Aug 25 09:46:06 PM UTC 24 |
6383081941 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3357599115 |
|
|
Aug 25 08:14:45 PM UTC 24 |
Aug 25 09:47:14 PM UTC 24 |
16558202560 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3264077777 |
|
|
Aug 25 09:33:36 PM UTC 24 |
Aug 25 09:48:06 PM UTC 24 |
5896719920 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_cpu_info.1884714105 |
|
|
Aug 25 09:30:04 PM UTC 24 |
Aug 25 09:48:28 PM UTC 24 |
5340222064 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2497819803 |
|
|
Aug 25 09:33:35 PM UTC 24 |
Aug 25 09:48:34 PM UTC 24 |
8917584918 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2297212404 |
|
|
Aug 25 09:35:08 PM UTC 24 |
Aug 25 09:49:05 PM UTC 24 |
5595030980 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2465873181 |
|
|
Aug 25 09:35:46 PM UTC 24 |
Aug 25 09:50:00 PM UTC 24 |
5336042236 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.790154134 |
|
|
Aug 25 09:39:05 PM UTC 24 |
Aug 25 09:50:15 PM UTC 24 |
4059338568 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2478684558 |
|
|
Aug 25 07:05:28 PM UTC 24 |
Aug 25 09:50:21 PM UTC 24 |
24482500094 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc.1653622340 |
|
|
Aug 25 09:45:06 PM UTC 24 |
Aug 25 09:50:29 PM UTC 24 |
2833406928 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.632825032 |
|
|
Aug 25 09:23:24 PM UTC 24 |
Aug 25 09:50:36 PM UTC 24 |
6897243002 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3211297990 |
|
|
Aug 25 09:35:27 PM UTC 24 |
Aug 25 09:50:40 PM UTC 24 |
4804412453 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_idle.1634748327 |
|
|
Aug 25 09:44:39 PM UTC 24 |
Aug 25 09:50:52 PM UTC 24 |
2921521738 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_test.1405585634 |
|
|
Aug 25 09:45:03 PM UTC 24 |
Aug 25 09:51:00 PM UTC 24 |
3324556560 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en.1572245638 |
|
|
Aug 25 09:44:50 PM UTC 24 |
Aug 25 09:51:10 PM UTC 24 |
2848054183 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1636182612 |
|
|
Aug 25 07:04:42 PM UTC 24 |
Aug 25 09:51:35 PM UTC 24 |
23894360504 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_masking_off.2105373906 |
|
|
Aug 25 09:45:06 PM UTC 24 |
Aug 25 09:51:48 PM UTC 24 |
2721550814 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2783327533 |
|
|
Aug 25 09:24:43 PM UTC 24 |
Aug 25 09:52:30 PM UTC 24 |
8112480678 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1623735061 |
|
|
Aug 25 09:32:07 PM UTC 24 |
Aug 25 09:53:17 PM UTC 24 |
7041031700 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.663873745 |
|
|
Aug 25 09:40:29 PM UTC 24 |
Aug 25 09:53:44 PM UTC 24 |
6960401568 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3732244290 |
|
|
Aug 25 09:41:45 PM UTC 24 |
Aug 25 09:54:06 PM UTC 24 |
4147093352 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_entropy.3248979768 |
|
|
Aug 25 09:49:45 PM UTC 24 |
Aug 25 09:54:26 PM UTC 24 |
2741527896 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.788281028 |
|
|
Aug 25 07:05:47 PM UTC 24 |
Aug 25 09:54:37 PM UTC 24 |
23883802152 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2910809335 |
|
|
Aug 25 09:41:44 PM UTC 24 |
Aug 25 09:54:41 PM UTC 24 |
18308645452 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.553037892 |
|
|
Aug 25 09:46:49 PM UTC 24 |
Aug 25 09:54:56 PM UTC 24 |
3562226758 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_wdog_reset.952396795 |
|
|
Aug 25 09:41:38 PM UTC 24 |
Aug 25 09:55:23 PM UTC 24 |
4422140328 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prodend.3603801200 |
|
|
Aug 25 09:28:26 PM UTC 24 |
Aug 25 09:55:42 PM UTC 24 |
11265658696 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2561773371 |
|
|
Aug 25 09:23:06 PM UTC 24 |
Aug 25 09:56:31 PM UTC 24 |
8732533472 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_kat_test.109051257 |
|
|
Aug 25 09:51:15 PM UTC 24 |
Aug 25 09:57:31 PM UTC 24 |
2570744960 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_escalation.4164771121 |
|
|
Aug 25 09:45:05 PM UTC 24 |
Aug 25 09:57:54 PM UTC 24 |
4345604632 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_kat_test.1107360167 |
|
|
Aug 25 09:52:34 PM UTC 24 |
Aug 25 09:58:13 PM UTC 24 |
2150582358 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2025643042 |
|
|
Aug 25 09:53:34 PM UTC 24 |
Aug 25 09:58:15 PM UTC 24 |
2695553400 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_entropy.392623567 |
|
|
Aug 25 09:49:25 PM UTC 24 |
Aug 25 09:58:49 PM UTC 24 |
2811178794 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4158490085 |
|
|
Aug 25 09:14:10 PM UTC 24 |
Aug 25 09:59:44 PM UTC 24 |
8829857697 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3088593544 |
|
|
Aug 25 07:05:04 PM UTC 24 |
Aug 25 10:00:06 PM UTC 24 |
24055253118 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3231390559 |
|
|
Aug 25 09:32:27 PM UTC 24 |
Aug 25 10:00:37 PM UTC 24 |
8669974273 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.306383467 |
|
|
Aug 25 09:33:59 PM UTC 24 |
Aug 25 10:00:59 PM UTC 24 |
9482721276 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc.2813447038 |
|
|
Aug 25 09:54:27 PM UTC 24 |
Aug 25 10:01:14 PM UTC 24 |
3056471180 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_timeout.3074800664 |
|
|
Aug 25 09:46:31 PM UTC 24 |
Aug 25 10:01:45 PM UTC 24 |
4819190616 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_randomness.3036541306 |
|
|
Aug 25 09:41:51 PM UTC 24 |
Aug 25 10:02:18 PM UTC 24 |
5825191528 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en.506241184 |
|
|
Aug 25 09:54:48 PM UTC 24 |
Aug 25 10:02:25 PM UTC 24 |
3522237711 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.612864384 |
|
|
Aug 25 08:14:46 PM UTC 24 |
Aug 25 10:02:28 PM UTC 24 |
18684515954 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_oneshot.681186113 |
|
|
Aug 25 09:56:12 PM UTC 24 |
Aug 25 10:03:31 PM UTC 24 |
3010910160 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.930802305 |
|
|
Aug 25 09:41:46 PM UTC 24 |
Aug 25 10:03:49 PM UTC 24 |
8994462288 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_cshake.3998623992 |
|
|
Aug 25 09:58:34 PM UTC 24 |
Aug 25 10:03:52 PM UTC 24 |
2846546416 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.1795001092 |
|
|
Aug 25 07:37:08 PM UTC 24 |
Aug 25 10:04:34 PM UTC 24 |
44697576928 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1294416606 |
|
|
Aug 25 09:53:27 PM UTC 24 |
Aug 25 10:04:35 PM UTC 24 |
5139276152 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_self_hash.3486280420 |
|
|
Aug 25 07:05:08 PM UTC 24 |
Aug 25 10:04:35 PM UTC 24 |
27292263800 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_idle.2963913680 |
|
|
Aug 25 09:56:05 PM UTC 24 |
Aug 25 10:04:50 PM UTC 24 |
3140786400 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_app_rom.31560970 |
|
|
Aug 25 09:59:29 PM UTC 24 |
Aug 25 10:04:54 PM UTC 24 |
2137835836 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_idle.4043417044 |
|
|
Aug 25 10:00:25 PM UTC 24 |
Aug 25 10:05:17 PM UTC 24 |
3131162608 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac.2095395473 |
|
|
Aug 25 09:59:05 PM UTC 24 |
Aug 25 10:05:39 PM UTC 24 |
3128897548 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4129018566 |
|
|
Aug 25 09:44:40 PM UTC 24 |
Aug 25 10:05:39 PM UTC 24 |
4549169222 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1178324922 |
|
|
Aug 25 09:59:06 PM UTC 24 |
Aug 25 10:05:45 PM UTC 24 |
3124010515 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1061762216 |
|
|
Aug 25 09:53:01 PM UTC 24 |
Aug 25 10:06:37 PM UTC 24 |
5907569232 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_kat.3741542395 |
|
|
Aug 25 09:52:41 PM UTC 24 |
Aug 25 10:06:37 PM UTC 24 |
3693997568 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_boot_mode.1591801594 |
|
|
Aug 25 09:52:09 PM UTC 24 |
Aug 25 10:06:47 PM UTC 24 |
2895667528 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_rnd.3668370958 |
|
|
Aug 25 09:44:41 PM UTC 24 |
Aug 25 10:07:01 PM UTC 24 |
5324528194 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_keymgr_sideload_otbn.952575233 |
|
|
Aug 25 08:35:41 PM UTC 24 |
Aug 25 10:09:12 PM UTC 24 |
14856418120 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.294943950 |
|
|
Aug 25 07:07:06 PM UTC 24 |
Aug 25 10:09:16 PM UTC 24 |
24096739816 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_status.2183931535 |
|
|
Aug 25 10:03:29 PM UTC 24 |
Aug 25 10:10:29 PM UTC 24 |
3556522506 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.212529950 |
|
|
Aug 25 09:33:06 PM UTC 24 |
Aug 25 10:11:42 PM UTC 24 |
16874050780 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_alert_info.2014124341 |
|
|
Aug 25 09:30:02 PM UTC 24 |
Aug 25 10:11:57 PM UTC 24 |
10669519394 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3045361392 |
|
|
Aug 25 10:00:48 PM UTC 24 |
Aug 25 10:12:21 PM UTC 24 |
9029763848 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init.2762058733 |
|
|
Aug 25 09:18:31 PM UTC 24 |
Aug 25 10:12:37 PM UTC 24 |
22865710088 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_ping_ok.2683051156 |
|
|
Aug 25 09:46:29 PM UTC 24 |
Aug 25 10:14:00 PM UTC 24 |
7856345554 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_plic_sw_irq.1091741364 |
|
|
Aug 25 10:06:40 PM UTC 24 |
Aug 25 10:14:17 PM UTC 24 |
2650107836 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_rma.3656033233 |
|
|
Aug 25 07:49:44 PM UTC 24 |
Aug 25 10:14:51 PM UTC 24 |
47433522335 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs.4117558774 |
|
|
Aug 25 09:53:32 PM UTC 24 |
Aug 25 10:14:57 PM UTC 24 |
6701459788 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3390769307 |
|
|
Aug 25 10:01:19 PM UTC 24 |
Aug 25 10:15:17 PM UTC 24 |
5198596552 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.356322575 |
|
|
Aug 25 10:02:26 PM UTC 24 |
Aug 25 10:15:59 PM UTC 24 |
8010914770 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.1329664436 |
|
|
Aug 25 10:05:12 PM UTC 24 |
Aug 25 10:16:15 PM UTC 24 |
4438769102 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_aes_trans.441971396 |
|
|
Aug 25 10:06:43 PM UTC 24 |
Aug 25 10:16:46 PM UTC 24 |
4788170248 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_auto_mode.296383966 |
|
|
Aug 25 09:51:53 PM UTC 24 |
Aug 25 10:16:46 PM UTC 24 |
4340083032 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4113775737 |
|
|
Aug 25 10:04:49 PM UTC 24 |
Aug 25 10:16:59 PM UTC 24 |
5104936652 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3435667230 |
|
|
Aug 25 10:01:49 PM UTC 24 |
Aug 25 10:17:23 PM UTC 24 |
4355818717 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter.2980669657 |
|
|
Aug 25 10:11:09 PM UTC 24 |
Aug 25 10:18:17 PM UTC 24 |
2425456547 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3969391853 |
|
|
Aug 25 10:06:51 PM UTC 24 |
Aug 25 10:19:09 PM UTC 24 |
4630076540 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1252956497 |
|
|
Aug 25 10:06:54 PM UTC 24 |
Aug 25 10:19:47 PM UTC 24 |
5542342680 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_execution_main.1741926498 |
|
|
Aug 25 10:01:56 PM UTC 24 |
Aug 25 10:19:55 PM UTC 24 |
6620331792 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_reset_frequency.1120729015 |
|
|
Aug 25 10:10:03 PM UTC 24 |
Aug 25 10:20:20 PM UTC 24 |
3389620520 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1983320741 |
|
|
Aug 25 09:53:56 PM UTC 24 |
Aug 25 10:20:44 PM UTC 24 |
5961679574 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.3062815019 |
|
|
Aug 25 10:03:27 PM UTC 24 |
Aug 25 10:21:02 PM UTC 24 |
6203237900 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2473091531 |
|
|
Aug 25 10:10:03 PM UTC 24 |
Aug 25 10:21:10 PM UTC 24 |
3290202966 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3032672825 |
|
|
Aug 25 10:08:20 PM UTC 24 |
Aug 25 10:21:17 PM UTC 24 |
3850981496 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_edn_sw_mode.17828742 |
|
|
Aug 25 09:52:56 PM UTC 24 |
Aug 25 10:21:57 PM UTC 24 |
5780149464 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.8021669 |
|
|
Aug 25 10:08:23 PM UTC 24 |
Aug 25 10:21:59 PM UTC 24 |
4678987236 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1933852142 |
|
|
Aug 25 10:08:23 PM UTC 24 |
Aug 25 10:22:00 PM UTC 24 |
4314358384 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2343957634 |
|
|
Aug 25 09:32:48 PM UTC 24 |
Aug 25 10:22:03 PM UTC 24 |
20708395980 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_reset.51458608 |
|
|
Aug 25 09:35:51 PM UTC 24 |
Aug 25 10:22:35 PM UTC 24 |
24467668040 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.303417301 |
|
|
Aug 25 09:28:27 PM UTC 24 |
Aug 25 10:22:38 PM UTC 24 |
34226060021 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_aes.2971861902 |
|
|
Aug 25 09:57:12 PM UTC 24 |
Aug 25 10:23:05 PM UTC 24 |
6771226072 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2521581101 |
|
|
Aug 25 09:47:56 PM UTC 24 |
Aug 25 10:23:14 PM UTC 24 |
11188249928 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_rma.2607416552 |
|
|
Aug 25 10:19:41 PM UTC 24 |
Aug 25 10:23:16 PM UTC 24 |
2477702202 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_dev.2389618558 |
|
|
Aug 25 10:18:47 PM UTC 24 |
Aug 25 10:23:53 PM UTC 24 |
3091102045 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3917665984 |
|
|
Aug 25 10:08:15 PM UTC 24 |
Aug 25 10:23:59 PM UTC 24 |
4351903836 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.220523326 |
|
|
Aug 25 10:03:23 PM UTC 24 |
Aug 25 10:24:08 PM UTC 24 |
9053544918 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_prod.2313733906 |
|
|
Aug 25 10:20:31 PM UTC 24 |
Aug 25 10:24:15 PM UTC 24 |
3028438177 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_rand_baudrate.1612149494 |
|
|
Aug 25 09:16:51 PM UTC 24 |
Aug 25 10:24:39 PM UTC 24 |
13668280176 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2333744364 |
|
|
Aug 25 10:08:05 PM UTC 24 |
Aug 25 10:24:40 PM UTC 24 |
4412130248 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2846133849 |
|
|
Aug 25 10:15:56 PM UTC 24 |
Aug 25 10:24:41 PM UTC 24 |
3549623232 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2923556373 |
|
|
Aug 25 10:07:36 PM UTC 24 |
Aug 25 10:24:46 PM UTC 24 |
3560030536 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1884723319 |
|
|
Aug 25 10:08:24 PM UTC 24 |
Aug 25 10:25:08 PM UTC 24 |
5393235776 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_rv_dm_ndm_reset_req.2074710793 |
|
|
Aug 25 10:18:11 PM UTC 24 |
Aug 25 10:25:34 PM UTC 24 |
3585172160 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_20.3533819459 |
|
|
Aug 25 10:07:36 PM UTC 24 |
Aug 25 10:25:40 PM UTC 24 |
5089237640 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_ctrl_program_error.2616020721 |
|
|
Aug 25 10:14:53 PM UTC 24 |
Aug 25 10:25:41 PM UTC 24 |
4875751090 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_test_unlocked0.789396659 |
|
|
Aug 25 09:03:52 PM UTC 24 |
Aug 25 10:25:57 PM UTC 24 |
11071469869 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1818812925 |
|
|
Aug 25 10:06:50 PM UTC 24 |
Aug 25 10:25:59 PM UTC 24 |
10449944964 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1804175292 |
|
|
Aug 25 10:21:01 PM UTC 24 |
Aug 25 10:26:07 PM UTC 24 |
2487808720 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_sleep_frequency.884089624 |
|
|
Aug 25 10:12:24 PM UTC 24 |
Aug 25 10:26:17 PM UTC 24 |
4499734086 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2091362127 |
|
|
Aug 25 10:15:00 PM UTC 24 |
Aug 25 10:26:30 PM UTC 24 |
8054206600 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_kmac.4157859014 |
|
|
Aug 25 09:56:37 PM UTC 24 |
Aug 25 10:26:44 PM UTC 24 |
6934933640 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1275858009 |
|
|
Aug 25 10:22:09 PM UTC 24 |
Aug 25 10:26:49 PM UTC 24 |
2714300022 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2359946978 |
|
|
Aug 25 10:20:38 PM UTC 24 |
Aug 25 10:27:06 PM UTC 24 |
2630506460 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4263941484 |
|
|
Aug 25 10:21:25 PM UTC 24 |
Aug 25 10:27:24 PM UTC 24 |
3375158924 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4286565983 |
|
|
Aug 25 10:18:10 PM UTC 24 |
Aug 25 10:27:25 PM UTC 24 |
5055786357 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_prod.783747585 |
|
|
Aug 25 09:56:36 PM UTC 24 |
Aug 25 10:27:27 PM UTC 24 |
8183848120 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_rma.1350949007 |
|
|
Aug 25 09:04:22 PM UTC 24 |
Aug 25 10:28:08 PM UTC 24 |
14883557539 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3116335941 |
|
|
Aug 25 10:16:52 PM UTC 24 |
Aug 25 10:28:28 PM UTC 24 |
6382106688 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3372274171 |
|
|
Aug 25 10:16:58 PM UTC 24 |
Aug 25 10:28:50 PM UTC 24 |
5586560952 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3111124343 |
|
|
Aug 25 10:23:49 PM UTC 24 |
Aug 25 10:29:08 PM UTC 24 |
2409568437 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2237333049 |
|
|
Aug 25 10:24:11 PM UTC 24 |
Aug 25 10:29:19 PM UTC 24 |
3315807935 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_tap_straps_testunlock0.798408416 |
|
|
Aug 25 10:19:31 PM UTC 24 |
Aug 25 10:29:28 PM UTC 24 |
4446480755 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3654402174 |
|
|
Aug 25 10:18:02 PM UTC 24 |
Aug 25 10:30:14 PM UTC 24 |
5205529270 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_multistream.1553994612 |
|
|
Aug 25 09:56:38 PM UTC 24 |
Aug 25 10:30:23 PM UTC 24 |
7723329636 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_volatile_raw_unlock.2110952793 |
|
|
Aug 25 10:29:06 PM UTC 24 |
Aug 25 10:31:22 PM UTC 24 |
1774678419 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_write_clear.284951202 |
|
|
Aug 25 10:22:10 PM UTC 24 |
Aug 25 10:31:36 PM UTC 24 |
3445807192 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.322737164 |
|
|
Aug 25 10:18:05 PM UTC 24 |
Aug 25 10:32:15 PM UTC 24 |
6606698750 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_csrng.3817200333 |
|
|
Aug 25 09:53:26 PM UTC 24 |
Aug 25 10:32:21 PM UTC 24 |
7556893854 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prod.1779623438 |
|
|
Aug 25 07:47:32 PM UTC 24 |
Aug 25 10:32:31 PM UTC 24 |
48251990692 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1796843644 |
|
|
Aug 25 10:26:20 PM UTC 24 |
Aug 25 10:32:47 PM UTC 24 |
3040861583 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.162306000 |
|
|
Aug 25 09:49:24 PM UTC 24 |
Aug 25 10:33:12 PM UTC 24 |
8106906096 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4048347025 |
|
|
Aug 25 10:24:45 PM UTC 24 |
Aug 25 10:34:02 PM UTC 24 |
4374599675 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4104920920 |
|
|
Aug 25 08:53:45 PM UTC 24 |
Aug 25 10:34:04 PM UTC 24 |
24173246076 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.794874463 |
|
|
Aug 25 09:56:31 PM UTC 24 |
Aug 25 10:34:17 PM UTC 24 |
8711925972 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_outputs.1389291858 |
|
|
Aug 25 10:13:18 PM UTC 24 |
Aug 25 10:34:29 PM UTC 24 |
6533354350 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.634456335 |
|
|
Aug 25 10:06:48 PM UTC 24 |
Aug 25 10:34:35 PM UTC 24 |
5606698678 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_off_peri.4088902828 |
|
|
Aug 25 10:06:44 PM UTC 24 |
Aug 25 10:35:24 PM UTC 24 |
11956345256 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3499686488 |
|
|
Aug 25 09:48:48 PM UTC 24 |
Aug 25 10:35:41 PM UTC 24 |
8078586288 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_exception_c.1680327618 |
|
|
Aug 25 09:01:26 PM UTC 24 |
Aug 25 10:36:05 PM UTC 24 |
14858916420 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3885652016 |
|
|
Aug 25 10:23:27 PM UTC 24 |
Aug 25 10:36:22 PM UTC 24 |
4611383575 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_crash_alert.354002765 |
|
|
Aug 25 10:22:11 PM UTC 24 |
Aug 25 10:36:46 PM UTC 24 |
4841262000 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_kmac_smoketest.2704289848 |
|
|
Aug 25 10:31:28 PM UTC 24 |
Aug 25 10:37:05 PM UTC 24 |
2857154940 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_scrambling_smoketest.4039713619 |
|
|
Aug 25 10:32:13 PM UTC 24 |
Aug 25 10:37:52 PM UTC 24 |
3151222942 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_clkmgr_smoketest.2024613598 |
|
|
Aug 25 10:31:29 PM UTC 24 |
Aug 25 10:37:57 PM UTC 24 |
2506593752 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aes_smoketest.2771353805 |
|
|
Aug 25 10:32:28 PM UTC 24 |
Aug 25 10:38:04 PM UTC 24 |
2427090930 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_raw_unlock.4206727033 |
|
|
Aug 25 10:31:49 PM UTC 24 |
Aug 25 10:38:10 PM UTC 24 |
5365932423 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otp_ctrl_smoketest.2924816874 |
|
|
Aug 25 10:32:53 PM UTC 24 |
Aug 25 10:38:36 PM UTC 24 |
3193711198 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_plic_smoketest.22973220 |
|
|
Aug 25 10:33:21 PM UTC 24 |
Aug 25 10:38:48 PM UTC 24 |
2661446456 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_shutdown_output.2449234126 |
|
|
Aug 25 09:04:21 PM UTC 24 |
Aug 25 10:39:12 PM UTC 24 |
27192963475 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_smoke.2347199982 |
|
|
Aug 25 09:00:02 PM UTC 24 |
Aug 25 10:39:26 PM UTC 24 |
15105660478 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1448594694 |
|
|
Aug 25 09:06:01 PM UTC 24 |
Aug 25 10:39:35 PM UTC 24 |
14963662104 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_sleep_load.3991295894 |
|
|
Aug 25 10:26:17 PM UTC 24 |
Aug 25 10:39:53 PM UTC 24 |
11657924132 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rstmgr_smoketest.3955680848 |
|
|
Aug 25 10:35:22 PM UTC 24 |
Aug 25 10:40:21 PM UTC 24 |
2702297760 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_hmac_smoketest.4279044496 |
|
|
Aug 25 10:31:18 PM UTC 24 |
Aug 25 10:40:23 PM UTC 24 |
2853069452 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_rv_timer_smoketest.3723416448 |
|
|
Aug 25 10:34:14 PM UTC 24 |
Aug 25 10:40:24 PM UTC 24 |
2825557786 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod_end.2699226344 |
|
|
Aug 25 09:05:22 PM UTC 24 |
Aug 25 10:40:40 PM UTC 24 |
15218019861 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_smoketest.2777339005 |
|
|
Aug 25 10:34:46 PM UTC 24 |
Aug 25 10:40:40 PM UTC 24 |
2842722332 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_gpio_smoketest.3030197286 |
|
|
Aug 25 10:34:12 PM UTC 24 |
Aug 25 10:40:48 PM UTC 24 |
3028349151 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_smoketest.2541986617 |
|
|
Aug 25 10:36:12 PM UTC 24 |
Aug 25 10:41:32 PM UTC 24 |
2846821624 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_smoketest.2601915396 |
|
|
Aug 25 10:35:47 PM UTC 24 |
Aug 25 10:42:07 PM UTC 24 |
2649682550 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sram_ctrl_smoketest.4042236593 |
|
|
Aug 25 10:35:48 PM UTC 24 |
Aug 25 10:42:51 PM UTC 24 |
2760709980 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2271086928 |
|
|
Aug 25 10:16:02 PM UTC 24 |
Aug 25 10:43:28 PM UTC 24 |
18582593250 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_idle_load.4261331163 |
|
|
Aug 25 10:30:31 PM UTC 24 |
Aug 25 10:43:33 PM UTC 24 |
4399969448 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_dev.3020130562 |
|
|
Aug 25 07:46:31 PM UTC 24 |
Aug 25 10:44:21 PM UTC 24 |
46035343898 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_dev.4018485258 |
|
|
Aug 25 10:39:32 PM UTC 24 |
Aug 25 10:45:48 PM UTC 24 |
3378107528 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_entropy_src_smoketest.3131034869 |
|
|
Aug 25 10:34:00 PM UTC 24 |
Aug 25 10:45:51 PM UTC 24 |
3911703100 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_keymgr_functest.55749811 |
|
|
Aug 25 10:34:11 PM UTC 24 |
Aug 25 10:46:02 PM UTC 24 |
4745623744 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_testunlock0.578993661 |
|
|
Aug 25 10:39:49 PM UTC 24 |
Aug 25 10:47:01 PM UTC 24 |
3567594151 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_smoketest.1236339972 |
|
|
Aug 25 10:33:07 PM UTC 24 |
Aug 25 10:47:21 PM UTC 24 |
6702071720 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_dev.2158232639 |
|
|
Aug 25 09:05:00 PM UTC 24 |
Aug 25 10:47:27 PM UTC 24 |
15652616347 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_mem_access.481883730 |
|
|
Aug 25 10:12:43 PM UTC 24 |
Aug 25 10:47:59 PM UTC 24 |
13326624672 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1540489207 |
|
|
Aug 25 10:12:20 PM UTC 24 |
Aug 25 10:48:00 PM UTC 24 |
13865342442 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749846188 |
|
|
Aug 25 10:39:39 PM UTC 24 |
Aug 25 10:48:18 PM UTC 24 |
4302815720 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1788384459 |
|
|
Aug 25 10:35:19 PM UTC 24 |
Aug 25 10:50:01 PM UTC 24 |
6294399922 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_static_critical.1064007788 |
|
|
Aug 25 09:06:05 PM UTC 24 |
Aug 25 10:50:15 PM UTC 24 |
17143916936 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx2.929761755 |
|
|
Aug 25 10:37:43 PM UTC 24 |
Aug 25 10:51:19 PM UTC 24 |
4210615792 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx1.2147634007 |
|
|
Aug 25 10:37:21 PM UTC 24 |
Aug 25 10:51:47 PM UTC 24 |
4019811560 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx.2861429054 |
|
|
Aug 25 10:37:07 PM UTC 24 |
Aug 25 10:51:50 PM UTC 24 |
4813678988 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_idx3.1609026229 |
|
|
Aug 25 10:37:07 PM UTC 24 |
Aug 25 10:51:54 PM UTC 24 |
4390221250 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4249092836 |
|
|
Aug 25 10:24:18 PM UTC 24 |
Aug 25 10:52:06 PM UTC 24 |
6948723234 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_asm_init_prod.3295852415 |
|
|
Aug 25 09:04:47 PM UTC 24 |
Aug 25 10:52:30 PM UTC 24 |
15770220406 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3189528005 |
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Aug 25 10:29:46 PM UTC 24 |
Aug 25 10:52:40 PM UTC 24 |
5309559400 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_all_escalation_resets.611628385 |
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Aug 25 10:37:29 PM UTC 24 |
Aug 25 10:53:08 PM UTC 24 |
5126864720 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_data_integrity_escalation.828862120 |
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Aug 25 10:36:06 PM UTC 24 |
Aug 25 10:53:13 PM UTC 24 |
6388055856 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1118237708 |
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Aug 25 10:15:57 PM UTC 24 |
Aug 25 10:53:21 PM UTC 24 |
21413360412 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_dev.3363769337 |
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Aug 25 10:46:38 PM UTC 24 |
Aug 25 10:53:21 PM UTC 24 |
4144828865 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.128252758 |
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Aug 25 09:05:55 PM UTC 24 |
Aug 25 10:53:53 PM UTC 24 |
14665937510 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_rma.1141051493 |
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Aug 25 10:47:35 PM UTC 24 |
Aug 25 10:54:04 PM UTC 24 |
3689993941 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.20493187 |
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Aug 25 10:39:28 PM UTC 24 |
Aug 25 10:54:10 PM UTC 24 |
6824071248 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.465056621 |
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Aug 25 10:44:23 PM UTC 24 |
Aug 25 10:54:24 PM UTC 24 |
7238791108 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3831458468 |
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Aug 25 10:44:24 PM UTC 24 |
Aug 25 10:54:33 PM UTC 24 |
4107174520 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_rma.1935053639 |
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Aug 25 10:39:57 PM UTC 24 |
Aug 25 10:54:36 PM UTC 24 |
5835090808 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_sensor_ctrl_alert.3082800198 |
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Aug 25 10:39:46 PM UTC 24 |
Aug 25 10:54:36 PM UTC 24 |
7169867594 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3134998171 |
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Aug 25 09:04:45 PM UTC 24 |
Aug 25 10:54:43 PM UTC 24 |
15219822268 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1109093723 |
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Aug 25 10:42:54 PM UTC 24 |
Aug 25 10:55:08 PM UTC 24 |
4271090566 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_lc_ctrl_transition.184696627 |
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Aug 25 10:43:32 PM UTC 24 |
Aug 25 10:55:08 PM UTC 24 |
6217151860 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_tap_straps_prod.4096166278 |
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Aug 25 10:40:06 PM UTC 24 |
Aug 25 10:55:28 PM UTC 24 |
7724214287 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx3.302161211 |
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Aug 25 10:42:29 PM UTC 24 |
Aug 25 10:55:31 PM UTC 24 |
4633212168 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_data_integrity_escalation.2296179755 |
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Aug 25 10:42:13 PM UTC 24 |
Aug 25 10:56:04 PM UTC 24 |
4735551752 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.923121056 |
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Aug 25 10:23:50 PM UTC 24 |
Aug 25 10:56:53 PM UTC 24 |
10858219835 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx2.4229534156 |
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Aug 25 10:42:15 PM UTC 24 |
Aug 25 10:57:05 PM UTC 24 |
4427566500 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx.2223602000 |
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Aug 25 10:42:14 PM UTC 24 |
Aug 25 10:57:13 PM UTC 24 |
4420433384 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_idx1.1909373518 |
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Aug 25 10:42:47 PM UTC 24 |
Aug 25 10:57:45 PM UTC 24 |
4953589200 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_all_escalation_resets.4197978070 |
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Aug 25 10:40:34 PM UTC 24 |
Aug 25 10:58:19 PM UTC 24 |
5042787068 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4177597408 |
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Aug 25 10:50:56 PM UTC 24 |
Aug 25 10:58:48 PM UTC 24 |
3501517124 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2561182696 |
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Aug 25 08:55:50 PM UTC 24 |
Aug 25 10:58:56 PM UTC 24 |
25365200959 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_sensor_ctrl_alert.4029870159 |
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Aug 25 10:46:42 PM UTC 24 |
Aug 25 11:00:10 PM UTC 24 |
4868063742 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1022024720 |
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Aug 25 10:37:53 PM UTC 24 |
Aug 25 11:00:25 PM UTC 24 |
8981059027 ps |