| T2513 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke.520629265 |
|
|
Aug 25 05:35:20 PM UTC 24 |
Aug 25 05:35:32 PM UTC 24 |
247173796 ps |
| T2514 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_unmapped_addr.3633502704 |
|
|
Aug 25 05:34:51 PM UTC 24 |
Aug 25 05:35:33 PM UTC 24 |
573819210 ps |
| T2515 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_large_delays.15460832 |
|
|
Aug 25 05:34:38 PM UTC 24 |
Aug 25 05:35:36 PM UTC 24 |
3301507330 ps |
| T2516 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1410803713 |
|
|
Aug 25 05:34:53 PM UTC 24 |
Aug 25 05:35:41 PM UTC 24 |
798706335 ps |
| T2517 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_zero_delays.696131728 |
|
|
Aug 25 05:35:32 PM UTC 24 |
Aug 25 05:35:43 PM UTC 24 |
41029174 ps |
| T2518 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_error_random.2362745924 |
|
|
Aug 25 05:34:51 PM UTC 24 |
Aug 25 05:35:43 PM UTC 24 |
1356558073 ps |
| T2519 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_error.4191124075 |
|
|
Aug 25 05:34:07 PM UTC 24 |
Aug 25 05:35:47 PM UTC 24 |
1268437417 ps |
| T2520 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device.200907196 |
|
|
Aug 25 05:34:46 PM UTC 24 |
Aug 25 05:35:50 PM UTC 24 |
470281159 ps |
| T2521 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1199829300 |
|
|
Aug 25 05:19:53 PM UTC 24 |
Aug 25 05:36:00 PM UTC 24 |
12701419897 ps |
| T2522 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3737525573 |
|
|
Aug 25 05:26:45 PM UTC 24 |
Aug 25 05:36:12 PM UTC 24 |
1008442782 ps |
| T2523 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_access_same_device.2220982423 |
|
|
Aug 25 05:33:56 PM UTC 24 |
Aug 25 05:36:25 PM UTC 24 |
2855570278 ps |
| T2524 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device.2095344242 |
|
|
Aug 25 05:33:01 PM UTC 24 |
Aug 25 05:36:26 PM UTC 24 |
3228128857 ps |
| T2525 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_access_same_device.455413934 |
|
|
Aug 25 05:36:00 PM UTC 24 |
Aug 25 05:36:34 PM UTC 24 |
392502278 ps |
| T2526 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_same_source.3221240471 |
|
|
Aug 25 05:36:07 PM UTC 24 |
Aug 25 05:36:38 PM UTC 24 |
208869868 ps |
| T2527 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_unmapped_addr.1101894187 |
|
|
Aug 25 05:36:12 PM UTC 24 |
Aug 25 05:36:39 PM UTC 24 |
155793253 ps |
| T2528 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_zero_delays.1667981062 |
|
|
Aug 25 05:35:51 PM UTC 24 |
Aug 25 05:36:50 PM UTC 24 |
406119458 ps |
| T2529 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.683857552 |
|
|
Aug 25 05:36:35 PM UTC 24 |
Aug 25 05:36:51 PM UTC 24 |
8215106 ps |
| T2530 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.522132542 |
|
|
Aug 25 05:34:19 PM UTC 24 |
Aug 25 05:36:51 PM UTC 24 |
6413556911 ps |
| T2531 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.4259222035 |
|
|
Aug 25 05:36:13 PM UTC 24 |
Aug 25 05:37:01 PM UTC 24 |
308240353 ps |
| T2532 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_error_random.4249992537 |
|
|
Aug 25 05:36:07 PM UTC 24 |
Aug 25 05:37:07 PM UTC 24 |
480913566 ps |
| T2533 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke.1028060134 |
|
|
Aug 25 05:36:59 PM UTC 24 |
Aug 25 05:37:10 PM UTC 24 |
43915022 ps |
| T2534 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_large_delays.1700559778 |
|
|
Aug 25 05:35:34 PM UTC 24 |
Aug 25 05:37:10 PM UTC 24 |
7676274593 ps |
| T2535 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2310996392 |
|
|
Aug 25 05:37:02 PM UTC 24 |
Aug 25 05:37:13 PM UTC 24 |
40458713 ps |
| T2536 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all.933231203 |
|
|
Aug 25 05:33:12 PM UTC 24 |
Aug 25 05:37:20 PM UTC 24 |
4523679550 ps |
| T2537 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_smoke_large_delays.1094617559 |
|
|
Aug 25 05:34:12 PM UTC 24 |
Aug 25 05:37:28 PM UTC 24 |
10289731205 ps |
| T2538 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2571331333 |
|
|
Aug 25 05:35:39 PM UTC 24 |
Aug 25 05:37:38 PM UTC 24 |
4699169287 ps |
| T2539 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_zero_delays.3879401934 |
|
|
Aug 25 05:37:17 PM UTC 24 |
Aug 25 05:37:46 PM UTC 24 |
168530319 ps |
| T2540 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1526030340 |
|
|
Aug 25 05:33:19 PM UTC 24 |
Aug 25 05:37:52 PM UTC 24 |
325555252 ps |
| T2541 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_error.742809701 |
|
|
Aug 25 05:33:20 PM UTC 24 |
Aug 25 05:37:59 PM UTC 24 |
4902441687 ps |
| T2542 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all.1703272486 |
|
|
Aug 25 05:34:51 PM UTC 24 |
Aug 25 05:38:01 PM UTC 24 |
1481708637 ps |
| T2543 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3261463102 |
|
|
Aug 25 05:29:47 PM UTC 24 |
Aug 25 05:38:02 PM UTC 24 |
6302261737 ps |
| T2544 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.240731712 |
|
|
Aug 25 05:33:04 PM UTC 24 |
Aug 25 05:38:06 PM UTC 24 |
12954085141 ps |
| T2545 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_access_same_device.2983450151 |
|
|
Aug 25 05:37:35 PM UTC 24 |
Aug 25 05:38:09 PM UTC 24 |
323530435 ps |
| T2546 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_same_source.345460713 |
|
|
Aug 25 05:37:39 PM UTC 24 |
Aug 25 05:38:14 PM UTC 24 |
790329141 ps |
| T2547 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random.1774943117 |
|
|
Aug 25 05:35:47 PM UTC 24 |
Aug 25 05:38:15 PM UTC 24 |
2571341622 ps |
| T2548 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random.1052544212 |
|
|
Aug 25 05:37:14 PM UTC 24 |
Aug 25 05:38:16 PM UTC 24 |
551031060 ps |
| T2549 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all.2552354777 |
|
|
Aug 25 05:34:05 PM UTC 24 |
Aug 25 05:38:19 PM UTC 24 |
2906312335 ps |
| T2550 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_unmapped_addr.1337083664 |
|
|
Aug 25 05:37:53 PM UTC 24 |
Aug 25 05:38:20 PM UTC 24 |
417314350 ps |
| T2551 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_slow_rsp.1814462499 |
|
|
Aug 25 05:20:42 PM UTC 24 |
Aug 25 05:38:24 PM UTC 24 |
46229375543 ps |
| T2552 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_large_delays.820756656 |
|
|
Aug 25 05:33:48 PM UTC 24 |
Aug 25 05:38:39 PM UTC 24 |
16613472854 ps |
| T2553 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3469604909 |
|
|
Aug 25 05:38:31 PM UTC 24 |
Aug 25 05:38:40 PM UTC 24 |
45387217 ps |
| T2554 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke.2672061190 |
|
|
Aug 25 05:38:27 PM UTC 24 |
Aug 25 05:38:42 PM UTC 24 |
194300719 ps |
| T2555 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.4206230219 |
|
|
Aug 25 05:23:29 PM UTC 24 |
Aug 25 05:38:43 PM UTC 24 |
9309695164 ps |
| T2556 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2135387492 |
|
|
Aug 25 05:38:03 PM UTC 24 |
Aug 25 05:38:43 PM UTC 24 |
581863186 ps |
| T2557 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_random_slow_rsp.1257988506 |
|
|
Aug 25 05:31:31 PM UTC 24 |
Aug 25 05:38:44 PM UTC 24 |
20493466913 ps |
| T2558 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_error_random.3996829582 |
|
|
Aug 25 05:37:45 PM UTC 24 |
Aug 25 05:38:53 PM UTC 24 |
1385478635 ps |
| T2559 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_zero_delays.1745235913 |
|
|
Aug 25 05:38:40 PM UTC 24 |
Aug 25 05:39:07 PM UTC 24 |
159639121 ps |
| T2560 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all.1598089822 |
|
|
Aug 25 05:38:11 PM UTC 24 |
Aug 25 05:39:07 PM UTC 24 |
1086930909 ps |
| T2561 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_large_delays.275871756 |
|
|
Aug 25 05:37:05 PM UTC 24 |
Aug 25 05:39:10 PM UTC 24 |
7865799699 ps |
| T2562 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_stress_all_with_error.3858177457 |
|
|
Aug 25 05:31:10 PM UTC 24 |
Aug 25 05:39:10 PM UTC 24 |
3865866557 ps |
| T2563 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2512003812 |
|
|
Aug 25 05:37:15 PM UTC 24 |
Aug 25 05:39:13 PM UTC 24 |
4729933115 ps |
| T2564 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_access_same_device.155863019 |
|
|
Aug 25 05:38:47 PM UTC 24 |
Aug 25 05:39:38 PM UTC 24 |
462407671 ps |
| T2565 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random.571696668 |
|
|
Aug 25 05:38:38 PM UTC 24 |
Aug 25 05:39:39 PM UTC 24 |
1109906336 ps |
| T2566 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_unmapped_addr.3717729044 |
|
|
Aug 25 05:39:08 PM UTC 24 |
Aug 25 05:39:41 PM UTC 24 |
392703892 ps |
| T2567 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke.1013853007 |
|
|
Aug 25 05:39:34 PM UTC 24 |
Aug 25 05:39:46 PM UTC 24 |
45571217 ps |
| T2568 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2875852566 |
|
|
Aug 25 05:39:34 PM UTC 24 |
Aug 25 05:39:46 PM UTC 24 |
47709083 ps |
| T2569 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2118766571 |
|
|
Aug 25 05:39:07 PM UTC 24 |
Aug 25 05:39:47 PM UTC 24 |
786391973 ps |
| T2570 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_error.1309634098 |
|
|
Aug 25 05:36:50 PM UTC 24 |
Aug 25 05:40:03 PM UTC 24 |
3980291718 ps |
| T2571 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_error_random.2519303541 |
|
|
Aug 25 05:39:07 PM UTC 24 |
Aug 25 05:40:06 PM UTC 24 |
497561087 ps |
| T2572 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all.2145077918 |
|
|
Aug 25 05:39:09 PM UTC 24 |
Aug 25 05:40:13 PM UTC 24 |
1351235059 ps |
| T2573 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/71.xbar_random_large_delays.3939983359 |
|
|
Aug 25 05:24:03 PM UTC 24 |
Aug 25 05:40:21 PM UTC 24 |
59928608804 ps |
| T2574 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random.3410515289 |
|
|
Aug 25 05:40:02 PM UTC 24 |
Aug 25 05:40:23 PM UTC 24 |
297095326 ps |
| T2575 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_large_delays.3963820883 |
|
|
Aug 25 05:33:01 PM UTC 24 |
Aug 25 05:40:27 PM UTC 24 |
27712032470 ps |
| T2576 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_zero_delays.3261571838 |
|
|
Aug 25 05:40:05 PM UTC 24 |
Aug 25 05:40:27 PM UTC 24 |
126545081 ps |
| T2577 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_random_slow_rsp.669445819 |
|
|
Aug 25 05:35:58 PM UTC 24 |
Aug 25 05:40:34 PM UTC 24 |
10162991599 ps |
| T2578 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3837707867 |
|
|
Aug 25 05:29:44 PM UTC 24 |
Aug 25 05:40:42 PM UTC 24 |
7735298613 ps |
| T2579 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.126477505 |
|
|
Aug 25 05:38:26 PM UTC 24 |
Aug 25 05:40:50 PM UTC 24 |
290632888 ps |
| T2580 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2556946617 |
|
|
Aug 25 05:21:25 PM UTC 24 |
Aug 25 05:40:53 PM UTC 24 |
20921478336 ps |
| T2581 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_same_source.3147247606 |
|
|
Aug 25 05:39:05 PM UTC 24 |
Aug 25 05:40:55 PM UTC 24 |
2316047696 ps |
| T2582 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3761105388 |
|
|
Aug 25 05:38:18 PM UTC 24 |
Aug 25 05:40:57 PM UTC 24 |
192203238 ps |
| T2583 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1865043459 |
|
|
Aug 25 05:38:39 PM UTC 24 |
Aug 25 05:40:57 PM UTC 24 |
5885301432 ps |
| T2584 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_access_same_device.2360013697 |
|
|
Aug 25 05:40:12 PM UTC 24 |
Aug 25 05:41:01 PM UTC 24 |
437626140 ps |
| T2585 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.452648770 |
|
|
Aug 25 05:32:20 PM UTC 24 |
Aug 25 05:41:04 PM UTC 24 |
3003841906 ps |
| T2586 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2507215869 |
|
|
Aug 25 05:40:45 PM UTC 24 |
Aug 25 05:41:16 PM UTC 24 |
161464019 ps |
| T2587 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.83920327 |
|
|
Aug 25 05:28:51 PM UTC 24 |
Aug 25 05:41:17 PM UTC 24 |
5987791150 ps |
| T2588 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_unmapped_addr.212886554 |
|
|
Aug 25 05:40:45 PM UTC 24 |
Aug 25 05:41:18 PM UTC 24 |
172439335 ps |
| T2589 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke.1820815352 |
|
|
Aug 25 05:41:12 PM UTC 24 |
Aug 25 05:41:23 PM UTC 24 |
44054443 ps |
| T2590 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all.1260272096 |
|
|
Aug 25 05:36:25 PM UTC 24 |
Aug 25 05:41:24 PM UTC 24 |
3257534972 ps |
| T2591 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_smoke_large_delays.3047188220 |
|
|
Aug 25 05:38:34 PM UTC 24 |
Aug 25 05:41:27 PM UTC 24 |
9651991377 ps |
| T2592 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_zero_delays.622268447 |
|
|
Aug 25 05:41:17 PM UTC 24 |
Aug 25 05:41:28 PM UTC 24 |
47605214 ps |
| T2593 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke.1808262727 |
|
|
Aug 25 05:45:36 PM UTC 24 |
Aug 25 05:45:50 PM UTC 24 |
172120450 ps |
| T2594 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3077509815 |
|
|
Aug 25 05:29:35 PM UTC 24 |
Aug 25 05:41:31 PM UTC 24 |
27250643345 ps |
| T2595 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random.1503500190 |
|
|
Aug 25 05:41:20 PM UTC 24 |
Aug 25 05:41:32 PM UTC 24 |
137120223 ps |
| T2596 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3340257502 |
|
|
Aug 25 05:33:22 PM UTC 24 |
Aug 25 05:41:46 PM UTC 24 |
3765976232 ps |
| T2597 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_random_zero_delays.3843073389 |
|
|
Aug 25 05:41:26 PM UTC 24 |
Aug 25 05:41:47 PM UTC 24 |
106026135 ps |
| T2598 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_error_random.2415683095 |
|
|
Aug 25 05:40:36 PM UTC 24 |
Aug 25 05:41:52 PM UTC 24 |
1480226290 ps |
| T2599 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device.2921386587 |
|
|
Aug 25 05:41:41 PM UTC 24 |
Aug 25 05:41:56 PM UTC 24 |
149921747 ps |
| T2600 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_large_delays.2504228411 |
|
|
Aug 25 05:39:38 PM UTC 24 |
Aug 25 05:42:00 PM UTC 24 |
8163681441 ps |
| T2601 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2299796229 |
|
|
Aug 25 05:41:52 PM UTC 24 |
Aug 25 05:42:01 PM UTC 24 |
20634391 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_error.1353532847 |
|
|
Aug 25 05:35:14 PM UTC 24 |
Aug 25 05:42:07 PM UTC 24 |
3834351149 ps |
| T2602 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_same_source.4071957216 |
|
|
Aug 25 05:41:45 PM UTC 24 |
Aug 25 05:42:10 PM UTC 24 |
553387025 ps |
| T2603 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.341509478 |
|
|
Aug 25 05:40:03 PM UTC 24 |
Aug 25 05:42:12 PM UTC 24 |
4517259848 ps |
| T2604 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_same_source.350736527 |
|
|
Aug 25 05:40:30 PM UTC 24 |
Aug 25 05:42:14 PM UTC 24 |
2177528178 ps |
| T2605 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_unmapped_addr.3161664007 |
|
|
Aug 25 05:41:51 PM UTC 24 |
Aug 25 05:42:24 PM UTC 24 |
428675111 ps |
| T2606 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/65.xbar_random_large_delays.3990417294 |
|
|
Aug 25 05:15:35 PM UTC 24 |
Aug 25 05:42:26 PM UTC 24 |
94267518338 ps |
| T2607 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_stress_all_with_error.225812730 |
|
|
Aug 25 05:38:24 PM UTC 24 |
Aug 25 05:42:26 PM UTC 24 |
2145317787 ps |
| T2608 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3755255428 |
|
|
Aug 25 05:42:16 PM UTC 24 |
Aug 25 05:42:27 PM UTC 24 |
38709954 ps |
| T2609 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke.440039462 |
|
|
Aug 25 05:42:14 PM UTC 24 |
Aug 25 05:42:30 PM UTC 24 |
230685135 ps |
| T2610 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2143136089 |
|
|
Aug 25 05:41:06 PM UTC 24 |
Aug 25 05:42:37 PM UTC 24 |
143163078 ps |
| T2611 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3401930525 |
|
|
Aug 25 05:42:12 PM UTC 24 |
Aug 25 05:42:37 PM UTC 24 |
7905523 ps |
| T2612 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_random_large_delays.2588228771 |
|
|
Aug 25 05:27:13 PM UTC 24 |
Aug 25 05:43:03 PM UTC 24 |
56913639597 ps |
| T2613 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_large_delays.707379609 |
|
|
Aug 25 05:40:10 PM UTC 24 |
Aug 25 05:43:14 PM UTC 24 |
11508207250 ps |
| T2614 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_zero_delays.867537784 |
|
|
Aug 25 05:42:35 PM UTC 24 |
Aug 25 05:43:15 PM UTC 24 |
243214259 ps |
| T2615 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_random_slow_rsp.3898802213 |
|
|
Aug 25 05:40:11 PM UTC 24 |
Aug 25 05:43:20 PM UTC 24 |
8136134967 ps |
| T2616 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/75.xbar_random_slow_rsp.1979857077 |
|
|
Aug 25 05:28:17 PM UTC 24 |
Aug 25 05:43:25 PM UTC 24 |
39986340920 ps |
| T2617 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_error_random.364655682 |
|
|
Aug 25 05:41:49 PM UTC 24 |
Aug 25 05:43:29 PM UTC 24 |
2642448403 ps |
| T2618 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_random.3047482434 |
|
|
Aug 25 05:42:52 PM UTC 24 |
Aug 25 05:43:30 PM UTC 24 |
639818585 ps |
| T2619 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_large_delays.2013071046 |
|
|
Aug 25 05:41:20 PM UTC 24 |
Aug 25 05:43:34 PM UTC 24 |
7425947850 ps |
| T2620 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/67.xbar_random_large_delays.3517627533 |
|
|
Aug 25 05:19:27 PM UTC 24 |
Aug 25 05:43:35 PM UTC 24 |
82827494477 ps |
| T2621 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random.2783710861 |
|
|
Aug 25 05:42:32 PM UTC 24 |
Aug 25 05:43:37 PM UTC 24 |
1161543189 ps |
| T2622 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3238835654 |
|
|
Aug 25 05:31:39 PM UTC 24 |
Aug 25 05:43:42 PM UTC 24 |
28371811601 ps |
| T2623 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3309656645 |
|
|
Aug 25 05:41:21 PM UTC 24 |
Aug 25 05:43:43 PM UTC 24 |
5267767902 ps |
| T2624 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.940213713 |
|
|
Aug 25 05:43:01 PM UTC 24 |
Aug 25 05:43:45 PM UTC 24 |
668290074 ps |
| T2625 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_random_large_delays.2634824562 |
|
|
Aug 25 05:38:43 PM UTC 24 |
Aug 25 05:43:46 PM UTC 24 |
18847098857 ps |
| T2626 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/78.xbar_stress_all.1912058312 |
|
|
Aug 25 05:32:05 PM UTC 24 |
Aug 25 05:43:50 PM UTC 24 |
11930235930 ps |
| T2627 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_unmapped_addr.1619012867 |
|
|
Aug 25 05:42:55 PM UTC 24 |
Aug 25 05:43:52 PM UTC 24 |
983764772 ps |
| T2628 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3574552252 |
|
|
Aug 25 04:57:23 PM UTC 24 |
Aug 25 05:43:56 PM UTC 24 |
110639071932 ps |
| T2629 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_same_source.134563154 |
|
|
Aug 25 05:42:52 PM UTC 24 |
Aug 25 05:43:59 PM UTC 24 |
1293909371 ps |
| T2630 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2026389107 |
|
|
Aug 25 05:43:48 PM UTC 24 |
Aug 25 05:44:00 PM UTC 24 |
57561455 ps |
| T2631 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke.2550294388 |
|
|
Aug 25 05:43:44 PM UTC 24 |
Aug 25 05:44:00 PM UTC 24 |
211695380 ps |
| T2632 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1853133852 |
|
|
Aug 25 05:36:51 PM UTC 24 |
Aug 25 05:44:17 PM UTC 24 |
7056838373 ps |
| T2633 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_large_delays.3597924918 |
|
|
Aug 25 05:42:25 PM UTC 24 |
Aug 25 05:44:24 PM UTC 24 |
7353054550 ps |
| T2634 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_random.3732511080 |
|
|
Aug 25 05:44:15 PM UTC 24 |
Aug 25 05:44:25 PM UTC 24 |
36096528 ps |
| T2635 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/76.xbar_random_large_delays.781996817 |
|
|
Aug 25 05:29:23 PM UTC 24 |
Aug 25 05:44:27 PM UTC 24 |
49881321430 ps |
| T2636 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_same_source.379195381 |
|
|
Aug 25 05:44:10 PM UTC 24 |
Aug 25 05:44:30 PM UTC 24 |
133853898 ps |
| T2637 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1826868166 |
|
|
Aug 25 05:42:24 PM UTC 24 |
Aug 25 05:44:31 PM UTC 24 |
5533635056 ps |
| T2638 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1638667386 |
|
|
Aug 25 05:44:21 PM UTC 24 |
Aug 25 05:44:32 PM UTC 24 |
116359885 ps |
| T2639 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all.3443351660 |
|
|
Aug 25 05:41:53 PM UTC 24 |
Aug 25 05:44:34 PM UTC 24 |
1207582552 ps |
| T2640 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_unmapped_addr.610286386 |
|
|
Aug 25 05:44:17 PM UTC 24 |
Aug 25 05:44:36 PM UTC 24 |
169458143 ps |
| T2641 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device.1437157235 |
|
|
Aug 25 05:42:50 PM UTC 24 |
Aug 25 05:44:41 PM UTC 24 |
996546666 ps |
| T2642 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/83.xbar_random_slow_rsp.2680078155 |
|
|
Aug 25 05:37:31 PM UTC 24 |
Aug 25 05:44:44 PM UTC 24 |
16595365962 ps |
| T2643 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/79.xbar_random_slow_rsp.915751984 |
|
|
Aug 25 05:33:00 PM UTC 24 |
Aug 25 05:44:53 PM UTC 24 |
29462032398 ps |
| T2644 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all.299730634 |
|
|
Aug 25 05:40:51 PM UTC 24 |
Aug 25 05:44:58 PM UTC 24 |
1976129851 ps |
| T2645 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_large_delays.2433942445 |
|
|
Aug 25 05:25:14 PM UTC 24 |
Aug 25 05:45:00 PM UTC 24 |
77897296714 ps |
| T2646 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_zero_delays.719379019 |
|
|
Aug 25 05:44:49 PM UTC 24 |
Aug 25 05:45:00 PM UTC 24 |
40476798 ps |
| T2647 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/64.xbar_random_large_delays.3866008292 |
|
|
Aug 25 05:13:52 PM UTC 24 |
Aug 25 05:45:03 PM UTC 24 |
106861388889 ps |
| T2648 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke.1997249697 |
|
|
Aug 25 05:44:49 PM UTC 24 |
Aug 25 05:45:04 PM UTC 24 |
201256885 ps |
| T2649 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_random_slow_rsp.4033499956 |
|
|
Aug 25 05:33:53 PM UTC 24 |
Aug 25 05:45:06 PM UTC 24 |
31587413132 ps |
| T2650 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_access_same_device.2866686400 |
|
|
Aug 25 05:44:07 PM UTC 24 |
Aug 25 05:45:07 PM UTC 24 |
855875335 ps |
| T2651 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_zero_delays.3331003254 |
|
|
Aug 25 05:44:00 PM UTC 24 |
Aug 25 05:45:12 PM UTC 24 |
485565631 ps |
| T2652 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_zero_delays.2121843643 |
|
|
Aug 25 05:44:56 PM UTC 24 |
Aug 25 05:45:13 PM UTC 24 |
78593225 ps |
| T2653 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_slow_rsp.230569210 |
|
|
Aug 25 05:30:49 PM UTC 24 |
Aug 25 05:45:20 PM UTC 24 |
39830128148 ps |
| T2654 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.517556080 |
|
|
Aug 25 05:25:22 PM UTC 24 |
Aug 25 05:45:23 PM UTC 24 |
48299408579 ps |
| T2655 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3251776678 |
|
|
Aug 25 05:45:26 PM UTC 24 |
Aug 25 05:45:41 PM UTC 24 |
151356088 ps |
| T2656 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_large_delays.2399681578 |
|
|
Aug 25 05:43:55 PM UTC 24 |
Aug 25 05:45:42 PM UTC 24 |
6828632776 ps |
| T2657 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2885208518 |
|
|
Aug 25 05:35:02 PM UTC 24 |
Aug 25 05:45:45 PM UTC 24 |
9691521109 ps |
| T2658 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_random_slow_rsp.467701627 |
|
|
Aug 25 05:34:39 PM UTC 24 |
Aug 25 05:45:47 PM UTC 24 |
33567412931 ps |
| T2659 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_aliasing.1182433719 |
|
|
Aug 25 03:31:44 PM UTC 24 |
Aug 25 05:45:48 PM UTC 24 |
29648560531 ps |
| T2660 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1008136296 |
|
|
Aug 25 05:45:37 PM UTC 24 |
Aug 25 05:45:49 PM UTC 24 |
46073223 ps |
| T2661 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_error_random.1933242965 |
|
|
Aug 25 05:45:23 PM UTC 24 |
Aug 25 05:45:49 PM UTC 24 |
461362159 ps |
| T2662 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.4107264772 |
|
|
Aug 25 05:34:06 PM UTC 24 |
Aug 25 05:45:49 PM UTC 24 |
9396874050 ps |
| T2663 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all_with_error.1582413518 |
|
|
Aug 25 05:43:38 PM UTC 24 |
Aug 25 05:46:08 PM UTC 24 |
2765274781 ps |
| T2664 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_unmapped_addr.1403981905 |
|
|
Aug 25 05:45:25 PM UTC 24 |
Aug 25 05:46:09 PM UTC 24 |
676969208 ps |
| T2665 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_stress_all_with_error.844540785 |
|
|
Aug 25 05:42:12 PM UTC 24 |
Aug 25 05:46:14 PM UTC 24 |
5004669238 ps |
| T2666 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random.287162161 |
|
|
Aug 25 05:43:58 PM UTC 24 |
Aug 25 05:46:16 PM UTC 24 |
2579745136 ps |
| T2667 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.758056409 |
|
|
Aug 25 05:39:18 PM UTC 24 |
Aug 25 05:46:20 PM UTC 24 |
3886424341 ps |
| T2668 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random.1981346100 |
|
|
Aug 25 05:44:57 PM UTC 24 |
Aug 25 05:46:23 PM UTC 24 |
1511260504 ps |
| T2669 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random_zero_delays.1649075098 |
|
|
Aug 25 05:46:05 PM UTC 24 |
Aug 25 05:46:23 PM UTC 24 |
87339014 ps |
| T2670 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_same_source.3518366518 |
|
|
Aug 25 05:45:18 PM UTC 24 |
Aug 25 05:46:24 PM UTC 24 |
1493199867 ps |
| T2671 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_same_source.943275609 |
|
|
Aug 25 05:46:14 PM UTC 24 |
Aug 25 05:46:31 PM UTC 24 |
226839369 ps |
| T2672 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1302482496 |
|
|
Aug 25 05:43:55 PM UTC 24 |
Aug 25 05:46:33 PM UTC 24 |
6321006194 ps |
| T2673 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_large_delays.2322523640 |
|
|
Aug 25 05:44:52 PM UTC 24 |
Aug 25 05:46:36 PM UTC 24 |
6162942416 ps |
| T2674 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2049470648 |
|
|
Aug 25 05:03:05 PM UTC 24 |
Aug 25 05:46:47 PM UTC 24 |
113470835823 ps |
| T2675 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_unmapped_addr.2361177197 |
|
|
Aug 25 05:46:14 PM UTC 24 |
Aug 25 05:46:52 PM UTC 24 |
514474133 ps |
| T2676 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.4069249696 |
|
|
Aug 25 04:49:38 PM UTC 24 |
Aug 25 05:46:55 PM UTC 24 |
147842002598 ps |
| T2677 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2901820884 |
|
|
Aug 25 05:46:46 PM UTC 24 |
Aug 25 05:46:56 PM UTC 24 |
57873467 ps |
| T2678 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1111903449 |
|
|
Aug 25 05:46:32 PM UTC 24 |
Aug 25 05:46:57 PM UTC 24 |
167119865 ps |
| T2679 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke.1806465902 |
|
|
Aug 25 05:46:46 PM UTC 24 |
Aug 25 05:46:58 PM UTC 24 |
41785753 ps |
| T2680 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_access_same_device.2999425025 |
|
|
Aug 25 05:45:06 PM UTC 24 |
Aug 25 05:47:03 PM UTC 24 |
2197228122 ps |
| T2681 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random.2277218962 |
|
|
Aug 25 05:46:57 PM UTC 24 |
Aug 25 05:47:07 PM UTC 24 |
23345925 ps |
| T2682 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_large_delays.282375261 |
|
|
Aug 25 05:45:45 PM UTC 24 |
Aug 25 05:47:12 PM UTC 24 |
5337044785 ps |
| T2683 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_zero_delays.1234010292 |
|
|
Aug 25 05:47:00 PM UTC 24 |
Aug 25 05:47:23 PM UTC 24 |
161486261 ps |
| T2684 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_error_random.315614095 |
|
|
Aug 25 05:46:10 PM UTC 24 |
Aug 25 05:47:26 PM UTC 24 |
1873951690 ps |
| T2685 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.364190004 |
|
|
Aug 25 05:44:55 PM UTC 24 |
Aug 25 05:47:28 PM UTC 24 |
6394510996 ps |
| T2686 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/73.xbar_random_large_delays.1502084132 |
|
|
Aug 25 05:26:15 PM UTC 24 |
Aug 25 05:47:34 PM UTC 24 |
85240497855 ps |
| T2687 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_stress_all.3100653472 |
|
|
Aug 25 05:43:01 PM UTC 24 |
Aug 25 05:47:37 PM UTC 24 |
2562483309 ps |
| T2688 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_same_source.1208487805 |
|
|
Aug 25 05:47:22 PM UTC 24 |
Aug 25 05:47:48 PM UTC 24 |
445034239 ps |
| T2689 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3498979902 |
|
|
Aug 25 05:47:46 PM UTC 24 |
Aug 25 05:47:54 PM UTC 24 |
8361642 ps |
| T2690 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_unmapped_addr.1500483642 |
|
|
Aug 25 05:47:26 PM UTC 24 |
Aug 25 05:47:55 PM UTC 24 |
158773629 ps |
| T2691 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_large_delays.3888520122 |
|
|
Aug 25 05:42:37 PM UTC 24 |
Aug 25 05:47:56 PM UTC 24 |
18465303787 ps |
| T2692 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2577668816 |
|
|
Aug 25 05:47:31 PM UTC 24 |
Aug 25 05:47:58 PM UTC 24 |
465933022 ps |
| T2693 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_error_random.3658561248 |
|
|
Aug 25 05:47:22 PM UTC 24 |
Aug 25 05:48:03 PM UTC 24 |
842719753 ps |
| T2694 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1479012633 |
|
|
Aug 25 05:39:31 PM UTC 24 |
Aug 25 05:48:10 PM UTC 24 |
5128463933 ps |
| T2695 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.471364323 |
|
|
Aug 25 05:27:51 PM UTC 24 |
Aug 25 05:48:12 PM UTC 24 |
17647359316 ps |
| T2696 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1347309052 |
|
|
Aug 25 05:48:01 PM UTC 24 |
Aug 25 05:48:13 PM UTC 24 |
50949146 ps |
| T2697 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.25897512 |
|
|
Aug 25 05:18:03 PM UTC 24 |
Aug 25 05:48:15 PM UTC 24 |
74599253903 ps |
| T2698 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke.929967837 |
|
|
Aug 25 05:47:57 PM UTC 24 |
Aug 25 05:48:16 PM UTC 24 |
272530022 ps |
| T2699 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2398582490 |
|
|
Aug 25 05:45:48 PM UTC 24 |
Aug 25 05:48:20 PM UTC 24 |
6400842315 ps |
| T2700 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_random.1323990776 |
|
|
Aug 25 05:46:01 PM UTC 24 |
Aug 25 05:48:25 PM UTC 24 |
2336902368 ps |
| T2701 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_access_same_device.3714841107 |
|
|
Aug 25 05:46:09 PM UTC 24 |
Aug 25 05:48:29 PM UTC 24 |
2127001176 ps |
| T2702 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_large_delays.4036373375 |
|
|
Aug 25 05:46:48 PM UTC 24 |
Aug 25 05:48:33 PM UTC 24 |
5403715113 ps |
| T2703 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.856019496 |
|
|
Aug 25 05:42:50 PM UTC 24 |
Aug 25 05:48:48 PM UTC 24 |
15990953376 ps |
| T2704 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3137708348 |
|
|
Aug 25 05:04:27 PM UTC 24 |
Aug 25 05:48:51 PM UTC 24 |
109068856886 ps |
| T2705 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random.4058368801 |
|
|
Aug 25 05:48:20 PM UTC 24 |
Aug 25 05:48:55 PM UTC 24 |
253560730 ps |
| T2706 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_unmapped_addr.904476881 |
|
|
Aug 25 05:48:39 PM UTC 24 |
Aug 25 05:48:59 PM UTC 24 |
272600982 ps |
| T2707 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2550241857 |
|
|
Aug 25 05:46:41 PM UTC 24 |
Aug 25 05:49:03 PM UTC 24 |
276593628 ps |
| T2708 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_access_same_device.2719705188 |
|
|
Aug 25 05:47:20 PM UTC 24 |
Aug 25 05:49:08 PM UTC 24 |
2006958808 ps |
| T2709 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_access_same_device.774708388 |
|
|
Aug 25 05:48:34 PM UTC 24 |
Aug 25 05:49:09 PM UTC 24 |
214101861 ps |
| T2710 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_random.459075321 |
|
|
Aug 25 05:48:39 PM UTC 24 |
Aug 25 05:49:10 PM UTC 24 |
544250649 ps |
| T2711 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1886290563 |
|
|
Aug 25 05:00:00 PM UTC 24 |
Aug 25 05:49:15 PM UTC 24 |
114706450368 ps |
| T2712 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_same_source.3303277979 |
|
|
Aug 25 05:48:37 PM UTC 24 |
Aug 25 05:49:16 PM UTC 24 |
713117756 ps |
| T2713 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1616524959 |
|
|
Aug 25 05:46:55 PM UTC 24 |
Aug 25 05:49:21 PM UTC 24 |
5752961102 ps |
| T2714 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_random_zero_delays.3469725920 |
|
|
Aug 25 05:48:20 PM UTC 24 |
Aug 25 05:49:23 PM UTC 24 |
432858912 ps |
| T2715 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3176986433 |
|
|
Aug 25 05:23:17 PM UTC 24 |
Aug 25 05:49:24 PM UTC 24 |
72633043961 ps |
| T2716 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1589256395 |
|
|
Aug 25 05:34:04 PM UTC 24 |
Aug 25 05:49:26 PM UTC 24 |
6407335129 ps |
| T2717 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke.2633975036 |
|
|
Aug 25 05:49:15 PM UTC 24 |
Aug 25 05:49:27 PM UTC 24 |
45324509 ps |
| T2718 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2838110138 |
|
|
Aug 25 05:49:19 PM UTC 24 |
Aug 25 05:49:29 PM UTC 24 |
48727280 ps |
| T2719 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.371244924 |
|
|
Aug 25 05:48:40 PM UTC 24 |
Aug 25 05:49:29 PM UTC 24 |
922571784 ps |
| T2720 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.477896784 |
|
|
Aug 25 05:35:18 PM UTC 24 |
Aug 25 05:49:36 PM UTC 24 |
4359521636 ps |
| T2721 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.917861123 |
|
|
Aug 25 05:45:31 PM UTC 24 |
Aug 25 05:49:47 PM UTC 24 |
405545084 ps |
| T2722 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random.2926923659 |
|
|
Aug 25 05:49:31 PM UTC 24 |
Aug 25 05:49:47 PM UTC 24 |
231897684 ps |
| T2723 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/84.xbar_stress_all_with_error.2459666369 |
|
|
Aug 25 05:39:31 PM UTC 24 |
Aug 25 05:50:02 PM UTC 24 |
14123555520 ps |
| T2724 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.696865117 |
|
|
Aug 25 05:41:42 PM UTC 24 |
Aug 25 05:50:02 PM UTC 24 |
20364687088 ps |
| T2725 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.285511469 |
|
|
Aug 25 05:40:52 PM UTC 24 |
Aug 25 05:50:06 PM UTC 24 |
2250092398 ps |
| T2726 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2757999241 |
|
|
Aug 25 05:46:35 PM UTC 24 |
Aug 25 05:50:11 PM UTC 24 |
311039555 ps |
| T2727 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_random_zero_delays.1540770800 |
|
|
Aug 25 05:49:34 PM UTC 24 |
Aug 25 05:50:18 PM UTC 24 |
299676240 ps |
| T2728 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1056274703 |
|
|
Aug 25 05:49:52 PM UTC 24 |
Aug 25 05:50:20 PM UTC 24 |
488780548 ps |
| T2729 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/68.xbar_random_large_delays.3605557697 |
|
|
Aug 25 05:20:37 PM UTC 24 |
Aug 25 05:50:23 PM UTC 24 |
109267561829 ps |
| T2730 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke.524675633 |
|
|
Aug 25 05:50:12 PM UTC 24 |
Aug 25 05:50:25 PM UTC 24 |
153902697 ps |
| T2731 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3455339286 |
|
|
Aug 25 05:48:18 PM UTC 24 |
Aug 25 05:50:25 PM UTC 24 |
4805630874 ps |
| T2732 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_random_slow_rsp.1325372300 |
|
|
Aug 25 05:44:06 PM UTC 24 |
Aug 25 05:50:26 PM UTC 24 |
14659138368 ps |
| T2733 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_smoke_zero_delays.469882835 |
|
|
Aug 25 05:50:26 PM UTC 24 |
Aug 25 05:50:37 PM UTC 24 |
37381435 ps |
| T2734 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2535309826 |
|
|
Aug 25 05:50:11 PM UTC 24 |
Aug 25 05:50:43 PM UTC 24 |
110777383 ps |
| T2735 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_same_source.3728366912 |
|
|
Aug 25 05:49:46 PM UTC 24 |
Aug 25 05:50:45 PM UTC 24 |
1156704429 ps |
| T2736 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/92.xbar_smoke_large_delays.2069739335 |
|
|
Aug 25 05:48:11 PM UTC 24 |
Aug 25 05:50:49 PM UTC 24 |
10190606754 ps |
| T2737 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2962853795 |
|
|
Aug 25 05:34:47 PM UTC 24 |
Aug 25 05:50:50 PM UTC 24 |
44966347806 ps |
| T2738 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/97.xbar_random_zero_delays.3593703498 |
|
|
Aug 25 05:54:06 PM UTC 24 |
Aug 25 05:55:15 PM UTC 24 |
539040057 ps |
| T2739 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3175016840 |
|
|
Aug 25 05:44:41 PM UTC 24 |
Aug 25 05:50:58 PM UTC 24 |
1157065367 ps |
| T2740 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/87.xbar_random_slow_rsp.2576406497 |
|
|
Aug 25 05:42:39 PM UTC 24 |
Aug 25 05:50:59 PM UTC 24 |
19048052033 ps |
| T2741 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_access_same_device.1184851501 |
|
|
Aug 25 05:49:40 PM UTC 24 |
Aug 25 05:51:02 PM UTC 24 |
1648858513 ps |
| T2742 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all_with_error.4273208803 |
|
|
Aug 25 05:50:00 PM UTC 24 |
Aug 25 05:51:06 PM UTC 24 |
526927788 ps |
| T2743 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/89.xbar_random_slow_rsp.88987810 |
|
|
Aug 25 05:45:02 PM UTC 24 |
Aug 25 05:51:07 PM UTC 24 |
14177156530 ps |
| T2744 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_unmapped_addr.1435874824 |
|
|
Aug 25 05:49:49 PM UTC 24 |
Aug 25 05:51:15 PM UTC 24 |
1266431333 ps |
| T2745 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random.3280802217 |
|
|
Aug 25 05:50:36 PM UTC 24 |
Aug 25 05:51:16 PM UTC 24 |
260253009 ps |
| T2746 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.4220190800 |
|
|
Aug 25 05:51:09 PM UTC 24 |
Aug 25 05:51:18 PM UTC 24 |
25037683 ps |
| T2747 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_large_delays.3762578878 |
|
|
Aug 25 05:49:19 PM UTC 24 |
Aug 25 05:51:18 PM UTC 24 |
6928035891 ps |
| T2748 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_unmapped_addr.1723558838 |
|
|
Aug 25 05:51:08 PM UTC 24 |
Aug 25 05:51:29 PM UTC 24 |
227860028 ps |
| T2749 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_same_source.417796282 |
|
|
Aug 25 05:50:50 PM UTC 24 |
Aug 25 05:51:33 PM UTC 24 |
348602110 ps |
| T2750 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke.952342535 |
|
|
Aug 25 05:51:26 PM UTC 24 |
Aug 25 05:51:40 PM UTC 24 |
130942608 ps |
| T2751 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3290645449 |
|
|
Aug 25 05:51:32 PM UTC 24 |
Aug 25 05:51:43 PM UTC 24 |
47672189 ps |
| T2752 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1690001738 |
|
|
Aug 25 05:49:28 PM UTC 24 |
Aug 25 05:51:44 PM UTC 24 |
5743366378 ps |
| T2753 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_random_zero_delays.1390041541 |
|
|
Aug 25 05:50:43 PM UTC 24 |
Aug 25 05:51:44 PM UTC 24 |
460633113 ps |
| T2754 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_error_random.344224642 |
|
|
Aug 25 05:51:00 PM UTC 24 |
Aug 25 05:51:53 PM UTC 24 |
427124784 ps |
| T2755 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/88.xbar_stress_all.688068459 |
|
|
Aug 25 05:44:24 PM UTC 24 |
Aug 25 05:51:55 PM UTC 24 |
7660268836 ps |
| T2756 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_stress_all.2218064227 |
|
|
Aug 25 05:49:52 PM UTC 24 |
Aug 25 05:51:57 PM UTC 24 |
963584779 ps |
| T2757 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/93.xbar_error_random.2606038971 |
|
|
Aug 25 05:49:48 PM UTC 24 |
Aug 25 05:51:59 PM UTC 24 |
2442150718 ps |
| T2758 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3504126955 |
|
|
Aug 25 05:51:15 PM UTC 24 |
Aug 25 05:52:03 PM UTC 24 |
69496141 ps |
| T2759 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/91.xbar_random_slow_rsp.3486052841 |
|
|
Aug 25 05:47:17 PM UTC 24 |
Aug 25 05:52:08 PM UTC 24 |
12201713588 ps |
| T2760 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/77.xbar_random_large_delays.750980098 |
|
|
Aug 25 05:30:51 PM UTC 24 |
Aug 25 05:52:10 PM UTC 24 |
83799983055 ps |
| T2761 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/72.xbar_random_slow_rsp.1972751249 |
|
|
Aug 25 05:25:15 PM UTC 24 |
Aug 25 05:52:20 PM UTC 24 |
61318249826 ps |