| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_lc_ctrl_transition.170930016 |
|
|
Aug 25 10:39:25 PM UTC 24 |
Aug 25 11:00:41 PM UTC 24 |
10468235280 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_all_escalation_resets.1475073508 |
|
|
Aug 25 10:48:12 PM UTC 24 |
Aug 25 11:01:36 PM UTC 24 |
4445806740 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_data_integrity_escalation.1929057055 |
|
|
Aug 25 10:49:03 PM UTC 24 |
Aug 25 11:03:31 PM UTC 24 |
4773321100 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_power_virus.451523607 |
|
|
Aug 25 10:34:55 PM UTC 24 |
Aug 25 11:04:01 PM UTC 24 |
5537860848 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_lc_ctrl_transition.1580881832 |
|
|
Aug 25 10:56:03 PM UTC 24 |
Aug 25 11:04:17 PM UTC 24 |
6418144351 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1088198687 |
|
|
Aug 25 10:55:28 PM UTC 24 |
Aug 25 11:04:31 PM UTC 24 |
3610424152 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978170389 |
|
|
Aug 25 10:56:34 PM UTC 24 |
Aug 25 11:04:37 PM UTC 24 |
3626951084 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127195425 |
|
|
Aug 25 10:55:16 PM UTC 24 |
Aug 25 11:05:33 PM UTC 24 |
4532008756 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.1038004946 |
|
|
Aug 25 10:57:13 PM UTC 24 |
Aug 25 11:06:15 PM UTC 24 |
3762555316 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000813573 |
|
|
Aug 25 10:57:09 PM UTC 24 |
Aug 25 11:07:09 PM UTC 24 |
4006458170 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_all_escalation_resets.2111105051 |
|
|
Aug 25 10:54:11 PM UTC 24 |
Aug 25 11:07:39 PM UTC 24 |
5045358720 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_init_reduced_freq.2135729743 |
|
|
Aug 25 10:24:33 PM UTC 24 |
Aug 25 11:07:41 PM UTC 24 |
18287204864 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2878909623 |
|
|
Aug 25 10:59:53 PM UTC 24 |
Aug 25 11:07:43 PM UTC 24 |
3555442224 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_all_escalation_resets.372790120 |
|
|
Aug 25 10:52:02 PM UTC 24 |
Aug 25 11:07:46 PM UTC 24 |
5018141880 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817550248 |
|
|
Aug 25 10:58:33 PM UTC 24 |
Aug 25 11:08:11 PM UTC 24 |
3595833904 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_lc_ctrl_transition.1030971528 |
|
|
Aug 25 10:49:10 PM UTC 24 |
Aug 25 11:08:47 PM UTC 24 |
11265162880 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.1758039021 |
|
|
Aug 25 10:56:36 PM UTC 24 |
Aug 25 11:09:45 PM UTC 24 |
4429524448 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2597730784 |
|
|
Aug 25 10:06:41 PM UTC 24 |
Aug 25 11:09:53 PM UTC 24 |
26817177420 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_all_escalation_resets.2685799710 |
|
|
Aug 25 10:59:12 PM UTC 24 |
Aug 25 11:10:11 PM UTC 24 |
5314952996 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300248947 |
|
|
Aug 25 11:01:36 PM UTC 24 |
Aug 25 11:10:50 PM UTC 24 |
4006989880 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_lc_ctrl_transition.2752004281 |
|
|
Aug 25 10:58:58 PM UTC 24 |
Aug 25 11:11:23 PM UTC 24 |
6245628882 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_all_escalation_resets.3485665778 |
|
|
Aug 25 10:58:55 PM UTC 24 |
Aug 25 11:11:26 PM UTC 24 |
5662459600 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_lc_ctrl_transition.2443740457 |
|
|
Aug 25 10:59:54 PM UTC 24 |
Aug 25 11:11:51 PM UTC 24 |
6440063237 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_lc_ctrl_transition.94376705 |
|
|
Aug 25 11:01:31 PM UTC 24 |
Aug 25 11:12:19 PM UTC 24 |
5052751086 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_uart_rand_baudrate.3943649563 |
|
|
Aug 25 10:58:57 PM UTC 24 |
Aug 25 11:13:23 PM UTC 24 |
4032595040 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_testunlock0.3949417156 |
|
|
Aug 25 10:46:36 PM UTC 24 |
Aug 25 11:13:36 PM UTC 24 |
11226457038 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4012880269 |
|
|
Aug 25 10:27:10 PM UTC 24 |
Aug 25 11:13:40 PM UTC 24 |
9338813240 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency.1033643653 |
|
|
Aug 25 08:29:17 PM UTC 24 |
Aug 25 11:13:55 PM UTC 24 |
26277778010 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_lc_ctrl_transition.1581900958 |
|
|
Aug 25 10:58:39 PM UTC 24 |
Aug 25 11:14:06 PM UTC 24 |
6018989430 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_all_escalation_resets.2387221204 |
|
|
Aug 25 10:58:49 PM UTC 24 |
Aug 25 11:14:16 PM UTC 24 |
6012516330 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861397001 |
|
|
Aug 25 11:05:34 PM UTC 24 |
Aug 25 11:14:40 PM UTC 24 |
3924186688 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_uart_rand_baudrate.2825592963 |
|
|
Aug 25 11:02:19 PM UTC 24 |
Aug 25 11:14:50 PM UTC 24 |
3637572200 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3164965469 |
|
|
Aug 25 10:37:44 PM UTC 24 |
Aug 25 11:14:54 PM UTC 24 |
8614138701 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_uart_rand_baudrate.4261967980 |
|
|
Aug 25 11:01:36 PM UTC 24 |
Aug 25 11:15:16 PM UTC 24 |
5127218248 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2709469081 |
|
|
Aug 25 09:39:06 PM UTC 24 |
Aug 25 11:15:16 PM UTC 24 |
20420013362 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3543433150 |
|
|
Aug 25 11:05:20 PM UTC 24 |
Aug 25 11:15:38 PM UTC 24 |
4189748600 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_all_escalation_resets.1206888744 |
|
|
Aug 25 11:01:37 PM UTC 24 |
Aug 25 11:15:39 PM UTC 24 |
5150699368 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_lc_ctrl_transition.1313700268 |
|
|
Aug 25 10:56:49 PM UTC 24 |
Aug 25 11:15:46 PM UTC 24 |
11029835491 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3259155525 |
|
|
Aug 25 10:58:36 PM UTC 24 |
Aug 25 11:15:51 PM UTC 24 |
5730622960 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3241864973 |
|
|
Aug 25 10:42:49 PM UTC 24 |
Aug 25 11:16:42 PM UTC 24 |
7827099304 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.485558888 |
|
|
Aug 25 11:07:51 PM UTC 24 |
Aug 25 11:17:00 PM UTC 24 |
3932628056 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/13.chip_sw_all_escalation_resets.1064723834 |
|
|
Aug 25 11:01:24 PM UTC 24 |
Aug 25 11:18:38 PM UTC 24 |
5708869880 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_lc_ctrl_transition.2481265448 |
|
|
Aug 25 10:53:44 PM UTC 24 |
Aug 25 11:18:46 PM UTC 24 |
12218235315 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1346782644 |
|
|
Aug 25 09:42:10 PM UTC 24 |
Aug 25 11:18:48 PM UTC 24 |
17689323944 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3470632001 |
|
|
Aug 25 11:09:47 PM UTC 24 |
Aug 25 11:19:01 PM UTC 24 |
4144265980 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442447163 |
|
|
Aug 25 11:09:55 PM UTC 24 |
Aug 25 11:19:36 PM UTC 24 |
3772442306 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_smoketest.1309248431 |
|
|
Aug 25 10:32:37 PM UTC 24 |
Aug 25 11:19:36 PM UTC 24 |
9693704770 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_all_escalation_resets.1768942556 |
|
|
Aug 25 11:06:16 PM UTC 24 |
Aug 25 11:20:00 PM UTC 24 |
4702507680 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3147105730 |
|
|
Aug 25 11:10:57 PM UTC 24 |
Aug 25 11:20:05 PM UTC 24 |
3581530740 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_all_escalation_resets.3867351827 |
|
|
Aug 25 11:05:32 PM UTC 24 |
Aug 25 11:20:09 PM UTC 24 |
4960835092 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.778783503 |
|
|
Aug 25 11:11:32 PM UTC 24 |
Aug 25 11:20:15 PM UTC 24 |
3710819650 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/16.chip_sw_uart_rand_baudrate.790291035 |
|
|
Aug 25 11:06:58 PM UTC 24 |
Aug 25 11:20:43 PM UTC 24 |
4643603130 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_tap_straps_prod.3663373974 |
|
|
Aug 25 10:48:06 PM UTC 24 |
Aug 25 11:20:56 PM UTC 24 |
11522954434 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220368348 |
|
|
Aug 25 11:12:32 PM UTC 24 |
Aug 25 11:21:04 PM UTC 24 |
3151770232 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.2872633733 |
|
|
Aug 25 11:09:47 PM UTC 24 |
Aug 25 11:21:40 PM UTC 24 |
4156108192 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_uart_rand_baudrate.837294115 |
|
|
Aug 25 10:37:52 PM UTC 24 |
Aug 25 11:21:53 PM UTC 24 |
9518159932 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1360280877 |
|
|
Aug 25 11:13:00 PM UTC 24 |
Aug 25 11:21:59 PM UTC 24 |
4023601950 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/14.chip_sw_lc_ctrl_transition.429743255 |
|
|
Aug 25 11:04:12 PM UTC 24 |
Aug 25 11:22:54 PM UTC 24 |
11570348826 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_uart_rand_baudrate.3210889103 |
|
|
Aug 25 11:10:49 PM UTC 24 |
Aug 25 11:22:58 PM UTC 24 |
3201329690 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/21.chip_sw_all_escalation_resets.2925107347 |
|
|
Aug 25 11:12:34 PM UTC 24 |
Aug 25 11:23:37 PM UTC 24 |
4880035320 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/22.chip_sw_all_escalation_resets.131947514 |
|
|
Aug 25 11:12:38 PM UTC 24 |
Aug 25 11:24:37 PM UTC 24 |
5289436040 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_uart_rand_baudrate.269781395 |
|
|
Aug 25 10:49:10 PM UTC 24 |
Aug 25 11:24:45 PM UTC 24 |
8566791292 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2491456047 |
|
|
Aug 25 11:15:39 PM UTC 24 |
Aug 25 11:24:52 PM UTC 24 |
4365502800 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2515446342 |
|
|
Aug 25 11:15:23 PM UTC 24 |
Aug 25 11:25:22 PM UTC 24 |
3215351476 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_uart_rand_baudrate.4253841839 |
|
|
Aug 25 10:42:12 PM UTC 24 |
Aug 25 11:25:57 PM UTC 24 |
9211612040 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/19.chip_sw_all_escalation_resets.4059134728 |
|
|
Aug 25 11:09:52 PM UTC 24 |
Aug 25 11:26:57 PM UTC 24 |
5990559450 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958035402 |
|
|
Aug 25 11:17:46 PM UTC 24 |
Aug 25 11:27:04 PM UTC 24 |
4004998584 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/20.chip_sw_all_escalation_resets.2339261289 |
|
|
Aug 25 11:10:59 PM UTC 24 |
Aug 25 11:27:26 PM UTC 24 |
5740938472 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.602533671 |
|
|
Aug 25 11:18:10 PM UTC 24 |
Aug 25 11:27:41 PM UTC 24 |
4086631768 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952168601 |
|
|
Aug 25 11:17:58 PM UTC 24 |
Aug 25 11:27:46 PM UTC 24 |
3513897184 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_uart_rand_baudrate.2051618880 |
|
|
Aug 25 10:53:43 PM UTC 24 |
Aug 25 11:27:48 PM UTC 24 |
7556037284 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552573360 |
|
|
Aug 25 11:17:53 PM UTC 24 |
Aug 25 11:27:56 PM UTC 24 |
3943019104 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.452288355 |
|
|
Aug 25 11:18:16 PM UTC 24 |
Aug 25 11:28:08 PM UTC 24 |
3499496114 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_all_escalation_resets.3823438001 |
|
|
Aug 25 11:09:53 PM UTC 24 |
Aug 25 11:28:48 PM UTC 24 |
5244037936 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/11.chip_sw_uart_rand_baudrate.3778340019 |
|
|
Aug 25 10:58:08 PM UTC 24 |
Aug 25 11:29:00 PM UTC 24 |
8315669600 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1876304722 |
|
|
Aug 25 11:20:43 PM UTC 24 |
Aug 25 11:29:26 PM UTC 24 |
3557033300 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_keymgr_sideload_otbn.4093635871 |
|
|
Aug 25 09:58:14 PM UTC 24 |
Aug 25 11:29:27 PM UTC 24 |
12396568564 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278740850 |
|
|
Aug 25 11:18:11 PM UTC 24 |
Aug 25 11:29:41 PM UTC 24 |
4001663916 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.3821395129 |
|
|
Aug 25 10:58:58 PM UTC 24 |
Aug 25 11:30:22 PM UTC 24 |
11808245839 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2209258487 |
|
|
Aug 25 11:18:06 PM UTC 24 |
Aug 25 11:30:38 PM UTC 24 |
5324544072 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3276290939 |
|
|
Aug 25 11:19:58 PM UTC 24 |
Aug 25 11:30:55 PM UTC 24 |
3962043536 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.838795238 |
|
|
Aug 25 11:22:11 PM UTC 24 |
Aug 25 11:31:02 PM UTC 24 |
3482762434 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/27.chip_sw_all_escalation_resets.2234106586 |
|
|
Aug 25 11:17:11 PM UTC 24 |
Aug 25 11:31:09 PM UTC 24 |
4383049960 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/23.chip_sw_all_escalation_resets.1441856598 |
|
|
Aug 25 11:15:25 PM UTC 24 |
Aug 25 11:31:22 PM UTC 24 |
4801217816 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/24.chip_sw_all_escalation_resets.2765359442 |
|
|
Aug 25 11:15:26 PM UTC 24 |
Aug 25 11:31:27 PM UTC 24 |
5710154760 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3229798706 |
|
|
Aug 25 09:42:43 PM UTC 24 |
Aug 25 11:31:34 PM UTC 24 |
19349940928 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.300234320 |
|
|
Aug 25 11:21:57 PM UTC 24 |
Aug 25 11:31:42 PM UTC 24 |
3540975616 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3462765186 |
|
|
Aug 25 11:22:53 PM UTC 24 |
Aug 25 11:31:57 PM UTC 24 |
3983832152 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.303486180 |
|
|
Aug 25 11:17:49 PM UTC 24 |
Aug 25 11:32:02 PM UTC 24 |
4488866374 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.717759492 |
|
|
Aug 25 11:22:40 PM UTC 24 |
Aug 25 11:32:03 PM UTC 24 |
4059446160 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.660904262 |
|
|
Aug 25 11:24:18 PM UTC 24 |
Aug 25 11:32:32 PM UTC 24 |
3541976212 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/32.chip_sw_all_escalation_resets.143138925 |
|
|
Aug 25 11:20:16 PM UTC 24 |
Aug 25 11:32:50 PM UTC 24 |
3962589868 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/30.chip_sw_all_escalation_resets.2875264550 |
|
|
Aug 25 11:18:08 PM UTC 24 |
Aug 25 11:33:04 PM UTC 24 |
6436642060 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718429255 |
|
|
Aug 25 11:22:37 PM UTC 24 |
Aug 25 11:33:09 PM UTC 24 |
3767957512 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.169897020 |
|
|
Aug 25 11:23:56 PM UTC 24 |
Aug 25 11:33:21 PM UTC 24 |
3478373912 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_uart_rand_baudrate.372459445 |
|
|
Aug 25 10:58:10 PM UTC 24 |
Aug 25 11:33:50 PM UTC 24 |
8168228360 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/28.chip_sw_all_escalation_resets.2785766761 |
|
|
Aug 25 11:17:59 PM UTC 24 |
Aug 25 11:34:02 PM UTC 24 |
5036258656 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_all_escalation_resets.3240537266 |
|
|
Aug 25 11:21:54 PM UTC 24 |
Aug 25 11:34:06 PM UTC 24 |
5102286760 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1513522699 |
|
|
Aug 25 11:26:09 PM UTC 24 |
Aug 25 11:34:33 PM UTC 24 |
4449531590 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4216494515 |
|
|
Aug 25 11:23:18 PM UTC 24 |
Aug 25 11:34:51 PM UTC 24 |
4521000280 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/25.chip_sw_all_escalation_resets.2699077974 |
|
|
Aug 25 11:18:00 PM UTC 24 |
Aug 25 11:35:09 PM UTC 24 |
6021243864 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/31.chip_sw_all_escalation_resets.1847078150 |
|
|
Aug 25 11:18:14 PM UTC 24 |
Aug 25 11:35:17 PM UTC 24 |
5678637196 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505244396 |
|
|
Aug 25 11:28:03 PM UTC 24 |
Aug 25 11:35:27 PM UTC 24 |
3228194350 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.86308732 |
|
|
Aug 25 11:26:00 PM UTC 24 |
Aug 25 11:36:26 PM UTC 24 |
3812348566 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_csrng_edn_concurrency.881697642 |
|
|
Aug 25 09:53:18 PM UTC 24 |
Aug 25 11:36:46 PM UTC 24 |
15934144610 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/38.chip_sw_all_escalation_resets.2236015170 |
|
|
Aug 25 11:23:18 PM UTC 24 |
Aug 25 11:37:10 PM UTC 24 |
4697368740 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/39.chip_sw_all_escalation_resets.1853084163 |
|
|
Aug 25 11:23:45 PM UTC 24 |
Aug 25 11:37:36 PM UTC 24 |
5692769400 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4237573634 |
|
|
Aug 25 11:30:22 PM UTC 24 |
Aug 25 11:37:53 PM UTC 24 |
3653656972 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/12.chip_sw_uart_rand_baudrate.314528462 |
|
|
Aug 25 10:59:49 PM UTC 24 |
Aug 25 11:37:56 PM UTC 24 |
8074061288 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/34.chip_sw_all_escalation_resets.3570792812 |
|
|
Aug 25 11:21:38 PM UTC 24 |
Aug 25 11:38:09 PM UTC 24 |
4915916052 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1731381014 |
|
|
Aug 25 11:30:27 PM UTC 24 |
Aug 25 11:38:17 PM UTC 24 |
3266265152 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/35.chip_sw_all_escalation_resets.1879858279 |
|
|
Aug 25 11:23:14 PM UTC 24 |
Aug 25 11:38:40 PM UTC 24 |
5530491508 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/42.chip_sw_all_escalation_resets.264953805 |
|
|
Aug 25 11:26:01 PM UTC 24 |
Aug 25 11:38:43 PM UTC 24 |
5195399764 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_all_escalation_resets.1999841611 |
|
|
Aug 25 11:22:11 PM UTC 24 |
Aug 25 11:39:11 PM UTC 24 |
5972803412 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/15.chip_sw_uart_rand_baudrate.4077616521 |
|
|
Aug 25 11:05:33 PM UTC 24 |
Aug 25 11:39:41 PM UTC 24 |
7694694486 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2428559500 |
|
|
Aug 25 11:29:42 PM UTC 24 |
Aug 25 11:39:49 PM UTC 24 |
3413852964 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/37.chip_sw_all_escalation_resets.658892711 |
|
|
Aug 25 11:22:34 PM UTC 24 |
Aug 25 11:40:00 PM UTC 24 |
4648531080 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/40.chip_sw_all_escalation_resets.1809668681 |
|
|
Aug 25 11:23:55 PM UTC 24 |
Aug 25 11:40:41 PM UTC 24 |
6650972968 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2486011781 |
|
|
Aug 25 11:31:01 PM UTC 24 |
Aug 25 11:40:54 PM UTC 24 |
3392340024 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/43.chip_sw_all_escalation_resets.1434582419 |
|
|
Aug 25 11:26:40 PM UTC 24 |
Aug 25 11:41:40 PM UTC 24 |
6394421368 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/46.chip_sw_all_escalation_resets.805634733 |
|
|
Aug 25 11:29:57 PM UTC 24 |
Aug 25 11:41:43 PM UTC 24 |
4154397984 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2902770863 |
|
|
Aug 25 11:33:00 PM UTC 24 |
Aug 25 11:43:28 PM UTC 24 |
4282111070 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883412818 |
|
|
Aug 25 11:34:32 PM UTC 24 |
Aug 25 11:43:57 PM UTC 24 |
3449698864 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/49.chip_sw_all_escalation_resets.1730685221 |
|
|
Aug 25 11:31:48 PM UTC 24 |
Aug 25 11:44:01 PM UTC 24 |
5106928152 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1838238589 |
|
|
Aug 25 11:35:26 PM UTC 24 |
Aug 25 11:44:22 PM UTC 24 |
3768421544 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/44.chip_sw_all_escalation_resets.1489762856 |
|
|
Aug 25 11:28:04 PM UTC 24 |
Aug 25 11:44:35 PM UTC 24 |
4790597464 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/45.chip_sw_all_escalation_resets.3995974027 |
|
|
Aug 25 11:29:44 PM UTC 24 |
Aug 25 11:44:39 PM UTC 24 |
6147821074 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/41.chip_sw_all_escalation_resets.1969341565 |
|
|
Aug 25 11:26:02 PM UTC 24 |
Aug 25 11:44:55 PM UTC 24 |
5465992496 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2694216879 |
|
|
Aug 25 11:35:24 PM UTC 24 |
Aug 25 11:45:12 PM UTC 24 |
4100686284 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708759546 |
|
|
Aug 25 11:37:01 PM UTC 24 |
Aug 25 11:45:17 PM UTC 24 |
3640501944 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_all_escalation_resets.3636429156 |
|
|
Aug 25 11:31:42 PM UTC 24 |
Aug 25 11:45:29 PM UTC 24 |
4993070052 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.452404514 |
|
|
Aug 25 11:33:23 PM UTC 24 |
Aug 25 11:45:32 PM UTC 24 |
4183661050 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.351625086 |
|
|
Aug 25 11:36:20 PM UTC 24 |
Aug 25 11:45:43 PM UTC 24 |
3658259776 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.448362515 |
|
|
Aug 25 11:36:12 PM UTC 24 |
Aug 25 11:46:02 PM UTC 24 |
4469573400 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/51.chip_sw_all_escalation_resets.3506806127 |
|
|
Aug 25 11:33:38 PM UTC 24 |
Aug 25 11:46:40 PM UTC 24 |
4600890726 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1264229372 |
|
|
Aug 25 11:38:30 PM UTC 24 |
Aug 25 11:46:46 PM UTC 24 |
3147393472 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/47.chip_sw_all_escalation_resets.2342310303 |
|
|
Aug 25 11:30:27 PM UTC 24 |
Aug 25 11:46:54 PM UTC 24 |
4905909082 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/52.chip_sw_all_escalation_resets.2575126611 |
|
|
Aug 25 11:33:01 PM UTC 24 |
Aug 25 11:47:01 PM UTC 24 |
5419417028 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_all_escalation_resets.3945772634 |
|
|
Aug 25 11:47:56 PM UTC 24 |
Aug 26 12:02:37 AM UTC 24 |
5135347432 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165632888 |
|
|
Aug 25 11:37:07 PM UTC 24 |
Aug 25 11:47:12 PM UTC 24 |
3836060360 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1351115998 |
|
|
Aug 25 10:30:54 PM UTC 24 |
Aug 25 11:47:13 PM UTC 24 |
11486699757 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3559113067 |
|
|
Aug 25 11:36:59 PM UTC 24 |
Aug 25 11:48:00 PM UTC 24 |
3762299940 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/48.chip_sw_all_escalation_resets.1369599894 |
|
|
Aug 25 11:30:26 PM UTC 24 |
Aug 25 11:48:15 PM UTC 24 |
5006968872 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1781640931 |
|
|
Aug 25 11:39:05 PM UTC 24 |
Aug 25 11:48:20 PM UTC 24 |
4233833358 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.989812649 |
|
|
Aug 25 11:40:04 PM UTC 24 |
Aug 25 11:48:22 PM UTC 24 |
3185225160 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/56.chip_sw_all_escalation_resets.833876928 |
|
|
Aug 25 11:37:07 PM UTC 24 |
Aug 25 11:48:31 PM UTC 24 |
3980823790 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2664267744 |
|
|
Aug 25 11:41:03 PM UTC 24 |
Aug 25 11:48:40 PM UTC 24 |
3083766516 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.988510125 |
|
|
Aug 25 11:37:04 PM UTC 24 |
Aug 25 11:48:55 PM UTC 24 |
4576443820 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/17.chip_sw_uart_rand_baudrate.387273801 |
|
|
Aug 25 11:09:37 PM UTC 24 |
Aug 25 11:49:11 PM UTC 24 |
8336863604 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564727227 |
|
|
Aug 25 11:40:34 PM UTC 24 |
Aug 25 11:49:13 PM UTC 24 |
3623037170 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1806354926 |
|
|
Aug 25 11:41:03 PM UTC 24 |
Aug 25 11:49:23 PM UTC 24 |
3495212472 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398599282 |
|
|
Aug 25 11:42:37 PM UTC 24 |
Aug 25 11:49:34 PM UTC 24 |
2962987460 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.1827458109 |
|
|
Aug 25 11:37:03 PM UTC 24 |
Aug 25 11:49:39 PM UTC 24 |
4522008800 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/61.chip_sw_all_escalation_resets.2670510452 |
|
|
Aug 25 11:37:06 PM UTC 24 |
Aug 25 11:50:01 PM UTC 24 |
5906901432 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939899207 |
|
|
Aug 25 11:40:56 PM UTC 24 |
Aug 25 11:50:07 PM UTC 24 |
4536481870 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/58.chip_sw_all_escalation_resets.3172712310 |
|
|
Aug 25 11:35:37 PM UTC 24 |
Aug 25 11:50:11 PM UTC 24 |
5768787306 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3815837638 |
|
|
Aug 25 11:38:50 PM UTC 24 |
Aug 25 11:50:40 PM UTC 24 |
4522152560 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.506908852 |
|
|
Aug 25 11:40:33 PM UTC 24 |
Aug 25 11:50:43 PM UTC 24 |
3600055032 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3049634480 |
|
|
Aug 25 11:39:51 PM UTC 24 |
Aug 25 11:51:30 PM UTC 24 |
3753932344 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/57.chip_sw_all_escalation_resets.3228609772 |
|
|
Aug 25 11:38:01 PM UTC 24 |
Aug 25 11:51:37 PM UTC 24 |
4315451928 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/65.chip_sw_all_escalation_resets.1831883541 |
|
|
Aug 25 11:40:19 PM UTC 24 |
Aug 25 11:51:38 PM UTC 24 |
4213281436 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/55.chip_sw_all_escalation_resets.158426493 |
|
|
Aug 25 11:35:22 PM UTC 24 |
Aug 25 11:51:41 PM UTC 24 |
5998851634 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/64.chip_sw_all_escalation_resets.1165807673 |
|
|
Aug 25 11:38:02 PM UTC 24 |
Aug 25 11:52:03 PM UTC 24 |
5146042856 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/54.chip_sw_all_escalation_resets.2609111095 |
|
|
Aug 25 11:38:02 PM UTC 24 |
Aug 25 11:52:04 PM UTC 24 |
5541158600 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086400972 |
|
|
Aug 25 11:44:52 PM UTC 24 |
Aug 25 11:52:46 PM UTC 24 |
3756203836 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/53.chip_sw_all_escalation_resets.3248269617 |
|
|
Aug 25 11:36:59 PM UTC 24 |
Aug 25 11:52:57 PM UTC 24 |
5757883936 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/63.chip_sw_all_escalation_resets.380426481 |
|
|
Aug 25 11:38:18 PM UTC 24 |
Aug 25 11:52:59 PM UTC 24 |
6439372798 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776681747 |
|
|
Aug 25 11:54:33 PM UTC 24 |
Aug 26 12:01:49 AM UTC 24 |
3574960952 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_ast_clk_rst_inputs.1665478612 |
|
|
Aug 25 10:27:37 PM UTC 24 |
Aug 25 11:53:13 PM UTC 24 |
21201235054 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/59.chip_sw_all_escalation_resets.3646529686 |
|
|
Aug 25 11:37:36 PM UTC 24 |
Aug 25 11:53:29 PM UTC 24 |
6238146168 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/70.chip_sw_all_escalation_resets.1509265399 |
|
|
Aug 25 11:41:16 PM UTC 24 |
Aug 25 11:53:36 PM UTC 24 |
6017185938 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3107692986 |
|
|
Aug 25 11:45:19 PM UTC 24 |
Aug 25 11:53:57 PM UTC 24 |
3930121514 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.2748700238 |
|
|
Aug 25 10:57:04 PM UTC 24 |
Aug 25 11:54:12 PM UTC 24 |
10577560500 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/72.chip_sw_all_escalation_resets.2126985428 |
|
|
Aug 25 11:42:38 PM UTC 24 |
Aug 25 11:54:12 PM UTC 24 |
6127877848 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/69.chip_sw_all_escalation_resets.2656781491 |
|
|
Aug 25 11:41:38 PM UTC 24 |
Aug 25 11:54:38 PM UTC 24 |
5600195950 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/68.chip_sw_all_escalation_resets.1133168336 |
|
|
Aug 25 11:40:48 PM UTC 24 |
Aug 25 11:54:39 PM UTC 24 |
4787467878 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.444515888 |
|
|
Aug 25 11:47:44 PM UTC 24 |
Aug 25 11:54:58 PM UTC 24 |
3714085048 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.2927494222 |
|
|
Aug 25 10:59:27 PM UTC 24 |
Aug 25 11:55:09 PM UTC 24 |
13141974848 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/67.chip_sw_all_escalation_resets.1041406097 |
|
|
Aug 25 11:40:49 PM UTC 24 |
Aug 25 11:55:22 PM UTC 24 |
5290703800 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428849130 |
|
|
Aug 25 11:47:36 PM UTC 24 |
Aug 25 11:55:53 PM UTC 24 |
3533170488 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2204118991 |
|
|
Aug 25 11:46:27 PM UTC 24 |
Aug 25 11:56:53 PM UTC 24 |
3560171840 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/66.chip_sw_all_escalation_resets.2840589550 |
|
|
Aug 25 11:40:31 PM UTC 24 |
Aug 25 11:56:54 PM UTC 24 |
4474381500 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3085875698 |
|
|
Aug 25 11:49:56 PM UTC 24 |
Aug 25 11:57:11 PM UTC 24 |
3530092928 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080638114 |
|
|
Aug 25 11:47:41 PM UTC 24 |
Aug 25 11:57:24 PM UTC 24 |
3971444316 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/71.chip_sw_all_escalation_resets.3551747286 |
|
|
Aug 25 11:41:43 PM UTC 24 |
Aug 25 11:57:37 PM UTC 24 |
6531765082 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_output.4066126590 |
|
|
Aug 25 10:34:55 PM UTC 24 |
Aug 25 11:57:49 PM UTC 24 |
24004593725 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556449025 |
|
|
Aug 25 11:49:22 PM UTC 24 |
Aug 25 11:58:31 PM UTC 24 |
3254611848 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_prod.2853121755 |
|
|
Aug 25 09:27:52 PM UTC 24 |
Aug 25 11:59:06 PM UTC 24 |
49187893629 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod.1842873683 |
|
|
Aug 25 10:31:18 PM UTC 24 |
Aug 25 11:59:07 PM UTC 24 |
15021630419 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.850848784 |
|
|
Aug 25 10:30:01 PM UTC 24 |
Aug 25 11:59:08 PM UTC 24 |
14571525116 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2043482760 |
|
|
Aug 25 10:24:32 PM UTC 24 |
Aug 25 11:59:33 PM UTC 24 |
24261383575 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/73.chip_sw_all_escalation_resets.238333377 |
|
|
Aug 25 11:45:31 PM UTC 24 |
Aug 25 11:59:34 PM UTC 24 |
5637193512 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.359717041 |
|
|
Aug 25 09:18:31 PM UTC 24 |
Aug 25 11:59:37 PM UTC 24 |
42597390647 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_all_escalation_resets.2961670461 |
|
|
Aug 25 11:47:35 PM UTC 24 |
Aug 25 11:59:40 PM UTC 24 |
6185572802 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.424203288 |
|
|
Aug 25 11:51:29 PM UTC 24 |
Aug 25 11:59:52 PM UTC 24 |
3883090324 ps |
| T1321 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2995747327 |
|
|
Aug 25 10:31:30 PM UTC 24 |
Aug 26 12:00:30 AM UTC 24 |
15143524450 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1413791796 |
|
|
Aug 25 11:52:44 PM UTC 24 |
Aug 26 12:00:33 AM UTC 24 |
3866007950 ps |
| T1322 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3555202890 |
|
|
Aug 25 11:55:03 PM UTC 24 |
Aug 26 12:00:56 AM UTC 24 |
3802174296 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1659234984 |
|
|
Aug 25 11:49:09 PM UTC 24 |
Aug 26 12:00:59 AM UTC 24 |
5295692514 ps |
| T1323 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_all_escalation_resets.2766854284 |
|
|
Aug 25 11:49:41 PM UTC 24 |
Aug 26 12:01:14 AM UTC 24 |
4766100632 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2176555015 |
|
|
Aug 25 11:51:13 PM UTC 24 |
Aug 26 12:01:24 AM UTC 24 |
4426347866 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.804522997 |
|
|
Aug 25 11:48:26 PM UTC 24 |
Aug 26 12:01:45 AM UTC 24 |
4906991756 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3796551557 |
|
|
Aug 25 11:55:05 PM UTC 24 |
Aug 26 12:02:27 AM UTC 24 |
3948438088 ps |
| T1324 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3693835536 |
|
|
Aug 25 11:53:45 PM UTC 24 |
Aug 26 12:02:44 AM UTC 24 |
4011771952 ps |
| T1325 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.962611592 |
|
|
Aug 25 11:54:53 PM UTC 24 |
Aug 26 12:02:44 AM UTC 24 |
3169353700 ps |
| T1326 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_smoke.3560896930 |
|
|
Aug 25 10:36:28 PM UTC 24 |
Aug 26 12:02:47 AM UTC 24 |
14923259744 ps |
| T1327 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_all_escalation_resets.2355906093 |
|
|
Aug 25 11:51:54 PM UTC 24 |
Aug 26 12:02:47 AM UTC 24 |
5704911610 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4126574280 |
|
|
Aug 25 11:54:19 PM UTC 24 |
Aug 26 12:02:49 AM UTC 24 |
4394619660 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.162255077 |
|
|
Aug 25 11:53:01 PM UTC 24 |
Aug 26 12:02:56 AM UTC 24 |
5035018944 ps |
| T1328 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_rma.2427280847 |
|
|
Aug 25 09:28:33 PM UTC 24 |
Aug 26 12:03:11 AM UTC 24 |
45202373730 ps |
| T1329 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.511815500 |
|
|
Aug 25 11:55:00 PM UTC 24 |
Aug 26 12:03:19 AM UTC 24 |
3153897048 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.2049120742 |
|
|
Aug 25 11:51:28 PM UTC 24 |
Aug 26 12:03:35 AM UTC 24 |
4973657404 ps |
| T1330 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.rom_e2e_self_hash.2523572426 |
|
|
Aug 25 09:06:07 PM UTC 24 |
Aug 26 12:03:43 AM UTC 24 |
26914429180 ps |
| T1331 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_shutdown_exception_c.2906570800 |
|
|
Aug 25 10:32:20 PM UTC 24 |
Aug 26 12:03:47 AM UTC 24 |
14341585652 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2770844455 |
|
|
Aug 25 11:52:24 PM UTC 24 |
Aug 26 12:03:59 AM UTC 24 |
5074861760 ps |
| T1332 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.480345458 |
|
|
Aug 25 11:52:32 PM UTC 24 |
Aug 26 12:04:02 AM UTC 24 |
5449915644 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.2998470774 |
|
|
Aug 25 11:54:03 PM UTC 24 |
Aug 26 12:04:03 AM UTC 24 |
5463348124 ps |
| T1333 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_uart_rand_baudrate.1856197795 |
|
|
Aug 25 11:09:53 PM UTC 24 |
Aug 26 12:04:18 AM UTC 24 |
13354838330 ps |
| T1334 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/92.chip_sw_all_escalation_resets.3068101907 |
|
|
Aug 25 11:54:35 PM UTC 24 |
Aug 26 12:04:20 AM UTC 24 |
5776841500 ps |
| T1335 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_dev.1835388760 |
|
|
Aug 25 10:34:08 PM UTC 24 |
Aug 26 12:04:22 AM UTC 24 |
15709720016 ps |
| T1336 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_prod_end.2602343308 |
|
|
Aug 25 10:32:52 PM UTC 24 |
Aug 26 12:04:24 AM UTC 24 |
16054255714 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.1672823963 |
|
|
Aug 25 11:53:26 PM UTC 24 |
Aug 26 12:04:24 AM UTC 24 |
5971614384 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3932535530 |
|
|
Aug 25 11:50:36 PM UTC 24 |
Aug 26 12:04:35 AM UTC 24 |
5529436514 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.4179385115 |
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Aug 25 11:54:59 PM UTC 24 |
Aug 26 12:04:53 AM UTC 24 |
5333651130 ps |
| T1337 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.3650377893 |
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Aug 25 11:54:33 PM UTC 24 |
Aug 26 12:05:12 AM UTC 24 |
4775588332 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_all_escalation_resets.164078114 |
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Aug 25 11:53:13 PM UTC 24 |
Aug 26 12:05:12 AM UTC 24 |
6483985240 ps |
| T1338 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.3438842184 |
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Aug 25 11:53:47 PM UTC 24 |
Aug 26 12:05:25 AM UTC 24 |
5648352992 ps |
| T1339 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.3257590750 |
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Aug 25 11:51:09 PM UTC 24 |
Aug 26 12:05:26 AM UTC 24 |
6069577184 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.2588709563 |
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Aug 25 11:53:33 PM UTC 24 |
Aug 26 12:05:26 AM UTC 24 |
5538474344 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.940598535 |
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Aug 25 11:53:46 PM UTC 24 |
Aug 26 12:05:52 AM UTC 24 |
5743486672 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.4097662489 |
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Aug 25 11:55:05 PM UTC 24 |
Aug 26 12:05:54 AM UTC 24 |
5208067300 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.2705624592 |
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Aug 25 11:54:30 PM UTC 24 |
Aug 26 12:06:14 AM UTC 24 |
5111942720 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_all_escalation_resets.3052847631 |
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Aug 25 11:54:34 PM UTC 24 |
Aug 26 12:06:31 AM UTC 24 |
6682657130 ps |
| T1340 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.3072103650 |
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Aug 25 11:54:19 PM UTC 24 |
Aug 26 12:06:59 AM UTC 24 |
5769878984 ps |
| T1341 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_asm_init_rma.2032299894 |
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Aug 25 10:36:28 PM UTC 24 |
Aug 26 12:07:47 AM UTC 24 |
14793716924 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.3287145556 |
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|
Aug 25 11:54:02 PM UTC 24 |
Aug 26 12:07:51 AM UTC 24 |
5431083848 ps |
| T1342 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_lc_walkthrough_dev.2872274868 |
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Aug 25 09:26:09 PM UTC 24 |
Aug 26 12:10:54 AM UTC 24 |
50882213507 ps |
| T1343 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3042554808 |
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|
Aug 25 10:36:44 PM UTC 24 |
Aug 26 12:11:44 AM UTC 24 |
14626714188 ps |
| T1344 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_static_critical.3589834965 |
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|
Aug 25 10:32:29 PM UTC 24 |
Aug 26 12:12:03 AM UTC 24 |
16339446504 ps |
| T1345 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/7.chip_sw_csrng_edn_concurrency.897889676 |
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|
Aug 25 10:58:54 PM UTC 24 |
Aug 26 12:24:51 AM UTC 24 |
17886632600 ps |
| T1346 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/3.chip_sw_csrng_edn_concurrency.3108409170 |
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|
Aug 25 10:39:48 PM UTC 24 |
Aug 26 12:32:00 AM UTC 24 |
20090831200 ps |
| T1347 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/5.chip_sw_csrng_edn_concurrency.2903229734 |
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|
Aug 25 10:51:00 PM UTC 24 |
Aug 26 12:32:28 AM UTC 24 |
18604170712 ps |
| T1348 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.rom_e2e_self_hash.1293601739 |
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|
Aug 25 10:32:51 PM UTC 24 |
Aug 26 12:33:20 AM UTC 24 |
27115637960 ps |
| T1349 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/6.chip_sw_csrng_edn_concurrency.1548482360 |
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|
Aug 25 10:56:51 PM UTC 24 |
Aug 26 12:40:32 AM UTC 24 |
22553392570 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2946252452 |
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|
Aug 25 06:08:33 PM UTC 24 |
Aug 26 12:42:45 AM UTC 24 |
79179177269 ps |
| T1350 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/4.chip_sw_csrng_edn_concurrency.932434427 |
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|
Aug 25 10:45:03 PM UTC 24 |
Aug 26 12:50:35 AM UTC 24 |
26257701500 ps |
| T1351 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.524411852 |
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|
Aug 25 10:59:41 PM UTC 24 |
Aug 26 01:03:16 AM UTC 24 |
26458746604 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2903159733 |
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|
Aug 25 07:20:58 PM UTC 24 |
Aug 26 01:20:41 AM UTC 24 |
79531365592 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_inject_scramble_seed.2679774619 |
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|
Aug 25 09:13:15 PM UTC 24 |
Aug 26 01:38:27 AM UTC 24 |
66847323197 ps |
| T1352 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1231758872 |
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Aug 25 09:13:11 PM UTC 24 |
Aug 26 02:06:59 AM UTC 24 |
78782475080 ps |