| T1794 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2184693674 |
|
|
Aug 25 04:33:57 PM UTC 24 |
Aug 25 04:41:08 PM UTC 24 |
6162346654 ps |
| T1795 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke.3198256471 |
|
|
Aug 25 04:40:58 PM UTC 24 |
Aug 25 04:41:10 PM UTC 24 |
51488414 ps |
| T1796 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_error_random.1519856616 |
|
|
Aug 25 04:40:38 PM UTC 24 |
Aug 25 04:41:12 PM UTC 24 |
558868173 ps |
| T1797 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.4244434958 |
|
|
Aug 25 04:35:02 PM UTC 24 |
Aug 25 04:41:12 PM UTC 24 |
594894240 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_random_slow_rsp.443024449 |
|
|
Aug 25 04:26:19 PM UTC 24 |
Aug 25 04:41:16 PM UTC 24 |
36234910292 ps |
| T1798 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_large_delays.311979301 |
|
|
Aug 25 04:28:06 PM UTC 24 |
Aug 25 04:41:18 PM UTC 24 |
47690069493 ps |
| T1799 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_zero_delays.4039127022 |
|
|
Aug 25 04:41:11 PM UTC 24 |
Aug 25 04:41:21 PM UTC 24 |
43701031 ps |
| T1800 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all.3181968253 |
|
|
Aug 25 04:34:56 PM UTC 24 |
Aug 25 04:41:43 PM UTC 24 |
6640273828 ps |
| T1801 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_unmapped_addr.1306970732 |
|
|
Aug 25 04:40:41 PM UTC 24 |
Aug 25 04:41:45 PM UTC 24 |
851053342 ps |
| T1802 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_stress_all.4137892648 |
|
|
Aug 25 04:32:15 PM UTC 24 |
Aug 25 04:41:54 PM UTC 24 |
11772093952 ps |
| T1803 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_random.2786481002 |
|
|
Aug 25 04:41:45 PM UTC 24 |
Aug 25 04:41:56 PM UTC 24 |
107003642 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3359033107 |
|
|
Aug 25 04:37:49 PM UTC 24 |
Aug 25 04:41:57 PM UTC 24 |
1512556013 ps |
| T1804 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_zero_delays.2387339289 |
|
|
Aug 25 04:41:33 PM UTC 24 |
Aug 25 04:42:06 PM UTC 24 |
220226427 ps |
| T1805 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_large_delays.3217892138 |
|
|
Aug 25 04:39:45 PM UTC 24 |
Aug 25 04:42:08 PM UTC 24 |
9084428535 ps |
| T1806 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_access_same_device.4022173387 |
|
|
Aug 25 04:40:17 PM UTC 24 |
Aug 25 04:42:12 PM UTC 24 |
1697592452 ps |
| T1807 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random.4055608332 |
|
|
Aug 25 04:41:26 PM UTC 24 |
Aug 25 04:42:12 PM UTC 24 |
304232105 ps |
| T1808 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_error.670509251 |
|
|
Aug 25 04:40:47 PM UTC 24 |
Aug 25 04:42:17 PM UTC 24 |
814980198 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1853152886 |
|
|
Aug 25 04:30:34 PM UTC 24 |
Aug 25 04:42:17 PM UTC 24 |
11658982064 ps |
| T1809 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_same_source.795176635 |
|
|
Aug 25 04:41:43 PM UTC 24 |
Aug 25 04:42:29 PM UTC 24 |
1169265913 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1570208678 |
|
|
Aug 25 04:27:12 PM UTC 24 |
Aug 25 04:42:40 PM UTC 24 |
10210274437 ps |
| T1810 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke.2912652083 |
|
|
Aug 25 04:42:33 PM UTC 24 |
Aug 25 04:42:46 PM UTC 24 |
184969371 ps |
| T1811 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3174914875 |
|
|
Aug 25 04:42:36 PM UTC 24 |
Aug 25 04:42:46 PM UTC 24 |
42419329 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3980745395 |
|
|
Aug 25 04:35:03 PM UTC 24 |
Aug 25 04:42:49 PM UTC 24 |
1733255320 ps |
| T1812 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.181376988 |
|
|
Aug 25 04:39:48 PM UTC 24 |
Aug 25 04:42:50 PM UTC 24 |
6310787199 ps |
| T1813 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_error.2143875226 |
|
|
Aug 25 04:36:48 PM UTC 24 |
Aug 25 04:42:55 PM UTC 24 |
3003030698 ps |
| T1814 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_unmapped_addr.2609825202 |
|
|
Aug 25 04:42:07 PM UTC 24 |
Aug 25 04:43:02 PM UTC 24 |
269155100 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_access_same_device.4008122797 |
|
|
Aug 25 04:41:37 PM UTC 24 |
Aug 25 04:43:04 PM UTC 24 |
1364059510 ps |
| T1815 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3274388762 |
|
|
Aug 25 04:42:09 PM UTC 24 |
Aug 25 04:43:07 PM UTC 24 |
1040927312 ps |
| T1816 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_large_delays.4216494993 |
|
|
Aug 25 04:30:48 PM UTC 24 |
Aug 25 04:43:09 PM UTC 24 |
50306696119 ps |
| T1817 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.541008749 |
|
|
Aug 25 04:41:23 PM UTC 24 |
Aug 25 04:43:11 PM UTC 24 |
4456279296 ps |
| T1818 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_error.3042391923 |
|
|
Aug 25 04:37:43 PM UTC 24 |
Aug 25 04:43:20 PM UTC 24 |
6179966735 ps |
| T1819 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_random_slow_rsp.3721816315 |
|
|
Aug 25 04:41:37 PM UTC 24 |
Aug 25 04:43:21 PM UTC 24 |
3665876802 ps |
| T1820 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2598083938 |
|
|
Aug 25 04:40:48 PM UTC 24 |
Aug 25 04:43:25 PM UTC 24 |
2824679586 ps |
| T1821 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_stress_all_with_error.1292654543 |
|
|
Aug 25 04:30:20 PM UTC 24 |
Aug 25 04:43:27 PM UTC 24 |
14132781482 ps |
| T1822 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_slow_rsp.391270894 |
|
|
Aug 25 04:17:35 PM UTC 24 |
Aug 25 04:43:38 PM UTC 24 |
62743833363 ps |
| T1823 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_smoke_large_delays.3145341660 |
|
|
Aug 25 04:41:17 PM UTC 24 |
Aug 25 04:43:42 PM UTC 24 |
8543440070 ps |
| T1824 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_zero_delays.95519870 |
|
|
Aug 25 04:42:50 PM UTC 24 |
Aug 25 04:43:46 PM UTC 24 |
371946359 ps |
| T1825 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke.2619304034 |
|
|
Aug 25 04:43:44 PM UTC 24 |
Aug 25 04:43:54 PM UTC 24 |
43548403 ps |
| T1826 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all.353230561 |
|
|
Aug 25 04:37:27 PM UTC 24 |
Aug 25 04:43:55 PM UTC 24 |
3804950814 ps |
| T1827 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_zero_delays.779689669 |
|
|
Aug 25 04:43:49 PM UTC 24 |
Aug 25 04:44:01 PM UTC 24 |
49107861 ps |
| T1828 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_error.2025963060 |
|
|
Aug 25 04:42:20 PM UTC 24 |
Aug 25 04:44:11 PM UTC 24 |
910367560 ps |
| T1829 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all.572946394 |
|
|
Aug 25 04:40:43 PM UTC 24 |
Aug 25 04:44:12 PM UTC 24 |
4630480293 ps |
| T1830 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_large_delays.3876025527 |
|
|
Aug 25 04:13:31 PM UTC 24 |
Aug 25 04:44:14 PM UTC 24 |
107119930301 ps |
| T1831 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device.1078155818 |
|
|
Aug 25 04:43:10 PM UTC 24 |
Aug 25 04:44:16 PM UTC 24 |
1009751002 ps |
| T1832 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_unmapped_addr.1747950043 |
|
|
Aug 25 04:43:26 PM UTC 24 |
Aug 25 04:44:16 PM UTC 24 |
829613443 ps |
| T1833 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2121079234 |
|
|
Aug 25 04:43:27 PM UTC 24 |
Aug 25 04:44:20 PM UTC 24 |
920147375 ps |
| T1834 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random.3466006687 |
|
|
Aug 25 04:42:40 PM UTC 24 |
Aug 25 04:44:23 PM UTC 24 |
1920965513 ps |
| T1835 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_smoke.4156985059 |
|
|
Aug 25 05:08:05 PM UTC 24 |
Aug 25 05:08:16 PM UTC 24 |
50487840 ps |
| T1836 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_large_delays.3788525085 |
|
|
Aug 25 04:19:20 PM UTC 24 |
Aug 25 04:44:26 PM UTC 24 |
106525721230 ps |
| T1837 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4075179468 |
|
|
Aug 25 04:43:44 PM UTC 24 |
Aug 25 04:44:27 PM UTC 24 |
83077156 ps |
| T1838 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.2628629242 |
|
|
Aug 25 03:50:47 PM UTC 24 |
Aug 25 04:44:30 PM UTC 24 |
16079402859 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1159634071 |
|
|
Aug 25 04:09:24 PM UTC 24 |
Aug 25 04:44:31 PM UTC 24 |
83847429687 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2851653643 |
|
|
Aug 25 04:42:30 PM UTC 24 |
Aug 25 04:44:32 PM UTC 24 |
265349494 ps |
| T1839 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_zero_delays.1964607826 |
|
|
Aug 25 04:44:08 PM UTC 24 |
Aug 25 04:44:34 PM UTC 24 |
177918603 ps |
| T1840 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_random_large_delays.2787812414 |
|
|
Aug 25 04:35:28 PM UTC 24 |
Aug 25 04:44:45 PM UTC 24 |
30972565199 ps |
| T1841 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2531419339 |
|
|
Aug 25 04:42:41 PM UTC 24 |
Aug 25 04:44:45 PM UTC 24 |
5608718561 ps |
| T1842 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_error.2148041046 |
|
|
Aug 25 04:43:34 PM UTC 24 |
Aug 25 04:44:46 PM UTC 24 |
1550293486 ps |
| T1843 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_error_random.94814190 |
|
|
Aug 25 04:43:18 PM UTC 24 |
Aug 25 04:44:47 PM UTC 24 |
2050835867 ps |
| T1844 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random.1835499687 |
|
|
Aug 25 04:44:07 PM UTC 24 |
Aug 25 04:44:57 PM UTC 24 |
342350622 ps |
| T1845 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/32.xbar_random_slow_rsp.2064830268 |
|
|
Aug 25 04:30:52 PM UTC 24 |
Aug 25 04:45:02 PM UTC 24 |
37645586761 ps |
| T1846 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1071438180 |
|
|
Aug 25 04:44:52 PM UTC 24 |
Aug 25 04:45:03 PM UTC 24 |
50310891 ps |
| T1847 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke.1616916627 |
|
|
Aug 25 04:44:49 PM UTC 24 |
Aug 25 04:45:03 PM UTC 24 |
139915900 ps |
| T1848 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.524157568 |
|
|
Aug 25 04:44:39 PM UTC 24 |
Aug 25 04:45:17 PM UTC 24 |
521355867 ps |
| T1849 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/30.xbar_random_slow_rsp.3656691206 |
|
|
Aug 25 04:28:10 PM UTC 24 |
Aug 25 04:45:18 PM UTC 24 |
38777240405 ps |
| T1850 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_smoke_large_delays.1606426958 |
|
|
Aug 25 04:42:36 PM UTC 24 |
Aug 25 04:45:20 PM UTC 24 |
9189795664 ps |
| T1851 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_unmapped_addr.2680115107 |
|
|
Aug 25 04:44:39 PM UTC 24 |
Aug 25 04:45:28 PM UTC 24 |
643000892 ps |
| T1852 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_error_random.3554847259 |
|
|
Aug 25 04:44:38 PM UTC 24 |
Aug 25 04:45:29 PM UTC 24 |
778322405 ps |
| T1853 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_slow_rsp.916153378 |
|
|
Aug 25 04:44:14 PM UTC 24 |
Aug 25 04:45:39 PM UTC 24 |
3434867553 ps |
| T1854 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_error.1578328797 |
|
|
Aug 25 04:39:27 PM UTC 24 |
Aug 25 04:45:40 PM UTC 24 |
3184350908 ps |
| T1855 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_unmapped_addr.1253701697 |
|
|
Aug 25 04:45:26 PM UTC 24 |
Aug 25 04:45:43 PM UTC 24 |
168986118 ps |
| T1856 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_same_source.3726314924 |
|
|
Aug 25 04:45:27 PM UTC 24 |
Aug 25 04:45:51 PM UTC 24 |
409897333 ps |
| T1857 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.933834699 |
|
|
Aug 25 04:44:01 PM UTC 24 |
Aug 25 04:45:59 PM UTC 24 |
5228758997 ps |
| T1858 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_same_source.3415869303 |
|
|
Aug 25 04:44:38 PM UTC 24 |
Aug 25 04:46:02 PM UTC 24 |
1776407843 ps |
| T1859 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_random.3096273383 |
|
|
Aug 25 04:45:27 PM UTC 24 |
Aug 25 04:46:06 PM UTC 24 |
633742131 ps |
| T1860 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3478677828 |
|
|
Aug 25 04:46:04 PM UTC 24 |
Aug 25 04:46:15 PM UTC 24 |
46122732 ps |
| T1861 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke.1432285456 |
|
|
Aug 25 04:46:03 PM UTC 24 |
Aug 25 04:46:17 PM UTC 24 |
229829245 ps |
| T1862 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3534747976 |
|
|
Aug 25 04:45:42 PM UTC 24 |
Aug 25 04:46:23 PM UTC 24 |
622988941 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_access_same_device.1451484702 |
|
|
Aug 25 04:44:25 PM UTC 24 |
Aug 25 04:46:25 PM UTC 24 |
1839178103 ps |
| T1863 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_zero_delays.2367153498 |
|
|
Aug 25 04:45:08 PM UTC 24 |
Aug 25 04:46:30 PM UTC 24 |
558043641 ps |
| T1864 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_smoke_large_delays.2033781235 |
|
|
Aug 25 04:43:48 PM UTC 24 |
Aug 25 04:46:48 PM UTC 24 |
10276976940 ps |
| T1865 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random.650533154 |
|
|
Aug 25 04:46:23 PM UTC 24 |
Aug 25 04:46:50 PM UTC 24 |
457767153 ps |
| T1866 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random.3112693327 |
|
|
Aug 25 04:44:58 PM UTC 24 |
Aug 25 04:47:07 PM UTC 24 |
2147865874 ps |
| T1867 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3568617837 |
|
|
Aug 25 04:44:54 PM UTC 24 |
Aug 25 04:47:08 PM UTC 24 |
5145325063 ps |
| T1868 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/27.xbar_random_large_delays.1848585896 |
|
|
Aug 25 04:22:28 PM UTC 24 |
Aug 25 04:47:08 PM UTC 24 |
85000764839 ps |
| T1869 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device.808945866 |
|
|
Aug 25 04:45:11 PM UTC 24 |
Aug 25 04:47:14 PM UTC 24 |
2336837434 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_access_same_device.694246534 |
|
|
Aug 25 04:46:40 PM UTC 24 |
Aug 25 04:47:21 PM UTC 24 |
266270631 ps |
| T1870 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_smoke_large_delays.8734982 |
|
|
Aug 25 04:44:55 PM UTC 24 |
Aug 25 04:47:25 PM UTC 24 |
10424461877 ps |
| T1871 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_error.2306596404 |
|
|
Aug 25 04:45:53 PM UTC 24 |
Aug 25 04:47:29 PM UTC 24 |
663284001 ps |
| T1872 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3057297346 |
|
|
Aug 25 04:47:14 PM UTC 24 |
Aug 25 04:47:33 PM UTC 24 |
257814307 ps |
| T1873 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_unmapped_addr.2181984806 |
|
|
Aug 25 04:47:12 PM UTC 24 |
Aug 25 04:47:34 PM UTC 24 |
97343634 ps |
| T1874 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_same_source.1770750726 |
|
|
Aug 25 04:46:50 PM UTC 24 |
Aug 25 04:47:47 PM UTC 24 |
1126272319 ps |
| T1875 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_zero_delays.4261915788 |
|
|
Aug 25 04:46:25 PM UTC 24 |
Aug 25 04:47:50 PM UTC 24 |
586089165 ps |
| T1876 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke.4261488415 |
|
|
Aug 25 04:47:39 PM UTC 24 |
Aug 25 04:47:52 PM UTC 24 |
149243560 ps |
| T1877 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3899201347 |
|
|
Aug 25 04:47:46 PM UTC 24 |
Aug 25 04:47:58 PM UTC 24 |
54203209 ps |
| T1878 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_large_delays.1566602436 |
|
|
Aug 25 04:46:07 PM UTC 24 |
Aug 25 04:48:08 PM UTC 24 |
7674254243 ps |
| T1879 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random.738231234 |
|
|
Aug 25 04:47:56 PM UTC 24 |
Aug 25 04:48:13 PM UTC 24 |
86864286 ps |
| T1880 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all.867599519 |
|
|
Aug 25 04:47:31 PM UTC 24 |
Aug 25 04:48:21 PM UTC 24 |
489534882 ps |
| T1881 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_random_zero_delays.1949321273 |
|
|
Aug 25 04:47:59 PM UTC 24 |
Aug 25 04:48:26 PM UTC 24 |
202991868 ps |
| T1882 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.146846790 |
|
|
Aug 25 04:46:15 PM UTC 24 |
Aug 25 04:48:30 PM UTC 24 |
5440900062 ps |
| T1883 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_access_same_device.3665045364 |
|
|
Aug 25 04:48:16 PM UTC 24 |
Aug 25 04:48:33 PM UTC 24 |
106051050 ps |
| T1884 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_random_large_delays.152474736 |
|
|
Aug 25 04:43:04 PM UTC 24 |
Aug 25 04:48:34 PM UTC 24 |
23410571736 ps |
| T1885 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all.1235630374 |
|
|
Aug 25 04:44:44 PM UTC 24 |
Aug 25 04:48:43 PM UTC 24 |
4453425573 ps |
| T1886 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all.3496196329 |
|
|
Aug 25 04:43:30 PM UTC 24 |
Aug 25 04:48:51 PM UTC 24 |
6399881321 ps |
| T1887 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all.4107694338 |
|
|
Aug 25 04:42:16 PM UTC 24 |
Aug 25 04:48:53 PM UTC 24 |
6967377518 ps |
| T1888 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1200581152 |
|
|
Aug 25 04:43:32 PM UTC 24 |
Aug 25 04:48:55 PM UTC 24 |
1514962640 ps |
| T1889 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.346279090 |
|
|
Aug 25 04:37:14 PM UTC 24 |
Aug 25 04:48:57 PM UTC 24 |
31496296366 ps |
| T1890 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_unmapped_addr.3921579304 |
|
|
Aug 25 04:48:44 PM UTC 24 |
Aug 25 04:48:58 PM UTC 24 |
162131713 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3591212757 |
|
|
Aug 25 04:36:48 PM UTC 24 |
Aug 25 04:49:10 PM UTC 24 |
6908612779 ps |
| T1891 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke.1386748873 |
|
|
Aug 25 04:50:21 PM UTC 24 |
Aug 25 04:50:35 PM UTC 24 |
201659982 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_same_csr_outstanding.2620976650 |
|
|
Aug 25 04:05:46 PM UTC 24 |
Aug 25 04:49:12 PM UTC 24 |
15530546268 ps |
| T1892 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_error.800739568 |
|
|
Aug 25 04:44:46 PM UTC 24 |
Aug 25 04:49:12 PM UTC 24 |
2770500086 ps |
| T1893 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_random.837173262 |
|
|
Aug 25 04:48:36 PM UTC 24 |
Aug 25 04:49:12 PM UTC 24 |
579949045 ps |
| T1894 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_error_random.1266540346 |
|
|
Aug 25 04:46:55 PM UTC 24 |
Aug 25 04:49:13 PM UTC 24 |
2360069562 ps |
| T1895 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1064737577 |
|
|
Aug 25 04:47:54 PM UTC 24 |
Aug 25 04:49:15 PM UTC 24 |
2970081542 ps |
| T1896 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_same_source.2017126983 |
|
|
Aug 25 04:48:32 PM UTC 24 |
Aug 25 04:49:18 PM UTC 24 |
363390315 ps |
| T1897 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke.1340813698 |
|
|
Aug 25 04:49:15 PM UTC 24 |
Aug 25 04:49:26 PM UTC 24 |
41805053 ps |
| T1898 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_zero_delays.162346133 |
|
|
Aug 25 04:49:15 PM UTC 24 |
Aug 25 04:49:27 PM UTC 24 |
42454248 ps |
| T1899 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2313738008 |
|
|
Aug 25 04:48:49 PM UTC 24 |
Aug 25 04:49:30 PM UTC 24 |
227116979 ps |
| T1900 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_smoke_large_delays.2483420834 |
|
|
Aug 25 04:47:50 PM UTC 24 |
Aug 25 04:49:43 PM UTC 24 |
6724720543 ps |
| T1901 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random.2139924678 |
|
|
Aug 25 04:49:21 PM UTC 24 |
Aug 25 04:49:43 PM UTC 24 |
143903871 ps |
| T1902 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_zero_delays.4012285634 |
|
|
Aug 25 04:49:36 PM UTC 24 |
Aug 25 04:49:57 PM UTC 24 |
133726259 ps |
| T1903 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_same_source.1328005565 |
|
|
Aug 25 04:49:39 PM UTC 24 |
Aug 25 04:50:13 PM UTC 24 |
235478132 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1100469307 |
|
|
Aug 25 04:44:45 PM UTC 24 |
Aug 25 04:50:13 PM UTC 24 |
708351992 ps |
| T1904 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3195002968 |
|
|
Aug 25 04:49:50 PM UTC 24 |
Aug 25 04:50:20 PM UTC 24 |
528416849 ps |
| T1905 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_slow_rsp.2089393275 |
|
|
Aug 25 04:33:11 PM UTC 24 |
Aug 25 04:50:31 PM UTC 24 |
40475995962 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1158574834 |
|
|
Aug 25 04:45:44 PM UTC 24 |
Aug 25 04:50:32 PM UTC 24 |
489657457 ps |
| T1906 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_unmapped_addr.922783402 |
|
|
Aug 25 04:49:42 PM UTC 24 |
Aug 25 04:50:38 PM UTC 24 |
940353587 ps |
| T1907 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_slow_rsp.2741996854 |
|
|
Aug 25 04:40:13 PM UTC 24 |
Aug 25 04:50:45 PM UTC 24 |
25670081373 ps |
| T1908 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1192446061 |
|
|
Aug 25 04:50:37 PM UTC 24 |
Aug 25 04:50:49 PM UTC 24 |
46074813 ps |
| T1909 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_access_same_device.4067658060 |
|
|
Aug 25 04:49:36 PM UTC 24 |
Aug 25 04:50:51 PM UTC 24 |
1286923585 ps |
| T1910 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_error_random.1856401343 |
|
|
Aug 25 04:49:41 PM UTC 24 |
Aug 25 04:50:52 PM UTC 24 |
1264040765 ps |
| T1911 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all.3515968106 |
|
|
Aug 25 04:48:52 PM UTC 24 |
Aug 25 04:50:56 PM UTC 24 |
2523117142 ps |
| T1912 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2207176529 |
|
|
Aug 25 04:49:21 PM UTC 24 |
Aug 25 04:51:03 PM UTC 24 |
4508189974 ps |
| T1913 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_zero_delays.1597296999 |
|
|
Aug 25 04:50:56 PM UTC 24 |
Aug 25 04:51:21 PM UTC 24 |
130961622 ps |
| T1914 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_same_source.2859065531 |
|
|
Aug 25 04:51:16 PM UTC 24 |
Aug 25 04:51:33 PM UTC 24 |
110981224 ps |
| T1915 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_same_csr_outstanding.854297076 |
|
|
Aug 25 04:01:10 PM UTC 24 |
Aug 25 04:51:35 PM UTC 24 |
15220484621 ps |
| T1916 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2990628445 |
|
|
Aug 25 04:51:25 PM UTC 24 |
Aug 25 04:51:36 PM UTC 24 |
43229303 ps |
| T1917 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_smoke_large_delays.3732257952 |
|
|
Aug 25 04:49:19 PM UTC 24 |
Aug 25 04:51:37 PM UTC 24 |
7714439945 ps |
| T1918 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_unmapped_addr.4094353237 |
|
|
Aug 25 04:51:20 PM UTC 24 |
Aug 25 04:51:42 PM UTC 24 |
93816330 ps |
| T1919 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all.2633001896 |
|
|
Aug 25 04:45:42 PM UTC 24 |
Aug 25 04:51:51 PM UTC 24 |
2968732983 ps |
| T1920 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2627021245 |
|
|
Aug 25 04:38:42 PM UTC 24 |
Aug 25 04:52:01 PM UTC 24 |
35744401690 ps |
| T1921 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1106390659 |
|
|
Aug 25 04:53:42 PM UTC 24 |
Aug 25 04:55:55 PM UTC 24 |
5534156388 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1038524777 |
|
|
Aug 25 04:45:19 PM UTC 24 |
Aug 25 04:52:05 PM UTC 24 |
19037918399 ps |
| T1922 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2510849465 |
|
|
Aug 25 04:52:02 PM UTC 24 |
Aug 25 04:52:13 PM UTC 24 |
40645175 ps |
| T1923 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_error_random.268746670 |
|
|
Aug 25 04:51:16 PM UTC 24 |
Aug 25 04:52:15 PM UTC 24 |
571539371 ps |
| T1924 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke.3826345671 |
|
|
Aug 25 04:52:02 PM UTC 24 |
Aug 25 04:52:16 PM UTC 24 |
202828393 ps |
| T1925 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.647068610 |
|
|
Aug 25 04:47:38 PM UTC 24 |
Aug 25 04:52:19 PM UTC 24 |
1730219811 ps |
| T1926 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1081377225 |
|
|
Aug 25 04:31:55 PM UTC 24 |
Aug 25 04:52:23 PM UTC 24 |
57786125490 ps |
| T1927 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random.2620317559 |
|
|
Aug 25 04:50:55 PM UTC 24 |
Aug 25 04:52:26 PM UTC 24 |
2332949852 ps |
| T1928 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1341272749 |
|
|
Aug 25 04:43:14 PM UTC 24 |
Aug 25 04:52:37 PM UTC 24 |
22042722589 ps |
| T1929 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.588326043 |
|
|
Aug 25 04:52:01 PM UTC 24 |
Aug 25 04:52:43 PM UTC 24 |
37679948 ps |
| T1930 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_large_delays.2653487544 |
|
|
Aug 25 04:50:39 PM UTC 24 |
Aug 25 04:52:47 PM UTC 24 |
7688020814 ps |
| T1931 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2232251608 |
|
|
Aug 25 04:50:43 PM UTC 24 |
Aug 25 04:52:48 PM UTC 24 |
5091903301 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2506458284 |
|
|
Aug 25 04:26:21 PM UTC 24 |
Aug 25 04:52:53 PM UTC 24 |
63660438970 ps |
| T1932 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.1843231770 |
|
|
Aug 25 03:28:52 PM UTC 24 |
Aug 25 04:52:54 PM UTC 24 |
28348924715 ps |
| T1933 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random.756794439 |
|
|
Aug 25 04:52:24 PM UTC 24 |
Aug 25 04:52:55 PM UTC 24 |
716402073 ps |
| T1934 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_error.1218298311 |
|
|
Aug 25 04:47:32 PM UTC 24 |
Aug 25 04:52:59 PM UTC 24 |
2743378863 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.597899127 |
|
|
Aug 25 04:40:47 PM UTC 24 |
Aug 25 04:53:01 PM UTC 24 |
4401479263 ps |
| T1935 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_access_same_device.4060358551 |
|
|
Aug 25 04:51:09 PM UTC 24 |
Aug 25 04:53:17 PM UTC 24 |
2337064741 ps |
| T1936 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3659177295 |
|
|
Aug 25 04:49:07 PM UTC 24 |
Aug 25 04:53:18 PM UTC 24 |
1977873406 ps |
| T1937 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_zero_delays.404247099 |
|
|
Aug 25 04:52:28 PM UTC 24 |
Aug 25 04:53:20 PM UTC 24 |
484567015 ps |
| T1938 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3627202560 |
|
|
Aug 25 04:49:54 PM UTC 24 |
Aug 25 04:53:32 PM UTC 24 |
1725729675 ps |
| T1939 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3066972326 |
|
|
Aug 25 04:53:22 PM UTC 24 |
Aug 25 04:53:32 PM UTC 24 |
35183958 ps |
| T1940 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke.3648055337 |
|
|
Aug 25 04:53:19 PM UTC 24 |
Aug 25 04:53:35 PM UTC 24 |
209813375 ps |
| T1941 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all.31322483 |
|
|
Aug 25 04:49:51 PM UTC 24 |
Aug 25 04:53:37 PM UTC 24 |
4540386651 ps |
| T1942 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.55610121 |
|
|
Aug 25 04:51:56 PM UTC 24 |
Aug 25 04:53:41 PM UTC 24 |
156512492 ps |
| T1943 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2566633640 |
|
|
Aug 25 04:53:07 PM UTC 24 |
Aug 25 04:53:41 PM UTC 24 |
644268345 ps |
| T1944 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_error_random.3507522966 |
|
|
Aug 25 04:52:50 PM UTC 24 |
Aug 25 04:53:44 PM UTC 24 |
415972109 ps |
| T1945 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_unmapped_addr.2552251442 |
|
|
Aug 25 04:53:02 PM UTC 24 |
Aug 25 04:53:53 PM UTC 24 |
730007874 ps |
| T1946 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3443749705 |
|
|
Aug 25 04:39:31 PM UTC 24 |
Aug 25 04:53:54 PM UTC 24 |
9232304498 ps |
| T1947 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_error.3660618769 |
|
|
Aug 25 04:50:07 PM UTC 24 |
Aug 25 04:54:01 PM UTC 24 |
4354580146 ps |
| T1948 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.4086526999 |
|
|
Aug 25 04:44:51 PM UTC 24 |
Aug 25 04:54:03 PM UTC 24 |
3182113104 ps |
| T1949 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_same_csr_outstanding.3448505676 |
|
|
Aug 25 04:04:02 PM UTC 24 |
Aug 25 04:55:57 PM UTC 24 |
15160240270 ps |
| T1950 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_random_large_delays.2701579136 |
|
|
Aug 25 04:50:58 PM UTC 24 |
Aug 25 04:54:06 PM UTC 24 |
10544699662 ps |
| T1951 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.73176595 |
|
|
Aug 25 04:53:12 PM UTC 24 |
Aug 25 04:54:18 PM UTC 24 |
111131630 ps |
| T1952 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_same_source.3821858162 |
|
|
Aug 25 04:54:06 PM UTC 24 |
Aug 25 04:54:20 PM UTC 24 |
88176021 ps |
| T1953 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_large_delays.2429549737 |
|
|
Aug 25 04:52:06 PM UTC 24 |
Aug 25 04:54:21 PM UTC 24 |
7221060862 ps |
| T1954 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/31.xbar_random_large_delays.2312539911 |
|
|
Aug 25 04:29:34 PM UTC 24 |
Aug 25 04:54:22 PM UTC 24 |
96985699142 ps |
| T1955 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3863492519 |
|
|
Aug 25 04:42:19 PM UTC 24 |
Aug 25 04:54:24 PM UTC 24 |
7894446291 ps |
| T1956 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_random_large_delays.864493026 |
|
|
Aug 25 04:45:09 PM UTC 24 |
Aug 25 04:54:24 PM UTC 24 |
34992342313 ps |
| T1957 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/42.xbar_random_large_delays.649922068 |
|
|
Aug 25 04:44:18 PM UTC 24 |
Aug 25 04:54:25 PM UTC 24 |
41137457997 ps |
| T1958 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_access_same_device.797798692 |
|
|
Aug 25 04:52:40 PM UTC 24 |
Aug 25 04:54:34 PM UTC 24 |
2393649492 ps |
| T1959 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1447709234 |
|
|
Aug 25 04:52:15 PM UTC 24 |
Aug 25 04:54:35 PM UTC 24 |
6147634768 ps |
| T1960 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_same_source.142125396 |
|
|
Aug 25 04:52:48 PM UTC 24 |
Aug 25 04:54:43 PM UTC 24 |
2389981438 ps |
| T1961 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random.3919427870 |
|
|
Aug 25 04:53:43 PM UTC 24 |
Aug 25 04:54:44 PM UTC 24 |
953649434 ps |
| T1962 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1084500559 |
|
|
Aug 25 04:54:17 PM UTC 24 |
Aug 25 04:54:50 PM UTC 24 |
454547775 ps |
| T1963 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_zero_delays.2332150009 |
|
|
Aug 25 04:53:44 PM UTC 24 |
Aug 25 04:54:50 PM UTC 24 |
473499274 ps |
| T1964 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1715121776 |
|
|
Aug 25 04:54:41 PM UTC 24 |
Aug 25 04:54:51 PM UTC 24 |
39984069 ps |
| T1965 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke.3029328905 |
|
|
Aug 25 04:54:40 PM UTC 24 |
Aug 25 04:54:54 PM UTC 24 |
225531879 ps |
| T1966 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_random_slow_rsp.3692600762 |
|
|
Aug 25 04:49:37 PM UTC 24 |
Aug 25 04:54:58 PM UTC 24 |
14036234893 ps |
| T1967 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_error_random.931425567 |
|
|
Aug 25 04:54:07 PM UTC 24 |
Aug 25 04:55:08 PM UTC 24 |
1088868708 ps |
| T1968 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random_zero_delays.3420635443 |
|
|
Aug 25 04:54:47 PM UTC 24 |
Aug 25 04:55:09 PM UTC 24 |
118631366 ps |
| T1969 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_unmapped_addr.1933364012 |
|
|
Aug 25 04:54:09 PM UTC 24 |
Aug 25 04:55:15 PM UTC 24 |
1087475394 ps |
| T1970 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_access_same_device.3698917853 |
|
|
Aug 25 04:54:00 PM UTC 24 |
Aug 25 04:55:21 PM UTC 24 |
636884983 ps |
| T1971 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_slow_rsp.3815820347 |
|
|
Aug 25 04:37:11 PM UTC 24 |
Aug 25 04:55:27 PM UTC 24 |
47259366720 ps |
| T1972 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_error.4280756400 |
|
|
Aug 25 04:48:55 PM UTC 24 |
Aug 25 04:55:27 PM UTC 24 |
3935528371 ps |
| T1973 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_random.2689896375 |
|
|
Aug 25 04:55:13 PM UTC 24 |
Aug 25 04:55:33 PM UTC 24 |
397170440 ps |
| T1974 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1646228711 |
|
|
Aug 25 04:55:15 PM UTC 24 |
Aug 25 04:55:45 PM UTC 24 |
222347818 ps |
| T1975 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_same_source.4103030557 |
|
|
Aug 25 04:55:07 PM UTC 24 |
Aug 25 04:55:49 PM UTC 24 |
319990163 ps |
| T1976 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_random_slow_rsp.953887205 |
|
|
Aug 25 04:53:57 PM UTC 24 |
Aug 25 04:55:50 PM UTC 24 |
4472965403 ps |
| T1977 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke.323836221 |
|
|
Aug 25 04:55:38 PM UTC 24 |
Aug 25 04:55:51 PM UTC 24 |
208069041 ps |
| T1978 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2924889220 |
|
|
Aug 25 04:55:44 PM UTC 24 |
Aug 25 04:55:54 PM UTC 24 |
52441995 ps |
| T1979 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all.555211164 |
|
|
Aug 25 04:55:16 PM UTC 24 |
Aug 25 05:02:17 PM UTC 24 |
8369175371 ps |
| T1980 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all.2757572033 |
|
|
Aug 25 04:51:44 PM UTC 24 |
Aug 25 04:55:57 PM UTC 24 |
4383986446 ps |
| T1981 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_random.4182829136 |
|
|
Aug 25 04:54:45 PM UTC 24 |
Aug 25 04:56:03 PM UTC 24 |
581794808 ps |
| T1982 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random.501759955 |
|
|
Aug 25 04:55:56 PM UTC 24 |
Aug 25 04:56:11 PM UTC 24 |
67092573 ps |
| T1983 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_slow_rsp.1178294946 |
|
|
Aug 25 04:46:38 PM UTC 24 |
Aug 25 04:56:12 PM UTC 24 |
26555565918 ps |
| T1984 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_unmapped_addr.3673936756 |
|
|
Aug 25 04:55:14 PM UTC 24 |
Aug 25 04:56:14 PM UTC 24 |
887675460 ps |
| T1985 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_smoke_large_delays.470132726 |
|
|
Aug 25 04:53:26 PM UTC 24 |
Aug 25 04:56:19 PM UTC 24 |
10313048893 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3301853666 |
|
|
Aug 25 04:47:31 PM UTC 24 |
Aug 25 04:56:26 PM UTC 24 |
5590029406 ps |
| T1986 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_access_same_device.2721866256 |
|
|
Aug 25 04:54:58 PM UTC 24 |
Aug 25 04:56:36 PM UTC 24 |
1609405947 ps |
| T1987 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2875594082 |
|
|
Aug 25 04:56:22 PM UTC 24 |
Aug 25 04:56:37 PM UTC 24 |
178003838 ps |
| T1988 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/49.xbar_stress_all.2977133556 |
|
|
Aug 25 04:54:18 PM UTC 24 |
Aug 25 04:56:39 PM UTC 24 |
942897896 ps |
| T1989 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3177929179 |
|
|
Aug 25 04:54:44 PM UTC 24 |
Aug 25 04:56:41 PM UTC 24 |
5399192159 ps |
| T1990 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_random_zero_delays.3017187725 |
|
|
Aug 25 04:56:00 PM UTC 24 |
Aug 25 04:56:51 PM UTC 24 |
460685395 ps |
| T1991 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke.2756415275 |
|
|
Aug 25 04:56:41 PM UTC 24 |
Aug 25 04:56:54 PM UTC 24 |
229677696 ps |
| T1992 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_access_same_device.400622975 |
|
|
Aug 25 04:56:15 PM UTC 24 |
Aug 25 04:56:59 PM UTC 24 |
697470733 ps |
| T1993 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_smoke_large_delays.3658121793 |
|
|
Aug 25 04:54:43 PM UTC 24 |
Aug 25 04:56:59 PM UTC 24 |
8623091107 ps |
| T1994 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1376565948 |
|
|
Aug 25 04:56:50 PM UTC 24 |
Aug 25 04:56:59 PM UTC 24 |
45092738 ps |
| T1995 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_error_random.385208152 |
|
|
Aug 25 04:56:18 PM UTC 24 |
Aug 25 04:57:18 PM UTC 24 |
551716467 ps |
| T1996 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random_zero_delays.1038176194 |
|
|
Aug 25 04:57:04 PM UTC 24 |
Aug 25 04:57:20 PM UTC 24 |
106578876 ps |
| T1997 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_same_source.3589347749 |
|
|
Aug 25 04:56:19 PM UTC 24 |
Aug 25 04:57:27 PM UTC 24 |
554504249 ps |
| T1998 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.394389107 |
|
|
Aug 25 04:48:55 PM UTC 24 |
Aug 25 04:57:30 PM UTC 24 |
1212567133 ps |
| T1999 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_same_source.4255412021 |
|
|
Aug 25 04:57:23 PM UTC 24 |
Aug 25 04:57:35 PM UTC 24 |
75196537 ps |
| T2000 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_unmapped_addr.693569756 |
|
|
Aug 25 04:56:20 PM UTC 24 |
Aug 25 04:57:36 PM UTC 24 |
1080756666 ps |
| T2001 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_large_delays.2950915564 |
|
|
Aug 25 04:55:51 PM UTC 24 |
Aug 25 04:57:38 PM UTC 24 |
7747356861 ps |
| T2002 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/39.xbar_random_large_delays.1429023540 |
|
|
Aug 25 04:40:08 PM UTC 24 |
Aug 25 04:57:44 PM UTC 24 |
70181916293 ps |
| T2003 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_error.2594389066 |
|
|
Aug 25 04:55:32 PM UTC 24 |
Aug 25 04:57:49 PM UTC 24 |
2461521802 ps |
| T2004 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_random.3918877708 |
|
|
Aug 25 04:57:39 PM UTC 24 |
Aug 25 04:57:51 PM UTC 24 |
86117722 ps |
| T2005 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.531503885 |
|
|
Aug 25 04:39:23 PM UTC 24 |
Aug 25 04:57:56 PM UTC 24 |
14690044113 ps |
| T2006 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_unmapped_addr.2252292794 |
|
|
Aug 25 04:57:45 PM UTC 24 |
Aug 25 04:58:17 PM UTC 24 |
178035991 ps |
| T2007 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1461493430 |
|
|
Aug 25 04:57:01 PM UTC 24 |
Aug 25 04:58:17 PM UTC 24 |
3246262541 ps |
| T2008 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke.2783981926 |
|
|
Aug 25 04:58:08 PM UTC 24 |
Aug 25 04:58:20 PM UTC 24 |
48056795 ps |
| T2009 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.3083217494 |
|
|
Aug 25 04:52:00 PM UTC 24 |
Aug 25 04:58:21 PM UTC 24 |
4124220792 ps |
| T2010 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1401784401 |
|
|
Aug 25 04:58:13 PM UTC 24 |
Aug 25 04:58:24 PM UTC 24 |
54226450 ps |
| T2011 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_stress_all_with_error.2166734468 |
|
|
Aug 25 04:56:36 PM UTC 24 |
Aug 25 04:58:30 PM UTC 24 |
1904769722 ps |
| T2012 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/48.xbar_random_large_delays.2940021273 |
|
|
Aug 25 04:52:38 PM UTC 24 |
Aug 25 04:58:32 PM UTC 24 |
21020155177 ps |
| T2013 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_smoke_large_delays.2402762759 |
|
|
Aug 25 04:57:00 PM UTC 24 |
Aug 25 04:58:33 PM UTC 24 |
4842448766 ps |
| T2014 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/34.xbar_random_large_delays.4053121807 |
|
|
Aug 25 04:33:05 PM UTC 24 |
Aug 25 04:58:34 PM UTC 24 |
114049104472 ps |
| T2015 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3835343978 |
|
|
Aug 25 04:45:51 PM UTC 24 |
Aug 25 04:58:39 PM UTC 24 |
11320522929 ps |
| T2016 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/44.xbar_random_large_delays.2796983106 |
|
|
Aug 25 04:46:31 PM UTC 24 |
Aug 25 04:58:43 PM UTC 24 |
48434505937 ps |
| T2017 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1009320771 |
|
|
Aug 25 04:55:48 PM UTC 24 |
Aug 25 04:58:48 PM UTC 24 |
6685724774 ps |
| T2018 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2376873325 |
|
|
Aug 25 04:57:51 PM UTC 24 |
Aug 25 04:58:48 PM UTC 24 |
839304792 ps |
| T2019 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.16612648 |
|
|
Aug 25 04:50:09 PM UTC 24 |
Aug 25 04:58:49 PM UTC 24 |
6601633903 ps |
| T2020 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_random.1206410816 |
|
|
Aug 25 04:57:01 PM UTC 24 |
Aug 25 04:58:53 PM UTC 24 |
2264596721 ps |
| T2021 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2089777064 |
|
|
Aug 25 04:55:21 PM UTC 24 |
Aug 25 04:59:04 PM UTC 24 |
256566244 ps |
| T2022 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/52.xbar_access_same_device.982160551 |
|
|
Aug 25 04:57:21 PM UTC 24 |
Aug 25 04:59:09 PM UTC 24 |
2127479412 ps |
| T2023 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.339996989 |
|
|
Aug 25 04:37:33 PM UTC 24 |
Aug 25 04:59:12 PM UTC 24 |
7344005044 ps |
| T2024 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/37.xbar_random_large_delays.2830358823 |
|
|
Aug 25 04:37:04 PM UTC 24 |
Aug 25 04:59:17 PM UTC 24 |
78892949862 ps |
| T2025 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/53.xbar_unmapped_addr.4217532133 |
|
|
Aug 25 04:58:57 PM UTC 24 |
Aug 25 04:59:19 PM UTC 24 |
126845420 ps |