| T599 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.2303724410 |
|
|
Aug 25 03:48:50 PM UTC 24 |
Aug 25 03:55:08 PM UTC 24 |
3769791792 ps |
| T1426 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3393059080 |
|
|
Aug 25 03:40:51 PM UTC 24 |
Aug 25 03:55:08 PM UTC 24 |
7307894201 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4283973218 |
|
|
Aug 25 03:50:37 PM UTC 24 |
Aug 25 03:55:12 PM UTC 24 |
548600414 ps |
| T1427 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2713246973 |
|
|
Aug 25 03:53:06 PM UTC 24 |
Aug 25 03:55:13 PM UTC 24 |
5434659594 ps |
| T1428 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1886222408 |
|
|
Aug 25 03:53:07 PM UTC 24 |
Aug 25 03:55:19 PM UTC 24 |
2224568851 ps |
| T1429 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1460275147 |
|
|
Aug 25 03:28:52 PM UTC 24 |
Aug 25 03:55:31 PM UTC 24 |
11294315052 ps |
| T1430 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke.785210841 |
|
|
Aug 25 03:55:15 PM UTC 24 |
Aug 25 03:55:31 PM UTC 24 |
204536962 ps |
| T1431 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2550703610 |
|
|
Aug 25 03:55:22 PM UTC 24 |
Aug 25 03:55:34 PM UTC 24 |
57149853 ps |
| T1432 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_large_delays.4124717853 |
|
|
Aug 25 03:39:29 PM UTC 24 |
Aug 25 03:55:36 PM UTC 24 |
57840513293 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.248544038 |
|
|
Aug 25 03:54:51 PM UTC 24 |
Aug 25 03:55:40 PM UTC 24 |
164287117 ps |
| T1433 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_large_delays.709188815 |
|
|
Aug 25 03:53:02 PM UTC 24 |
Aug 25 03:55:50 PM UTC 24 |
9896665990 ps |
| T1434 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device.1254634110 |
|
|
Aug 25 03:55:36 PM UTC 24 |
Aug 25 03:55:58 PM UTC 24 |
237369951 ps |
| T1435 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.3006557153 |
|
|
Aug 25 03:28:47 PM UTC 24 |
Aug 25 03:55:58 PM UTC 24 |
104164960719 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all.3114878643 |
|
|
Aug 25 03:38:13 PM UTC 24 |
Aug 25 03:56:00 PM UTC 24 |
19281600714 ps |
| T1436 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.308642232 |
|
|
Aug 25 03:55:58 PM UTC 24 |
Aug 25 03:56:06 PM UTC 24 |
22623335 ps |
| T1437 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_error_random.3032965966 |
|
|
Aug 25 03:55:51 PM UTC 24 |
Aug 25 03:56:09 PM UTC 24 |
94353223 ps |
| T1438 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_unmapped_addr.1011310263 |
|
|
Aug 25 03:55:58 PM UTC 24 |
Aug 25 03:56:10 PM UTC 24 |
44012506 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_zero_delays.2262012433 |
|
|
Aug 25 03:55:31 PM UTC 24 |
Aug 25 03:56:12 PM UTC 24 |
288978840 ps |
| T1439 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_same_source.3559365446 |
|
|
Aug 25 03:55:54 PM UTC 24 |
Aug 25 03:56:23 PM UTC 24 |
643003979 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_slow_rsp.957724882 |
|
|
Aug 25 03:37:14 PM UTC 24 |
Aug 25 03:56:27 PM UTC 24 |
45514045002 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_rw.2515046995 |
|
|
Aug 25 03:46:22 PM UTC 24 |
Aug 25 03:56:37 PM UTC 24 |
3881651187 ps |
| T1440 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke.3861770011 |
|
|
Aug 25 03:56:37 PM UTC 24 |
Aug 25 03:56:54 PM UTC 24 |
247765248 ps |
| T1441 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2750145147 |
|
|
Aug 25 03:56:46 PM UTC 24 |
Aug 25 03:56:57 PM UTC 24 |
43065302 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.4246858410 |
|
|
Aug 25 03:50:17 PM UTC 24 |
Aug 25 03:57:02 PM UTC 24 |
3408286558 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3078342010 |
|
|
Aug 25 03:48:38 PM UTC 24 |
Aug 25 03:57:06 PM UTC 24 |
9402017714 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random.168513807 |
|
|
Aug 25 03:55:28 PM UTC 24 |
Aug 25 03:57:18 PM UTC 24 |
2043605961 ps |
| T1442 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1458972003 |
|
|
Aug 25 03:55:26 PM UTC 24 |
Aug 25 03:57:25 PM UTC 24 |
5052863133 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all.2373582636 |
|
|
Aug 25 03:56:04 PM UTC 24 |
Aug 25 03:57:27 PM UTC 24 |
529509059 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.2112804765 |
|
|
Aug 25 03:40:47 PM UTC 24 |
Aug 25 03:57:30 PM UTC 24 |
5706589000 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_smoke_large_delays.1788825108 |
|
|
Aug 25 03:55:24 PM UTC 24 |
Aug 25 03:57:41 PM UTC 24 |
8089092346 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all.3253548048 |
|
|
Aug 25 03:54:31 PM UTC 24 |
Aug 25 03:57:47 PM UTC 24 |
3702707468 ps |
| T1443 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2868603494 |
|
|
Aug 25 03:44:43 PM UTC 24 |
Aug 25 03:58:04 PM UTC 24 |
6624520170 ps |
| T1444 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_zero_delays.2277779827 |
|
|
Aug 25 03:57:21 PM UTC 24 |
Aug 25 03:58:06 PM UTC 24 |
367915224 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1382897216 |
|
|
Aug 25 03:52:02 PM UTC 24 |
Aug 25 03:58:14 PM UTC 24 |
8589839156 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_same_source.2186633190 |
|
|
Aug 25 03:57:51 PM UTC 24 |
Aug 25 03:58:37 PM UTC 24 |
421530605 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.4076172009 |
|
|
Aug 25 03:48:42 PM UTC 24 |
Aug 25 03:58:45 PM UTC 24 |
4055262469 ps |
| T1445 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2217415566 |
|
|
Aug 25 03:58:10 PM UTC 24 |
Aug 25 03:58:47 PM UTC 24 |
589834634 ps |
| T1446 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.1604647202 |
|
|
Aug 25 03:47:36 PM UTC 24 |
Aug 25 03:58:52 PM UTC 24 |
29897215329 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all.2719274567 |
|
|
Aug 25 03:46:07 PM UTC 24 |
Aug 25 03:58:53 PM UTC 24 |
12978080837 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random.3554300658 |
|
|
Aug 25 03:57:19 PM UTC 24 |
Aug 25 03:58:54 PM UTC 24 |
1792429406 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2302217877 |
|
|
Aug 25 03:50:12 PM UTC 24 |
Aug 25 03:58:55 PM UTC 24 |
9579025985 ps |
| T1447 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_unmapped_addr.3841686277 |
|
|
Aug 25 03:58:04 PM UTC 24 |
Aug 25 03:58:55 PM UTC 24 |
745093736 ps |
| T1448 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.890812320 |
|
|
Aug 25 03:57:01 PM UTC 24 |
Aug 25 03:59:06 PM UTC 24 |
5033266298 ps |
| T1449 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_smoke_large_delays.2548915880 |
|
|
Aug 25 03:56:50 PM UTC 24 |
Aug 25 03:59:14 PM UTC 24 |
8618615763 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_error.1037350123 |
|
|
Aug 25 03:54:56 PM UTC 24 |
Aug 25 03:59:18 PM UTC 24 |
2099002507 ps |
| T1450 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1691596066 |
|
|
Aug 25 03:59:00 PM UTC 24 |
Aug 25 03:59:20 PM UTC 24 |
43243916 ps |
| T1451 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_error.915478213 |
|
|
Aug 25 03:56:21 PM UTC 24 |
Aug 25 03:59:21 PM UTC 24 |
1396287264 ps |
| T1452 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_zero_delays.4105380852 |
|
|
Aug 25 03:59:19 PM UTC 24 |
Aug 25 03:59:29 PM UTC 24 |
46717231 ps |
| T1453 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke.1620722306 |
|
|
Aug 25 03:59:19 PM UTC 24 |
Aug 25 03:59:34 PM UTC 24 |
173145837 ps |
| T1454 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.1657134827 |
|
|
Aug 25 03:51:26 PM UTC 24 |
Aug 25 03:59:45 PM UTC 24 |
22254366572 ps |
| T1455 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random.4161416521 |
|
|
Aug 25 03:59:40 PM UTC 24 |
Aug 25 03:59:52 PM UTC 24 |
44771831 ps |
| T1456 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_error_random.2936577466 |
|
|
Aug 25 03:57:53 PM UTC 24 |
Aug 25 03:59:57 PM UTC 24 |
2203886027 ps |
| T1457 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_zero_delays.342692432 |
|
|
Aug 25 03:59:43 PM UTC 24 |
Aug 25 03:59:59 PM UTC 24 |
84963398 ps |
| T1458 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device.2601184134 |
|
|
Aug 25 03:59:52 PM UTC 24 |
Aug 25 04:00:06 PM UTC 24 |
63722860 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3723572005 |
|
|
Aug 25 03:32:44 PM UTC 24 |
Aug 25 04:00:31 PM UTC 24 |
79186797631 ps |
| T1459 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_unmapped_addr.3480009339 |
|
|
Aug 25 04:00:20 PM UTC 24 |
Aug 25 04:00:32 PM UTC 24 |
41445495 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.3838670720 |
|
|
Aug 25 03:52:52 PM UTC 24 |
Aug 25 04:00:33 PM UTC 24 |
3613346504 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_slow_rsp.3061913308 |
|
|
Aug 25 03:41:21 PM UTC 24 |
Aug 25 04:00:43 PM UTC 24 |
45225724997 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_random.2496609824 |
|
|
Aug 25 04:00:15 PM UTC 24 |
Aug 25 04:00:44 PM UTC 24 |
225619436 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1783270460 |
|
|
Aug 25 03:50:39 PM UTC 24 |
Aug 25 04:00:46 PM UTC 24 |
4589516090 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.3293790604 |
|
|
Aug 25 03:49:44 PM UTC 24 |
Aug 25 04:01:14 PM UTC 24 |
29851963831 ps |
| T1460 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_large_delays.143229880 |
|
|
Aug 25 03:45:35 PM UTC 24 |
Aug 25 04:01:16 PM UTC 24 |
53597040944 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device.1413986101 |
|
|
Aug 25 03:57:43 PM UTC 24 |
Aug 25 04:01:22 PM UTC 24 |
3387114878 ps |
| T1461 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1600212381 |
|
|
Aug 25 04:00:22 PM UTC 24 |
Aug 25 04:01:48 PM UTC 24 |
1291913387 ps |
| T1462 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke.2068162227 |
|
|
Aug 25 04:01:39 PM UTC 24 |
Aug 25 04:01:49 PM UTC 24 |
49273749 ps |
| T1463 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3589330728 |
|
|
Aug 25 03:58:29 PM UTC 24 |
Aug 25 04:01:53 PM UTC 24 |
288020778 ps |
| T1464 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1346204750 |
|
|
Aug 25 03:59:31 PM UTC 24 |
Aug 25 04:01:55 PM UTC 24 |
6042716663 ps |
| T1465 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1990345668 |
|
|
Aug 25 04:01:44 PM UTC 24 |
Aug 25 04:01:55 PM UTC 24 |
42198883 ps |
| T1466 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_smoke_large_delays.3714598994 |
|
|
Aug 25 03:59:19 PM UTC 24 |
Aug 25 04:01:59 PM UTC 24 |
9272462593 ps |
| T1467 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_same_source.756418772 |
|
|
Aug 25 04:00:09 PM UTC 24 |
Aug 25 04:02:01 PM UTC 24 |
2191418134 ps |
| T1468 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.740950596 |
|
|
Aug 25 04:00:55 PM UTC 24 |
Aug 25 04:02:12 PM UTC 24 |
57280519 ps |
| T1469 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_error.2319718438 |
|
|
Aug 25 04:00:55 PM UTC 24 |
Aug 25 04:02:25 PM UTC 24 |
1797178281 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_tl_errors.2061608972 |
|
|
Aug 25 03:56:34 PM UTC 24 |
Aug 25 04:02:34 PM UTC 24 |
3702933733 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.273030310 |
|
|
Aug 25 03:30:28 PM UTC 24 |
Aug 25 04:02:46 PM UTC 24 |
115636123424 ps |
| T1470 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3506827195 |
|
|
Aug 25 03:52:46 PM UTC 24 |
Aug 25 04:02:51 PM UTC 24 |
6417690420 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_zero_delays.770085983 |
|
|
Aug 25 04:02:20 PM UTC 24 |
Aug 25 04:02:57 PM UTC 24 |
297259393 ps |
| T1471 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_slow_rsp.504989532 |
|
|
Aug 25 03:45:43 PM UTC 24 |
Aug 25 04:03:02 PM UTC 24 |
49195861018 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_tl_errors.657430208 |
|
|
Aug 25 03:55:14 PM UTC 24 |
Aug 25 04:03:04 PM UTC 24 |
4939320003 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.263973351 |
|
|
Aug 25 03:35:18 PM UTC 24 |
Aug 25 04:03:05 PM UTC 24 |
73884842419 ps |
| T1472 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random.358749785 |
|
|
Aug 25 04:02:17 PM UTC 24 |
Aug 25 04:03:13 PM UTC 24 |
1346861958 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.67894987 |
|
|
Aug 25 03:37:20 PM UTC 24 |
Aug 25 04:03:35 PM UTC 24 |
58082244749 ps |
| T1473 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3141317413 |
|
|
Aug 25 04:03:14 PM UTC 24 |
Aug 25 04:03:38 PM UTC 24 |
343058465 ps |
| T1474 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_same_source.48998040 |
|
|
Aug 25 04:02:48 PM UTC 24 |
Aug 25 04:03:39 PM UTC 24 |
932028621 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1063199122 |
|
|
Aug 25 03:57:47 PM UTC 24 |
Aug 25 04:03:41 PM UTC 24 |
13819707957 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2918140978 |
|
|
Aug 25 03:47:35 PM UTC 24 |
Aug 25 04:03:42 PM UTC 24 |
62072806698 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device.3126170010 |
|
|
Aug 25 04:02:25 PM UTC 24 |
Aug 25 04:03:52 PM UTC 24 |
1445538394 ps |
| T1475 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_unmapped_addr.1890305274 |
|
|
Aug 25 04:03:11 PM UTC 24 |
Aug 25 04:03:55 PM UTC 24 |
258067945 ps |
| T1476 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_error_random.1837227388 |
|
|
Aug 25 04:02:59 PM UTC 24 |
Aug 25 04:04:13 PM UTC 24 |
555942670 ps |
| T1477 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1688582742 |
|
|
Aug 25 04:04:06 PM UTC 24 |
Aug 25 04:04:17 PM UTC 24 |
45999280 ps |
| T1478 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke.731651920 |
|
|
Aug 25 04:04:05 PM UTC 24 |
Aug 25 04:04:17 PM UTC 24 |
59003742 ps |
| T1479 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3317366609 |
|
|
Aug 25 03:55:02 PM UTC 24 |
Aug 25 04:04:25 PM UTC 24 |
3927369688 ps |
| T1480 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.467268294 |
|
|
Aug 25 04:02:13 PM UTC 24 |
Aug 25 04:04:25 PM UTC 24 |
5031356629 ps |
| T1481 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1760984233 |
|
|
Aug 25 03:50:44 PM UTC 24 |
Aug 25 04:04:32 PM UTC 24 |
6460583276 ps |
| T1482 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_tl_errors.2881118166 |
|
|
Aug 25 04:01:38 PM UTC 24 |
Aug 25 04:04:34 PM UTC 24 |
3025209748 ps |
| T1483 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_smoke_large_delays.4283230760 |
|
|
Aug 25 04:02:11 PM UTC 24 |
Aug 25 04:04:44 PM UTC 24 |
8910175020 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.705697893 |
|
|
Aug 25 04:03:25 PM UTC 24 |
Aug 25 04:04:44 PM UTC 24 |
219647785 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1094500318 |
|
|
Aug 25 03:48:41 PM UTC 24 |
Aug 25 04:04:56 PM UTC 24 |
14727107217 ps |
| T1484 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.403788483 |
|
|
Aug 25 03:55:09 PM UTC 24 |
Aug 25 04:04:58 PM UTC 24 |
6237943768 ps |
| T1485 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random.4155879867 |
|
|
Aug 25 04:04:37 PM UTC 24 |
Aug 25 04:05:01 PM UTC 24 |
163531480 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3699228600 |
|
|
Aug 25 04:00:57 PM UTC 24 |
Aug 25 04:05:02 PM UTC 24 |
556659398 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1948892554 |
|
|
Aug 25 03:54:59 PM UTC 24 |
Aug 25 04:05:12 PM UTC 24 |
8056101845 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all.2720086309 |
|
|
Aug 25 03:58:28 PM UTC 24 |
Aug 25 04:05:17 PM UTC 24 |
7601281902 ps |
| T1486 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_unmapped_addr.982490813 |
|
|
Aug 25 04:05:07 PM UTC 24 |
Aug 25 04:05:23 PM UTC 24 |
57676053 ps |
| T1487 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3829274227 |
|
|
Aug 25 03:53:34 PM UTC 24 |
Aug 25 04:05:23 PM UTC 24 |
38901960463 ps |
| T1488 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4057174454 |
|
|
Aug 25 04:05:19 PM UTC 24 |
Aug 25 04:05:28 PM UTC 24 |
54236744 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_slow_rsp.65451326 |
|
|
Aug 25 03:53:43 PM UTC 24 |
Aug 25 04:05:38 PM UTC 24 |
29312385622 ps |
| T1489 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_slow_rsp.2367704292 |
|
|
Aug 25 03:55:35 PM UTC 24 |
Aug 25 04:05:44 PM UTC 24 |
28270904008 ps |
| T1490 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_random_large_delays.2906602782 |
|
|
Aug 25 03:55:32 PM UTC 24 |
Aug 25 04:05:45 PM UTC 24 |
43730460160 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3536494760 |
|
|
Aug 25 04:05:24 PM UTC 24 |
Aug 25 04:05:53 PM UTC 24 |
37490035 ps |
| T1491 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_random_zero_delays.3947194989 |
|
|
Aug 25 04:04:40 PM UTC 24 |
Aug 25 04:05:56 PM UTC 24 |
520947503 ps |
| T1492 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_error_random.485852382 |
|
|
Aug 25 04:05:09 PM UTC 24 |
Aug 25 04:05:59 PM UTC 24 |
1071200730 ps |
| T1493 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3834589892 |
|
|
Aug 25 04:04:17 PM UTC 24 |
Aug 25 04:06:00 PM UTC 24 |
5860318258 ps |
| T1494 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke.1991774357 |
|
|
Aug 25 04:05:58 PM UTC 24 |
Aug 25 04:06:09 PM UTC 24 |
46580630 ps |
| T1495 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_same_source.721221890 |
|
|
Aug 25 04:04:58 PM UTC 24 |
Aug 25 04:06:16 PM UTC 24 |
1538303883 ps |
| T1496 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3936945660 |
|
|
Aug 25 04:06:06 PM UTC 24 |
Aug 25 04:06:17 PM UTC 24 |
47263475 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device.3565414139 |
|
|
Aug 25 04:04:50 PM UTC 24 |
Aug 25 04:06:23 PM UTC 24 |
1325400014 ps |
| T1497 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_smoke_large_delays.1550272709 |
|
|
Aug 25 04:04:15 PM UTC 24 |
Aug 25 04:06:35 PM UTC 24 |
8507418162 ps |
| T1498 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random_zero_delays.3252772866 |
|
|
Aug 25 04:06:22 PM UTC 24 |
Aug 25 04:06:49 PM UTC 24 |
147115445 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3612141622 |
|
|
Aug 25 04:03:18 PM UTC 24 |
Aug 25 04:06:58 PM UTC 24 |
1932540149 ps |
| T1499 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.chip_csr_rw.138055288 |
|
|
Aug 25 03:59:10 PM UTC 24 |
Aug 25 04:07:11 PM UTC 24 |
4459536790 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_same_csr_outstanding.2748719787 |
|
|
Aug 25 03:31:45 PM UTC 24 |
Aug 25 04:07:21 PM UTC 24 |
15199554581 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device.1070299903 |
|
|
Aug 25 04:06:39 PM UTC 24 |
Aug 25 04:07:22 PM UTC 24 |
541942969 ps |
| T1500 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2194419200 |
|
|
Aug 25 04:07:20 PM UTC 24 |
Aug 25 04:07:35 PM UTC 24 |
152009698 ps |
| T1501 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_random.3154222596 |
|
|
Aug 25 04:06:18 PM UTC 24 |
Aug 25 04:07:42 PM UTC 24 |
508562808 ps |
| T1502 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_random_slow_rsp.2163977443 |
|
|
Aug 25 03:59:45 PM UTC 24 |
Aug 25 04:07:43 PM UTC 24 |
21830284754 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_same_source.1919519982 |
|
|
Aug 25 04:06:46 PM UTC 24 |
Aug 25 04:07:51 PM UTC 24 |
515423092 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1618623355 |
|
|
Aug 25 03:41:23 PM UTC 24 |
Aug 25 04:08:05 PM UTC 24 |
70449144690 ps |
| T1503 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_unmapped_addr.2460773872 |
|
|
Aug 25 04:07:12 PM UTC 24 |
Aug 25 04:08:06 PM UTC 24 |
250638310 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.872476680 |
|
|
Aug 25 04:05:23 PM UTC 24 |
Aug 25 04:08:10 PM UTC 24 |
1169502575 ps |
| T1504 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1680136903 |
|
|
Aug 25 04:06:15 PM UTC 24 |
Aug 25 04:08:22 PM UTC 24 |
5667075171 ps |
| T1505 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke.2990569604 |
|
|
Aug 25 04:08:29 PM UTC 24 |
Aug 25 04:08:42 PM UTC 24 |
137528178 ps |
| T1506 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2073495191 |
|
|
Aug 25 04:08:31 PM UTC 24 |
Aug 25 04:08:42 PM UTC 24 |
42640731 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2711242943 |
|
|
Aug 25 03:43:29 PM UTC 24 |
Aug 25 04:08:51 PM UTC 24 |
68698527722 ps |
| T1507 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_error_random.3376545177 |
|
|
Aug 25 04:06:58 PM UTC 24 |
Aug 25 04:08:52 PM UTC 24 |
2257740783 ps |
| T1508 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_smoke_large_delays.2917815092 |
|
|
Aug 25 04:06:07 PM UTC 24 |
Aug 25 04:08:54 PM UTC 24 |
9659519625 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1610182589 |
|
|
Aug 25 03:56:22 PM UTC 24 |
Aug 25 04:08:59 PM UTC 24 |
7672413261 ps |
| T1509 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3245052001 |
|
|
Aug 25 04:07:46 PM UTC 24 |
Aug 25 04:09:10 PM UTC 24 |
158777069 ps |
| T1510 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_stress_all_with_error.99008324 |
|
|
Aug 25 03:58:38 PM UTC 24 |
Aug 25 04:09:16 PM UTC 24 |
14785293222 ps |
| T1511 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random.760727581 |
|
|
Aug 25 04:09:06 PM UTC 24 |
Aug 25 04:09:33 PM UTC 24 |
383154148 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_stress_all.3750558001 |
|
|
Aug 25 04:00:31 PM UTC 24 |
Aug 25 04:09:54 PM UTC 24 |
11207676701 ps |
| T1512 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_access_same_device.2692349916 |
|
|
Aug 25 04:09:18 PM UTC 24 |
Aug 25 04:09:55 PM UTC 24 |
266444701 ps |
| T1513 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3800613265 |
|
|
Aug 25 03:48:43 PM UTC 24 |
Aug 25 04:10:08 PM UTC 24 |
11507995046 ps |
| T1514 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3854333534 |
|
|
Aug 25 04:07:59 PM UTC 24 |
Aug 25 04:10:09 PM UTC 24 |
400358455 ps |
| T1515 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_zero_delays.62624454 |
|
|
Aug 25 04:09:07 PM UTC 24 |
Aug 25 04:10:11 PM UTC 24 |
434802929 ps |
| T1516 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_same_source.585038245 |
|
|
Aug 25 04:09:35 PM UTC 24 |
Aug 25 04:10:16 PM UTC 24 |
860640580 ps |
| T1517 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3496874791 |
|
|
Aug 25 03:52:08 PM UTC 24 |
Aug 25 04:10:22 PM UTC 24 |
5789546478 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_tl_errors.3172786653 |
|
|
Aug 25 03:59:17 PM UTC 24 |
Aug 25 04:10:35 PM UTC 24 |
4646899478 ps |
| T1518 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_unmapped_addr.1331954994 |
|
|
Aug 25 04:09:58 PM UTC 24 |
Aug 25 04:10:42 PM UTC 24 |
204726040 ps |
| T1519 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke.778260740 |
|
|
Aug 25 04:10:43 PM UTC 24 |
Aug 25 04:10:56 PM UTC 24 |
180794163 ps |
| T1520 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_large_delays.3123827320 |
|
|
Aug 25 04:08:34 PM UTC 24 |
Aug 25 04:10:59 PM UTC 24 |
8962292441 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.908798995 |
|
|
Aug 25 03:59:58 PM UTC 24 |
Aug 25 04:11:00 PM UTC 24 |
25979511314 ps |
| T1521 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_random.3390207410 |
|
|
Aug 25 04:09:40 PM UTC 24 |
Aug 25 04:11:03 PM UTC 24 |
560327185 ps |
| T1522 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_slow_rsp.3521649379 |
|
|
Aug 25 03:43:29 PM UTC 24 |
Aug 25 04:11:05 PM UTC 24 |
68633969599 ps |
| T1523 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2834233021 |
|
|
Aug 25 04:08:47 PM UTC 24 |
Aug 25 04:11:07 PM UTC 24 |
6251896889 ps |
| T1524 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_zero_delays.365790381 |
|
|
Aug 25 04:10:58 PM UTC 24 |
Aug 25 04:11:08 PM UTC 24 |
39801069 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_tl_errors.3301780134 |
|
|
Aug 25 04:05:52 PM UTC 24 |
Aug 25 04:11:24 PM UTC 24 |
2950470452 ps |
| T1525 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2564334565 |
|
|
Aug 25 04:10:18 PM UTC 24 |
Aug 25 04:11:35 PM UTC 24 |
1417074367 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1199681382 |
|
|
Aug 25 03:48:38 PM UTC 24 |
Aug 25 04:11:37 PM UTC 24 |
22710579912 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1451639178 |
|
|
Aug 25 03:51:31 PM UTC 24 |
Aug 25 04:11:43 PM UTC 24 |
48059808163 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.chip_tl_errors.3691160852 |
|
|
Aug 25 04:08:16 PM UTC 24 |
Aug 25 04:11:46 PM UTC 24 |
2813493636 ps |
| T1526 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_zero_delays.4062063759 |
|
|
Aug 25 04:11:24 PM UTC 24 |
Aug 25 04:11:47 PM UTC 24 |
107104648 ps |
| T1527 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random.651184933 |
|
|
Aug 25 04:11:23 PM UTC 24 |
Aug 25 04:12:15 PM UTC 24 |
347402860 ps |
| T1528 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_random.2798349716 |
|
|
Aug 25 04:11:59 PM UTC 24 |
Aug 25 04:12:32 PM UTC 24 |
212922297 ps |
| T1529 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_random_slow_rsp.537938143 |
|
|
Aug 25 04:11:29 PM UTC 24 |
Aug 25 04:12:32 PM UTC 24 |
3328584086 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_error.3659611439 |
|
|
Aug 25 04:03:25 PM UTC 24 |
Aug 25 04:12:44 PM UTC 24 |
10082515108 ps |
| T1530 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_same_source.1981246516 |
|
|
Aug 25 04:11:48 PM UTC 24 |
Aug 25 04:12:45 PM UTC 24 |
1101319907 ps |
| T1531 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_large_delays.1926134446 |
|
|
Aug 25 04:11:06 PM UTC 24 |
Aug 25 04:12:58 PM UTC 24 |
6968015664 ps |
| T1532 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_rw.1687431255 |
|
|
Aug 25 03:56:24 PM UTC 24 |
Aug 25 04:12:59 PM UTC 24 |
6282037325 ps |
| T1533 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2580483706 |
|
|
Aug 25 03:46:25 PM UTC 24 |
Aug 25 04:13:00 PM UTC 24 |
8373682349 ps |
| T1534 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1307452716 |
|
|
Aug 25 04:12:07 PM UTC 24 |
Aug 25 04:13:02 PM UTC 24 |
989718166 ps |
| T1535 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_unmapped_addr.887089188 |
|
|
Aug 25 04:12:02 PM UTC 24 |
Aug 25 04:13:07 PM UTC 24 |
879879346 ps |
| T1536 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.666439139 |
|
|
Aug 25 04:11:18 PM UTC 24 |
Aug 25 04:13:10 PM UTC 24 |
4924015175 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all_with_error.1282078069 |
|
|
Aug 25 04:07:44 PM UTC 24 |
Aug 25 04:13:11 PM UTC 24 |
3490187647 ps |
| T1537 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4212978702 |
|
|
Aug 25 04:13:08 PM UTC 24 |
Aug 25 04:13:20 PM UTC 24 |
58737443 ps |
| T1538 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke.2725431590 |
|
|
Aug 25 04:13:10 PM UTC 24 |
Aug 25 04:13:28 PM UTC 24 |
269660379 ps |
| T1539 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_random_large_delays.1283920729 |
|
|
Aug 25 04:09:16 PM UTC 24 |
Aug 25 04:13:42 PM UTC 24 |
15994526160 ps |
| T1540 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random_zero_delays.1269036060 |
|
|
Aug 25 04:13:27 PM UTC 24 |
Aug 25 04:13:53 PM UTC 24 |
143487758 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_random_slow_rsp.3138270122 |
|
|
Aug 25 04:02:23 PM UTC 24 |
Aug 25 04:13:56 PM UTC 24 |
30879378239 ps |
| T1541 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_access_same_device.393992429 |
|
|
Aug 25 04:11:30 PM UTC 24 |
Aug 25 04:14:04 PM UTC 24 |
2355580575 ps |
| T1542 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_access_same_device.1469278487 |
|
|
Aug 25 04:13:35 PM UTC 24 |
Aug 25 04:14:13 PM UTC 24 |
202688637 ps |
| T1543 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_large_delays.3783177376 |
|
|
Aug 25 03:57:26 PM UTC 24 |
Aug 25 04:14:14 PM UTC 24 |
58414778116 ps |
| T1544 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_random.626123528 |
|
|
Aug 25 04:14:05 PM UTC 24 |
Aug 25 04:14:28 PM UTC 24 |
175169302 ps |
| T1545 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1281034730 |
|
|
Aug 25 04:14:20 PM UTC 24 |
Aug 25 04:14:31 PM UTC 24 |
70024535 ps |
| T1546 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.chip_csr_rw.3971575437 |
|
|
Aug 25 04:01:06 PM UTC 24 |
Aug 25 04:14:40 PM UTC 24 |
5923501176 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_stress_all.4201448690 |
|
|
Aug 25 04:07:35 PM UTC 24 |
Aug 25 04:14:45 PM UTC 24 |
3804598927 ps |
| T1547 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_random.449140761 |
|
|
Aug 25 04:13:24 PM UTC 24 |
Aug 25 04:14:46 PM UTC 24 |
1430099632 ps |
| T1548 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.1130110889 |
|
|
Aug 25 03:49:37 PM UTC 24 |
Aug 25 04:15:01 PM UTC 24 |
97853276514 ps |
| T1549 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_large_delays.377741447 |
|
|
Aug 25 04:13:22 PM UTC 24 |
Aug 25 04:15:03 PM UTC 24 |
7179970200 ps |
| T1550 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_unmapped_addr.3821540950 |
|
|
Aug 25 04:14:17 PM UTC 24 |
Aug 25 04:15:08 PM UTC 24 |
256215636 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_same_csr_outstanding.1123969369 |
|
|
Aug 25 03:29:43 PM UTC 24 |
Aug 25 04:15:11 PM UTC 24 |
17135620508 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_same_source.1487097537 |
|
|
Aug 25 04:13:54 PM UTC 24 |
Aug 25 04:15:12 PM UTC 24 |
1826618534 ps |
| T1551 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke.2274734200 |
|
|
Aug 25 04:15:02 PM UTC 24 |
Aug 25 04:15:13 PM UTC 24 |
44509325 ps |
| T1552 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1411661559 |
|
|
Aug 25 04:15:08 PM UTC 24 |
Aug 25 04:15:17 PM UTC 24 |
40371009 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.545797911 |
|
|
Aug 25 04:05:36 PM UTC 24 |
Aug 25 04:15:20 PM UTC 24 |
8288491969 ps |
| T1553 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3344889801 |
|
|
Aug 25 04:13:23 PM UTC 24 |
Aug 25 04:15:34 PM UTC 24 |
5116317718 ps |
| T1554 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3271243826 |
|
|
Aug 25 04:14:35 PM UTC 24 |
Aug 25 04:15:38 PM UTC 24 |
97949944 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2658080704 |
|
|
Aug 25 03:56:13 PM UTC 24 |
Aug 25 04:15:51 PM UTC 24 |
11265040373 ps |
| T1555 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_same_source.3872920408 |
|
|
Aug 25 04:15:43 PM UTC 24 |
Aug 25 04:15:57 PM UTC 24 |
230158778 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_unmapped_addr.3961934639 |
|
|
Aug 25 04:16:02 PM UTC 24 |
Aug 25 04:16:16 PM UTC 24 |
134514039 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2212971006 |
|
|
Aug 25 04:14:51 PM UTC 24 |
Aug 25 04:16:19 PM UTC 24 |
219433478 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4040195124 |
|
|
Aug 25 04:03:29 PM UTC 24 |
Aug 25 04:16:23 PM UTC 24 |
11946914061 ps |
| T1556 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.xbar_stress_all_with_error.1280900546 |
|
|
Aug 25 04:14:37 PM UTC 24 |
Aug 25 04:16:28 PM UTC 24 |
1924889913 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.chip_tl_errors.1495571799 |
|
|
Aug 25 04:04:02 PM UTC 24 |
Aug 25 04:16:37 PM UTC 24 |
4509756007 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random_zero_delays.1628295940 |
|
|
Aug 25 04:15:32 PM UTC 24 |
Aug 25 04:16:41 PM UTC 24 |
486718499 ps |
| T1557 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_random.1990561864 |
|
|
Aug 25 04:15:26 PM UTC 24 |
Aug 25 04:16:43 PM UTC 24 |
555343759 ps |
| T1558 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_access_same_device.3263926720 |
|
|
Aug 25 04:15:35 PM UTC 24 |
Aug 25 04:16:51 PM UTC 24 |
1280975550 ps |
| T1559 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/22.chip_tl_errors.198076096 |
|
|
Aug 25 04:12:55 PM UTC 24 |
Aug 25 04:17:06 PM UTC 24 |
3395100594 ps |
| T1560 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke.1873145418 |
|
|
Aug 25 04:16:57 PM UTC 24 |
Aug 25 04:17:07 PM UTC 24 |
44436953 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.4157146945 |
|
|
Aug 25 03:45:52 PM UTC 24 |
Aug 25 04:17:10 PM UTC 24 |
74146629584 ps |
| T1561 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4075539605 |
|
|
Aug 25 04:16:14 PM UTC 24 |
Aug 25 04:17:13 PM UTC 24 |
902145744 ps |
| T1562 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_error_random.849882782 |
|
|
Aug 25 04:15:59 PM UTC 24 |
Aug 25 04:17:16 PM UTC 24 |
1461831048 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4288325111 |
|
|
Aug 25 04:17:05 PM UTC 24 |
Aug 25 04:17:18 PM UTC 24 |
51797357 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_large_delays.1255614711 |
|
|
Aug 25 04:15:07 PM UTC 24 |
Aug 25 04:17:25 PM UTC 24 |
8774309283 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1635275540 |
|
|
Aug 25 04:16:38 PM UTC 24 |
Aug 25 04:17:27 PM UTC 24 |
52354813 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3119582216 |
|
|
Aug 25 04:15:24 PM UTC 24 |
Aug 25 04:17:27 PM UTC 24 |
5135311808 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.chip_csr_rw.161649908 |
|
|
Aug 25 04:03:37 PM UTC 24 |
Aug 25 04:17:36 PM UTC 24 |
5511168400 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1428251204 |
|
|
Aug 25 03:51:25 PM UTC 24 |
Aug 25 04:17:44 PM UTC 24 |
90870962513 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.chip_tl_errors.1107285737 |
|
|
Aug 25 04:10:40 PM UTC 24 |
Aug 25 04:17:46 PM UTC 24 |
4506827760 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.1538072752 |
|
|
Aug 25 04:12:10 PM UTC 24 |
Aug 25 04:17:49 PM UTC 24 |
2407541017 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_random.3929904694 |
|
|
Aug 25 04:17:50 PM UTC 24 |
Aug 25 04:18:15 PM UTC 24 |
167057672 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_same_source.634497272 |
|
|
Aug 25 04:17:44 PM UTC 24 |
Aug 25 04:18:21 PM UTC 24 |
718900285 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_access_same_device.3200591959 |
|
|
Aug 25 04:17:39 PM UTC 24 |
Aug 25 04:18:22 PM UTC 24 |
429547859 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_zero_delays.569643903 |
|
|
Aug 25 04:17:31 PM UTC 24 |
Aug 25 04:18:24 PM UTC 24 |
395933233 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random.4142508991 |
|
|
Aug 25 04:17:30 PM UTC 24 |
Aug 25 04:18:41 PM UTC 24 |
485723435 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2880509122 |
|
|
Aug 25 04:17:59 PM UTC 24 |
Aug 25 04:18:42 PM UTC 24 |
289975435 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2990372120 |
|
|
Aug 25 04:17:15 PM UTC 24 |
Aug 25 04:18:51 PM UTC 24 |
4484846301 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_unmapped_addr.3752516512 |
|
|
Aug 25 04:17:50 PM UTC 24 |
Aug 25 04:18:56 PM UTC 24 |
902922411 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke.1958747579 |
|
|
Aug 25 04:18:45 PM UTC 24 |
Aug 25 04:18:56 PM UTC 24 |
48856840 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_error.1558741589 |
|
|
Aug 25 04:10:33 PM UTC 24 |
Aug 25 04:18:58 PM UTC 24 |
4442551668 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_smoke_zero_delays.443162928 |
|
|
Aug 25 04:18:49 PM UTC 24 |
Aug 25 04:18:59 PM UTC 24 |
44658415 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all_with_error.3940511315 |
|
|
Aug 25 04:05:26 PM UTC 24 |
Aug 25 04:19:17 PM UTC 24 |
15189802688 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.4164275206 |
|
|
Aug 25 04:06:39 PM UTC 24 |
Aug 25 04:19:18 PM UTC 24 |
35756170923 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.3084700034 |
|
|
Aug 25 04:16:46 PM UTC 24 |
Aug 25 04:19:23 PM UTC 24 |
330048443 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_random_large_delays.1922404454 |
|
|
Aug 25 04:17:34 PM UTC 24 |
Aug 25 04:19:24 PM UTC 24 |
6233147659 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_smoke_large_delays.2649795631 |
|
|
Aug 25 04:17:08 PM UTC 24 |
Aug 25 04:19:56 PM UTC 24 |
9643645068 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_error.340421194 |
|
|
Aug 25 04:12:36 PM UTC 24 |
Aug 25 04:19:58 PM UTC 24 |
10236032425 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_same_source.2717571196 |
|
|
Aug 25 04:19:40 PM UTC 24 |
Aug 25 04:19:58 PM UTC 24 |
312380051 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all.4250850506 |
|
|
Aug 25 04:16:23 PM UTC 24 |
Aug 25 04:20:02 PM UTC 24 |
3418170537 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random.2262352686 |
|
|
Aug 25 04:19:14 PM UTC 24 |
Aug 25 04:20:11 PM UTC 24 |
371332101 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1515417129 |
|
|
Aug 25 04:12:11 PM UTC 24 |
Aug 25 04:20:12 PM UTC 24 |
759499718 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_random.3866817278 |
|
|
Aug 25 04:19:46 PM UTC 24 |
Aug 25 04:20:25 PM UTC 24 |
335809269 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2804893038 |
|
|
Aug 25 04:10:34 PM UTC 24 |
Aug 25 04:20:27 PM UTC 24 |
8668789327 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_unmapped_addr.1204307727 |
|
|
Aug 25 04:19:47 PM UTC 24 |
Aug 25 04:20:28 PM UTC 24 |
676290293 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3027800182 |
|
|
Aug 25 04:20:20 PM UTC 24 |
Aug 25 04:20:30 PM UTC 24 |
45645684 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/23.xbar_stress_all_with_error.4040953513 |
|
|
Aug 25 04:16:43 PM UTC 24 |
Aug 25 04:20:34 PM UTC 24 |
2096247662 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/25.xbar_random_zero_delays.1967870188 |
|
|
Aug 25 04:19:17 PM UTC 24 |
Aug 25 04:20:35 PM UTC 24 |
547405634 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/19.chip_csr_rw.3367149251 |
|
|
Aug 25 04:08:06 PM UTC 24 |
Aug 25 04:20:38 PM UTC 24 |
6317141960 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2037461670 |
|
|
Aug 25 04:18:38 PM UTC 24 |
Aug 25 04:20:39 PM UTC 24 |
229274091 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2757745669 |
|
|
Aug 25 03:56:29 PM UTC 24 |
Aug 25 04:20:42 PM UTC 24 |
11209925373 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_random_slow_rsp.1429682879 |
|
|
Aug 25 03:57:29 PM UTC 24 |
Aug 25 04:20:44 PM UTC 24 |
60856873895 ps |