| T653 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.334749513 |
|
|
Aug 25 06:52:52 PM UTC 24 |
Aug 26 02:09:19 AM UTC 24 |
145327786429 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1238900167 |
|
|
Aug 25 03:28:45 PM UTC 24 |
Aug 25 03:28:55 PM UTC 24 |
48459114 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.605915202 |
|
|
Aug 25 03:28:44 PM UTC 24 |
Aug 25 03:28:57 PM UTC 24 |
182183994 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3209580632 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:28:59 PM UTC 24 |
34912430 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.907961834 |
|
|
Aug 25 03:28:56 PM UTC 24 |
Aug 25 03:29:04 PM UTC 24 |
47095586 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1871825366 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:29:08 PM UTC 24 |
289948021 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.311692545 |
|
|
Aug 25 03:28:55 PM UTC 24 |
Aug 25 03:29:09 PM UTC 24 |
181633395 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.2389129571 |
|
|
Aug 25 03:29:05 PM UTC 24 |
Aug 25 03:29:14 PM UTC 24 |
35672358 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.1564910649 |
|
|
Aug 25 03:28:49 PM UTC 24 |
Aug 25 03:29:16 PM UTC 24 |
202449074 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.1624014052 |
|
|
Aug 25 03:28:46 PM UTC 24 |
Aug 25 03:29:17 PM UTC 24 |
224558112 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1999541375 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:29:18 PM UTC 24 |
152788737 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.824026249 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:29:33 PM UTC 24 |
902040987 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2326110618 |
|
|
Aug 25 03:29:17 PM UTC 24 |
Aug 25 03:29:43 PM UTC 24 |
444595436 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.235201969 |
|
|
Aug 25 03:29:29 PM UTC 24 |
Aug 25 03:29:53 PM UTC 24 |
121446448 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2930963695 |
|
|
Aug 25 03:28:55 PM UTC 24 |
Aug 25 03:29:58 PM UTC 24 |
451520412 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.3542201430 |
|
|
Aug 25 03:28:57 PM UTC 24 |
Aug 25 03:30:05 PM UTC 24 |
1153178333 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.3563813224 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:30:06 PM UTC 24 |
1242237962 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2057983406 |
|
|
Aug 25 03:30:08 PM UTC 24 |
Aug 25 03:30:19 PM UTC 24 |
38294593 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.823957212 |
|
|
Aug 25 03:28:58 PM UTC 24 |
Aug 25 03:30:22 PM UTC 24 |
1723891428 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke.3171306319 |
|
|
Aug 25 03:30:08 PM UTC 24 |
Aug 25 03:30:23 PM UTC 24 |
206802575 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.3980236403 |
|
|
Aug 25 03:29:10 PM UTC 24 |
Aug 25 03:30:26 PM UTC 24 |
1239014234 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2464264374 |
|
|
Aug 25 03:28:45 PM UTC 24 |
Aug 25 03:30:28 PM UTC 24 |
3961858610 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.334607254 |
|
|
Aug 25 03:28:54 PM UTC 24 |
Aug 25 03:30:31 PM UTC 24 |
3951932728 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.2090927968 |
|
|
Aug 25 03:28:55 PM UTC 24 |
Aug 25 03:30:34 PM UTC 24 |
2209154178 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.3840993895 |
|
|
Aug 25 03:28:56 PM UTC 24 |
Aug 25 03:30:48 PM UTC 24 |
7084575198 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_unmapped_addr.2374758966 |
|
|
Aug 25 03:30:53 PM UTC 24 |
Aug 25 03:31:16 PM UTC 24 |
124135202 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.3338855245 |
|
|
Aug 25 03:28:47 PM UTC 24 |
Aug 25 03:31:17 PM UTC 24 |
2363227526 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.3983249462 |
|
|
Aug 25 03:30:44 PM UTC 24 |
Aug 25 03:31:20 PM UTC 24 |
301795540 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_random.977001339 |
|
|
Aug 25 03:30:50 PM UTC 24 |
Aug 25 03:31:20 PM UTC 24 |
495584404 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_same_source.731239177 |
|
|
Aug 25 03:30:45 PM UTC 24 |
Aug 25 03:31:23 PM UTC 24 |
746454925 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_zero_delays.1437113728 |
|
|
Aug 25 03:30:30 PM UTC 24 |
Aug 25 03:31:25 PM UTC 24 |
387525454 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1631955103 |
|
|
Aug 25 03:28:45 PM UTC 24 |
Aug 25 03:31:27 PM UTC 24 |
9624276574 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random.3348534131 |
|
|
Aug 25 03:30:27 PM UTC 24 |
Aug 25 03:31:31 PM UTC 24 |
421859667 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1761562541 |
|
|
Aug 25 03:29:23 PM UTC 24 |
Aug 25 03:31:37 PM UTC 24 |
2030237762 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3722452829 |
|
|
Aug 25 03:29:22 PM UTC 24 |
Aug 25 03:31:51 PM UTC 24 |
185202487 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_large_delays.4075432464 |
|
|
Aug 25 03:30:18 PM UTC 24 |
Aug 25 03:31:59 PM UTC 24 |
6118534726 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke.3968352265 |
|
|
Aug 25 03:31:50 PM UTC 24 |
Aug 25 03:32:00 PM UTC 24 |
41768095 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4024556242 |
|
|
Aug 25 03:30:56 PM UTC 24 |
Aug 25 03:32:02 PM UTC 24 |
1087753665 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_zero_delays.366904538 |
|
|
Aug 25 03:31:53 PM UTC 24 |
Aug 25 03:32:05 PM UTC 24 |
53269233 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3197136042 |
|
|
Aug 25 03:29:20 PM UTC 24 |
Aug 25 03:32:19 PM UTC 24 |
2839915597 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.620733685 |
|
|
Aug 25 03:30:21 PM UTC 24 |
Aug 25 03:32:51 PM UTC 24 |
5532650624 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_zero_delays.3021301323 |
|
|
Aug 25 03:32:25 PM UTC 24 |
Aug 25 03:32:55 PM UTC 24 |
228714998 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.1848309081 |
|
|
Aug 25 03:28:42 PM UTC 24 |
Aug 25 03:33:20 PM UTC 24 |
4188211984 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random.4228823655 |
|
|
Aug 25 03:32:15 PM UTC 24 |
Aug 25 03:33:35 PM UTC 24 |
526591249 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_large_delays.979690379 |
|
|
Aug 25 03:31:56 PM UTC 24 |
Aug 25 03:33:41 PM UTC 24 |
5014464570 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3651775298 |
|
|
Aug 25 03:32:01 PM UTC 24 |
Aug 25 03:33:50 PM UTC 24 |
4279091145 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.4029820738 |
|
|
Aug 25 03:33:38 PM UTC 24 |
Aug 25 03:34:00 PM UTC 24 |
315902407 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_access_same_device.2396972586 |
|
|
Aug 25 03:32:29 PM UTC 24 |
Aug 25 03:34:07 PM UTC 24 |
1789396769 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.512539478 |
|
|
Aug 25 03:28:49 PM UTC 24 |
Aug 25 03:34:12 PM UTC 24 |
587961050 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_same_source.117795367 |
|
|
Aug 25 03:33:10 PM UTC 24 |
Aug 25 03:34:12 PM UTC 24 |
501832060 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3483005304 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:34:25 PM UTC 24 |
4257690693 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.1471279085 |
|
|
Aug 25 03:29:56 PM UTC 24 |
Aug 25 03:34:41 PM UTC 24 |
3407024068 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_unmapped_addr.508445619 |
|
|
Aug 25 03:33:19 PM UTC 24 |
Aug 25 03:34:44 PM UTC 24 |
1254725223 ps |
| T1353 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke.2496058067 |
|
|
Aug 25 03:34:42 PM UTC 24 |
Aug 25 03:34:52 PM UTC 24 |
47579754 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all.2777769110 |
|
|
Aug 25 03:30:57 PM UTC 24 |
Aug 25 03:34:53 PM UTC 24 |
2444466701 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all.1630598066 |
|
|
Aug 25 03:33:44 PM UTC 24 |
Aug 25 03:34:54 PM UTC 24 |
669239361 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.3516178411 |
|
|
Aug 25 03:31:12 PM UTC 24 |
Aug 25 03:34:59 PM UTC 24 |
2222559545 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_zero_delays.3018557572 |
|
|
Aug 25 03:34:48 PM UTC 24 |
Aug 25 03:35:00 PM UTC 24 |
50396845 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1391229787 |
|
|
Aug 25 03:33:55 PM UTC 24 |
Aug 25 03:35:08 PM UTC 24 |
1784143664 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.1131426715 |
|
|
Aug 25 03:31:48 PM UTC 24 |
Aug 25 03:35:11 PM UTC 24 |
2455004996 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2181034928 |
|
|
Aug 25 03:33:46 PM UTC 24 |
Aug 25 03:35:20 PM UTC 24 |
270661215 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_error_random.3131561882 |
|
|
Aug 25 03:33:16 PM UTC 24 |
Aug 25 03:35:26 PM UTC 24 |
2632966872 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random.3536037635 |
|
|
Aug 25 03:35:09 PM UTC 24 |
Aug 25 03:35:29 PM UTC 24 |
335472865 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_random.440876767 |
|
|
Aug 25 03:35:24 PM UTC 24 |
Aug 25 03:35:36 PM UTC 24 |
64315254 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_zero_delays.782243399 |
|
|
Aug 25 03:35:08 PM UTC 24 |
Aug 25 03:35:48 PM UTC 24 |
352557413 ps |
| T1354 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2863525062 |
|
|
Aug 25 03:28:55 PM UTC 24 |
Aug 25 03:35:53 PM UTC 24 |
8731060926 ps |
| T1355 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_unmapped_addr.3776987055 |
|
|
Aug 25 03:35:31 PM UTC 24 |
Aug 25 03:35:57 PM UTC 24 |
277007655 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3925263076 |
|
|
Aug 25 03:35:36 PM UTC 24 |
Aug 25 03:36:23 PM UTC 24 |
600520400 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_large_delays.732488969 |
|
|
Aug 25 03:35:11 PM UTC 24 |
Aug 25 03:36:24 PM UTC 24 |
4019683972 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.3599103954 |
|
|
Aug 25 03:28:53 PM UTC 24 |
Aug 25 03:36:26 PM UTC 24 |
3571245408 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_same_source.1620129118 |
|
|
Aug 25 03:35:23 PM UTC 24 |
Aug 25 03:36:41 PM UTC 24 |
1713241333 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_slow_rsp.4245208223 |
|
|
Aug 25 03:30:34 PM UTC 24 |
Aug 25 03:36:52 PM UTC 24 |
17354065298 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_large_delays.3822900251 |
|
|
Aug 25 03:34:49 PM UTC 24 |
Aug 25 03:36:57 PM UTC 24 |
7301031699 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_zero_delays.890346379 |
|
|
Aug 25 03:36:49 PM UTC 24 |
Aug 25 03:37:00 PM UTC 24 |
40962394 ps |
| T1356 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke.2405255726 |
|
|
Aug 25 03:36:49 PM UTC 24 |
Aug 25 03:37:04 PM UTC 24 |
217364307 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device.210472819 |
|
|
Aug 25 03:35:17 PM UTC 24 |
Aug 25 03:37:07 PM UTC 24 |
2257014981 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3073761010 |
|
|
Aug 25 03:35:05 PM UTC 24 |
Aug 25 03:37:13 PM UTC 24 |
5222647754 ps |
| T1357 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1094902489 |
|
|
Aug 25 03:37:38 PM UTC 24 |
Aug 25 03:37:49 PM UTC 24 |
38813945 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_unmapped_addr.929322108 |
|
|
Aug 25 03:37:31 PM UTC 24 |
Aug 25 03:37:56 PM UTC 24 |
109037037 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_bit_bash.2322871147 |
|
|
Aug 25 03:31:41 PM UTC 24 |
Aug 25 03:38:00 PM UTC 24 |
3527300700 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.251137606 |
|
|
Aug 25 03:34:01 PM UTC 24 |
Aug 25 03:38:04 PM UTC 24 |
1783970263 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_large_delays.423828328 |
|
|
Aug 25 03:32:24 PM UTC 24 |
Aug 25 03:38:04 PM UTC 24 |
20517049109 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_zero_delays.1356152498 |
|
|
Aug 25 03:37:03 PM UTC 24 |
Aug 25 03:38:16 PM UTC 24 |
583748889 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_error_random.355540068 |
|
|
Aug 25 03:37:29 PM UTC 24 |
Aug 25 03:38:22 PM UTC 24 |
988387358 ps |
| T1358 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.1519311161 |
|
|
Aug 25 03:28:45 PM UTC 24 |
Aug 25 03:38:37 PM UTC 24 |
8288060370 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.339538906 |
|
|
Aug 25 03:37:00 PM UTC 24 |
Aug 25 03:38:52 PM UTC 24 |
1944899601 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1582762736 |
|
|
Aug 25 03:36:57 PM UTC 24 |
Aug 25 03:38:39 PM UTC 24 |
5771288836 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.243201755 |
|
|
Aug 25 03:29:33 PM UTC 24 |
Aug 25 03:38:44 PM UTC 24 |
7235835983 ps |
| T1359 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke.1520619919 |
|
|
Aug 25 03:38:46 PM UTC 24 |
Aug 25 03:39:03 PM UTC 24 |
231075513 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_same_source.2879310219 |
|
|
Aug 25 03:37:22 PM UTC 24 |
Aug 25 03:39:04 PM UTC 24 |
2564567931 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.646438572 |
|
|
Aug 25 03:28:50 PM UTC 24 |
Aug 25 03:39:12 PM UTC 24 |
6173941775 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3197075689 |
|
|
Aug 25 03:39:01 PM UTC 24 |
Aug 25 03:39:12 PM UTC 24 |
44291953 ps |
| T1360 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random.638092744 |
|
|
Aug 25 03:39:16 PM UTC 24 |
Aug 25 03:39:27 PM UTC 24 |
42849951 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device.536650002 |
|
|
Aug 25 03:37:16 PM UTC 24 |
Aug 25 03:39:28 PM UTC 24 |
2175281605 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.3432653047 |
|
|
Aug 25 03:31:27 PM UTC 24 |
Aug 25 03:39:44 PM UTC 24 |
7862678688 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_zero_delays.3218819834 |
|
|
Aug 25 03:39:26 PM UTC 24 |
Aug 25 03:39:48 PM UTC 24 |
123810597 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.2255423092 |
|
|
Aug 25 03:34:05 PM UTC 24 |
Aug 25 03:40:02 PM UTC 24 |
4682994375 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.828123840 |
|
|
Aug 25 03:28:50 PM UTC 24 |
Aug 25 03:40:03 PM UTC 24 |
12085409153 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.3157500361 |
|
|
Aug 25 03:34:35 PM UTC 24 |
Aug 25 03:40:07 PM UTC 24 |
3024433911 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.2090008555 |
|
|
Aug 25 03:28:51 PM UTC 24 |
Aug 25 03:40:10 PM UTC 24 |
4834846203 ps |
| T1361 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3720961999 |
|
|
Aug 25 03:28:45 PM UTC 24 |
Aug 25 03:40:15 PM UTC 24 |
13486178547 ps |
| T1362 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_prim_tl_access.3390533674 |
|
|
Aug 25 03:29:58 PM UTC 24 |
Aug 25 03:40:22 PM UTC 24 |
8795873786 ps |
| T1363 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_same_source.2810527382 |
|
|
Aug 25 03:39:52 PM UTC 24 |
Aug 25 03:40:27 PM UTC 24 |
702340366 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_smoke_large_delays.4122653972 |
|
|
Aug 25 03:36:50 PM UTC 24 |
Aug 25 03:40:27 PM UTC 24 |
11602675261 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.977247066 |
|
|
Aug 25 03:35:50 PM UTC 24 |
Aug 25 03:40:27 PM UTC 24 |
1513706141 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all.2311272457 |
|
|
Aug 25 03:41:39 PM UTC 24 |
Aug 25 03:47:17 PM UTC 24 |
6571993898 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.2424227036 |
|
|
Aug 25 03:34:13 PM UTC 24 |
Aug 25 03:40:33 PM UTC 24 |
4072011528 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.104739466 |
|
|
Aug 25 03:39:07 PM UTC 24 |
Aug 25 03:40:40 PM UTC 24 |
4494820893 ps |
| T1364 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3918942971 |
|
|
Aug 25 03:40:24 PM UTC 24 |
Aug 25 03:40:45 PM UTC 24 |
106291700 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2355633533 |
|
|
Aug 25 03:31:00 PM UTC 24 |
Aug 25 03:40:48 PM UTC 24 |
3248066496 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all.1365834424 |
|
|
Aug 25 03:35:43 PM UTC 24 |
Aug 25 03:40:49 PM UTC 24 |
7690211531 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2755964074 |
|
|
Aug 25 03:36:00 PM UTC 24 |
Aug 25 03:40:51 PM UTC 24 |
1461343907 ps |
| T1365 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random_large_delays.1481065987 |
|
|
Aug 25 03:37:13 PM UTC 24 |
Aug 25 03:40:58 PM UTC 24 |
14521785268 ps |
| T1366 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_random_slow_rsp.3033287366 |
|
|
Aug 25 03:39:34 PM UTC 24 |
Aug 25 03:40:59 PM UTC 24 |
4028332103 ps |
| T1367 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_smoke_large_delays.4283236490 |
|
|
Aug 25 03:39:00 PM UTC 24 |
Aug 25 03:41:00 PM UTC 24 |
7022218210 ps |
| T1368 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_error_random.2252789607 |
|
|
Aug 25 03:40:08 PM UTC 24 |
Aug 25 03:41:04 PM UTC 24 |
476467488 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4064918025 |
|
|
Aug 25 03:31:27 PM UTC 24 |
Aug 25 03:41:07 PM UTC 24 |
2829418729 ps |
| T1369 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke.952510672 |
|
|
Aug 25 03:40:58 PM UTC 24 |
Aug 25 03:41:11 PM UTC 24 |
156934385 ps |
| T1370 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3669781860 |
|
|
Aug 25 03:41:03 PM UTC 24 |
Aug 25 03:41:15 PM UTC 24 |
39825440 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3852237220 |
|
|
Aug 25 03:31:34 PM UTC 24 |
Aug 25 03:41:16 PM UTC 24 |
4562215960 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device.3214539655 |
|
|
Aug 25 03:39:36 PM UTC 24 |
Aug 25 03:41:17 PM UTC 24 |
992107723 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_unmapped_addr.1758242517 |
|
|
Aug 25 03:40:13 PM UTC 24 |
Aug 25 03:41:42 PM UTC 24 |
1404341909 ps |
| T1371 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_unmapped_addr.927231358 |
|
|
Aug 25 03:41:35 PM UTC 24 |
Aug 25 03:41:47 PM UTC 24 |
35474927 ps |
| T1372 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3816868904 |
|
|
Aug 25 03:41:38 PM UTC 24 |
Aug 25 03:41:54 PM UTC 24 |
76955013 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_zero_delays.1071318955 |
|
|
Aug 25 03:41:15 PM UTC 24 |
Aug 25 03:42:13 PM UTC 24 |
457504218 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_error.3131604042 |
|
|
Aug 25 03:38:18 PM UTC 24 |
Aug 25 03:42:19 PM UTC 24 |
1836674607 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random.3188575370 |
|
|
Aug 25 03:41:13 PM UTC 24 |
Aug 25 03:42:26 PM UTC 24 |
1504090725 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_access_same_device.3228785222 |
|
|
Aug 25 03:41:24 PM UTC 24 |
Aug 25 03:42:29 PM UTC 24 |
388216629 ps |
| T1373 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3153702150 |
|
|
Aug 25 03:41:11 PM UTC 24 |
Aug 25 03:42:29 PM UTC 24 |
4059919872 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_error_random.1917336804 |
|
|
Aug 25 03:41:29 PM UTC 24 |
Aug 25 03:42:30 PM UTC 24 |
1275559040 ps |
| T1374 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.4009870639 |
|
|
Aug 25 03:29:58 PM UTC 24 |
Aug 25 03:42:48 PM UTC 24 |
10513239062 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_tl_errors.3218325607 |
|
|
Aug 25 03:38:41 PM UTC 24 |
Aug 25 03:42:54 PM UTC 24 |
3061855912 ps |
| T1375 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2474446063 |
|
|
Aug 25 03:28:54 PM UTC 24 |
Aug 25 03:43:01 PM UTC 24 |
15405591080 ps |
| T1376 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke.2187043335 |
|
|
Aug 25 03:42:52 PM UTC 24 |
Aug 25 03:43:03 PM UTC 24 |
46440229 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_same_source.829903392 |
|
|
Aug 25 03:41:27 PM UTC 24 |
Aug 25 03:43:04 PM UTC 24 |
2467319807 ps |
| T1377 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_zero_delays.303168987 |
|
|
Aug 25 03:42:53 PM UTC 24 |
Aug 25 03:43:06 PM UTC 24 |
48031734 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.1665143817 |
|
|
Aug 25 03:28:56 PM UTC 24 |
Aug 25 03:43:09 PM UTC 24 |
48266806976 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.367683428 |
|
|
Aug 25 03:31:40 PM UTC 24 |
Aug 25 03:43:26 PM UTC 24 |
7312968790 ps |
| T1378 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random.3713215133 |
|
|
Aug 25 03:43:18 PM UTC 24 |
Aug 25 03:43:35 PM UTC 24 |
214077642 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all.1135489415 |
|
|
Aug 25 03:40:28 PM UTC 24 |
Aug 25 03:43:41 PM UTC 24 |
1447713736 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_error.371645901 |
|
|
Aug 25 03:42:06 PM UTC 24 |
Aug 25 03:43:45 PM UTC 24 |
746714127 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_error.3009195945 |
|
|
Aug 25 03:40:35 PM UTC 24 |
Aug 25 03:44:00 PM UTC 24 |
3961513099 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_zero_delays.437959654 |
|
|
Aug 25 03:43:24 PM UTC 24 |
Aug 25 03:44:08 PM UTC 24 |
446788517 ps |
| T1379 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_smoke_large_delays.451054710 |
|
|
Aug 25 03:41:09 PM UTC 24 |
Aug 25 03:44:11 PM UTC 24 |
9652714577 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3265389185 |
|
|
Aug 25 03:42:11 PM UTC 24 |
Aug 25 03:44:18 PM UTC 24 |
605995704 ps |
| T1380 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_large_delays.585523821 |
|
|
Aug 25 03:42:54 PM UTC 24 |
Aug 25 03:44:25 PM UTC 24 |
5505120235 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2733740810 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:44:42 PM UTC 24 |
10188348825 ps |
| T1381 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3775376166 |
|
|
Aug 25 03:43:12 PM UTC 24 |
Aug 25 03:44:53 PM UTC 24 |
3806545816 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3067282904 |
|
|
Aug 25 03:29:39 PM UTC 24 |
Aug 25 03:44:57 PM UTC 24 |
8005729778 ps |
| T1382 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_random.2058383087 |
|
|
Aug 25 03:43:59 PM UTC 24 |
Aug 25 03:45:02 PM UTC 24 |
480109449 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.3364481075 |
|
|
Aug 25 03:35:53 PM UTC 24 |
Aug 25 03:45:03 PM UTC 24 |
10304000433 ps |
| T1383 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3119823920 |
|
|
Aug 25 03:44:05 PM UTC 24 |
Aug 25 03:45:08 PM UTC 24 |
1316158944 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.4288916194 |
|
|
Aug 25 03:40:52 PM UTC 24 |
Aug 25 03:45:09 PM UTC 24 |
3674540489 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.110462298 |
|
|
Aug 25 03:43:28 PM UTC 24 |
Aug 25 03:45:15 PM UTC 24 |
2154737027 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_unmapped_addr.1421865882 |
|
|
Aug 25 03:44:01 PM UTC 24 |
Aug 25 03:45:19 PM UTC 24 |
1371729391 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2644647691 |
|
|
Aug 25 03:44:33 PM UTC 24 |
Aug 25 03:45:20 PM UTC 24 |
139491532 ps |
| T1384 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke.4229713534 |
|
|
Aug 25 03:45:16 PM UTC 24 |
Aug 25 03:45:28 PM UTC 24 |
176643269 ps |
| T1385 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2118779120 |
|
|
Aug 25 03:45:21 PM UTC 24 |
Aug 25 03:45:31 PM UTC 24 |
40753618 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1299307336 |
|
|
Aug 25 03:40:31 PM UTC 24 |
Aug 25 03:45:41 PM UTC 24 |
548081247 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2588999152 |
|
|
Aug 25 03:40:41 PM UTC 24 |
Aug 25 03:45:42 PM UTC 24 |
1244922540 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.1395212051 |
|
|
Aug 25 03:29:34 PM UTC 24 |
Aug 25 03:45:43 PM UTC 24 |
5049098816 ps |
| T1386 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random.1876887974 |
|
|
Aug 25 03:45:29 PM UTC 24 |
Aug 25 03:45:50 PM UTC 24 |
102903920 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_same_source.1865987956 |
|
|
Aug 25 03:43:49 PM UTC 24 |
Aug 25 03:45:52 PM UTC 24 |
2626218199 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_hw_reset.1526176869 |
|
|
Aug 25 03:36:04 PM UTC 24 |
Aug 25 03:45:53 PM UTC 24 |
8374121966 ps |
| T1387 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device.1054176327 |
|
|
Aug 25 03:45:43 PM UTC 24 |
Aug 25 03:45:57 PM UTC 24 |
27296881 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_tl_errors.2792250702 |
|
|
Aug 25 03:36:26 PM UTC 24 |
Aug 25 03:46:02 PM UTC 24 |
4104895679 ps |
| T1388 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_random_zero_delays.442543068 |
|
|
Aug 25 03:45:31 PM UTC 24 |
Aug 25 03:46:03 PM UTC 24 |
231955779 ps |
| T1389 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3844345387 |
|
|
Aug 25 03:46:06 PM UTC 24 |
Aug 25 03:46:43 PM UTC 24 |
662419776 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.4236121255 |
|
|
Aug 25 03:28:58 PM UTC 24 |
Aug 25 03:46:44 PM UTC 24 |
36984587820 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.4292867460 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:46:44 PM UTC 24 |
44424078224 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_unmapped_addr.564765764 |
|
|
Aug 25 03:46:05 PM UTC 24 |
Aug 25 03:46:59 PM UTC 24 |
889893367 ps |
| T1390 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_error_random.3360385111 |
|
|
Aug 25 03:45:55 PM UTC 24 |
Aug 25 03:47:00 PM UTC 24 |
1376401169 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_same_source.2828172460 |
|
|
Aug 25 03:45:52 PM UTC 24 |
Aug 25 03:47:03 PM UTC 24 |
1488765038 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1434718378 |
|
|
Aug 25 03:34:17 PM UTC 24 |
Aug 25 03:47:08 PM UTC 24 |
6000254100 ps |
| T1391 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2581386901 |
|
|
Aug 25 03:45:27 PM UTC 24 |
Aug 25 03:47:10 PM UTC 24 |
4781164078 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1763178832 |
|
|
Aug 25 03:28:48 PM UTC 24 |
Aug 25 03:47:11 PM UTC 24 |
49202298396 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.2133944262 |
|
|
Aug 25 03:47:07 PM UTC 24 |
Aug 25 03:47:22 PM UTC 24 |
197535244 ps |
| T1392 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.445750864 |
|
|
Aug 25 03:47:10 PM UTC 24 |
Aug 25 03:47:22 PM UTC 24 |
40499250 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_random_slow_rsp.3765526130 |
|
|
Aug 25 03:35:17 PM UTC 24 |
Aug 25 03:47:26 PM UTC 24 |
27255956488 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2505154598 |
|
|
Aug 25 03:44:08 PM UTC 24 |
Aug 25 03:47:27 PM UTC 24 |
263409892 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3377164313 |
|
|
Aug 25 03:38:25 PM UTC 24 |
Aug 25 03:47:46 PM UTC 24 |
5257943904 ps |
| T1393 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.4065691542 |
|
|
Aug 25 03:47:52 PM UTC 24 |
Aug 25 03:48:13 PM UTC 24 |
110541560 ps |
| T1394 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.3575835411 |
|
|
Aug 25 03:47:26 PM UTC 24 |
Aug 25 03:48:13 PM UTC 24 |
996945402 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_rw.2921816786 |
|
|
Aug 25 03:38:28 PM UTC 24 |
Aug 25 03:48:17 PM UTC 24 |
4630515800 ps |
| T1395 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.635083521 |
|
|
Aug 25 03:28:44 PM UTC 24 |
Aug 25 03:48:18 PM UTC 24 |
8816192268 ps |
| T1396 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_smoke_large_delays.2811363400 |
|
|
Aug 25 03:45:27 PM UTC 24 |
Aug 25 03:48:18 PM UTC 24 |
9021385251 ps |
| T1397 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2934035921 |
|
|
Aug 25 03:48:12 PM UTC 24 |
Aug 25 03:48:23 PM UTC 24 |
88396769 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.3304044596 |
|
|
Aug 25 03:47:31 PM UTC 24 |
Aug 25 03:48:44 PM UTC 24 |
566558579 ps |
| T1398 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.3158163428 |
|
|
Aug 25 03:47:47 PM UTC 24 |
Aug 25 03:48:53 PM UTC 24 |
511070703 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all.2923114369 |
|
|
Aug 25 03:44:06 PM UTC 24 |
Aug 25 03:49:03 PM UTC 24 |
2323133047 ps |
| T1399 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2466251776 |
|
|
Aug 25 03:48:57 PM UTC 24 |
Aug 25 03:49:07 PM UTC 24 |
46822040 ps |
| T1400 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.358266216 |
|
|
Aug 25 03:48:56 PM UTC 24 |
Aug 25 03:49:14 PM UTC 24 |
225996160 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_error.800479630 |
|
|
Aug 25 03:46:15 PM UTC 24 |
Aug 25 03:49:20 PM UTC 24 |
1876842288 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.2136761186 |
|
|
Aug 25 03:47:42 PM UTC 24 |
Aug 25 03:49:25 PM UTC 24 |
1046912612 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.34533725 |
|
|
Aug 25 03:47:46 PM UTC 24 |
Aug 25 03:49:38 PM UTC 24 |
2343981277 ps |
| T1401 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2014621106 |
|
|
Aug 25 03:47:23 PM UTC 24 |
Aug 25 03:49:40 PM UTC 24 |
5994562180 ps |
| T1402 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.1104784412 |
|
|
Aug 25 03:47:23 PM UTC 24 |
Aug 25 03:49:44 PM UTC 24 |
7513654571 ps |
| T1403 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.2578088461 |
|
|
Aug 25 03:49:27 PM UTC 24 |
Aug 25 03:49:48 PM UTC 24 |
130796057 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.491009858 |
|
|
Aug 25 03:49:31 PM UTC 24 |
Aug 25 03:49:49 PM UTC 24 |
90484010 ps |
| T1404 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.630484968 |
|
|
Aug 25 03:48:41 PM UTC 24 |
Aug 25 03:49:54 PM UTC 24 |
703263609 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_random_slow_rsp.3457099749 |
|
|
Aug 25 03:32:26 PM UTC 24 |
Aug 25 03:50:13 PM UTC 24 |
45118459867 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.988880948 |
|
|
Aug 25 03:38:29 PM UTC 24 |
Aug 25 03:50:15 PM UTC 24 |
7516683180 ps |
| T1405 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.730468175 |
|
|
Aug 25 03:50:02 PM UTC 24 |
Aug 25 03:50:22 PM UTC 24 |
302510254 ps |
| T1406 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.1845462457 |
|
|
Aug 25 03:47:06 PM UTC 24 |
Aug 25 03:50:23 PM UTC 24 |
2843161624 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_bit_bash.1526522584 |
|
|
Aug 25 03:29:40 PM UTC 24 |
Aug 25 03:50:23 PM UTC 24 |
6772552864 ps |
| T1407 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2201053331 |
|
|
Aug 25 03:50:08 PM UTC 24 |
Aug 25 03:50:33 PM UTC 24 |
126167874 ps |
| T1408 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.2931045114 |
|
|
Aug 25 03:50:01 PM UTC 24 |
Aug 25 03:50:37 PM UTC 24 |
506761693 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_random_large_delays.1017326425 |
|
|
Aug 25 03:43:27 PM UTC 24 |
Aug 25 03:50:57 PM UTC 24 |
25471937826 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.1862823810 |
|
|
Aug 25 03:50:48 PM UTC 24 |
Aug 25 03:51:01 PM UTC 24 |
192928349 ps |
| T1409 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2934005702 |
|
|
Aug 25 03:49:17 PM UTC 24 |
Aug 25 03:51:03 PM UTC 24 |
4419258731 ps |
| T1410 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.1766730620 |
|
|
Aug 25 03:50:02 PM UTC 24 |
Aug 25 03:51:05 PM UTC 24 |
580953398 ps |
| T1411 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2525949147 |
|
|
Aug 25 03:50:55 PM UTC 24 |
Aug 25 03:51:06 PM UTC 24 |
40560081 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3282842938 |
|
|
Aug 25 03:38:15 PM UTC 24 |
Aug 25 03:51:11 PM UTC 24 |
10054470869 ps |
| T1412 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.4144428506 |
|
|
Aug 25 03:49:08 PM UTC 24 |
Aug 25 03:51:13 PM UTC 24 |
7578032345 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_random_large_delays.3835918081 |
|
|
Aug 25 03:41:21 PM UTC 24 |
Aug 25 03:51:14 PM UTC 24 |
37605811812 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3563581115 |
|
|
Aug 25 03:41:40 PM UTC 24 |
Aug 25 03:51:29 PM UTC 24 |
788345699 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_stress_all_with_error.3955736855 |
|
|
Aug 25 03:44:24 PM UTC 24 |
Aug 25 03:51:34 PM UTC 24 |
3687072330 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_tl_errors.4109076501 |
|
|
Aug 25 03:42:49 PM UTC 24 |
Aug 25 03:51:38 PM UTC 24 |
4288540470 ps |
| T1413 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.4120514383 |
|
|
Aug 25 03:51:23 PM UTC 24 |
Aug 25 03:51:44 PM UTC 24 |
125185369 ps |
| T1414 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.1862008926 |
|
|
Aug 25 03:51:21 PM UTC 24 |
Aug 25 03:51:45 PM UTC 24 |
311004414 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3755839933 |
|
|
Aug 25 03:45:06 PM UTC 24 |
Aug 25 03:52:22 PM UTC 24 |
3606611990 ps |
| T1415 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.344193002 |
|
|
Aug 25 03:51:53 PM UTC 24 |
Aug 25 03:52:26 PM UTC 24 |
738542720 ps |
| T1416 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.2484878639 |
|
|
Aug 25 03:51:36 PM UTC 24 |
Aug 25 03:52:28 PM UTC 24 |
987251281 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.1103167775 |
|
|
Aug 25 03:49:45 PM UTC 24 |
Aug 25 03:52:30 PM UTC 24 |
2389337411 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.3709318785 |
|
|
Aug 25 03:51:34 PM UTC 24 |
Aug 25 03:52:33 PM UTC 24 |
464419813 ps |
| T1417 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.4267868753 |
|
|
Aug 25 03:51:38 PM UTC 24 |
Aug 25 03:52:38 PM UTC 24 |
1065040213 ps |
| T1418 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4107631112 |
|
|
Aug 25 03:51:00 PM UTC 24 |
Aug 25 03:52:42 PM UTC 24 |
4474712459 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3895762697 |
|
|
Aug 25 03:46:14 PM UTC 24 |
Aug 25 03:52:43 PM UTC 24 |
490643912 ps |
| T1419 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3067971647 |
|
|
Aug 25 03:52:57 PM UTC 24 |
Aug 25 03:53:08 PM UTC 24 |
54508699 ps |
| T1420 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_smoke.2923060934 |
|
|
Aug 25 03:52:54 PM UTC 24 |
Aug 25 03:53:10 PM UTC 24 |
229131675 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2805496032 |
|
|
Aug 25 03:30:48 PM UTC 24 |
Aug 25 03:53:18 PM UTC 24 |
54295513327 ps |
| T1421 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.463424138 |
|
|
Aug 25 03:50:57 PM UTC 24 |
Aug 25 03:53:21 PM UTC 24 |
8800551101 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2052894496 |
|
|
Aug 25 03:50:12 PM UTC 24 |
Aug 25 03:53:21 PM UTC 24 |
3816138203 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1883078032 |
|
|
Aug 25 03:46:16 PM UTC 24 |
Aug 25 03:53:40 PM UTC 24 |
2886511074 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.2193899059 |
|
|
Aug 25 03:51:53 PM UTC 24 |
Aug 25 03:53:47 PM UTC 24 |
761924391 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.219452359 |
|
|
Aug 25 03:36:17 PM UTC 24 |
Aug 25 03:53:56 PM UTC 24 |
9088814214 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.2099432788 |
|
|
Aug 25 03:51:28 PM UTC 24 |
Aug 25 03:54:05 PM UTC 24 |
3307319338 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_csr_rw.3852371839 |
|
|
Aug 25 03:36:11 PM UTC 24 |
Aug 25 03:54:08 PM UTC 24 |
6438994721 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1818526102 |
|
|
Aug 25 03:52:08 PM UTC 24 |
Aug 25 03:54:27 PM UTC 24 |
488770462 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_rw.2732466471 |
|
|
Aug 25 03:42:18 PM UTC 24 |
Aug 25 03:54:33 PM UTC 24 |
6104068750 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.239700939 |
|
|
Aug 25 03:53:44 PM UTC 24 |
Aug 25 03:54:34 PM UTC 24 |
748003296 ps |
| T1422 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_unmapped_addr.3632151550 |
|
|
Aug 25 03:54:19 PM UTC 24 |
Aug 25 03:54:40 PM UTC 24 |
217053453 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_zero_delays.3179443750 |
|
|
Aug 25 03:53:33 PM UTC 24 |
Aug 25 03:54:46 PM UTC 24 |
641466502 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.chip_csr_rw.1613325171 |
|
|
Aug 25 03:44:35 PM UTC 24 |
Aug 25 03:54:50 PM UTC 24 |
4594530986 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.952070698 |
|
|
Aug 25 03:51:59 PM UTC 24 |
Aug 25 03:54:50 PM UTC 24 |
373744506 ps |
| T1423 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1615028182 |
|
|
Aug 25 03:54:12 PM UTC 24 |
Aug 25 03:54:52 PM UTC 24 |
828433565 ps |
| T1424 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3692615606 |
|
|
Aug 25 03:54:29 PM UTC 24 |
Aug 25 03:54:59 PM UTC 24 |
502670055 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_same_source.3516389067 |
|
|
Aug 25 03:54:05 PM UTC 24 |
Aug 25 03:55:02 PM UTC 24 |
558316613 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.1701526120 |
|
|
Aug 25 03:50:48 PM UTC 24 |
Aug 25 03:55:03 PM UTC 24 |
3265168682 ps |
| T1425 |
/workspaces/repo/scratch/os_regression_2024_08_24/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3960174993 |
|
|
Aug 25 03:42:37 PM UTC 24 |
Aug 25 03:55:04 PM UTC 24 |
6978997605 ps |